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authorDimitry Andric <dim@FreeBSD.org>2017-12-24 01:00:08 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-12-24 01:00:08 +0000
commitc7dac04c3480f3c20487f912f77343139fce2d99 (patch)
tree21a09bce0171e27bd1e92649db9df797fa097cea /lib/Target/ARM/ARMSubtarget.cpp
parent044eb2f6afba375a914ac9d8024f8f5142bb912e (diff)
Notes
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.cpp')
-rw-r--r--lib/Target/ARM/ARMSubtarget.cpp5
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 4d4a88126ce65..23027e92481f1 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -348,11 +348,6 @@ unsigned ARMSubtarget::getMispredictionPenalty() const {
return SchedModel.MispredictPenalty;
}
-bool ARMSubtarget::hasSinCos() const {
- return isTargetWatchOS() ||
- (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
-}
-
bool ARMSubtarget::enableMachineScheduler() const {
// Enable the MachineScheduler before register allocation for subtargets
// with the use-misched feature.