diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2018-06-27 19:14:09 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2018-06-27 19:14:09 +0000 |
commit | eb1edd4d5902fdc561fd68fa70400fbd11127998 (patch) | |
tree | 0b10ccde4b5d3acf243966db54f4f3afef10cf93 /lib/Target/Mips/AsmParser | |
parent | 2ed8710148a921286717212737771dd31c518fb7 (diff) |
Notes
Diffstat (limited to 'lib/Target/Mips/AsmParser')
-rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 345b081500a42..f36a4317b1b9c 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction // and registers Rd and Base for microMIPS lwp instruction case Mips::JALR_HB: + case Mips::JALR_HB64: case Mips::JALRC_HB_MMR6: case Mips::JALRC_MMR6: if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) |