diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-02-01 21:34:47 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-02-01 21:34:47 +0000 |
| commit | 823f87a1f80708ce9ba318cc0b07632e76b74d43 (patch) | |
| tree | 400cc7e5d4548d5f3829f7feea7f7942b4e62dd4 /lib/Target/Mips/MipsFastISel.cpp | |
| parent | aac4ca60bc813a35242145a1f92f325303d5df6e (diff) | |
Diffstat (limited to 'lib/Target/Mips/MipsFastISel.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 29f3e2c07e048..a44192f57aa06 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -698,8 +698,8 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) + .addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) |