diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-12-01 15:41:24 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-12-01 15:41:24 +0000 |
| commit | d17fea9f4160084012c9596029dfeba3220a5ff3 (patch) | |
| tree | 7e3aea25e33e59b34dbce3a86580fe0af17efd9d /lib/Target/Mips/MipsFastISel.cpp | |
| parent | 86392292ee722abb03af4befe2d2c8baaeadaf22 (diff) | |
Diffstat (limited to 'lib/Target/Mips/MipsFastISel.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 19b30a44e86ad..22ade31a72cdb 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -953,6 +953,11 @@ bool MipsFastISel::selectBranch(const Instruction *I) { MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // For now, just try the simplest case where it's fed by a compare. if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { + MVT CIMVT = + TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT(); + if (CIMVT == MVT::i1) + return false; + unsigned CondReg = getRegForValue(CI); BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) .addReg(CondReg) |