diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-01-06 21:34:26 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-01-06 21:34:26 +0000 |
| commit | d215fd3b74b90f5dc1964610926fcc2a20f959aa (patch) | |
| tree | 0c9f21e40eae033d6760008729f37d2103e2c654 /lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | |
| parent | b8a2042aa938069e862750553db0e4d82d25822c (diff) | |
Diffstat (limited to 'lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp')
| -rw-r--r-- | lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index b91467fe1455f..6e06a4975e2af 100644 --- a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -230,9 +230,10 @@ RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { } // end anonymous namespace MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, + const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { + const Triple &TT = STI.getTargetTriple(); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); return new RISCVAsmBackend(OSABI, TT.isArch64Bit()); } |