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authorRoman Divacky <rdivacky@FreeBSD.org>2010-01-15 15:37:28 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-01-15 15:37:28 +0000
commit829000e035f46f2a227a5466e4e427a2f3cc00a9 (patch)
treebe5a687969f682edded4aa6f13594ffd9aa9030e /lib/Target/X86/X86InstrInfo.h
parent1e7804dbd25b8dbf534c850355d70ad215206f4b (diff)
Notes
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.h')
-rw-r--r--lib/Target/X86/X86InstrInfo.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index b83441d89effd..0ab85f4f45b2f 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -448,6 +448,16 @@ public:
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
+ /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
+ /// extension instruction. That is, it's like a copy where it's legal for the
+ /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
+ /// true, then it's expected the pre-extension value is available as a subreg
+ /// of the result register. This also returns the sub-register index in
+ /// SubIdx.
+ virtual bool isCoalescableExtInstr(const MachineInstr &MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SubIdx) const;
+
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
/// stack locations as well. This uses a heuristic so it isn't