summaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/BreakFalseDeps.cpp
diff options
context:
space:
mode:
authorDimitry Andric <dim@FreeBSD.org>2020-07-26 19:36:28 +0000
committerDimitry Andric <dim@FreeBSD.org>2020-07-26 19:36:28 +0000
commitcfca06d7963fa0909f90483b42a6d7d194d01e08 (patch)
tree209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/CodeGen/BreakFalseDeps.cpp
parent706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff)
Notes
Diffstat (limited to 'llvm/lib/CodeGen/BreakFalseDeps.cpp')
-rw-r--r--llvm/lib/CodeGen/BreakFalseDeps.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 9bae9d36add16..b01a264dd97d7 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -106,9 +106,18 @@ FunctionPass *llvm::createBreakFalseDeps() { return new BreakFalseDeps(); }
bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
unsigned Pref) {
+
+ // We can't change tied operands.
+ if (MI->isRegTiedToDefOperand(OpIdx))
+ return false;
+
MachineOperand &MO = MI->getOperand(OpIdx);
assert(MO.isUndef() && "Expected undef machine operand");
+ // We can't change registers that aren't renamable.
+ if (!MO.isRenamable())
+ return false;
+
Register OriginalReg = MO.getReg();
// Update only undef operands that have reg units that are mapped to one root.