diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
| commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
| tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp | |
| parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
Notes
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp index b9c90e69ddb2e..2fedc034d315f 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp @@ -42,7 +42,7 @@ bool InstructionSelector::constrainOperandRegToRegClass( MachineRegisterInfo &MRI = MF.getRegInfo(); return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, - I.getOperand(OpIdx), OpIdx); + I.getOperand(OpIdx)); } bool InstructionSelector::isOperandImmEqual( |