diff options
| author | Attilio Rao <attilio@FreeBSD.org> | 2010-12-08 15:32:54 +0000 |
|---|---|---|
| committer | Attilio Rao <attilio@FreeBSD.org> | 2010-12-08 15:32:54 +0000 |
| commit | cb1f5a37e9e2ed26974e6e55c708178a2d4055a4 (patch) | |
| tree | cffdc42c6e92bea66ca5367aae8950f54dc0ea04 /sys/dev/ichwd | |
| parent | 8d5fa60980e77f0a204432b3a0ab49218e59eca1 (diff) | |
Notes
Diffstat (limited to 'sys/dev/ichwd')
| -rw-r--r-- | sys/dev/ichwd/ichwd.c | 23 | ||||
| -rw-r--r-- | sys/dev/ichwd/ichwd.h | 11 |
2 files changed, 19 insertions, 15 deletions
diff --git a/sys/dev/ichwd/ichwd.c b/sys/dev/ichwd/ichwd.c index 83ce5a72c4a27..c64468aafba20 100644 --- a/sys/dev/ichwd/ichwd.c +++ b/sys/dev/ichwd/ichwd.c @@ -288,30 +288,23 @@ static __inline void ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) { - /* - * If the datasheets are to be believed, the minimum value - * actually varies from chipset to chipset - 4 for ICH5 and 2 for - * all other chipsets. I suspect this is a bug in the ICH5 - * datasheet and that the minimum is uniformly 2, but I'd rather - * err on the side of caution. - */ - if (timeout < 4) - timeout = 4; + if (timeout < TCO_RLD_TMR_MIN) + timeout = TCO_RLD_TMR_MIN; if (sc->ich_version <= 5) { uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); - tmr_val8 &= 0xc0; - if (timeout > 0x3f) - timeout = 0x3f; + tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); + if (timeout > TCO_RLD1_TMR_MAX) + timeout = TCO_RLD1_TMR_MAX; tmr_val8 |= timeout; ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); } else { uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); - tmr_val16 &= 0xfc00; - if (timeout > 0x03ff) - timeout = 0x03ff; + tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); + if (timeout > TCO_RLD2_TMR_MAX) + timeout = TCO_RLD2_TMR_MAX; tmr_val16 |= timeout; ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); } diff --git a/sys/dev/ichwd/ichwd.h b/sys/dev/ichwd/ichwd.h index c0a11414468c2..442460ba550ff 100644 --- a/sys/dev/ichwd/ichwd.h +++ b/sys/dev/ichwd/ichwd.h @@ -199,6 +199,17 @@ struct ichwd_softc { #define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ #define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ +/* + * Masks for the TCO timer value field in TCO_RLD. + * If the datasheets are to be believed, the minimum value actually varies + * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. + * I suspect this is a bug in the ICH5 datasheet and that the minimum is + * uniformly 2, but I'd rather err on the side of caution. + */ +#define TCO_RLD_TMR_MIN 0x0004 +#define TCO_RLD1_TMR_MAX 0x003f +#define TCO_RLD2_TMR_MAX 0x03ff + /* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ #define ICHWD_TICK 600000000 |