2 files changed, 8 insertions, 88 deletions

diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c
index 0cbc2638e9086..b5d8a1513a83a 100644
--- a/sys/dev/msk/if_msk.c
+++ b/sys/dev/msk/if_msk.c
@@ -1357,7 +1357,8 @@ mskc_reset(struct msk_softc *sc)
 	CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
 	/* Set the status list last index. */
 	CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
-	if (HW_FEATURE(sc, HWF_WA_DEV_43_418)) {
+	if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
+	    sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
 		/* WA for dev. #4.3 */
 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
 		/* WA for dev. #4.18 */
@@ -1366,8 +1367,11 @@ mskc_reset(struct msk_softc *sc)
 	} else {
 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
 		CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
-		CSR_WRITE_1(sc, STAT_FIFO_ISR_WM,
-		    HW_FEATURE(sc, HWF_WA_DEV_4109) ? 0x10 : 0x04);
+		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
+		    sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
+			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
+		else
+			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
 		CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
 	}
 	/*
@@ -1639,74 +1643,20 @@ mskc_attach(device_t dev)
 	else
 		sc->msk_bustype = MSK_PCI_BUS;
 
-	/* Get H/W features(bugs). */
 	switch (sc->msk_hw_id) {
 	case CHIP_ID_YUKON_EC:
-		sc->msk_clock = 125;	/* 125 Mhz */
-		if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_42  | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
-			    HWF_WA_DEV_420 | HWF_WA_DEV_423 |
-			    HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
-			    HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
-		} else {
-			/* A2/A3 */
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
-			    HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
-		}
-		break;
 	case CHIP_ID_YUKON_EC_U:
 		sc->msk_clock = 125;	/* 125 Mhz */
-		if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
-			sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_483 |
-			    HWF_WA_DEV_4109;
-		} else if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
-			uint16_t v;
-
-			sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4185;
-			v = CSR_READ_2(sc, Q_ADDR(Q_XA1, Q_WM));
-			if (v == 0)
-				sc->msk_hw_feature |= HWF_WA_DEV_4185CS |
-				    HWF_WA_DEV_4200;
-		}
 		break;
 	case CHIP_ID_YUKON_FE:
 		sc->msk_clock = 100;	/* 100 Mhz */
-		sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
-		    HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
 		break;
 	case CHIP_ID_YUKON_XL:
 		sc->msk_clock = 156;	/* 156 Mhz */
-		switch (sc->msk_hw_rev) {
-		case CHIP_REV_YU_XL_A0:
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
-			    HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
-			    HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
-			break;
-		case CHIP_REV_YU_XL_A1:
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
-			break;
-		case CHIP_REV_YU_XL_A2:
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
-			break;
-		case CHIP_REV_YU_XL_A3:
-			sc->msk_hw_feature =
-			    HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
-			    HWF_WA_DEV_4115;
-		}
 		break;
 	default:
 		sc->msk_clock = 156;	/* 156 Mhz */
-		sc->msk_hw_feature = 0;
+		break;
 	}
 
 	/* Allocate IRQ resources. */
diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h
index 7502adc4edb41..256d148baed41 100644
--- a/sys/dev/msk/if_mskreg.h
+++ b/sys/dev/msk/if_mskreg.h
@@ -2024,35 +2024,6 @@
 /* GPHY address (bits 15..11 of SMI control reg) */
 #define PHY_ADDR_MARV	0
 
-/*-RMV- DWORD 1: Deviations */
-#define HWF_WA_DEV_4200		0x10200000UL	/*-RMV- 4.200 (D3 Blue Screen)*/
-#define HWF_WA_DEV_4185CS	0x10100000UL	/*-RMV- 4.185 (ECU 100 CS cal)*/
-#define HWF_WA_DEV_4185		0x10080000UL	/*-RMV- 4.185 (ECU Tx h check)*/
-#define HWF_WA_DEV_4167		0x10040000UL	/*-RMV- 4.167 (Rx OvSize Hang)*/
-#define HWF_WA_DEV_4152		0x10020000UL	/*-RMV- 4.152 (RSS issue) */
-#define HWF_WA_DEV_4115		0x10010000UL	/*-RMV- 4.115 (Rx MAC FIFO) */
-#define HWF_WA_DEV_4109		0x10008000UL	/*-RMV- 4.109 (BIU hang) */
-#define HWF_WA_DEV_483		0x10004000UL	/*-RMV- 4.83 (Rx TCP wrong) */
-#define HWF_WA_DEV_479		0x10002000UL	/*-RMV- 4.79 (Rx BMU hang II) */
-#define HWF_WA_DEV_472		0x10001000UL	/*-RMV- 4.72 (GPHY2 MDC clk) */
-#define HWF_WA_DEV_463		0x10000800UL	/*-RMV- 4.63 (Rx BMU hang I) */
-#define HWF_WA_DEV_427		0x10000400UL	/*-RMV- 4.27 (Tx Done Rep) */
-#define HWF_WA_DEV_42		0x10000200UL	/*-RMV- 4.2 (pref unit burst) */
-#define HWF_WA_DEV_46		0x10000100UL	/*-RMV- 4.6 (CPU crash II) */
-#define HWF_WA_DEV_43_418	0x10000080UL	/*-RMV- 4.3 & 4.18 (PCI unexp */
-/*-RMV- compl&Stat BMU deadl) */
-#define HWF_WA_DEV_420		0x10000040UL	/*-RMV- 4.20 (Status BMU ov) */
-#define HWF_WA_DEV_423		0x10000020UL	/*-RMV- 4.23 (TCP Segm Hang) */
-#define HWF_WA_DEV_424		0x10000010UL	/*-RMV- 4.24 (MAC reg overwr) */
-#define HWF_WA_DEV_425		0x10000008UL	/*-RMV- 4.25 (Magic packet */
-/*-RMV- with odd offset) */
-#define HWF_WA_DEV_428		0x10000004UL	/*-RMV- 4.28 (Poll-U &BigEndi)*/
-#define HWF_WA_FIFO_FLUSH_YLA0	0x10000002UL	/*-RMV- dis Rx GMAC FIFO Flush*/
-
-#define HW_FEATURE(sc, f)	\
-	(((((sc)->msk_hw_feature & 0x30000000) >> 28) & ((f) & 0x0fffffff)) != 0)
-
-
 #define MSK_ADDR_LO(x)	((uint64_t) (x) & 0xffffffffUL)
 #define MSK_ADDR_HI(x)	((uint64_t) (x) >> 32)
 
@@ -2335,7 +2306,6 @@ struct msk_softc {
 	uint32_t		msk_intrmask;
 	uint32_t		msk_intrhwemask;
 	int			msk_suspended;
-	int			msk_hw_feature;
 	int			msk_clock;
 	int			msk_marvell_phy;
 	int			msk_msi;