diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-07-13 19:25:18 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-07-13 19:25:18 +0000 |
| commit | ca089b24d48ef6fa8da2d0bb8c25bb802c4a95c0 (patch) | |
| tree | 3a28a772df9b17aef34f49e3c727965ad28c0c93 /test/CodeGen/AMDGPU/select.f16.ll | |
| parent | 9df3605dea17e84f8183581f6103bd0c79e2a606 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/AMDGPU/select.f16.ll')
| -rw-r--r-- | test/CodeGen/AMDGPU/select.f16.ll | 63 |
1 files changed, 37 insertions, 26 deletions
diff --git a/test/CodeGen/AMDGPU/select.f16.ll b/test/CodeGen/AMDGPU/select.f16.ll index 92ee2eb7f403f..e79ce3af0cf9d 100644 --- a/test/CodeGen/AMDGPU/select.f16.ll +++ b/test/CodeGen/AMDGPU/select.f16.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; GCN-LABEL: {{^}}select_f16: ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] @@ -104,8 +104,8 @@ entry: ; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[D_F32]], vcc ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] -; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] ; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x3800{{$}} +; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] ; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[C_F16]], v[[D_F16]], vcc ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm @@ -134,8 +134,8 @@ entry: ; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]] ; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], 0.5, v[[C_F32]] ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] -; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] ; VI: v_mov_b32_e32 v[[D_F16:[0-9]+]], 0x3800{{$}} +; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]] ; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm @@ -159,16 +159,16 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI: v_cmp_lt_f32_e64 ; SI: v_cmp_lt_f32_e32 ; SI: v_cndmask_b32_e32 -; SI: v_cndmask_b32_e64 +; SI: v_cmp_lt_f32_e32 +; SI: v_cndmask_b32_e32 ; SI: v_cvt_f16_f32_e32 ; SI: v_cvt_f16_f32_e32 -; VI: v_cmp_lt_f16_e64 ; VI: v_cmp_lt_f16_e32 -; VI: v_cndmask_b32_e64 +; VI: v_cndmask_b32_e32 +; VI: v_cmp_lt_f16_e32 ; VI: v_cndmask_b32_e32 ; GCN: s_endpgm @@ -196,13 +196,17 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI-DAG: v_cmp_gt_f32_e64 -; SI-DAG: v_cmp_lt_f32_e32 vcc, 0.5 -; VI: v_cmp_lt_f16_e32 -; VI: v_cmp_gt_f16_e64 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e64 +; SI: v_cmp_lt_f32_e32 vcc, 0.5 +; SI: v_cndmask_b32_e32 +; SI: v_cmp_gt_f32_e32 +; SI: v_cndmask_b32_e32 + +; VI: v_cmp_lt_f16_e32 +; VI: v_cndmask_b32_e32 +; VI: v_cmp_gt_f16_e32 +; VI: v_cndmask_b32_e32 + ; SI: v_cvt_f16_f32_e32 ; SI: v_cvt_f16_f32_e32 ; GCN: s_endpgm @@ -228,13 +232,16 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI-DAG: v_cmp_lt_f32_e64 -; SI-DAG: v_cmp_gt_f32_e32 vcc, 0.5 -; VI: v_cmp_gt_f16_e32 -; VI: v_cmp_lt_f16_e64 -; GCN: v_cndmask_b32_e32 -; GCN: v_cndmask_b32_e64 +; SI: v_cmp_gt_f32_e32 vcc, 0.5 +; SI: v_cndmask_b32_e32 +; SI: v_cmp_lt_f32_e32 +; SI: v_cndmask_b32_e32 + +; VI: v_cmp_gt_f16_e32 +; VI: v_cndmask_b32_e32 +; VI: v_cmp_lt_f16_e32 +; VI: v_cndmask_b32_e32 ; SI: v_cvt_f16_f32_e32 ; SI: v_cvt_f16_f32_e32 @@ -263,8 +270,8 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cmp_nlt_f32_e32 -; SI: v_cmp_nlt_f32_e64 -; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e32 +; SI: v_cmp_nlt_f32_e32 ; SI: v_cndmask_b32_e32 ; VI: v_cmp_nlt_f16_e32 @@ -298,13 +305,17 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI: v_cmp_lt_f32_e64 + ; SI: v_cmp_lt_f32_e32 +; SI: v_cndmask_b32 +; SI: v_cmp_lt_f32_e32 +; SI: v_cndmask_b32 ; VI: v_cmp_lt_f16_e32 -; VI: v_cmp_lt_f16_e64 -; GCN: v_cndmask_b32 -; GCN: v_cndmask_b32 +; VI: v_cndmask_b32 +; VI: v_cmp_lt_f16_e32 +; VI: v_cndmask_b32 + ; SI: v_cvt_f16_f32_e32 ; SI: v_cvt_f16_f32_e32 ; GCN: s_endpgm |