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authorDimitry Andric <dim@FreeBSD.org>2011-10-20 21:10:27 +0000
committerDimitry Andric <dim@FreeBSD.org>2011-10-20 21:10:27 +0000
commit30815c536baacc07e925f0aef23a5395883173dc (patch)
tree2cbcf22585e99f8a87d12d5ff94f392c0d266819 /test/CodeGen/ARM/shifter_operand.ll
parent411bd29eea3c360d5b48a18a17b5e87f5671af0e (diff)
Diffstat (limited to 'test/CodeGen/ARM/shifter_operand.ll')
-rw-r--r--test/CodeGen/ARM/shifter_operand.ll9
1 files changed, 4 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll
index f0e2d102610de..964cef084f177 100644
--- a/test/CodeGen/ARM/shifter_operand.ll
+++ b/test/CodeGen/ARM/shifter_operand.ll
@@ -54,13 +54,12 @@ declare i8* @malloc(...)
define fastcc void @test4(i16 %addr) nounwind {
entry:
; A8: test4:
-; A8: ldr r2, [r0, r1, lsl #2]
-; A8: str r2, [r0, r1, lsl #2]
+; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A8: str [[REG]], [r0, r1, lsl #2]
; A9: test4:
-; A9: add r0, r0, r{{[0-9]+}}, lsl #2
-; A9: ldr r1, [r0]
-; A9: str r1, [r0]
+; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A9: str [[REG]], [r0, r1, lsl #2]
%0 = tail call i8* (...)* @malloc(i32 undef) nounwind
%1 = bitcast i8* %0 to i32*
%2 = sext i16 %addr to i32