vendor/llvm/llvm-trunk-r305575

11 files changed, 445 insertions, 579 deletions

diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 2039c1f57f17e..f402cb78bd189 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -109,7 +109,7 @@ entry:
   %tmp = load atomic i64, i64* %mem acquire, align 64
 ; CHECK-NOT: ldarx
 ; CHECK: ld [[VAL:r[0-9]+]]
-; CHECK: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
+; CHECK: cmpd [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
 ; CHECK: bne- [[CR]], .+4
 ; CHECK: isync
   ret i64 %tmp
diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll
index a92ca813af857..77825c608a3bb 100644
--- a/test/CodeGen/PowerPC/atomics-constant.ll
+++ b/test/CodeGen/PowerPC/atomics-constant.ll
@@ -11,7 +11,7 @@ define i64 @foo() {
 ; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
-; CHECK-NEXT:    cmpw 7, 4, 4
+; CHECK-NEXT:    cmpd 7, 4, 4
 ; CHECK-NEXT:    ld 3, 0(3)
 ; CHECK-NEXT:    bne- 7, .+4
 ; CHECK-NEXT:    isync
diff --git a/test/CodeGen/PowerPC/atomics-regression.ll b/test/CodeGen/PowerPC/atomics-regression.ll
index 054d3a4146b03..d57b3a203791c 100644
--- a/test/CodeGen/PowerPC/atomics-regression.ll
+++ b/test/CodeGen/PowerPC/atomics-regression.ll
@@ -23,7 +23,7 @@ define i8 @test2(i8* %ptr) {
 ; PPC64LE-LABEL: test2:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lbz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -37,7 +37,7 @@ define i8 @test3(i8* %ptr) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lbz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -67,7 +67,7 @@ define i16 @test6(i16* %ptr) {
 ; PPC64LE-LABEL: test6:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lhz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -81,7 +81,7 @@ define i16 @test7(i16* %ptr) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lhz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -111,7 +111,7 @@ define i32 @test10(i32* %ptr) {
 ; PPC64LE-LABEL: test10:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -125,7 +125,7 @@ define i32 @test11(i32* %ptr) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -155,7 +155,7 @@ define i64 @test14(i64* %ptr) {
 ; PPC64LE-LABEL: test14:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    ld 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -169,7 +169,7 @@ define i64 @test15(i64* %ptr) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    ld 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
@@ -9566,7 +9566,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering0:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 4, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 4, 4
+; PPC64LE-NEXT:    cmpd 7, 4, 4
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    lwz 3, 0(3)
@@ -9583,7 +9583,7 @@ define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering1:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    stw 4, 0(5)
diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll
new file mode 100644
index 0000000000000..ecdfcba6e3b7a
--- /dev/null
+++ b/test/CodeGen/PowerPC/licm-tocReg.ll
@@ -0,0 +1,110 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; The instructions ADDIStocHA/LDtocL are used to calculate the address of 
+; globals. The ones that are in bb.3.if.end could not be hoisted by Machine 
+; LICM due to BCTRL_LDinto_toc in bb2.if.then.  This call causes the compiler
+; to insert a save TOC to stack before the call and load into X2 to restore TOC
+; after. By communicating to Machine LICM that X2 is guaranteed to have the 
+; same value before and after BCTRL_LDinto_toc, these instructions can be
+; hoisted out of bb.3.if.end to outside of the loop.
+
+; Pre Machine LICM MIR
+;
+;body:             
+;  bb.0.entry:
+;    successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000)
+;    liveins: %x3
+;  
+;    %4 = COPY %x3
+;    %5 = ADDIStocHA %x2, @ga
+;    %6 = LDtocL @ga, killed %5 :: (load 8 from got)
+;    %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
+;    %8 = ADDIStocHA %x2, @gb
+;    %9 = LDtocL @gb, killed %8 :: (load 8 from got)
+;    %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
+;    %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
+;    %11 = CMPW killed %7, killed %10
+;    BCC 44, killed %11, %bb.2.if.then
+;    B %bb.3.if.end
+;  
+;  bb.2.if.then:
+;    %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
+;    ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1
+;    %20 = COPY %x2
+;    STD %20, 24, %x1 :: (store 8 into stack + 24)
+;    %21 = EXTSW_32_64 %1
+;    %x3 = COPY %21
+;    %x12 = COPY %4
+;    MTCTR8 %4, implicit-def %ctr8
+;    BCTRL8_LDinto_toc 24, %x1, csr_svr464_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3
+;    ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1
+;    %22 = COPY %x3
+;    %x3 = COPY %22
+;    BLR8 implicit %lr8, implicit %rm, implicit %x3
+;  
+;  bb.3.if.end:
+;    successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000)
+;  
+;    %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
+;    %12 = ADDI %2, 1
+;    %13 = ADDIStocHA %x2, @ga
+;    %14 = LDtocL @ga, killed %13 :: (load 8 from got)
+;    STW killed %12, 0, %14 :: (volatile store 4 into @ga)
+;    %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
+;    %16 = ADDIStocHA %x2, @gb
+;    %17 = LDtocL @gb, killed %16 :: (load 8 from got)
+;    %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
+;    %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
+;    %19 = CMPW killed %15, killed %18
+;    BCC 44, killed %19, %bb.2.if.then
+;    B %bb.3.if.end
+
+@ga = external global i32, align 4
+@gb = external global i32, align 4
+
+; Function Attrs: nounwind
+define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 {
+; CHECK-LABEL: test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 4, .LC0@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC1@toc@l(5)
+; CHECK-NEXT:    lwz 6, 0(4)
+; CHECK-NEXT:    lwz 5, 0(5)
+; CHECK-NEXT:    cmpw 6, 5
+; CHECK-NEXT:    lwz 5, 0(4)
+; CHECK-NEXT:    mr 4, 3
+; CHECK-NEXT:    bgt 0, .LBB0_3
+; CHECK-NEXT:  # BB#1:
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    addis 6, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 6, .LC1@toc@l(6)
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC0@toc@ha
+; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC1@toc@ha
+; CHECK:    blr
+entry:
+  %0 = load volatile i32, i32* @ga, align 4
+  %1 = load volatile i32, i32* @gb, align 4
+  %cmp1 = icmp sgt i32 %0, %1
+  %2 = load volatile i32, i32* @ga, align 4
+  br i1 %cmp1, label %if.then, label %if.end
+
+if.then:                                          ; preds = %if.end, %entry
+  %.lcssa = phi i32 [ %2, %entry ], [ %6, %if.end ]
+  %call = tail call signext i32 %FP(i32 signext %.lcssa) #1
+  ret i32 %call
+
+if.end:                                           ; preds = %entry, %if.end
+  %3 = phi i32 [ %6, %if.end ], [ %2, %entry ]
+  %inc = add nsw i32 %3, 1
+  store volatile i32 %inc, i32* @ga, align 4
+  %4 = load volatile i32, i32* @ga, align 4
+  %5 = load volatile i32, i32* @gb, align 4
+  %cmp = icmp sgt i32 %4, %5
+  %6 = load volatile i32, i32* @ga, align 4
+  br i1 %cmp, label %if.then, label %if.end
+}
diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
index 5a507e9ff678c..df021c20ea86e 100644
--- a/test/CodeGen/PowerPC/logic-ops-on-compares.ll
+++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
@@ -40,8 +40,8 @@ return:                                           ; preds = %if.end, %if.then
   ret i32 %retval.0
 }
 
-define void @neg_truncate_i32_eq(i32 *%ptr) {
-; CHECK-LABEL: neg_truncate_i32_eq:
+define void @neg_truncate_i32(i32 *%ptr) {
+; CHECK-LABEL: neg_truncate_i32:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
@@ -66,8 +66,8 @@ if.end29:                                         ; preds = %if.else
 }
 
 ; Function Attrs: nounwind
-define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) {
-; CHECK-LABEL: logic_eq_64:
+define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: logic_ne_64:
 ; CHECK:    xor r7, r3, r4
 ; CHECK-NEXT:    li r6, 55
 ; CHECK-NEXT:    xor r5, r5, r6
@@ -99,8 +99,8 @@ return:                                           ; preds = %if.end, %if.then
   ret i64 %retval.0
 }
 
-define void @neg_truncate_i64_eq(i64 *%ptr) {
-; CHECK-LABEL: neg_truncate_i64_eq:
+define void @neg_truncate_i64(i64 *%ptr) {
+; CHECK-LABEL: neg_truncate_i64:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
@@ -124,67 +124,6 @@ if.end29:                                         ; preds = %if.else
 
 }
 
-; Function Attrs: nounwind
-define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
-; CHECK-LABEL: logic_ne_64:
-; CHECK:    xor r7, r3, r4
-; CHECK-NEXT:    li r6, 55
-; CHECK-NEXT:    addic r8, r7, -1
-; CHECK-NEXT:    xor r5, r5, r6
-; CHECK-NEXT:    subfe r7, r8, r7
-; CHECK-NEXT:    cntlzd r5, r5
-; CHECK-NEXT:    addic r12, r4, -1
-; CHECK-NEXT:    rldicl r5, r5, 58, 63
-; CHECK-NEXT:    subfe r6, r12, r4
-; CHECK-NEXT:    and r6, r7, r6
-; CHECK-NEXT:    or. r5, r6, r5
-; CHECK-NEXT:    bc 4, 1
-entry:
-  %tobool = icmp ne i64 %a, %b
-  %tobool1 = icmp ne i64 %b, 0
-  %or.cond = and i1 %tobool, %tobool1
-  %tobool3 = icmp eq i64 %c, 55
-  %or.cond5 = or i1 %or.cond, %tobool3
-  br i1 %or.cond5, label %if.end, label %if.then
-
-if.then:                                          ; preds = %entry
-  %call = tail call i64 @foo64(i64 %a) #2
-  br label %return
-
-if.end:                                           ; preds = %entry
-  %call4 = tail call i64 @bar64(i64 %b) #2
-  br label %return
-
-return:                                           ; preds = %if.end, %if.then
-  %retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
-  ret i64 %retval.0
-}
-
-define void @neg_truncate_i64_ne(i64 *%ptr) {
-; CHECK-LABEL: neg_truncate_i64_ne:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    andi. r3, r3, 1
-; CHECK-NEXT:    bclr 12, 1, 0
-; CHECK-NEXT:  # BB#1: # %if.end29.thread136
-; CHECK-NEXT:  .LBB5_2: # %if.end29
-entry:
-  %0 = load i64, i64* %ptr, align 4
-  %rem17127 = and i64 %0, 1
-  %cmp18 = icmp ne i64 %rem17127, 0
-  br label %if.else
-
-if.else:                                          ; preds = %entry
-  br i1 %cmp18, label %if.end29, label %if.end29.thread136
-
-if.end29.thread136:                               ; preds = %if.else
-  unreachable
-
-if.end29:                                         ; preds = %if.else
-  ret void
-
-}
-
 declare signext i32 @foo(i32 signext)
 declare signext i32 @bar(i32 signext)
 declare i64 @foo64(i64)
diff --git a/test/CodeGen/PowerPC/ppc64-P9-mod.ll b/test/CodeGen/PowerPC/ppc64-P9-mod.ll
new file mode 100644
index 0000000000000..46e347becbb67
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-P9-mod.ll
@@ -0,0 +1,263 @@
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not mod[us][wd]
+
+@mod_resultsw = common local_unnamed_addr global i32 0, align 4
+@mod_resultud = common local_unnamed_addr global i64 0, align 8
+@div_resultsw = common local_unnamed_addr global i32 0, align 4
+@mod_resultuw = common local_unnamed_addr global i32 0, align 4
+@div_resultuw = common local_unnamed_addr global i32 0, align 4
+@div_resultsd = common local_unnamed_addr global i64 0, align 8
+@mod_resultsd = common local_unnamed_addr global i64 0, align 8
+@div_resultud = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind
+define void @modulo_sw(i32 signext %a, i32 signext %b) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, %b
+  store i32 %rem, i32* @mod_resultsw, align 4
+  ret void
+; CHECK-LABEL: modulo_sw
+; CHECK: modsw {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_sw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i32 @modulo_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr {
+entry:
+  %rem = urem i32 %a, %b
+  ret i32 %rem
+; CHECK-LABEL: modulo_uw
+; CHECK: moduw {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_uw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @modulo_sd(i64 %a, i64 %b) local_unnamed_addr {
+entry:
+  %rem = srem i64 %a, %b
+  ret i64 %rem
+; CHECK-LABEL: modulo_sd
+; CHECK: modsd {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_sd
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_ud(i64 %a, i64 %b) local_unnamed_addr {
+entry:
+  %rem = urem i64 %a, %b
+  store i64 %rem, i64* @mod_resultud, align 8
+  ret void
+; CHECK-LABEL: modulo_ud
+; CHECK: modud {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_ud
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_div_sw(i32 signext %a, i32 signext %b) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, %b
+  store i32 %rem, i32* @mod_resultsw, align 4
+  %div = sdiv i32 %a, %b
+  store i32 %div, i32* @div_resultsw, align 4
+  ret void
+; CHECK-LABEL: modulo_div_sw
+; CHECK-NOT: modsw
+; CHECK: div
+; CHECK-NOT: modsw
+; CHECK: mull
+; CHECK-NOT: modsw
+; CHECK: sub
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_div_sw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_div_abc_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, %c
+  store i32 %rem, i32* @mod_resultsw, align 4
+  %div = sdiv i32 %b, %c
+  store i32 %div, i32* @div_resultsw, align 4
+  ret void
+; CHECK-LABEL: modulo_div_abc_sw
+; CHECK: modsw {{[0-9]+}}, 3, 5
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_div_abc_sw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_div_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr {
+entry:
+  %rem = urem i32 %a, %b
+  store i32 %rem, i32* @mod_resultuw, align 4
+  %div = udiv i32 %a, %b
+  store i32 %div, i32* @div_resultuw, align 4
+  ret void
+; CHECK-LABEL: modulo_div_uw
+; CHECK-NOT: modsw
+; CHECK: div
+; CHECK-NOT: modsw
+; CHECK: mull
+; CHECK-NOT: modsw
+; CHECK: sub
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_div_uw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_div_swuw(i32 signext %a, i32 signext %b) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, %b
+  store i32 %rem, i32* @mod_resultsw, align 4
+  %div = udiv i32 %a, %b
+  store i32 %div, i32* @div_resultsw, align 4
+  ret void
+; CHECK-LABEL: modulo_div_swuw
+; CHECK: modsw {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_div_swuw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_div_udsd(i64 %a, i64 %b) local_unnamed_addr {
+entry:
+  %rem = urem i64 %a, %b
+  store i64 %rem, i64* @mod_resultud, align 8
+  %div = sdiv i64 %a, %b
+  store i64 %div, i64* @div_resultsd, align 8
+  ret void
+; CHECK-LABEL: modulo_div_udsd
+; CHECK: modud {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_div_udsd
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @modulo_const32_sw(i32 signext %a) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, 32
+  store i32 %rem, i32* @mod_resultsw, align 4
+  ret void
+; CHECK-LABEL: modulo_const32_sw
+; CHECK-NOT: modsw
+; CHECK: srawi
+; CHECK-NOT: modsw
+; CHECK: addze
+; CHECK-NOT: modsw
+; CHECK: slwi
+; CHECK-NOT: modsw
+; CHECK: subf
+; CHECK-NOT: modsw
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_const32_sw
+; CHECK-PWR8: srawi
+; CHECK-PWR8: addze
+; CHECK-PWR8: slwi
+; CHECK-PWR8: subf
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @modulo_const3_sw(i32 signext %a) local_unnamed_addr {
+entry:
+  %rem = srem i32 %a, 3
+  ret i32 %rem
+; CHECK-LABEL: modulo_const3_sw
+; CHECK-NOT: modsw
+; CHECK: mull
+; CHECK-NOT: modsw
+; CHECK: sub
+; CHECK-NOT: modsw
+; CHECK: blr
+; CHECK-PWR8-LABEL: modulo_const3_sw
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @const2_modulo_sw(i32 signext %a) local_unnamed_addr {
+entry:
+  %rem = srem i32 2, %a
+  ret i32 %rem
+; CHECK-LABEL: const2_modulo_sw
+; CHECK: modsw {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: blr
+; CHECK-PWR8-LABEL: const2_modulo_sw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+; FIXME On power 9 this test will still produce modsw because the divide is in
+; a different block than the remainder. Due to the nature of the SDAG we cannot
+; see the div in the other block.
+define void @blocks_modulo_div_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr {
+entry:
+  %div = sdiv i32 %a, %b
+  store i32 %div, i32* @div_resultsw, align 4
+  %cmp = icmp sgt i32 %c, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %rem = srem i32 %a, %b
+  store i32 %rem, i32* @mod_resultsw, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+; CHECK-LABEL: blocks_modulo_div_sw
+; CHECK: div
+; CHECK: modsw {{[0-9]+}}, 3, 4
+; CHECK: blr
+; CHECK-PWR8-LABEL: blocks_modulo_div_sw
+; CHECK-PWR8: div
+; CHECK-PWR8: mull
+; CHECK-PWR8: sub
+; CHECK-PWR8: blr
+}
+
+
diff --git a/test/CodeGen/PowerPC/testComparesinesll.ll b/test/CodeGen/PowerPC/testComparesinesll.ll
deleted file mode 100644
index 9e93694558579..0000000000000
--- a/test/CodeGen/PowerPC/testComparesinesll.ll
+++ /dev/null
@@ -1,125 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-
-@glob = common local_unnamed_addr global i64 0, align 8
-
-define signext i32 @test_inesll(i64 %a, i64 %b) {
-; CHECK-LABEL: test_inesll:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
-}
-
-define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
-; CHECK-LABEL: test_inesll_sext:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %sub = sext i1 %cmp to i32
-  ret i32 %sub
-}
-
-define signext i32 @test_inesll_z(i64 %a) {
-; CHECK-LABEL: test_inesll_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
-}
-
-define signext i32 @test_inesll_sext_z(i64 %a) {
-; CHECK-LABEL: test_inesll_sext_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %sub = sext i1 %cmp to i32
-  ret i32 %sub
-}
-
-define void @test_inesll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_inesll_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_inesll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_inesll_sext_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_inesll_z_store(i64 %a) {
-; CHECK-LABEL: test_inesll_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_inesll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_inesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
diff --git a/test/CodeGen/PowerPC/testComparesineull.ll b/test/CodeGen/PowerPC/testComparesineull.ll
deleted file mode 100644
index 7f0fed15157c5..0000000000000
--- a/test/CodeGen/PowerPC/testComparesineull.ll
+++ /dev/null
@@ -1,125 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-
-@glob = common local_unnamed_addr global i64 0, align 8
-
-define signext i32 @test_ineull(i64 %a, i64 %b) {
-; CHECK-LABEL: test_ineull:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
-}
-
-define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
-; CHECK-LABEL: test_ineull_sext:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %sub = sext i1 %cmp to i32
-  ret i32 %sub
-}
-
-define signext i32 @test_ineull_z(i64 %a) {
-; CHECK-LABEL: test_ineull_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
-}
-
-define signext i32 @test_ineull_sext_z(i64 %a) {
-; CHECK-LABEL: test_ineull_sext_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %sub = sext i1 %cmp to i32
-  ret i32 %sub
-}
-
-define void @test_ineull_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_ineull_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_ineull_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_ineull_sext_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_ineull_z_store(i64 %a) {
-; CHECK-LABEL: test_ineull_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_ineull_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_ineull_sext_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
diff --git a/test/CodeGen/PowerPC/testComparesllnesll.ll b/test/CodeGen/PowerPC/testComparesllnesll.ll
deleted file mode 100644
index d87ff55739fc8..0000000000000
--- a/test/CodeGen/PowerPC/testComparesllnesll.ll
+++ /dev/null
@@ -1,125 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-
-@glob = common local_unnamed_addr global i64 0, align 8
-
-define i64 @test_llnesll(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llnesll:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llnesll_sext(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llnesll_sext:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llnesll_z(i64 %a) {
-; CHECK-LABEL: test_llnesll_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llnesll_sext_z(i64 %a) {
-; CHECK-LABEL: test_llnesll_sext_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define void @test_llnesll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llnesll_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llnesll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llnesll_sext_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llnesll_z_store(i64 %a) {
-; CHECK-LABEL: test_llnesll_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llnesll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_llnesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
diff --git a/test/CodeGen/PowerPC/testComparesllneull.ll b/test/CodeGen/PowerPC/testComparesllneull.ll
deleted file mode 100644
index 7309d5899068b..0000000000000
--- a/test/CodeGen/PowerPC/testComparesllneull.ll
+++ /dev/null
@@ -1,125 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-
-@glob = common local_unnamed_addr global i64 0, align 8
-
-define i64 @test_llneull(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llneull:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llneull_sext(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llneull_sext:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llneull_z(i64 %a) {
-; CHECK-LABEL: test_llneull_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addic r4, r3, -1
-; CHECK-NEXT:    subfe r3, r4, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define i64 @test_llneull_sext_z(i64 %a) {
-; CHECK-LABEL: test_llneull_sext_z:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-define void @test_llneull_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llneull_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llneull_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llneull_sext_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    xor r3, r3, r4
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, %b
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llneull_z_store(i64 %a) {
-; CHECK-LABEL: test_llneull_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    addic r5, r3, -1
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r5, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = zext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
-
-define void @test_llneull_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_llneull_sext_z_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    subfic r3, r3, 0
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    subfe r3, r3, r3
-; CHECK-NEXT:    std r3, 0(r4)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp ne i64 %a, 0
-  %conv1 = sext i1 %cmp to i64
-  store i64 %conv1, i64* @glob, align 8
-  ret void
-}
diff --git a/test/CodeGen/PowerPC/vec_revb.ll b/test/CodeGen/PowerPC/vec_revb.ll
new file mode 100644
index 0000000000000..c09164bae13eb
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_revb.ll
@@ -0,0 +1,54 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+
+define <8 x i16> @testXXBRH(<8 x i16> %a) {
+; CHECK-LABEL: testXXBRH:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xxbrh 34, 34
+; CHECK-NEXT:    blr
+
+entry:
+  %0 = bitcast <8 x i16> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+  %2 = bitcast <16 x i8> %1 to <8 x i16>
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @testXXBRW(<4 x i32> %a) {
+; CHECK-LABEL: testXXBRW:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xxbrw 34, 34
+; CHECK-NEXT:    blr
+
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+}
+
+define <2 x double> @testXXBRD(<2 x double> %a) {
+; CHECK-LABEL: testXXBRD:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xxbrd 34, 34
+; CHECK-NEXT:    blr
+
+entry:
+  %0 = bitcast <2 x double> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+  %2 = bitcast <16 x i8> %1 to <2 x double>
+  ret <2 x double> %2
+}
+
+define <1 x i128> @testXXBRQ(<1 x i128> %a) {
+; CHECK-LABEL: testXXBRQ:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xxbrq 34, 34
+; CHECK-NEXT:    blr
+
+entry:
+  %0 = bitcast <1 x i128> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  %2 = bitcast <16 x i8> %1 to <1 x i128>
+  ret <1 x i128> %2
+}