vendor/llvm/llvm-r72732

10 files changed, 144 insertions, 0 deletions

diff --git a/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll b/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
new file mode 100644
index 0000000000000..15af046618f6e
--- /dev/null
+++ b/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=sparc
+
+define void @execute_list() {
+        %tmp.33.i = fdiv float 0.000000e+00, 0.000000e+00               ; <float> [#uses=1]
+        %tmp.37.i = mul float 0.000000e+00, %tmp.33.i           ; <float> [#uses=1]
+        %tmp.42.i = add float %tmp.37.i, 0.000000e+00           ; <float> [#uses=1]
+        call void @gl_EvalCoord1f( float %tmp.42.i )
+        ret void
+}
+
+declare void @gl_EvalCoord1f(float)
+
diff --git a/test/CodeGen/SPARC/2007-05-09-JumpTables.ll b/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
new file mode 100644
index 0000000000000..a014acefa904a
--- /dev/null
+++ b/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
@@ -0,0 +1,30 @@
+; RUN: llvm-as < %s | llc -march=sparc
+
+; We cannot emit jump tables on Sparc, but we should correctly handle this case.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+
+define i32 @foo(i32 %f) {
+entry:
+	switch i32 %f, label %bb14 [
+		 i32 0, label %UnifiedReturnBlock
+		 i32 1, label %bb4
+		 i32 2, label %bb7
+		 i32 3, label %bb10
+	]
+
+bb4:		; preds = %entry
+	ret i32 2
+
+bb7:		; preds = %entry
+	ret i32 5
+
+bb10:		; preds = %entry
+	ret i32 9
+
+bb14:		; preds = %entry
+	ret i32 0
+
+UnifiedReturnBlock:		; preds = %entry
+	ret i32 1
+}
diff --git a/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll b/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
new file mode 100644
index 0000000000000..d1ca44dbb112f
--- /dev/null
+++ b/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -march=sparc
+; PR1540
+
+declare float @sinf(float)
+declare double @sin(double)
+define double @test_sin(float %F) {
+        %G = call float @sinf( float %F )               ; <float> [#uses=1]
+        %H = fpext float %G to double           ; <double> [#uses=1]
+        %I = call double @sin( double %H )              ; <double> [#uses=1]
+        ret double %I
+}
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
new file mode 100644
index 0000000000000..f9f4c21fe1eac
--- /dev/null
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=sparc
+; PR 1557
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+@llvm.global_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @set_fast_math } ]		; <[1 x { i32, void ()* }]*> [#uses=0]
+
+define internal void @set_fast_math() nounwind {
+entry:
+	%fsr = alloca i32		; <i32*> [#uses=4]
+	call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
+	%0 = load i32* %fsr, align 4		; <i32> [#uses=1]
+	%1 = or i32 %0, 4194304		; <i32> [#uses=1]
+	store i32 %1, i32* %fsr, align 4
+	call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
+	ret void
+}
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
new file mode 100644
index 0000000000000..aaa7bde683836
--- /dev/null
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=sparc
+; PR 1557
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+module asm "\09.section\09\22.ctors\22,#alloc,#write"
+module asm "\09.section\09\22.dtors\22,#alloc,#write"
+
+define void @frame_dummy() nounwind {
+entry:
+	%asmtmp = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind		; <void (i8*)*> [#uses=0]
+	unreachable
+}
+
+declare void @_Jv_RegisterClasses(i8*)
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
new file mode 100644
index 0000000000000..5c3e07543b9da
--- /dev/null
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc -march=sparc
+
+define i32 @test(i32 %X) {
+	%tmp.1 = add i32 %X, 1
+	ret i32 %tmp.1
+}
diff --git a/test/CodeGen/SPARC/ctpop.ll b/test/CodeGen/SPARC/ctpop.ll
new file mode 100644
index 0000000000000..d603baa465dee
--- /dev/null
+++ b/test/CodeGen/SPARC/ctpop.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | \
+; RUN:   llc -march=sparc -mattr=v9 -enable-sparc-v9-insts
+; RUN: llvm-as < %s | llc -march=sparc -mattr=-v9 | \
+; RUN:   not grep popc
+; RUN: llvm-as < %s | \
+; RUN:   llc -march=sparc -mattr=v9 -enable-sparc-v9-insts | grep popc
+
+declare i32 @llvm.ctpop.i32(i32)
+
+define i32 @test(i32 %X) {
+        %Y = call i32 @llvm.ctpop.i32( i32 %X )         ; <i32> [#uses=1]
+        ret i32 %Y
+}
+
diff --git a/test/CodeGen/SPARC/dg.exp b/test/CodeGen/SPARC/dg.exp
new file mode 100644
index 0000000000000..6c0a9975fe414
--- /dev/null
+++ b/test/CodeGen/SPARC/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target Sparc] } {
+  RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/SPARC/private.ll b/test/CodeGen/SPARC/private.ll
new file mode 100644
index 0000000000000..a9850b7def463
--- /dev/null
+++ b/test/CodeGen/SPARC/private.ll
@@ -0,0 +1,21 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llvm-as < %s | llc  -march=sparc > %t
+; RUN: grep .foo: %t
+; RUN: grep call.*\.foo %t
+; RUN: grep .baz: %t
+; RUN: grep ld.*\.baz %t
+
+declare void @foo()
+
+define private void @foo() {
+        ret void
+}
+
+@baz = private global i32 4;
+
+define i32 @bar() {
+        call void @foo()
+	%1 = load i32* @baz, align 4
+        ret i32 %1
+}
diff --git a/test/CodeGen/SPARC/xnor.ll b/test/CodeGen/SPARC/xnor.ll
new file mode 100644
index 0000000000000..9d8994c006132
--- /dev/null
+++ b/test/CodeGen/SPARC/xnor.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=sparc | \
+; RUN:   grep xnor | count 2
+
+define i32 @test1(i32 %X, i32 %Y) {
+        %A = xor i32 %X, %Y             ; <i32> [#uses=1]
+        %B = xor i32 %A, -1             ; <i32> [#uses=1]
+        ret i32 %B
+}
+
+define i32 @test2(i32 %X, i32 %Y) {
+        %A = xor i32 %X, -1             ; <i32> [#uses=1]
+        %B = xor i32 %A, %Y             ; <i32> [#uses=1]
+        ret i32 %B
+}
+