diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2010-02-16 09:30:23 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2010-02-16 09:30:23 +0000 |
| commit | 6fe5c7aa327e188b7176daa5595bbf075a6b94df (patch) | |
| tree | 4cfca640904d1896e25032757a61f8959c066919 /test/CodeGen/X86 | |
| parent | 989df958a10f0beb90b89ccadd8351cbe51d90b1 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/X86')
68 files changed, 1772 insertions, 740 deletions
diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll index bdbe713a29568..56d6aa960e213 100644 --- a/test/CodeGen/X86/2006-05-11-InstrSched.ll +++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\ -; RUN: grep {asm-printer} | grep 31 +; RUN: grep {asm-printer} | grep 34 target datalayout = "e-p:32:32" define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { @@ -40,7 +40,7 @@ cond_true: ; preds = %cond_true, %entry %tmp137.upgrd.7 = bitcast i32* %tmp137 to <2 x i64>* ; <<2 x i64>*> [#uses=1] store <2 x i64> %tmp131, <2 x i64>* %tmp137.upgrd.7 %tmp147 = add nsw i32 %tmp.10, 8 ; <i32> [#uses=1] - %tmp.upgrd.8 = icmp slt i32 %tmp147, %M ; <i1> [#uses=1] + %tmp.upgrd.8 = icmp ne i32 %tmp147, %M ; <i1> [#uses=1] %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] br i1 %tmp.upgrd.8, label %cond_true, label %return diff --git a/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll new file mode 100644 index 0000000000000..50a244b9e05bf --- /dev/null +++ b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -march=x86 +; PR1049 +target datalayout = "e-p:32:32" +target triple = "i686-pc-linux-gnu" + %struct.QBasicAtomic = type { i32 } + %struct.QByteArray = type { %"struct.QByteArray::Data"* } + %"struct.QByteArray::Data" = type { %struct.QBasicAtomic, i32, i32, i8*, [1 x i8] } + %struct.QFactoryLoader = type { %struct.QObject } + %struct.QImageIOHandler = type { i32 (...)**, %struct.QImageIOHandlerPrivate* } + %struct.QImageIOHandlerPrivate = type opaque + %struct.QImageWriter = type { %struct.QImageWriterPrivate* } + %struct.QImageWriterPrivate = type { %struct.QByteArray, %struct.QFactoryLoader*, i1, %struct.QImageIOHandler*, i32, float, %struct.QString, %struct.QString, i32, %struct.QString, %struct.QImageWriter* } + %"struct.QList<QByteArray>" = type { %"struct.QList<QByteArray>::._20" } + %"struct.QList<QByteArray>::._20" = type { %struct.QListData } + %struct.QListData = type { %"struct.QListData::Data"* } + %"struct.QListData::Data" = type { %struct.QBasicAtomic, i32, i32, i32, i8, [1 x i8*] } + %struct.QObject = type { i32 (...)**, %struct.QObjectData* } + %struct.QObjectData = type { i32 (...)**, %struct.QObject*, %struct.QObject*, %"struct.QList<QByteArray>", i8, [3 x i8], i32, i32 } + %struct.QString = type { %"struct.QString::Data"* } + %"struct.QString::Data" = type { %struct.QBasicAtomic, i32, i32, i16*, i8, i8, [1 x i16] } + +define i1 @_ZNK12QImageWriter8canWriteEv() { + %tmp62 = load %struct.QImageWriterPrivate** null ; <%struct.QImageWriterPrivate*> [#uses=1] + %tmp = getelementptr %struct.QImageWriterPrivate* %tmp62, i32 0, i32 9 ; <%struct.QString*> [#uses=1] + %tmp75 = call %struct.QString* @_ZN7QStringaSERKS_( %struct.QString* %tmp, %struct.QString* null ) ; <%struct.QString*> [#uses=0] + call void asm sideeffect "lock\0Adecl $0\0Asetne 1", "=*m"( i32* null ) + ret i1 false +} + +declare %struct.QString* @_ZN7QStringaSERKS_(%struct.QString*, %struct.QString*) diff --git a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll new file mode 100644 index 0000000000000..a8f0e576b95e7 --- /dev/null +++ b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll @@ -0,0 +1,13 @@ +; PR1219 +; RUN: llc < %s -march=x86 | grep {movl \$1, %eax} + +define i32 @test(i1 %X) { +old_entry1: + %hvar2 = zext i1 %X to i32 + %C = icmp sgt i32 %hvar2, -1 + br i1 %C, label %cond_true15, label %cond_true +cond_true15: + ret i32 1 +cond_true: + ret i32 2 +} diff --git a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll index 4cac9b4c4a216..e1f890192d127 100644 --- a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll +++ b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mtriple=i686-darwin | \ ; RUN: grep push | count 3 -define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) { +define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) nounwind { entry: icmp sgt i32 %size, 0 ; <i1>:0 [#uses=1] br i1 %0, label %bb.preheader, label %return diff --git a/test/CodeGen/X86/2007-10-05-3AddrConvert.ll b/test/CodeGen/X86/2007-10-05-3AddrConvert.ll index 67323e87eff57..2c2706de5d3a5 100644 --- a/test/CodeGen/X86/2007-10-05-3AddrConvert.ll +++ b/test/CodeGen/X86/2007-10-05-3AddrConvert.ll @@ -36,7 +36,9 @@ bb.i6.i: ; preds = %bb.i6.i, %stepsystem.exit.i bb107.i.i: ; preds = %bb107.i.i, %bb.i6.i %q_addr.0.i.i.in = phi %struct.bnode** [ null, %bb107.i.i ], [ %4, %bb.i6.i ] ; <%struct.bnode**> [#uses=1] - %q_addr.0.i.i = load %struct.bnode** %q_addr.0.i.i.in ; <%struct.bnode*> [#uses=0] + %q_addr.0.i.i = load %struct.bnode** %q_addr.0.i.i.in ; <%struct.bnode*> [#uses=1] + %q_addr.1 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 1 + store %struct.bnode* %q_addr.0.i.i, %struct.bnode** %q_addr.1, align 4 br label %bb107.i.i bb47.loopexit.i: ; preds = %bb32.i diff --git a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll index 721d4c945b144..8e315f4d80ff4 100644 --- a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll +++ b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll @@ -35,7 +35,7 @@ cond_next36.i: ; preds = %cond_next.i bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i ; CHECK: %bb.i28.i ; CHECK: addl $2 -; CHECK: addl $2 +; CHECK: addl $-2 %j.0.reg2mem.0.i16.i = phi i32 [ 0, %cond_next36.i ], [ %indvar.next39.i, %bb.i28.i ] ; <i32> [#uses=2] %din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28.i ] ; <double> [#uses=1] %tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; <i32> [#uses=2] diff --git a/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll b/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll deleted file mode 100644 index debb46121698f..0000000000000 --- a/test/CodeGen/X86/2007-11-30-TestLoadFolding.ll +++ /dev/null @@ -1,58 +0,0 @@ -; RUN: llc < %s -march=x86 -stats |& \ -; RUN: grep {1 .*folded into instructions} -; RUN: llc < %s -march=x86 | grep cmp | count 4 - - %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } - -define fastcc i32 @perimeter(%struct.quad_struct* %tree, i32 %size) { -entry: - %tree.idx7.val = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] - %tmp8.i51 = icmp eq %struct.quad_struct* %tree.idx7.val, null ; <i1> [#uses=2] - br i1 %tmp8.i51, label %cond_next, label %cond_next.i52 - -cond_next.i52: ; preds = %entry - ret i32 0 - -cond_next: ; preds = %entry - %tmp59 = load i32* null, align 4 ; <i32> [#uses=1] - %tmp70 = icmp eq i32 %tmp59, 2 ; <i1> [#uses=1] - br i1 %tmp70, label %cond_true.i35, label %bb80 - -cond_true.i35: ; preds = %cond_next - %tmp14.i.i37 = load %struct.quad_struct** null, align 4 ; <%struct.quad_struct*> [#uses=1] - %tmp3.i160 = load i32* null, align 4 ; <i32> [#uses=1] - %tmp4.i161 = icmp eq i32 %tmp3.i160, 2 ; <i1> [#uses=1] - br i1 %tmp4.i161, label %cond_true.i163, label %cond_false.i178 - -cond_true.i163: ; preds = %cond_true.i35 - %tmp7.i162 = sdiv i32 %size, 4 ; <i32> [#uses=2] - %tmp13.i168 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* null, i32 3, i32 2, i32 %tmp7.i162 ) ; <i32> [#uses=1] - %tmp18.i11.i170 = getelementptr %struct.quad_struct* %tmp14.i.i37, i32 0, i32 4 ; <%struct.quad_struct**> [#uses=1] - %tmp19.i12.i171 = load %struct.quad_struct** %tmp18.i11.i170, align 4 ; <%struct.quad_struct*> [#uses=1] - %tmp21.i173 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* %tmp19.i12.i171, i32 3, i32 2, i32 %tmp7.i162 ) ; <i32> [#uses=1] - %tmp22.i174 = add i32 %tmp21.i173, %tmp13.i168 ; <i32> [#uses=1] - br i1 %tmp4.i161, label %cond_true.i141, label %cond_false.i156 - -cond_false.i178: ; preds = %cond_true.i35 - ret i32 0 - -cond_true.i141: ; preds = %cond_true.i163 - %tmp7.i140 = sdiv i32 %size, 4 ; <i32> [#uses=1] - %tmp21.i151 = tail call fastcc i32 @sum_adjacent( %struct.quad_struct* null, i32 3, i32 2, i32 %tmp7.i140 ) ; <i32> [#uses=0] - ret i32 0 - -cond_false.i156: ; preds = %cond_true.i163 - %tmp22.i44 = add i32 0, %tmp22.i174 ; <i32> [#uses=0] - br i1 %tmp8.i51, label %bb22.i, label %cond_next.i - -bb80: ; preds = %cond_next - ret i32 0 - -cond_next.i: ; preds = %cond_false.i156 - ret i32 0 - -bb22.i: ; preds = %cond_false.i156 - ret i32 0 -} - -declare fastcc i32 @sum_adjacent(%struct.quad_struct*, i32, i32, i32) diff --git a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll index b936686798f03..387645f743662 100644 --- a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep nop +; RUN: llc < %s -march=x86 | grep {.byte 0} target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll index 88a5fde07e1e7..548b44db6d272 100644 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll @@ -1,9 +1,7 @@ -; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false | FileCheck %s +; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false -asm-verbose=0 | FileCheck %s ; PR2536 - -; CHECK: movw %cx -; CHECK-NEXT: andl $65534, % +; CHECK: andl $65534, % ; CHECK-NEXT: movl % ; CHECK-NEXT: movl $17 diff --git a/test/CodeGen/X86/2009-02-07-CoalescerBug.ll b/test/CodeGen/X86/2009-02-07-CoalescerBug.ll deleted file mode 100644 index 2d0bbe607279f..0000000000000 --- a/test/CodeGen/X86/2009-02-07-CoalescerBug.ll +++ /dev/null @@ -1,491 +0,0 @@ -; RUN: llc < %s -march=x86 -relocation-model=pic -stats |& grep {Number of valno def marked dead} | grep 1 -; rdar://6566708 - -target triple = "i386-apple-darwin9.6" - %"struct..0$_58" = type { i32, %"struct.llvm::MachineOperand"**, %"struct.llvm::MachineOperand"* } - %"struct..1$_60" = type { i32 } - %"struct..3$_53" = type { i64 } - %struct.__false_type = type <{ i8 }> - %"struct.llvm::APFloat" = type { %"struct.llvm::fltSemantics"*, %"struct..3$_53", i16, i16 } - %"struct.llvm::AbstractTypeUser" = type { i32 (...)** } - %"struct.llvm::AnalysisResolver" = type { %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >", %"struct.llvm::PMDataManager"* } - %"struct.llvm::Annotable" = type { %"struct.llvm::Annotation"* } - %"struct.llvm::Annotation" = type { i32 (...)**, %"struct..1$_60", %"struct.llvm::Annotation"* } - %"struct.llvm::Argument" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::Argument>", %"struct.llvm::Function"* } - %"struct.llvm::AttrListPtr" = type { %"struct.llvm::AttributeListImpl"* } - %"struct.llvm::AttributeListImpl" = type opaque - %"struct.llvm::BasicBlock" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::BasicBlock>", %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >", %"struct.llvm::Function"* } - %"struct.llvm::BitVector" = type { i32*, i32, i32 } - %"struct.llvm::BumpPtrAllocator" = type { i8* } - %"struct.llvm::CalleeSavedInfo" = type { i32, %"struct.llvm::TargetRegisterClass"*, i32 } - %"struct.llvm::CondCodeSDNode" = type { %"struct.llvm::SDNode", i32 } - %"struct.llvm::Constant" = type { %"struct.llvm::User" } - %"struct.llvm::DebugLocTracker" = type { %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >", %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" } - %"struct.llvm::DebugLocTuple" = type { i32, i32, i32 } - %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" = type { i32, %"struct.std::pair<llvm::DebugLocTuple,unsigned int>"*, i32, i32 } - %"struct.llvm::DwarfWriter" = type opaque - %"struct.llvm::FoldingSet<llvm::SDNode>" = type { %"struct.llvm::FoldingSetImpl" } - %"struct.llvm::FoldingSetImpl" = type { i32 (...)**, i8**, i32, i32 } - %"struct.llvm::Function" = type { %"struct.llvm::GlobalValue", %"struct.llvm::Annotable", %"struct.llvm::ilist_node<llvm::Function>", %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >", %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >", %"struct.llvm::ValueSymbolTable"*, %"struct.llvm::AttrListPtr" } - %"struct.llvm::FunctionLoweringInfo" = type opaque - %"struct.llvm::GlobalAddressSDNode" = type { %"struct.llvm::SDNode", %"struct.llvm::GlobalValue"*, i64 } - %"struct.llvm::GlobalValue" = type { %"struct.llvm::Constant", %"struct.llvm::Module"*, i32, %"struct.std::string" } - %"struct.llvm::GlobalVariable" = type { %"struct.llvm::GlobalValue", %"struct.llvm::ilist_node<llvm::GlobalVariable>", i8 } - %"struct.llvm::ImmutablePass" = type { %"struct.llvm::ModulePass" } - %"struct.llvm::Instruction" = type { %"struct.llvm::User", %"struct.llvm::ilist_node<llvm::Instruction>", %"struct.llvm::BasicBlock"* } - %"struct.llvm::LandingPadInfo" = type <{ %"struct.llvm::MachineBasicBlock"*, [12 x i8], %"struct.llvm::SmallVector<unsigned int,1u>", %"struct.llvm::SmallVector<unsigned int,1u>", i32, %"struct.llvm::Function"*, %"struct.std::vector<int,std::allocator<int> >", [3 x i32] }> - %"struct.llvm::MVT" = type { %"struct..1$_60" } - %"struct.llvm::MachineBasicBlock" = type { %"struct.llvm::ilist_node<llvm::MachineBasicBlock>", %"struct.llvm::ilist<llvm::MachineInstr>", %"struct.llvm::BasicBlock"*, i32, %"struct.llvm::MachineFunction"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<int,std::allocator<int> >", i32, i8 } - %"struct.llvm::MachineConstantPool" = type opaque - %"struct.llvm::MachineFrameInfo" = type { %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >", i32, i8, i8, i64, i32, i32, i8, i32, i32, %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >", %"struct.llvm::MachineModuleInfo"*, %"struct.llvm::TargetFrameInfo"* } - %"struct.llvm::MachineFrameInfo::StackObject" = type { i64, i32, i8, i64 } - %"struct.llvm::MachineFunction" = type { %"struct.llvm::Annotation", %"struct.llvm::Function"*, %"struct.llvm::TargetMachine"*, %"struct.llvm::MachineRegisterInfo"*, %"struct.llvm::AbstractTypeUser"*, %"struct.llvm::MachineFrameInfo"*, %"struct.llvm::MachineConstantPool"*, %"struct.llvm::MachineJumpTableInfo"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.llvm::BumpPtrAllocator", %"struct.llvm::Recycler<llvm::MachineBasicBlock,116ul,4ul>", %"struct.llvm::Recycler<llvm::MachineBasicBlock,116ul,4ul>", %"struct.llvm::ilist<llvm::MachineBasicBlock>", %"struct.llvm::DebugLocTracker" } - %"struct.llvm::MachineInstr" = type { %"struct.llvm::ilist_node<llvm::MachineInstr>", %"struct.llvm::TargetInstrDesc"*, i16, %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >", %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >", %"struct.llvm::MachineBasicBlock"*, %"struct..1$_60" } - %"struct.llvm::MachineJumpTableInfo" = type opaque - %"struct.llvm::MachineLocation" = type { i8, i32, i32 } - %"struct.llvm::MachineModuleInfo" = type { %"struct.llvm::ImmutablePass", %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<llvm::MachineMove,std::allocator<llvm::MachineMove> >", %"struct.std::vector<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >", %"struct.std::vector<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >", %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<llvm::Function*,std::allocator<llvm::Function*> >", %"struct.llvm::SmallPtrSet<const llvm::Function*,32u>", i8, i8, i8 } - %"struct.llvm::MachineMove" = type { i32, %"struct.llvm::MachineLocation", %"struct.llvm::MachineLocation" } - %"struct.llvm::MachineOperand" = type { i8, i8, i8, %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineOperand::$_57" } - %"struct.llvm::MachineOperand::$_57" = type { %"struct..0$_58" } - %"struct.llvm::MachineRegisterInfo" = type { %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >", %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >", %"struct.llvm::MachineOperand"**, %"struct.llvm::BitVector", %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >", %"struct.std::vector<int,std::allocator<int> >" } - %"struct.llvm::Module" = type opaque - %"struct.llvm::ModulePass" = type { %"struct.llvm::Pass" } - %"struct.llvm::PATypeHandle" = type { %"struct.llvm::Type"*, %"struct.llvm::AbstractTypeUser"* } - %"struct.llvm::PATypeHolder" = type { %"struct.llvm::Type"* } - %"struct.llvm::PMDataManager" = type opaque - %"struct.llvm::Pass" = type { i32 (...)**, %"struct.llvm::AnalysisResolver"*, i32, %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" } - %"struct.llvm::PassInfo" = type { i8*, i8*, i32, i8, i8, i8, %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >", %"struct.llvm::Pass"* ()* } - %"struct.llvm::Recycler<llvm::MachineBasicBlock,116ul,4ul>" = type { %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" } - %"struct.llvm::RecyclerStruct" = type { %"struct.llvm::RecyclerStruct"*, %"struct.llvm::RecyclerStruct"* } - %"struct.llvm::RecyclingAllocator<llvm::BumpPtrAllocator,llvm::SDNode,132ul,4ul>" = type { %"struct.llvm::Recycler<llvm::MachineBasicBlock,116ul,4ul>", %"struct.llvm::BumpPtrAllocator" } - %"struct.llvm::SDNode" = type { %"struct.llvm::BumpPtrAllocator", %"struct.llvm::ilist_node<llvm::SDNode>", i16, i16, i32, %"struct.llvm::SDUse"*, %"struct.llvm::MVT"*, %"struct.llvm::SDUse"*, i16, i16, %"struct..1$_60" } - %"struct.llvm::SDUse" = type { %"struct.llvm::SDValue", %"struct.llvm::SDNode"*, %"struct.llvm::SDUse"**, %"struct.llvm::SDUse"* } - %"struct.llvm::SDVTList" = type { %"struct.llvm::MVT"*, i16 } - %"struct.llvm::SDValue" = type { %"struct.llvm::SDNode"*, i32 } - %"struct.llvm::SelectionDAG" = type { %"struct.llvm::TargetLowering"*, %"struct.llvm::MachineFunction"*, %"struct.llvm::FunctionLoweringInfo"*, %"struct.llvm::MachineModuleInfo"*, %"struct.llvm::DwarfWriter"*, %"struct.llvm::SDNode", %"struct.llvm::SDValue", %"struct.llvm::ilist<llvm::SDNode>", %"struct.llvm::RecyclingAllocator<llvm::BumpPtrAllocator,llvm::SDNode,132ul,4ul>", %"struct.llvm::FoldingSet<llvm::SDNode>", %"struct.llvm::BumpPtrAllocator", %"struct.llvm::BumpPtrAllocator", %"struct.std::map<const llvm::SDNode*,std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >", %"struct.std::vector<llvm::SDVTList,std::allocator<llvm::SDVTList> >", %"struct.std::vector<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >", %"struct.std::vector<llvm::SDNode*,std::allocator<llvm::SDNode*> >", %"struct.std::map<const llvm::SDNode*,std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >", %"struct.llvm::StringMap<llvm::SDNode*,llvm::MallocAllocator>", %"struct.llvm::StringMap<llvm::SDNode*,llvm::MallocAllocator>" } - %"struct.llvm::SmallPtrSet<const llvm::Function*,32u>" = type { %"struct.llvm::SmallPtrSetImpl", [32 x i8*] } - %"struct.llvm::SmallPtrSetImpl" = type { i8**, i32, i32, i32, [1 x i8*] } - %"struct.llvm::SmallVector<llvm::SDValue,16u>" = type <{ [17 x i8], [127 x i8] }> - %"struct.llvm::SmallVector<unsigned int,1u>" = type <{ [17 x i8], [3 x i8], [3 x i32] }> - %"struct.llvm::StringMap<llvm::SDNode*,llvm::MallocAllocator>" = type { %"struct.llvm::StringMapImpl", %struct.__false_type } - %"struct.llvm::StringMapImpl" = type { %"struct.llvm::StringMapImpl::ItemBucket"*, i32, i32, i32, i32 } - %"struct.llvm::StringMapImpl::ItemBucket" = type { i32, %"struct..1$_60"* } - %"struct.llvm::TargetAsmInfo" = type opaque - %"struct.llvm::TargetData" = type <{ %"struct.llvm::ImmutablePass", i8, i8, i8, i8, [4 x i8], %"struct.llvm::SmallVector<llvm::SDValue,16u>" }> - %"struct.llvm::TargetFrameInfo" = type { i32 (...)**, i32, i32, i32 } - %"struct.llvm::TargetInstrDesc" = type { i16, i16, i16, i16, i8*, i32, i32, i32*, i32*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetOperandInfo"* } - %"struct.llvm::TargetLowering" = type { i32 (...)**, %"struct.llvm::TargetMachine"*, %"struct.llvm::TargetData"*, %"struct.llvm::MVT", i8, i8, i8, i8, i8, i8, i8, %"struct.llvm::MVT", i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [30 x %"struct.llvm::TargetRegisterClass"*], [30 x i8], [30 x %"struct.llvm::MVT"], [30 x %"struct.llvm::MVT"], [179 x i64], [4 x i64], [30 x i64], [2 x [5 x i64]], [30 x i64], [24 x i64], %"struct.llvm::TargetLowering::ValueTypeActionImpl", %"struct.std::vector<llvm::APFloat,std::allocator<llvm::APFloat> >", %"struct.std::vector<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >", [23 x i8], %"struct.std::map<const llvm::SDNode*,std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >", [180 x i8*], [180 x i32], i32, i32, i32, i8 } - %"struct.llvm::TargetLowering::ValueTypeActionImpl" = type { [2 x i32] } - %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.llvm::TargetAsmInfo"* } - %"struct.llvm::TargetOperandInfo" = type { i16, i16, i32 } - %"struct.llvm::TargetRegisterClass" = type { i32 (...)**, i32, i8, %"struct.llvm::MVT"*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, i32, i32, i32, i32*, i32* } - %"struct.llvm::Type" = type { %"struct.llvm::AbstractTypeUser", i8, [3 x i8], i32, %"struct.llvm::Type"*, %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >", i32, %"struct.llvm::PATypeHandle"* } - %"struct.llvm::Use" = type { %"struct.llvm::Value"*, %"struct.llvm::Use"*, %"struct..1$_60" } - %"struct.llvm::User" = type { %"struct.llvm::Value", %"struct.llvm::Use"*, i32 } - %"struct.llvm::Value" = type { i32 (...)**, i16, i16, %"struct.llvm::PATypeHolder", %"struct.llvm::Use"*, %"struct.llvm::ValueName"* } - %"struct.llvm::ValueName" = type opaque - %"struct.llvm::ValueSymbolTable" = type opaque - %"struct.llvm::fltSemantics" = type opaque - %"struct.llvm::ilist<llvm::MachineBasicBlock>" = type { %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" } - %"struct.llvm::ilist<llvm::MachineInstr>" = type { %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" } - %"struct.llvm::ilist<llvm::SDNode>" = type { %"struct.llvm::iplist<llvm::SDNode,llvm::ilist_traits<llvm::SDNode> >" } - %"struct.llvm::ilist_node<llvm::Argument>" = type { %"struct.llvm::Argument"*, %"struct.llvm::Argument"* } - %"struct.llvm::ilist_node<llvm::BasicBlock>" = type { %"struct.llvm::BasicBlock"*, %"struct.llvm::BasicBlock"* } - %"struct.llvm::ilist_node<llvm::Function>" = type { %"struct.llvm::Function"*, %"struct.llvm::Function"* } - %"struct.llvm::ilist_node<llvm::GlobalVariable>" = type { %"struct.llvm::GlobalVariable"*, %"struct.llvm::GlobalVariable"* } - %"struct.llvm::ilist_node<llvm::Instruction>" = type { %"struct.llvm::Instruction"*, %"struct.llvm::Instruction"* } - %"struct.llvm::ilist_node<llvm::MachineBasicBlock>" = type { %"struct.llvm::MachineBasicBlock"*, %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::ilist_node<llvm::MachineInstr>" = type { %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineInstr"* } - %"struct.llvm::ilist_node<llvm::SDNode>" = type { %"struct.llvm::SDNode"*, %"struct.llvm::SDNode"* } - %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>" = type { %"struct.llvm::MachineBasicBlock" } - %"struct.llvm::ilist_traits<llvm::MachineInstr>" = type { %"struct.llvm::MachineInstr", %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" = type { %"struct.llvm::RecyclerStruct" } - %"struct.llvm::ilist_traits<llvm::SDNode>" = type { %"struct.llvm::SDNode" } - %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >" = type { %"struct.llvm::Argument"* } - %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >" = type { %"struct.llvm::BasicBlock"* } - %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >" = type { %"struct.llvm::Instruction"* } - %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" = type { %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>", %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" = type { %"struct.llvm::ilist_traits<llvm::MachineInstr>", %"struct.llvm::MachineInstr"* } - %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>", %"struct.llvm::RecyclerStruct"* } - %"struct.llvm::iplist<llvm::SDNode,llvm::ilist_traits<llvm::SDNode> >" = type { %"struct.llvm::ilist_traits<llvm::SDNode>", %"struct.llvm::SDNode"* } - %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" } - %"struct.std::_Rb_tree<const llvm::SDNode*,std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > >,std::_Select1st<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >" = type { %"struct.std::_Rb_tree<const llvm::SDNode*,std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > >,std::_Select1st<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >::_Rb_tree_impl<std::less<const llvm::SDNode*>,false>" } - %"struct.std::_Rb_tree<const llvm::SDNode*,std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > >,std::_Select1st<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >::_Rb_tree_impl<std::less<const llvm::SDNode*>,false>" = type { %struct.__false_type, %"struct.std::_Rb_tree_node_base", i32 } - %"struct.std::_Rb_tree_node_base" = type { i32, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"* } - %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" } - %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" = type { %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"** } - %"struct.std::_Vector_base<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" } - %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" = type { i32*, i32*, i32* } - %"struct.std::_Vector_base<llvm::APFloat,std::allocator<llvm::APFloat> >" = type { %"struct.std::_Vector_base<llvm::APFloat,std::allocator<llvm::APFloat> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::APFloat,std::allocator<llvm::APFloat> >::_Vector_impl" = type { %"struct.llvm::APFloat"*, %"struct.llvm::APFloat"*, %"struct.llvm::APFloat"* } - %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" = type { %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"** } - %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" = type { %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"* } - %"struct.std::_Vector_base<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >" = type { %"struct.std::_Vector_base<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >::_Vector_impl" = type { %"struct.llvm::CondCodeSDNode"**, %"struct.llvm::CondCodeSDNode"**, %"struct.llvm::CondCodeSDNode"** } - %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" = type { %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"* } - %"struct.std::_Vector_base<llvm::Function*,std::allocator<llvm::Function*> >" = type { %"struct.std::_Vector_base<llvm::Function*,std::allocator<llvm::Function*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::Function*,std::allocator<llvm::Function*> >::_Vector_impl" = type { %"struct.llvm::Function"**, %"struct.llvm::Function"**, %"struct.llvm::Function"** } - %"struct.std::_Vector_base<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >" = type { %"struct.std::_Vector_base<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >::_Vector_impl" = type { %"struct.llvm::GlobalVariable"**, %"struct.llvm::GlobalVariable"**, %"struct.llvm::GlobalVariable"** } - %"struct.std::_Vector_base<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >" = type { %"struct.std::_Vector_base<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >::_Vector_impl" = type { %"struct.llvm::LandingPadInfo"*, %"struct.llvm::LandingPadInfo"*, %"struct.llvm::LandingPadInfo"* } - %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" = type { %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"** } - %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" = type { %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"* } - %"struct.std::_Vector_base<llvm::MachineMove,std::allocator<llvm::MachineMove> >" = type { %"struct.std::_Vector_base<llvm::MachineMove,std::allocator<llvm::MachineMove> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineMove,std::allocator<llvm::MachineMove> >::_Vector_impl" = type { %"struct.llvm::MachineMove"*, %"struct.llvm::MachineMove"*, %"struct.llvm::MachineMove"* } - %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" = type { %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"* } - %"struct.std::_Vector_base<llvm::SDNode*,std::allocator<llvm::SDNode*> >" = type { %"struct.std::_Vector_base<llvm::SDNode*,std::allocator<llvm::SDNode*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::SDNode*,std::allocator<llvm::SDNode*> >::_Vector_impl" = type { %"struct.llvm::SDNode"**, %"struct.llvm::SDNode"**, %"struct.llvm::SDNode"** } - %"struct.std::_Vector_base<llvm::SDVTList,std::allocator<llvm::SDVTList> >" = type { %"struct.std::_Vector_base<llvm::SDVTList,std::allocator<llvm::SDVTList> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::SDVTList,std::allocator<llvm::SDVTList> >::_Vector_impl" = type { %"struct.llvm::SDVTList"*, %"struct.llvm::SDVTList"*, %"struct.llvm::SDVTList"* } - %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"* } - %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"* } - %"struct.std::_Vector_base<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >" = type { %"struct.std::_Vector_base<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >::_Vector_impl" = type { %"struct.std::pair<llvm::MVT,llvm::TargetRegisterClass*>"*, %"struct.std::pair<llvm::MVT,llvm::TargetRegisterClass*>"*, %"struct.std::pair<llvm::MVT,llvm::TargetRegisterClass*>"* } - %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" = type { %"struct.std::pair<int,int>"*, %"struct.std::pair<int,int>"*, %"struct.std::pair<int,int>"* } - %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" } - %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" = type { %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"* } - %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" } - %"struct.std::map<const llvm::SDNode*,std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >" = type { %"struct.std::_Rb_tree<const llvm::SDNode*,std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > >,std::_Select1st<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >,std::less<const llvm::SDNode*>,std::allocator<std::pair<const llvm::SDNode* const, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > > >" } - %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>" = type { %"struct.llvm::PassInfo"*, %"struct.llvm::Pass"* } - %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>" = type { %"struct.llvm::TargetRegisterClass"*, %"struct.llvm::MachineOperand"* } - %"struct.std::pair<int,int>" = type { i32, i32 } - %"struct.std::pair<llvm::DebugLocTuple,unsigned int>" = type { %"struct.llvm::DebugLocTuple", i32 } - %"struct.std::pair<llvm::MVT,llvm::TargetRegisterClass*>" = type { %"struct.llvm::MVT", %"struct.llvm::TargetRegisterClass"* } - %"struct.std::string" = type { %"struct.llvm::BumpPtrAllocator" } - %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" } - %"struct.std::vector<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >" } - %"struct.std::vector<llvm::APFloat,std::allocator<llvm::APFloat> >" = type { %"struct.std::_Vector_base<llvm::APFloat,std::allocator<llvm::APFloat> >" } - %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" } - %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" } - %"struct.std::vector<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >" = type { %"struct.std::_Vector_base<llvm::CondCodeSDNode*,std::allocator<llvm::CondCodeSDNode*> >" } - %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" } - %"struct.std::vector<llvm::Function*,std::allocator<llvm::Function*> >" = type { %"struct.std::_Vector_base<llvm::Function*,std::allocator<llvm::Function*> >" } - %"struct.std::vector<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >" = type { %"struct.std::_Vector_base<llvm::GlobalVariable*,std::allocator<llvm::GlobalVariable*> >" } - %"struct.std::vector<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >" = type { %"struct.std::_Vector_base<llvm::LandingPadInfo,std::allocator<llvm::LandingPadInfo> >" } - %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" } - %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" } - %"struct.std::vector<llvm::MachineMove,std::allocator<llvm::MachineMove> >" = type { %"struct.std::_Vector_base<llvm::MachineMove,std::allocator<llvm::MachineMove> >" } - %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" } - %"struct.std::vector<llvm::SDNode*,std::allocator<llvm::SDNode*> >" = type { %"struct.std::_Vector_base<llvm::SDNode*,std::allocator<llvm::SDNode*> >" } - %"struct.std::vector<llvm::SDVTList,std::allocator<llvm::SDVTList> >" = type { %"struct.std::_Vector_base<llvm::SDVTList,std::allocator<llvm::SDVTList> >" } - %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" } - %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" } - %"struct.std::vector<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >" = type { %"struct.std::_Vector_base<std::pair<llvm::MVT, llvm::TargetRegisterClass*>,std::allocator<std::pair<llvm::MVT, llvm::TargetRegisterClass*> > >" } - %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" } - %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" } -@"\01LC81" = internal constant [65 x i8] c"/Users/echeng/LLVM/llvm/include/llvm/CodeGen/SelectionDAGNodes.h\00" ; <[65 x i8]*> [#uses=1] -@_ZZNK4llvm6SDNode12getValueTypeEjE8__func__ = internal constant [13 x i8] c"getValueType\00" ; <[13 x i8]*> [#uses=1] -@"\01LC83" = internal constant [46 x i8] c"ResNo < NumValues && \22Illegal result number!\22\00" ; <[46 x i8]*> [#uses=1] -@"\01LC197" = internal constant [16 x i8] c"___tls_get_addr\00" ; <[16 x i8]*> [#uses=1] -@llvm.used1 = appending global [1 x i8*] [ i8* bitcast (i64 (%"struct.llvm::GlobalAddressSDNode"*, %"struct.llvm::SelectionDAG"*, %"struct.llvm::MVT"*)* @_ZL31LowerToTLSGeneralDynamicModel32PN4llvm19GlobalAddressSDNodeERNS_12SelectionDAGENS_3MVTE to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define fastcc i64 @_ZL31LowerToTLSGeneralDynamicModel32PN4llvm19GlobalAddressSDNodeERNS_12SelectionDAGENS_3MVTE(%"struct.llvm::GlobalAddressSDNode"* %GA, %"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %PtrVT) nounwind noinline { -entry: - %VT2.i185 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT1.i186 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %Ops.i187 = alloca [4 x %"struct.llvm::SDValue"], align 8 ; <[4 x %"struct.llvm::SDValue"]*> [#uses=9] - %0 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT182 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT2.i173 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT1.i174 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %Ops.i175 = alloca [4 x %"struct.llvm::SDValue"], align 8 ; <[4 x %"struct.llvm::SDValue"]*> [#uses=9] - %1 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT3.i = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT2.i = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %VT1.i = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %Ops.i = alloca [3 x %"struct.llvm::SDValue"], align 8 ; <[3 x %"struct.llvm::SDValue"]*> [#uses=7] - %VT = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %Ops1 = alloca [5 x %"struct.llvm::SDValue"], align 8 ; <[5 x %"struct.llvm::SDValue"]*> [#uses=11] - %Ops = alloca [3 x %"struct.llvm::SDValue"], align 8 ; <[3 x %"struct.llvm::SDValue"]*> [#uses=7] - %NodeTys = alloca %"struct.llvm::SDVTList", align 8 ; <%"struct.llvm::SDVTList"*> [#uses=4] - %2 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %3 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %4 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %5 = alloca %"struct.llvm::MVT", align 8 ; <%"struct.llvm::MVT"*> [#uses=2] - %6 = getelementptr %"struct.llvm::GlobalAddressSDNode"* %GA, i32 0, i32 0, i32 10, i32 0 ; <i32*> [#uses=1] - %7 = load i32* %6, align 4 ; <i32> [#uses=5] - %8 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocENS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 208, i32 0, %"struct.llvm::MVT"* byval align 4 %PtrVT) nounwind ; <i64> [#uses=2] - %9 = trunc i64 %8 to i32 ; <i32> [#uses=1] - %sroa.store.elt = lshr i64 %8, 32 ; <i64> [#uses=1] - %10 = trunc i64 %sroa.store.elt to i32 ; <i32> [#uses=3] - %tmp52 = inttoptr i32 %9 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=3] - %11 = getelementptr %"struct.llvm::SelectionDAG"* %DAG, i32 0, i32 5 ; <%"struct.llvm::SDNode"*> [#uses=1] - %12 = getelementptr %"struct.llvm::MVT"* %VT1.i186, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 0, i32* %12, align 8 - %13 = getelementptr %"struct.llvm::MVT"* %VT2.i185, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 12, i32* %13, align 8 - %14 = call i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %VT1.i186, %"struct.llvm::MVT"* byval align 4 %VT2.i185) nounwind ; <i64> [#uses=1] - %15 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 0, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %11, %"struct.llvm::SDNode"** %15, align 8 - %16 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 0, i32* %16, align 4 - %17 = getelementptr %"struct.llvm::SDNode"* %tmp52, i32 0, i32 9 ; <i16*> [#uses=1] - %18 = load i16* %17, align 2 ; <i16> [#uses=1] - %19 = zext i16 %18 to i32 ; <i32> [#uses=1] - %20 = icmp ugt i32 %19, %10 ; <i1> [#uses=1] - br i1 %20, label %_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit193, label %bb.i.i.i188 - -bb.i.i.i188: ; preds = %entry - call void @__assert_rtn(i8* getelementptr ([13 x i8]* @_ZZNK4llvm6SDNode12getValueTypeEjE8__func__, i32 0, i32 0), i8* getelementptr ([65 x i8]* @"\01LC81", i32 0, i32 0), i32 1314, i8* getelementptr ([46 x i8]* @"\01LC83", i32 0, i32 0)) noreturn nounwind - unreachable - -_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit193: ; preds = %entry - %21 = trunc i64 %14 to i32 ; <i32> [#uses=1] - %tmp4.i.i189 = inttoptr i32 %21 to %"struct.llvm::MVT"* ; <%"struct.llvm::MVT"*> [#uses=1] - %22 = getelementptr %"struct.llvm::SDNode"* %tmp52, i32 0, i32 6 ; <%"struct.llvm::MVT"**> [#uses=1] - %23 = load %"struct.llvm::MVT"** %22, align 4 ; <%"struct.llvm::MVT"*> [#uses=1] - %24 = getelementptr %"struct.llvm::MVT"* %23, i32 %10, i32 0, i32 0 ; <i32*> [#uses=1] - %25 = load i32* %24, align 4 ; <i32> [#uses=1] - %26 = getelementptr %"struct.llvm::MVT"* %0, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 %25, i32* %26, align 8 - %27 = call i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 19, %"struct.llvm::MVT"* byval align 4 %0) nounwind ; <i64> [#uses=2] - %28 = trunc i64 %27 to i32 ; <i32> [#uses=1] - %sroa.store.elt.i190 = lshr i64 %27, 32 ; <i64> [#uses=1] - %29 = trunc i64 %sroa.store.elt.i190 to i32 ; <i32> [#uses=1] - %30 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 1, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp5.i191 = inttoptr i32 %28 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp5.i191, %"struct.llvm::SDNode"** %30, align 8 - %31 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 1, i32 1 ; <i32*> [#uses=1] - store i32 %29, i32* %31, align 4 - %32 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 2, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp52, %"struct.llvm::SDNode"** %32, align 8 - %33 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 2, i32 1 ; <i32*> [#uses=1] - store i32 %10, i32* %33, align 4 - %34 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 3, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* null, %"struct.llvm::SDNode"** %34, align 8 - %35 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 3, i32 1 ; <i32*> [#uses=1] - store i32 0, i32* %35, align 4 - %36 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i187, i32 0, i32 0 ; <%"struct.llvm::SDValue"*> [#uses=1] - %37 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocEPKNS_3MVTEjPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"* %DAG, i32 36, i32 %7, %"struct.llvm::MVT"* %tmp4.i.i189, i32 2, %"struct.llvm::SDValue"* %36, i32 3) nounwind ; <i64> [#uses=2] - %38 = trunc i64 %37 to i32 ; <i32> [#uses=1] - %tmp66 = inttoptr i32 %38 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=2] - %39 = getelementptr %"struct.llvm::MVT"* %5, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 12, i32* %39, align 8 - %40 = getelementptr %"struct.llvm::MVT"* %4, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 0, i32* %40, align 8 - %41 = call i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_S1_(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %PtrVT, %"struct.llvm::MVT"* byval align 4 %4, %"struct.llvm::MVT"* byval align 4 %5) nounwind ; <i64> [#uses=2] - %42 = trunc i64 %41 to i32 ; <i32> [#uses=1] - %sroa.store.elt75 = lshr i64 %41, 32 ; <i64> [#uses=1] - %43 = trunc i64 %sroa.store.elt75 to i16 ; <i16> [#uses=1] - %44 = getelementptr %"struct.llvm::SDVTList"* %NodeTys, i32 0, i32 0 ; <%"struct.llvm::MVT"**> [#uses=2] - %tmp78 = inttoptr i32 %42 to %"struct.llvm::MVT"* ; <%"struct.llvm::MVT"*> [#uses=1] - store %"struct.llvm::MVT"* %tmp78, %"struct.llvm::MVT"** %44, align 8 - %45 = getelementptr %"struct.llvm::SDVTList"* %NodeTys, i32 0, i32 1 ; <i16*> [#uses=2] - store i16 %43, i16* %45, align 4 - %46 = getelementptr %"struct.llvm::GlobalAddressSDNode"* %GA, i32 0, i32 0, i32 9 ; <i16*> [#uses=1] - %47 = load i16* %46, align 2 ; <i16> [#uses=1] - %48 = icmp eq i16 %47, 0 ; <i1> [#uses=1] - br i1 %48, label %bb.i, label %_ZNK4llvm6SDNode12getValueTypeEj.exit - -bb.i: ; preds = %_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit193 - call void @__assert_rtn(i8* getelementptr ([13 x i8]* @_ZZNK4llvm6SDNode12getValueTypeEjE8__func__, i32 0, i32 0), i8* getelementptr ([65 x i8]* @"\01LC81", i32 0, i32 0), i32 1314, i8* getelementptr ([46 x i8]* @"\01LC83", i32 0, i32 0)) noreturn nounwind - unreachable - -_ZNK4llvm6SDNode12getValueTypeEj.exit: ; preds = %_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit193 - %sroa.store.elt63 = lshr i64 %37, 32 ; <i64> [#uses=1] - %49 = trunc i64 %sroa.store.elt63 to i32 ; <i32> [#uses=1] - %50 = getelementptr %"struct.llvm::GlobalAddressSDNode"* %GA, i32 0, i32 2 ; <i64*> [#uses=1] - %51 = load i64* %50, align 4 ; <i64> [#uses=1] - %52 = getelementptr %"struct.llvm::GlobalAddressSDNode"* %GA, i32 0, i32 0, i32 6 ; <%"struct.llvm::MVT"**> [#uses=1] - %53 = load %"struct.llvm::MVT"** %52, align 4 ; <%"struct.llvm::MVT"*> [#uses=1] - %54 = getelementptr %"struct.llvm::MVT"* %53, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - %55 = load i32* %54, align 4 ; <i32> [#uses=1] - %56 = getelementptr %"struct.llvm::GlobalAddressSDNode"* %GA, i32 0, i32 1 ; <%"struct.llvm::GlobalValue"**> [#uses=1] - %57 = load %"struct.llvm::GlobalValue"** %56, align 4 ; <%"struct.llvm::GlobalValue"*> [#uses=1] - %58 = getelementptr %"struct.llvm::MVT"* %VT182, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 %55, i32* %58, align 8 - %59 = call i64 @_ZN4llvm12SelectionDAG16getGlobalAddressEPKNS_11GlobalValueENS_3MVTExb(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::GlobalValue"* %57, %"struct.llvm::MVT"* byval align 4 %VT182, i64 %51, i8 zeroext 1) nounwind ; <i64> [#uses=2] - %60 = trunc i64 %59 to i32 ; <i32> [#uses=1] - %sroa.store.elt83 = lshr i64 %59, 32 ; <i64> [#uses=1] - %61 = trunc i64 %sroa.store.elt83 to i32 ; <i32> [#uses=1] - %tmp86 = inttoptr i32 %60 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - %62 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 0, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp66, %"struct.llvm::SDNode"** %62, align 8 - %63 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %49, i32* %63, align 4 - %64 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 1, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp86, %"struct.llvm::SDNode"** %64, align 8 - %65 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 1, i32 1 ; <i32*> [#uses=1] - store i32 %61, i32* %65, align 4 - %66 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 2, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp66, %"struct.llvm::SDNode"** %66, align 8 - %67 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 2, i32 1 ; <i32*> [#uses=1] - store i32 1, i32* %67, align 4 - %68 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops, i32 0, i32 0 ; <%"struct.llvm::SDValue"*> [#uses=1] - %69 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocENS_8SDVTListEPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"* %DAG, i32 220, i32 %7, %"struct.llvm::SDVTList"* byval align 4 %NodeTys, %"struct.llvm::SDValue"* %68, i32 3) nounwind ; <i64> [#uses=2] - %70 = trunc i64 %69 to i32 ; <i32> [#uses=1] - %sroa.store.elt89 = lshr i64 %69, 32 ; <i64> [#uses=1] - %71 = trunc i64 %sroa.store.elt89 to i32 ; <i32> [#uses=3] - %tmp92 = inttoptr i32 %70 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=7] - call void @_ZNK4llvm6SDNode4dumpEv(%"struct.llvm::SDNode"* %tmp92) nounwind - %72 = getelementptr %"struct.llvm::MVT"* %VT1.i174, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 0, i32* %72, align 8 - %73 = getelementptr %"struct.llvm::MVT"* %VT2.i173, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 12, i32* %73, align 8 - %74 = call i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %VT1.i174, %"struct.llvm::MVT"* byval align 4 %VT2.i173) nounwind ; <i64> [#uses=1] - %75 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 0, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp92, %"struct.llvm::SDNode"** %75, align 8 - %76 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 1, i32* %76, align 4 - %77 = getelementptr %"struct.llvm::SDNode"* %tmp92, i32 0, i32 9 ; <i16*> [#uses=1] - %78 = load i16* %77, align 2 ; <i16> [#uses=1] - %79 = zext i16 %78 to i32 ; <i32> [#uses=1] - %80 = icmp ugt i32 %79, %71 ; <i1> [#uses=1] - br i1 %80, label %_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit, label %bb.i.i.i - -bb.i.i.i: ; preds = %_ZNK4llvm6SDNode12getValueTypeEj.exit - call void @__assert_rtn(i8* getelementptr ([13 x i8]* @_ZZNK4llvm6SDNode12getValueTypeEjE8__func__, i32 0, i32 0), i8* getelementptr ([65 x i8]* @"\01LC81", i32 0, i32 0), i32 1314, i8* getelementptr ([46 x i8]* @"\01LC83", i32 0, i32 0)) noreturn nounwind - unreachable - -_ZN4llvm12SelectionDAG12getCopyToRegENS_7SDValueENS_8DebugLocEjS1_S1_.exit: ; preds = %_ZNK4llvm6SDNode12getValueTypeEj.exit - %81 = trunc i64 %74 to i32 ; <i32> [#uses=1] - %tmp4.i.i176 = inttoptr i32 %81 to %"struct.llvm::MVT"* ; <%"struct.llvm::MVT"*> [#uses=1] - %82 = getelementptr %"struct.llvm::SDNode"* %tmp92, i32 0, i32 6 ; <%"struct.llvm::MVT"**> [#uses=1] - %83 = load %"struct.llvm::MVT"** %82, align 4 ; <%"struct.llvm::MVT"*> [#uses=1] - %84 = getelementptr %"struct.llvm::MVT"* %83, i32 %71, i32 0, i32 0 ; <i32*> [#uses=1] - %85 = load i32* %84, align 4 ; <i32> [#uses=1] - %86 = getelementptr %"struct.llvm::MVT"* %1, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 %85, i32* %86, align 8 - %87 = call i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 17, %"struct.llvm::MVT"* byval align 4 %1) nounwind ; <i64> [#uses=2] - %88 = trunc i64 %87 to i32 ; <i32> [#uses=1] - %sroa.store.elt.i177 = lshr i64 %87, 32 ; <i64> [#uses=1] - %89 = trunc i64 %sroa.store.elt.i177 to i32 ; <i32> [#uses=1] - %90 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 1, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp5.i178 = inttoptr i32 %88 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp5.i178, %"struct.llvm::SDNode"** %90, align 8 - %91 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 1, i32 1 ; <i32*> [#uses=1] - store i32 %89, i32* %91, align 4 - %92 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 2, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp92, %"struct.llvm::SDNode"** %92, align 8 - %93 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 2, i32 1 ; <i32*> [#uses=1] - store i32 %71, i32* %93, align 4 - %94 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 3, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp92, %"struct.llvm::SDNode"** %94, align 8 - %95 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 3, i32 1 ; <i32*> [#uses=1] - store i32 2, i32* %95, align 4 - %96 = icmp eq %"struct.llvm::SDNode"* %tmp92, null ; <i1> [#uses=1] - %iftmp.583.0.i = select i1 %96, i32 3, i32 4 ; <i32> [#uses=1] - %97 = getelementptr [4 x %"struct.llvm::SDValue"]* %Ops.i175, i32 0, i32 0 ; <%"struct.llvm::SDValue"*> [#uses=1] - %98 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocEPKNS_3MVTEjPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"* %DAG, i32 36, i32 %7, %"struct.llvm::MVT"* %tmp4.i.i176, i32 2, %"struct.llvm::SDValue"* %97, i32 %iftmp.583.0.i) nounwind ; <i64> [#uses=2] - %99 = trunc i64 %98 to i32 ; <i32> [#uses=1] - %sroa.store.elt107 = lshr i64 %98, 32 ; <i64> [#uses=1] - %100 = trunc i64 %sroa.store.elt107 to i32 ; <i32> [#uses=1] - %tmp110 = inttoptr i32 %99 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=2] - %101 = getelementptr %"struct.llvm::MVT"* %3, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 12, i32* %101, align 8 - %102 = getelementptr %"struct.llvm::MVT"* %2, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 0, i32* %102, align 8 - %103 = call i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %2, %"struct.llvm::MVT"* byval align 4 %3) nounwind ; <i64> [#uses=2] - %104 = trunc i64 %103 to i32 ; <i32> [#uses=1] - %sroa.store.elt119 = lshr i64 %103, 32 ; <i64> [#uses=1] - %105 = trunc i64 %sroa.store.elt119 to i16 ; <i16> [#uses=1] - %tmp122 = inttoptr i32 %104 to %"struct.llvm::MVT"* ; <%"struct.llvm::MVT"*> [#uses=1] - store %"struct.llvm::MVT"* %tmp122, %"struct.llvm::MVT"** %44, align 8 - store i16 %105, i16* %45, align 4 - %106 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 0, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp110, %"struct.llvm::SDNode"** %106, align 8 - %107 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %100, i32* %107, align 4 - %108 = call i64 @_ZN4llvm12SelectionDAG23getTargetExternalSymbolEPKcNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i8* getelementptr ([16 x i8]* @"\01LC197", i32 0, i32 0), %"struct.llvm::MVT"* byval align 4 %PtrVT) nounwind ; <i64> [#uses=2] - %109 = trunc i64 %108 to i32 ; <i32> [#uses=1] - %sroa.store.elt125 = lshr i64 %108, 32 ; <i64> [#uses=1] - %110 = trunc i64 %sroa.store.elt125 to i32 ; <i32> [#uses=1] - %111 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 1, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp128 = inttoptr i32 %109 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp128, %"struct.llvm::SDNode"** %111, align 8 - %112 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 1, i32 1 ; <i32*> [#uses=1] - store i32 %110, i32* %112, align 4 - %113 = call i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 17, %"struct.llvm::MVT"* byval align 4 %PtrVT) nounwind ; <i64> [#uses=2] - %114 = trunc i64 %113 to i32 ; <i32> [#uses=1] - %sroa.store.elt131 = lshr i64 %113, 32 ; <i64> [#uses=1] - %115 = trunc i64 %sroa.store.elt131 to i32 ; <i32> [#uses=1] - %116 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 2, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp134 = inttoptr i32 %114 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp134, %"struct.llvm::SDNode"** %116, align 8 - %117 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 2, i32 1 ; <i32*> [#uses=1] - store i32 %115, i32* %117, align 4 - %118 = call i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 19, %"struct.llvm::MVT"* byval align 4 %PtrVT) nounwind ; <i64> [#uses=2] - %119 = trunc i64 %118 to i32 ; <i32> [#uses=1] - %sroa.store.elt137 = lshr i64 %118, 32 ; <i64> [#uses=1] - %120 = trunc i64 %sroa.store.elt137 to i32 ; <i32> [#uses=1] - %121 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 3, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp140 = inttoptr i32 %119 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp140, %"struct.llvm::SDNode"** %121, align 8 - %122 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 3, i32 1 ; <i32*> [#uses=1] - store i32 %120, i32* %122, align 4 - %123 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 4, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp110, %"struct.llvm::SDNode"** %123, align 8 - %124 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 4, i32 1 ; <i32*> [#uses=1] - store i32 1, i32* %124, align 4 - %125 = getelementptr [5 x %"struct.llvm::SDValue"]* %Ops1, i32 0, i32 0 ; <%"struct.llvm::SDValue"*> [#uses=1] - %126 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocENS_8SDVTListEPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"* %DAG, i32 195, i32 %7, %"struct.llvm::SDVTList"* byval align 4 %NodeTys, %"struct.llvm::SDValue"* %125, i32 5) nounwind ; <i64> [#uses=2] - %127 = trunc i64 %126 to i32 ; <i32> [#uses=1] - %sroa.store.elt143 = lshr i64 %126, 32 ; <i64> [#uses=1] - %128 = trunc i64 %sroa.store.elt143 to i32 ; <i32> [#uses=1] - %tmp146 = inttoptr i32 %127 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=3] - %tmp171195 = getelementptr %"struct.llvm::MVT"* %PtrVT, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - %tmp197 = load i32* %tmp171195, align 1 ; <i32> [#uses=2] - %129 = getelementptr %"struct.llvm::MVT"* %VT, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 %tmp197, i32* %129, align 8 - %130 = getelementptr %"struct.llvm::MVT"* %VT1.i, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 %tmp197, i32* %130, align 8 - %131 = getelementptr %"struct.llvm::MVT"* %VT2.i, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 0, i32* %131, align 8 - %132 = getelementptr %"struct.llvm::MVT"* %VT3.i, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 12, i32* %132, align 8 - %133 = call i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_S1_(%"struct.llvm::SelectionDAG"* %DAG, %"struct.llvm::MVT"* byval align 4 %VT1.i, %"struct.llvm::MVT"* byval align 4 %VT2.i, %"struct.llvm::MVT"* byval align 4 %VT3.i) nounwind ; <i64> [#uses=1] - %134 = trunc i64 %133 to i32 ; <i32> [#uses=1] - %tmp4.i.i = inttoptr i32 %134 to %"struct.llvm::MVT"* ; <%"struct.llvm::MVT"*> [#uses=1] - %135 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 0, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp146, %"struct.llvm::SDNode"** %135, align 8 - %136 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %128, i32* %136, align 4 - %137 = call i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"* %DAG, i32 17, %"struct.llvm::MVT"* byval align 4 %VT) nounwind ; <i64> [#uses=2] - %138 = trunc i64 %137 to i32 ; <i32> [#uses=1] - %sroa.store.elt.i = lshr i64 %137, 32 ; <i64> [#uses=1] - %139 = trunc i64 %sroa.store.elt.i to i32 ; <i32> [#uses=1] - %140 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 1, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - %tmp5.i = inttoptr i32 %138 to %"struct.llvm::SDNode"* ; <%"struct.llvm::SDNode"*> [#uses=1] - store %"struct.llvm::SDNode"* %tmp5.i, %"struct.llvm::SDNode"** %140, align 8 - %141 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 1, i32 1 ; <i32*> [#uses=1] - store i32 %139, i32* %141, align 4 - %142 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 2, i32 0 ; <%"struct.llvm::SDNode"**> [#uses=1] - store %"struct.llvm::SDNode"* %tmp146, %"struct.llvm::SDNode"** %142, align 8 - %143 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 2, i32 1 ; <i32*> [#uses=1] - store i32 1, i32* %143, align 4 - %144 = icmp eq %"struct.llvm::SDNode"* %tmp146, null ; <i1> [#uses=1] - %iftmp.588.0.i = select i1 %144, i32 2, i32 3 ; <i32> [#uses=1] - %145 = getelementptr [3 x %"struct.llvm::SDValue"]* %Ops.i, i32 0, i32 0 ; <%"struct.llvm::SDValue"*> [#uses=1] - %146 = call i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocEPKNS_3MVTEjPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"* %DAG, i32 37, i32 %7, %"struct.llvm::MVT"* %tmp4.i.i, i32 3, %"struct.llvm::SDValue"* %145, i32 %iftmp.588.0.i) nounwind ; <i64> [#uses=1] - ret i64 %146 -} - -declare void @__assert_rtn(i8*, i8*, i32, i8*) noreturn - -declare i64 @_ZN4llvm12SelectionDAG16getGlobalAddressEPKNS_11GlobalValueENS_3MVTExb(%"struct.llvm::SelectionDAG"*, %"struct.llvm::GlobalValue"*, %"struct.llvm::MVT"* byval align 4, i64, i8 zeroext) - -declare i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_(%"struct.llvm::SelectionDAG"*, %"struct.llvm::MVT"* byval align 4, %"struct.llvm::MVT"* byval align 4) - -declare i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocENS_8SDVTListEPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"*, i32, i32, %"struct.llvm::SDVTList"* byval align 4, %"struct.llvm::SDValue"*, i32) - -declare i64 @_ZN4llvm12SelectionDAG11getRegisterEjNS_3MVTE(%"struct.llvm::SelectionDAG"*, i32, %"struct.llvm::MVT"* byval align 4) - -declare i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocEPKNS_3MVTEjPKNS_7SDValueEj(%"struct.llvm::SelectionDAG"*, i32, i32, %"struct.llvm::MVT"*, i32, %"struct.llvm::SDValue"*, i32) - -declare i64 @_ZN4llvm12SelectionDAG9getVTListENS_3MVTES1_S1_(%"struct.llvm::SelectionDAG"*, %"struct.llvm::MVT"* byval align 4, %"struct.llvm::MVT"* byval align 4, %"struct.llvm::MVT"* byval align 4) - -declare i64 @_ZN4llvm12SelectionDAG23getTargetExternalSymbolEPKcNS_3MVTE(%"struct.llvm::SelectionDAG"*, i8*, %"struct.llvm::MVT"* byval align 4) - -declare i64 @_ZN4llvm12SelectionDAG7getNodeEjNS_8DebugLocENS_3MVTE(%"struct.llvm::SelectionDAG"*, i32, i32, %"struct.llvm::MVT"* byval align 4) - -declare void @_ZNK4llvm6SDNode4dumpEv(%"struct.llvm::SDNode"*) diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index 5bd956a016269..abbe97ac193e3 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic \ +; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -asm-verbose=false \ ; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \ ; RUN: FileCheck %s ; rdar://6808032 diff --git a/test/CodeGen/X86/2009-09-07-CoalescerBug.ll b/test/CodeGen/X86/2009-09-07-CoalescerBug.ll index 55432be1c2c98..a5b4a79401ea8 100644 --- a/test/CodeGen/X86/2009-09-07-CoalescerBug.ll +++ b/test/CodeGen/X86/2009-09-07-CoalescerBug.ll @@ -8,8 +8,8 @@ define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat { ; CHECK: hammer_time: ; CHECK: movq $Xrsvd, %rax +; CHECK: movq $Xrsvd, %rsi ; CHECK: movq $Xrsvd, %rdi -; CHECK: movq $Xrsvd, %r8 entry: br i1 undef, label %if.then, label %if.end diff --git a/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll index 9e58872b73c85..7b5e871246c1f 100644 --- a/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll +++ b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll @@ -13,7 +13,6 @@ define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64 entry: ; CHECK: _t: ; CHECK: movl 16(%rbp), -; CHECK: movl 16(%rbp), %edx %0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1] %1 = zext i32 %clientPort to i64 ; <i64> [#uses=1] %2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1] diff --git a/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll index 628b8993f3470..b5be65fb002bc 100644 --- a/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll +++ b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll @@ -5,7 +5,7 @@ define void @bar(i32 %b, i32 %a) nounwind optsize ssp { entry: ; CHECK: leal 15(%rsi), %edi ; CHECK-NOT: movl -; CHECK: callq _foo +; CHECK: _foo %0 = add i32 %a, 15 ; <i32> [#uses=1] %1 = zext i32 %0 to i64 ; <i64> [#uses=1] tail call void @foo(i64 %1) nounwind diff --git a/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll b/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll new file mode 100644 index 0000000000000..275117483d621 --- /dev/null +++ b/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu +; PR6196 + +%"char[]" = type [1 x i8] + +@.str = external constant %"char[]", align 1 ; <%"char[]"*> [#uses=1] + +define i32 @regex_subst() nounwind { +entry: + %0 = tail call i32 bitcast (%"char[]"* @.str to i32 (i32)*)(i32 0) nounwind ; <i32> [#uses=1] + ret i32 %0 +} diff --git a/test/CodeGen/X86/2010-02-03-DualUndef.ll b/test/CodeGen/X86/2010-02-03-DualUndef.ll new file mode 100644 index 0000000000000..d116ecc6bde83 --- /dev/null +++ b/test/CodeGen/X86/2010-02-03-DualUndef.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -march=x86-64 +; PR6086 +define fastcc void @prepOutput() nounwind { +bb: ; preds = %output.exit + br label %bb.i1 + +bb.i1: ; preds = %bb7.i, %bb + br i1 undef, label %bb7.i, label %bb.nph.i + +bb.nph.i: ; preds = %bb.i1 + br label %bb3.i + +bb3.i: ; preds = %bb5.i6, %bb.nph.i + %tmp10.i = trunc i64 undef to i32 ; <i32> [#uses=1] + br i1 undef, label %bb4.i, label %bb5.i6 + +bb4.i: ; preds = %bb3.i + br label %bb5.i6 + +bb5.i6: ; preds = %bb4.i, %bb3.i + %0 = phi i32 [ undef, %bb4.i ], [ undef, %bb3.i ] ; <i32> [#uses=1] + %1 = icmp slt i32 %0, %tmp10.i ; <i1> [#uses=1] + br i1 %1, label %bb7.i, label %bb3.i + +bb7.i: ; preds = %bb5.i6, %bb.i1 + br label %bb.i1 +} diff --git a/test/CodeGen/X86/2010-02-04-SchedulerBug.ll b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll new file mode 100644 index 0000000000000..c966e21d52dfc --- /dev/null +++ b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin11 +; rdar://7604000 + +%struct.a_t = type { i8*, i64*, i8*, i32, i32, i64*, i64*, i64* } +%struct.b_t = type { i32, i32, i32, i32, i64, i64, i64, i64 } + +define void @t(i32 %cNum, i64 %max) nounwind optsize ssp noimplicitfloat { +entry: + %0 = load %struct.b_t** null, align 4 ; <%struct.b_t*> [#uses=1] + %1 = getelementptr inbounds %struct.b_t* %0, i32 %cNum, i32 5 ; <i64*> [#uses=1] + %2 = load i64* %1, align 4 ; <i64> [#uses=1] + %3 = icmp ult i64 %2, %max ; <i1> [#uses=1] + %4 = getelementptr inbounds %struct.a_t* null, i32 0, i32 7 ; <i64**> [#uses=1] + %5 = load i64** %4, align 4 ; <i64*> [#uses=0] + %6 = load i64* null, align 4 ; <i64> [#uses=1] + br i1 %3, label %bb2, label %bb + +bb: ; preds = %entry + br label %bb3 + +bb2: ; preds = %entry + %7 = or i64 %6, undef ; <i64> [#uses=1] + br label %bb3 + +bb3: ; preds = %bb2, %bb + %misc_enables.0 = phi i64 [ undef, %bb ], [ %7, %bb2 ] ; <i64> [#uses=0] + ret void +} diff --git a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll new file mode 100644 index 0000000000000..c5d3d16f81aab --- /dev/null +++ b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll @@ -0,0 +1,260 @@ +; RUN: llc < %s > %t +; PR6283 + +; Tricky coalescer bug: +; After coalescing %RAX with a virtual register, this instruction was rematted: +; +; %EAX<def> = MOV32rr %reg1070<kill> +; +; This instruction silently defined %RAX, and when rematting removed the +; instruction, the live interval for %RAX was not properly updated. The valno +; referred to a deleted instruction and bad things happened. +; +; The fix is to implicitly define %RAX when coalescing: +; +; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def> +; + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\22" + +%0 = type { %"union gimple_statement_d"* } +%"BITMAP_WORD[]" = type [2 x i64] +%"char[]" = type [4 x i8] +%"enum dom_state[]" = type [2 x i32] +%"int[]" = type [4 x i32] +%"struct VEC_basic_block_base" = type { i32, i32, [1 x %"struct basic_block_def"*] } +%"struct VEC_basic_block_gc" = type { %"struct VEC_basic_block_base" } +%"struct VEC_edge_base" = type { i32, i32, [1 x %"struct edge_def"*] } +%"struct VEC_edge_gc" = type { %"struct VEC_edge_base" } +%"struct VEC_gimple_base" = type { i32, i32, [1 x %"union gimple_statement_d"*] } +%"struct VEC_gimple_gc" = type { %"struct VEC_gimple_base" } +%"struct VEC_iv_cand_p_base" = type { i32, i32, [1 x %"struct iv_cand"*] } +%"struct VEC_iv_cand_p_heap" = type { %"struct VEC_iv_cand_p_base" } +%"struct VEC_iv_use_p_base" = type { i32, i32, [1 x %"struct iv_use"*] } +%"struct VEC_iv_use_p_heap" = type { %"struct VEC_iv_use_p_base" } +%"struct VEC_loop_p_base" = type { i32, i32, [1 x %"struct loop"*] } +%"struct VEC_loop_p_gc" = type { %"struct VEC_loop_p_base" } +%"struct VEC_rtx_base" = type { i32, i32, [1 x %"struct rtx_def"*] } +%"struct VEC_rtx_gc" = type { %"struct VEC_rtx_base" } +%"struct VEC_tree_base" = type { i32, i32, [1 x %"union tree_node"*] } +%"struct VEC_tree_gc" = type { %"struct VEC_tree_base" } +%"struct _obstack_chunk" = type { i8*, %"struct _obstack_chunk"*, %"char[]" } +%"struct basic_block_def" = type { %"struct VEC_edge_gc"*, %"struct VEC_edge_gc"*, i8*, %"struct loop"*, [2 x %"struct et_node"*], %"struct basic_block_def"*, %"struct basic_block_def"*, %"union basic_block_il_dependent", i64, i32, i32, i32, i32, i32 } +%"struct bitmap_element" = type { %"struct bitmap_element"*, %"struct bitmap_element"*, i32, %"BITMAP_WORD[]" } +%"struct bitmap_head_def" = type { %"struct bitmap_element"*, %"struct bitmap_element"*, i32, %"struct bitmap_obstack"* } +%"struct bitmap_obstack" = type { %"struct bitmap_element"*, %"struct bitmap_head_def"*, %"struct obstack" } +%"struct block_symbol" = type { [3 x %"union rtunion"], %"struct object_block"*, i64 } +%"struct comp_cost" = type { i32, i32 } +%"struct control_flow_graph" = type { %"struct basic_block_def"*, %"struct basic_block_def"*, %"struct VEC_basic_block_gc"*, i32, i32, i32, %"struct VEC_basic_block_gc"*, i32, %"enum dom_state[]", %"enum dom_state[]", i32, i32 } +%"struct cost_pair" = type { %"struct iv_cand"*, %"struct comp_cost", %"struct bitmap_head_def"*, %"union tree_node"* } +%"struct def_optype_d" = type { %"struct def_optype_d"*, %"union tree_node"** } +%"struct double_int" = type { i64, i64 } +%"struct edge_def" = type { %"struct basic_block_def"*, %"struct basic_block_def"*, %"union edge_def_insns", i8*, %"union tree_node"*, i32, i32, i32, i32, i64 } +%"struct eh_status" = type opaque +%"struct et_node" = type opaque +%"struct function" = type { %"struct eh_status"*, %"struct control_flow_graph"*, %"struct gimple_seq_d"*, %"struct gimple_df"*, %"struct loops"*, %"struct htab"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"struct machine_function"*, %"struct language_function"*, %"struct htab"*, i32, i32, i32, i32, i32, i32, i8*, i8, i8, i8, i8 } +%"struct gimple_bb_info" = type { %"struct gimple_seq_d"*, %"struct gimple_seq_d"* } +%"struct gimple_df" = type { %"struct htab"*, %"struct VEC_gimple_gc"*, %"struct VEC_tree_gc"*, %"union tree_node"*, %"struct pt_solution", %"struct pt_solution", %"struct pointer_map_t"*, %"union tree_node"*, %"struct htab"*, %"struct bitmap_head_def"*, i8, %"struct ssa_operands" } +%"struct gimple_seq_d" = type { %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_d"* } +%"struct gimple_seq_node_d" = type { %"union gimple_statement_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"* } +%"struct gimple_statement_base" = type { i8, i8, i16, i32, i32, i32, %"struct basic_block_def"*, %"union tree_node"* } +%"struct gimple_statement_phi" = type { %"struct gimple_statement_base", i32, i32, %"union tree_node"*, %"struct phi_arg_d[]" } +%"struct htab" = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i64, i64, i64, i32, i32, i8* (i64, i64)*, void (i8*)*, i8*, i8* (i8*, i64, i64)*, void (i8*, i8*)*, i32 } +%"struct iv" = type { %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, i8, i8, i32 } +%"struct iv_cand" = type { i32, i8, i32, %"union gimple_statement_d"*, %"union tree_node"*, %"union tree_node"*, %"struct iv"*, i32, i32, %"struct iv_use"*, %"struct bitmap_head_def"* } +%"struct iv_use" = type { i32, i32, %"struct iv"*, %"union gimple_statement_d"*, %"union tree_node"**, %"struct bitmap_head_def"*, i32, %"struct cost_pair"*, %"struct iv_cand"* } +%"struct ivopts_data" = type { %"struct loop"*, %"struct pointer_map_t"*, i32, i32, %"struct version_info"*, %"struct bitmap_head_def"*, %"struct VEC_iv_use_p_heap"*, %"struct VEC_iv_cand_p_heap"*, %"struct bitmap_head_def"*, i32, i8, i8 } +%"struct lang_decl" = type opaque +%"struct language_function" = type opaque +%"struct loop" = type { i32, i32, %"struct basic_block_def"*, %"struct basic_block_def"*, %"struct comp_cost", i32, i32, %"struct VEC_loop_p_gc"*, %"struct loop"*, %"struct loop"*, i8*, %"union tree_node"*, %"struct double_int", %"struct double_int", i8, i8, i32, %"struct nb_iter_bound"*, %"struct loop_exit"*, i8, %"union tree_node"* } +%"struct loop_exit" = type { %"struct edge_def"*, %"struct loop_exit"*, %"struct loop_exit"*, %"struct loop_exit"* } +%"struct loops" = type { i32, %"struct VEC_loop_p_gc"*, %"struct htab"*, %"struct loop"* } +%"struct machine_cfa_state" = type { %"struct rtx_def"*, i64 } +%"struct machine_function" = type { %"struct stack_local_entry"*, i8*, i32, i32, %"int[]", i32, %"struct machine_cfa_state", i32, i8 } +%"struct nb_iter_bound" = type { %"union gimple_statement_d"*, %"struct double_int", i8, %"struct nb_iter_bound"* } +%"struct object_block" = type { %"union section"*, i32, i64, %"struct VEC_rtx_gc"*, %"struct VEC_rtx_gc"* } +%"struct obstack" = type { i64, %"struct _obstack_chunk"*, i8*, i8*, i8*, i64, i32, %"struct _obstack_chunk"* (i8*, i64)*, void (i8*, %"struct _obstack_chunk"*)*, i8*, i8 } +%"struct phi_arg_d" = type { %"struct ssa_use_operand_d", %"union tree_node"*, i32 } +%"struct phi_arg_d[]" = type [1 x %"struct phi_arg_d"] +%"struct pointer_map_t" = type opaque +%"struct pt_solution" = type { i8, %"struct bitmap_head_def"* } +%"struct rtx_def" = type { i16, i8, i8, %"union u" } +%"struct section_common" = type { i32 } +%"struct ssa_operand_memory_d" = type { %"struct ssa_operand_memory_d"*, %"uchar[]" } +%"struct ssa_operands" = type { %"struct ssa_operand_memory_d"*, i32, i32, i8, %"struct def_optype_d"*, %"struct use_optype_d"* } +%"struct ssa_use_operand_d" = type { %"struct ssa_use_operand_d"*, %"struct ssa_use_operand_d"*, %0, %"union tree_node"** } +%"struct stack_local_entry" = type opaque +%"struct tree_base" = type <{ i16, i8, i8, i8, [2 x i8], i8 }> +%"struct tree_common" = type { %"struct tree_base", %"union tree_node"*, %"union tree_node"* } +%"struct tree_decl_common" = type { %"struct tree_decl_minimal", %"union tree_node"*, i8, i8, i8, i8, i8, i32, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"struct lang_decl"* } +%"struct tree_decl_minimal" = type { %"struct tree_common", i32, i32, %"union tree_node"*, %"union tree_node"* } +%"struct tree_decl_non_common" = type { %"struct tree_decl_with_vis", %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"* } +%"struct tree_decl_with_rtl" = type { %"struct tree_decl_common", %"struct rtx_def"* } +%"struct tree_decl_with_vis" = type { %"struct tree_decl_with_rtl", %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, i8, i8, i8 } +%"struct tree_function_decl" = type { %"struct tree_decl_non_common", %"struct function"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, i16, i8, i8 } +%"struct unnamed_section" = type { %"struct section_common", void (i8*)*, i8*, %"union section"* } +%"struct use_optype_d" = type { %"struct use_optype_d"*, %"struct ssa_use_operand_d" } +%"struct version_info" = type { %"union tree_node"*, %"struct iv"*, i8, i32, i8 } +%"uchar[]" = type [1 x i8] +%"union basic_block_il_dependent" = type { %"struct gimple_bb_info"* } +%"union edge_def_insns" = type { %"struct gimple_seq_d"* } +%"union gimple_statement_d" = type { %"struct gimple_statement_phi" } +%"union rtunion" = type { i8* } +%"union section" = type { %"struct unnamed_section" } +%"union tree_node" = type { %"struct tree_function_decl" } +%"union u" = type { %"struct block_symbol" } + +declare fastcc %"union tree_node"* @get_computation_at(%"struct loop"*, %"struct iv_use"* nocapture, %"struct iv_cand"* nocapture, %"union gimple_statement_d"*) nounwind + +declare fastcc i32 @computation_cost(%"union tree_node"*, i8 zeroext) nounwind + +define fastcc i64 @get_computation_cost_at(%"struct ivopts_data"* %data, %"struct iv_use"* nocapture %use, %"struct iv_cand"* nocapture %cand, i8 zeroext %address_p, %"struct bitmap_head_def"** %depends_on, %"union gimple_statement_d"* %at, i8* %can_autoinc) nounwind { +entry: + br i1 undef, label %"100", label %"4" + +"4": ; preds = %entry + br i1 undef, label %"6", label %"5" + +"5": ; preds = %"4" + unreachable + +"6": ; preds = %"4" + br i1 undef, label %"8", label %"7" + +"7": ; preds = %"6" + unreachable + +"8": ; preds = %"6" + br i1 undef, label %"100", label %"10" + +"10": ; preds = %"8" + br i1 undef, label %"17", label %"16" + +"16": ; preds = %"10" + unreachable + +"17": ; preds = %"10" + br i1 undef, label %"19", label %"18" + +"18": ; preds = %"17" + unreachable + +"19": ; preds = %"17" + br i1 undef, label %"93", label %"20" + +"20": ; preds = %"19" + br i1 undef, label %"23", label %"21" + +"21": ; preds = %"20" + unreachable + +"23": ; preds = %"20" + br i1 undef, label %"100", label %"25" + +"25": ; preds = %"23" + br i1 undef, label %"100", label %"26" + +"26": ; preds = %"25" + br i1 undef, label %"30", label %"28" + +"28": ; preds = %"26" + unreachable + +"30": ; preds = %"26" + br i1 undef, label %"59", label %"51" + +"51": ; preds = %"30" + br i1 undef, label %"55", label %"52" + +"52": ; preds = %"51" + unreachable + +"55": ; preds = %"51" + %0 = icmp ugt i32 0, undef ; <i1> [#uses=1] + br i1 %0, label %"50.i", label %"9.i" + +"9.i": ; preds = %"55" + unreachable + +"50.i": ; preds = %"55" + br i1 undef, label %"55.i", label %"54.i" + +"54.i": ; preds = %"50.i" + br i1 undef, label %"57.i", label %"55.i" + +"55.i": ; preds = %"54.i", %"50.i" + unreachable + +"57.i": ; preds = %"54.i" + br label %"63.i" + +"61.i": ; preds = %"63.i" + br i1 undef, label %"64.i", label %"62.i" + +"62.i": ; preds = %"61.i" + br label %"63.i" + +"63.i": ; preds = %"62.i", %"57.i" + br i1 undef, label %"61.i", label %"64.i" + +"64.i": ; preds = %"63.i", %"61.i" + unreachable + +"59": ; preds = %"30" + br i1 undef, label %"60", label %"82" + +"60": ; preds = %"59" + br i1 undef, label %"61", label %"82" + +"61": ; preds = %"60" + br i1 undef, label %"62", label %"82" + +"62": ; preds = %"61" + br i1 undef, label %"100", label %"63" + +"63": ; preds = %"62" + br i1 undef, label %"65", label %"64" + +"64": ; preds = %"63" + unreachable + +"65": ; preds = %"63" + br i1 undef, label %"66", label %"67" + +"66": ; preds = %"65" + unreachable + +"67": ; preds = %"65" + %1 = load i32* undef, align 4 ; <i32> [#uses=0] + br label %"100" + +"82": ; preds = %"61", %"60", %"59" + unreachable + +"93": ; preds = %"19" + %2 = call fastcc %"union tree_node"* @get_computation_at(%"struct loop"* undef, %"struct iv_use"* %use, %"struct iv_cand"* %cand, %"union gimple_statement_d"* %at) nounwind ; <%"union tree_node"*> [#uses=1] + br i1 undef, label %"100", label %"97" + +"97": ; preds = %"93" + br i1 undef, label %"99", label %"98" + +"98": ; preds = %"97" + br label %"99" + +"99": ; preds = %"98", %"97" + %3 = phi %"union tree_node"* [ undef, %"98" ], [ %2, %"97" ] ; <%"union tree_node"*> [#uses=1] + %4 = call fastcc i32 @computation_cost(%"union tree_node"* %3, i8 zeroext undef) nounwind ; <i32> [#uses=1] + br label %"100" + +"100": ; preds = %"99", %"93", %"67", %"62", %"25", %"23", %"8", %entry + %memtmp1.1.0 = phi i32 [ 0, %"99" ], [ 10000000, %entry ], [ 10000000, %"8" ], [ 10000000, %"23" ], [ 10000000, %"25" ], [ undef, %"62" ], [ undef, %"67" ], [ 10000000, %"93" ] ; <i32> [#uses=1] + %memtmp1.0.0 = phi i32 [ %4, %"99" ], [ 10000000, %entry ], [ 10000000, %"8" ], [ 10000000, %"23" ], [ 10000000, %"25" ], [ undef, %"62" ], [ undef, %"67" ], [ 10000000, %"93" ] ; <i32> [#uses=1] + %5 = zext i32 %memtmp1.0.0 to i64 ; <i64> [#uses=1] + %6 = zext i32 %memtmp1.1.0 to i64 ; <i64> [#uses=1] + %7 = shl i64 %6, 32 ; <i64> [#uses=1] + %8 = or i64 %7, %5 ; <i64> [#uses=1] + ret i64 %8 +} diff --git a/test/CodeGen/X86/2010-02-15-ImplicitDefBug.ll b/test/CodeGen/X86/2010-02-15-ImplicitDefBug.ll new file mode 100644 index 0000000000000..c429172852dfc --- /dev/null +++ b/test/CodeGen/X86/2010-02-15-ImplicitDefBug.ll @@ -0,0 +1,80 @@ +; RUN: llc < %s > %t +; PR6300 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +; When the "154" loops back onto itself, it defines a register after using it. +; The first value of the register is implicit-def. + +%"struct location_chain_def" = type { %"struct location_chain_def"*, %"struct rtx_def"*, %"struct rtx_def"*, i32 } +%"struct real_value" = type { i32, [5 x i32] } +%"struct rtx_def" = type { i16, i8, i8, %"union u" } +%"union u" = type { %"struct real_value" } + +define i32 @variable_union(i8** nocapture %slot, i8* nocapture %data) nounwind { +entry: + br i1 undef, label %"4.thread", label %"3" + +"4.thread": ; preds = %entry + unreachable + +"3": ; preds = %entry + br i1 undef, label %"19", label %"20" + +"19": ; preds = %"3" + unreachable + +"20": ; preds = %"3" + br i1 undef, label %"56.preheader", label %dv_onepart_p.exit + +dv_onepart_p.exit: ; preds = %"20" + unreachable + +"56.preheader": ; preds = %"20" + br label %"56" + +"50": ; preds = %"57" + br label %"56" + +"56": ; preds = %"50", %"56.preheader" + br i1 undef, label %"57", label %"58" + +"57": ; preds = %"56" + br i1 undef, label %"50", label %"58" + +"58": ; preds = %"57", %"56" + br i1 undef, label %"62", label %"63" + +"62": ; preds = %"58" + unreachable + +"63": ; preds = %"58" + br i1 undef, label %"67", label %"66" + +"66": ; preds = %"63" + br label %"67" + +"67": ; preds = %"66", %"63" + br label %"68" + +"68": ; preds = %"161", %"67" + br i1 undef, label %"153", label %"161" + +"153": ; preds = %"68" + br i1 undef, label %"160", label %bb.nph46 + +bb.nph46: ; preds = %"153" + br label %"154" + +"154": ; preds = %"154", %bb.nph46 + %0 = phi %"struct location_chain_def"** [ undef, %bb.nph46 ], [ %1, %"154" ] ; <%"struct location_chain_def"**> [#uses=1] + %1 = bitcast i8* undef to %"struct location_chain_def"** ; <%"struct location_chain_def"**> [#uses=1] + store %"struct location_chain_def"* undef, %"struct location_chain_def"** %0, align 4 + br i1 undef, label %"160", label %"154" + +"160": ; preds = %"154", %"153" + br label %"161" + +"161": ; preds = %"160", %"68" + br label %"68" +} diff --git a/test/CodeGen/X86/SwitchLowering.ll b/test/CodeGen/X86/SwitchLowering.ll new file mode 100644 index 0000000000000..29a0e82bf59f1 --- /dev/null +++ b/test/CodeGen/X86/SwitchLowering.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=x86 | grep cmp | count 1 +; PR964 + +define i8* @FindChar(i8* %CurPtr) { +entry: + br label %bb + +bb: ; preds = %bb, %entry + %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3] + %CurPtr_addr.0.rec = bitcast i32 %indvar to i32 ; <i32> [#uses=1] + %gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1] + %CurPtr_addr.0 = getelementptr i8* %CurPtr, i64 %gep.upgrd.1 ; <i8*> [#uses=1] + %tmp = load i8* %CurPtr_addr.0 ; <i8> [#uses=3] + %tmp2.rec = add i32 %CurPtr_addr.0.rec, 1 ; <i32> [#uses=1] + %tmp2 = getelementptr i8* %CurPtr, i32 %tmp2.rec ; <i8*> [#uses=1] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] + switch i8 %tmp, label %bb [ + i8 0, label %bb7 + i8 120, label %bb7 + ] + +bb7: ; preds = %bb, %bb + tail call void @foo( i8 %tmp ) + ret i8* %tmp2 +} + +declare void @foo(i8) + diff --git a/test/CodeGen/X86/add-trick32.ll b/test/CodeGen/X86/add-trick32.ll deleted file mode 100644 index e86045db0abb0..0000000000000 --- a/test/CodeGen/X86/add-trick32.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: not grep add %t -; RUN: grep subl %t | count 1 - -; The immediate can be encoded in a smaller way if the -; instruction is a sub instead of an add. - -define i32 @foo(i32 inreg %a) nounwind { - %b = add i32 %a, 128 - ret i32 %b -} diff --git a/test/CodeGen/X86/add-trick64.ll b/test/CodeGen/X86/add-trick64.ll deleted file mode 100644 index 2f1fceea5ea49..0000000000000 --- a/test/CodeGen/X86/add-trick64.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: not grep add %t -; RUN: grep subq %t | count 2 - -; The immediate can be encoded in a smaller way if the -; instruction is a sub instead of an add. - -define i64 @foo(i64 inreg %a) nounwind { - %b = add i64 %a, 2147483648 - ret i64 %b -} -define i64 @bar(i64 inreg %a) nounwind { - %b = add i64 %a, 128 - ret i64 %b -} diff --git a/test/CodeGen/X86/add-with-overflow.ll b/test/CodeGen/X86/add-with-overflow.ll deleted file mode 100644 index 0f705dc020883..0000000000000 --- a/test/CodeGen/X86/add-with-overflow.ll +++ /dev/null @@ -1,75 +0,0 @@ -; RUN: llc < %s -march=x86 | grep {jo} | count 2 -; RUN: llc < %s -march=x86 | grep {jb} | count 2 -; RUN: llc < %s -march=x86 -O0 | grep {jo} | count 2 -; RUN: llc < %s -march=x86 -O0 | grep {jb} | count 2 - -@ok = internal constant [4 x i8] c"%d\0A\00" -@no = internal constant [4 x i8] c"no\0A\00" - -define i1 @func1(i32 %v1, i32 %v2) nounwind { -entry: - %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) - %sum = extractvalue {i32, i1} %t, 0 - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %overflow, label %normal - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind - ret i1 true - -overflow: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false -} - -define i1 @func2(i32 %v1, i32 %v2) nounwind { -entry: - %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) - %sum = extractvalue {i32, i1} %t, 0 - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %carry, label %normal - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind - ret i1 true - -carry: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false -} - -define i1 @func3() nounwind { -entry: - %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 0, i32 0) - %sum = extractvalue {i32, i1} %t, 0 - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %carry, label %normal - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind - ret i1 true - -carry: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false -} - -define i1 @func4() nounwind { -entry: - %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 0, i32 0) - %sum = extractvalue {i32, i1} %t, 0 - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %carry, label %normal - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind - ret i1 true - -carry: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false -} - -declare i32 @printf(i8*, ...) nounwind -declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) -declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll new file mode 100644 index 0000000000000..3991a6849f3ed --- /dev/null +++ b/test/CodeGen/X86/add.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64 + +; The immediate can be encoded in a smaller way if the +; instruction is a sub instead of an add. + +define i32 @test1(i32 inreg %a) nounwind { + %b = add i32 %a, 128 + ret i32 %b +; X32: subl $-128, %eax +; X64: subl $-128, +} +define i64 @test2(i64 inreg %a) nounwind { + %b = add i64 %a, 2147483648 + ret i64 %b +; X32: addl $-2147483648, %eax +; X64: subq $-2147483648, +} +define i64 @test3(i64 inreg %a) nounwind { + %b = add i64 %a, 128 + ret i64 %b + +; X32: addl $128, %eax +; X64: subq $-128, +} + +define i1 @test4(i32 %v1, i32 %v2, i32* %X) nounwind { +entry: + %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) + %sum = extractvalue {i32, i1} %t, 0 + %obit = extractvalue {i32, i1} %t, 1 + br i1 %obit, label %overflow, label %normal + +normal: + store i32 0, i32* %X + br label %overflow + +overflow: + ret i1 false + +; X32: test4: +; X32: addl +; X32-NEXT: jo + +; X64: test4: +; X64: addl %esi, %edi +; X64-NEXT: jo +} + +define i1 @test5(i32 %v1, i32 %v2, i32* %X) nounwind { +entry: + %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) + %sum = extractvalue {i32, i1} %t, 0 + %obit = extractvalue {i32, i1} %t, 1 + br i1 %obit, label %carry, label %normal + +normal: + store i32 0, i32* %X + br label %carry + +carry: + ret i1 false + +; X32: test5: +; X32: addl +; X32-NEXT: jb + +; X64: test5: +; X64: addl %esi, %edi +; X64-NEXT: jb +} + +declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) +declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) + + +define i64 @test6(i64 %A, i32 %B) nounwind { + %tmp12 = zext i32 %B to i64 ; <i64> [#uses=1] + %tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1] + %tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1] + ret i64 %tmp5 + +; X32: test6: +; X32: movl 12(%esp), %edx +; X32-NEXT: addl 8(%esp), %edx +; X32-NEXT: movl 4(%esp), %eax +; X32-NEXT: ret + +; X64: test6: +; X64: shlq $32, %rsi +; X64: leaq (%rsi,%rdi), %rax +; X64: ret +} + diff --git a/test/CodeGen/X86/addr-label-difference.ll b/test/CodeGen/X86/addr-label-difference.ll index 547d6b57657a7..be0908aa1a9d7 100644 --- a/test/CodeGen/X86/addr-label-difference.ll +++ b/test/CodeGen/X86/addr-label-difference.ll @@ -9,14 +9,18 @@ target triple = "i386-apple-darwin10.0" define void @test(i32 %i) nounwind ssp { entry: + call void @test(i32 1) br label %foo -foo: ; preds = %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto +foo: + call void @test(i32 1) br label %bar -bar: ; preds = %foo, %indirectgoto +bar: + call void @test(i32 1) br label %hack -hack: ; preds = %bar, %indirectgoto +hack: + call void @test(i32 1) ret void } diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll index 0b26859b04c73..3020eb3c7192b 100644 --- a/test/CodeGen/X86/aliases.ll +++ b/test/CodeGen/X86/aliases.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t -; RUN: grep set %t | count 7 +; RUN: grep { = } %t | count 7 +; RUN: grep set %t | count 16 ; RUN: grep globl %t | count 6 ; RUN: grep weak %t | count 1 ; RUN: grep hidden %t | count 1 diff --git a/test/CodeGen/X86/aligned-comm.ll b/test/CodeGen/X86/aligned-comm.ll index c0f3a81c4d67e..7715869ed99cf 100644 --- a/test/CodeGen/X86/aligned-comm.ll +++ b/test/CodeGen/X86/aligned-comm.ll @@ -1,8 +1,6 @@ ; RUN: llc < %s -march=x86 ; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep {array,16512,7} ; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep {array,16512,7} -; RUN: llc < %s -mtriple=i386-apple-darwin8 | not grep {7} -; Darwin 9+ should get alignment on common symbols. Darwin8 does -; not support this. +; Darwin 9+ should get alignment on common symbols. @array = common global [4128 x i32] zeroinitializer, align 128 diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll index 7bae5cd2464d5..02cbccc1a492f 100644 --- a/test/CodeGen/X86/call-push.ll +++ b/test/CodeGen/X86/call-push.ll @@ -1,9 +1,14 @@ -; RUN: llc < %s -march=x86 -disable-fp-elim | grep subl | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim | FileCheck %s %struct.decode_t = type { i8, i8, i8, i8, i16, i8, i8, %struct.range_t** } %struct.range_t = type { float, float, i32, i32, i32, [0 x i8] } -define i32 @decode_byte(%struct.decode_t* %decode) { +define i32 @decode_byte(%struct.decode_t* %decode) nounwind { +; CHECK: decode_byte: +; CHECK: pushl +; CHECK: popl +; CHECK: popl +; CHECK: jmp entry: %tmp2 = getelementptr %struct.decode_t* %decode, i32 0, i32 4 ; <i16*> [#uses=1] %tmp23 = bitcast i16* %tmp2 to i32* ; <i32*> [#uses=1] diff --git a/test/CodeGen/X86/twoaddr-delete.ll b/test/CodeGen/X86/codegen-dce.ll index 77e3c75c6dd0b..d83efaf577661 100644 --- a/test/CodeGen/X86/twoaddr-delete.ll +++ b/test/CodeGen/X86/codegen-dce.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -stats |& grep {twoaddrinstr} | grep {Number of dead instructions deleted} +; RUN: llc < %s -march=x86 -stats |& grep {codegen-dce} | grep {Number of dead instructions deleted} %struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] } %struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* } diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 337f1b2a8e75f..8e38fe309f7c5 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,19 +1,20 @@ ; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \ -; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5 +; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10 ; RUN: grep {leal 1(\%rsi),} %t -define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind optsize { +define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize { entry: %0 = add i32 %i2, 1 ; <i32> [#uses=1] %1 = sext i32 %0 to i64 ; <i64> [#uses=1] - %2 = getelementptr i8* null, i64 %1 ; <i8*> [#uses=1] + %2 = getelementptr i8* %ptr, i64 %1 ; <i8*> [#uses=1] %3 = load i8* %2, align 1 ; <i8> [#uses=1] %4 = icmp eq i8 0, %3 ; <i1> [#uses=1] br i1 %4, label %bb3, label %bb34 bb3: ; preds = %entry %5 = add i32 %i2, 4 ; <i32> [#uses=0] - ret i8 0 + %6 = trunc i32 %5 to i8 + ret i8 %6 bb34: ; preds = %entry ret i8 0 diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll new file mode 100644 index 0000000000000..2c699bfb0db42 --- /dev/null +++ b/test/CodeGen/X86/dllexport.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s | FileCheck %s +; PR2936 + +target triple = "i386-mingw32" + +define dllexport x86_fastcallcc i32 @foo() nounwind { +entry: + ret i32 0 +} + +; CHECK: .section .drectve +; CHECK: -export:@foo@0
\ No newline at end of file diff --git a/test/CodeGen/X86/fastcall-correct-mangling.ll b/test/CodeGen/X86/fastcall-correct-mangling.ll index 2b48f5f371d9d..33b18bb8cc6ec 100644 --- a/test/CodeGen/X86/fastcall-correct-mangling.ll +++ b/test/CodeGen/X86/fastcall-correct-mangling.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -mtriple=i386-unknown-mingw32 | \ -; RUN: grep {@12} +; RUN: llc < %s -mtriple=i386-unknown-mingw32 | FileCheck %s ; Check that a fastcall function gets correct mangling define x86_fastcallcc void @func(i64 %X, i8 %Y, i8 %G, i16 %Z) { +; CHECK: @func@20: ret void } diff --git a/test/CodeGen/X86/full-lsr.ll b/test/CodeGen/X86/full-lsr.ll index 3bd58b65be498..ff9b1b0b6a5a8 100644 --- a/test/CodeGen/X86/full-lsr.ll +++ b/test/CodeGen/X86/full-lsr.ll @@ -1,12 +1,7 @@ ; RUN: llc < %s -march=x86 >%t -; TODO: Enhance full lsr mode to get this: -; RUNX: grep {addl \\\$4,} %t | count 3 -; RUNX: not grep {,%} %t - -; For now, it should find this, which is still pretty good: -; RUN: not grep {addl \\\$4,} %t -; RUN: grep {,%} %t | count 6 +; RUN: grep {addl \\\$4,} %t | count 3 +; RUN: not grep {,%} %t define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind { entry: diff --git a/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/test/CodeGen/X86/ins_subreg_coalesce-3.ll index e44308583297c..627edc51c18d7 100644 --- a/test/CodeGen/X86/ins_subreg_coalesce-3.ll +++ b/test/CodeGen/X86/ins_subreg_coalesce-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep mov | count 11 +; RUN: llc < %s -march=x86-64 | grep mov | count 5 %struct.COMPOSITE = type { i8, i16, i16 } %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } diff --git a/test/CodeGen/X86/iv-users-in-other-loops.ll b/test/CodeGen/X86/iv-users-in-other-loops.ll index c695c29e068f5..408fb20b8d891 100644 --- a/test/CodeGen/X86/iv-users-in-other-loops.ll +++ b/test/CodeGen/X86/iv-users-in-other-loops.ll @@ -1,11 +1,11 @@ ; RUN: llc < %s -march=x86-64 -o %t -; RUN: grep inc %t | count 1 +; RUN: not grep inc %t ; RUN: grep dec %t | count 2 ; RUN: grep addq %t | count 13 ; RUN: not grep addb %t -; RUN: grep leaq %t | count 9 -; RUN: grep leal %t | count 3 -; RUN: grep movq %t | count 5 +; RUN: not grep leaq %t +; RUN: not grep leal %t +; RUN: not grep movq %t ; IV users in each of the loops from other loops shouldn't cause LSR ; to insert new induction variables. Previously it would create a diff --git a/test/CodeGen/X86/loop-strength-reduce-2.ll b/test/CodeGen/X86/loop-strength-reduce-2.ll index 30b5114349480..b546462b684fb 100644 --- a/test/CodeGen/X86/loop-strength-reduce-2.ll +++ b/test/CodeGen/X86/loop-strength-reduce-2.ll @@ -1,11 +1,24 @@ -; RUN: llc < %s -march=x86 -relocation-model=pic | \ -; RUN: grep {, 4} | count 1 -; RUN: llc < %s -march=x86 | not grep lea +; RUN: llc < %s -march=x86 -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s -check-prefix=STATIC ; ; Make sure the common loop invariant A is hoisted up to preheader, ; since too many registers are needed to subsume it into the addressing modes. ; It's safe to sink A in when it's not pic. +; PIC: align +; PIC: movl $4, -4([[REG:%e[a-z]+]]) +; PIC: movl $5, ([[REG]]) +; PIC: addl $4, [[REG]] +; PIC: decl {{%e[[a-z]+}} +; PIC: jne + +; STATIC: align +; STATIC: movl $4, -4(%ecx) +; STATIC: movl $5, (%ecx) +; STATIC: addl $4, %ecx +; STATIC: decl %eax +; STATIC: jne + @A = global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2] define void @test(i32 %row, i32 %N.in) nounwind { diff --git a/test/CodeGen/X86/loop-strength-reduce-3.ll b/test/CodeGen/X86/loop-strength-reduce-3.ll index 70c91340c9488..b1c9fb9c0772b 100644 --- a/test/CodeGen/X86/loop-strength-reduce-3.ll +++ b/test/CodeGen/X86/loop-strength-reduce-3.ll @@ -1,8 +1,11 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | \ -; RUN: grep {A+} | count 2 -; -; Make sure the common loop invariant A is not hoisted up to preheader, -; since it can be subsumed it into the addressing modes. +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s + +; CHECK: align +; CHECK: movl $4, -4(%ecx) +; CHECK: movl $5, (%ecx) +; CHECK: addl $4, %ecx +; CHECK: decl %eax +; CHECK: jne @A = global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2] diff --git a/test/CodeGen/X86/loop-strength-reduce.ll b/test/CodeGen/X86/loop-strength-reduce.ll index 4cb56ca9ed245..42c6ac4983dbe 100644 --- a/test/CodeGen/X86/loop-strength-reduce.ll +++ b/test/CodeGen/X86/loop-strength-reduce.ll @@ -1,8 +1,11 @@ -; RUN: llc < %s -march=x86 -relocation-model=static | \ -; RUN: grep {A+} | count 2 -; -; Make sure the common loop invariant A is not hoisted up to preheader, -; since it can be subsumed into the addressing mode in all uses. +; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s + +; CHECK: align +; CHECK: movl $4, -4(%ecx) +; CHECK: movl $5, (%ecx) +; CHECK: addl $4, %ecx +; CHECK: decl %eax +; CHECK: jne @A = internal global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2] diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll index 07e46eca75e9f..6c0eb8c0df93d 100644 --- a/test/CodeGen/X86/loop-strength-reduce4.ll +++ b/test/CodeGen/X86/loop-strength-reduce4.ll @@ -1,5 +1,19 @@ -; RUN: llc < %s -march=x86 | grep cmp | grep 64 -; RUN: llc < %s -march=x86 | not grep inc +; RUN: llc < %s -march=x86 -relocation-model=static -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -march=x86 -relocation-model=pic | FileCheck %s -check-prefix=PIC + +; By starting the IV at -64 instead of 0, a cmp is eliminated, +; as the flags from the add can be used directly. + +; STATIC: movl $-64, %ecx + +; STATIC: movl %eax, _state+76(%ecx) +; STATIC: addl $16, %ecx +; STATIC: jne + +; In PIC mode the symbol can't be folded, so the change-compare-stride +; trick applies. + +; PIC: cmpl $64 @state = external global [0 x i32] ; <[0 x i32]*> [#uses=4] @S = external global [0 x i32] ; <[0 x i32]*> [#uses=4] diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll index e14cd8a99e35e..6b2247d1d6197 100644 --- a/test/CodeGen/X86/loop-strength-reduce8.ll +++ b/test/CodeGen/X86/loop-strength-reduce8.ll @@ -1,4 +1,10 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | grep leal | not grep 16 +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s + +; CHECK: leal 16(%eax), %edx +; CHECK: align +; CHECK: addl $4, %edx +; CHECK: decl %ecx +; CHECK: jne LBB1_2 %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 } %struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] } diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll new file mode 100644 index 0000000000000..d1d714491faab --- /dev/null +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; Full strength reduction wouldn't reduce register pressure, so LSR should +; stick with indexing here. + +; CHECK: movaps (%rsi,%rax,4), %xmm3 +; CHECK: movaps %xmm3, (%rdi,%rax,4) +; CHECK: addq $4, %rax +; CHECK: cmpl %eax, (%rdx) +; CHECK-NEXT: jg + +define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { +entry: + %0 = load i32* %n, align 4 + %1 = icmp sgt i32 %0, 0 + br i1 %1, label %bb, label %return + +bb: + %indvar = phi i64 [ %indvar.next, %bb ], [ 0, %entry ] + %tmp = shl i64 %indvar, 2 + %scevgep = getelementptr float* %y, i64 %tmp + %scevgep9 = bitcast float* %scevgep to <4 x float>* + %scevgep10 = getelementptr float* %x, i64 %tmp + %scevgep1011 = bitcast float* %scevgep10 to <4 x float>* + %2 = load <4 x float>* %scevgep1011, align 16 + %3 = bitcast <4 x float> %2 to <4 x i32> + %4 = and <4 x i32> %3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> + %5 = bitcast <4 x i32> %4 to <4 x float> + %6 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> + %7 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %5, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) nounwind + %tmp.i4 = bitcast <4 x float> %7 to <4 x i32> + %8 = xor <4 x i32> %tmp.i4, <i32 -1, i32 -1, i32 -1, i32 -1> + %9 = and <4 x i32> %8, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> + %10 = or <4 x i32> %9, %6 + %11 = bitcast <4 x i32> %10 to <4 x float> + %12 = fadd <4 x float> %2, %11 + %13 = fsub <4 x float> %12, %11 + %14 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %2, <4 x float> %13, i8 1) nounwind + %15 = bitcast <4 x float> %14 to <4 x i32> + %16 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %15) nounwind readnone + %17 = fadd <4 x float> %13, %16 + %tmp.i = bitcast <4 x float> %17 to <4 x i32> + %18 = or <4 x i32> %tmp.i, %6 + %19 = bitcast <4 x i32> %18 to <4 x float> + store <4 x float> %19, <4 x float>* %scevgep9, align 16 + %tmp12 = add i64 %tmp, 4 + %tmp13 = trunc i64 %tmp12 to i32 + %20 = load i32* %n, align 4 + %21 = icmp sgt i32 %20, %tmp13 + %indvar.next = add i64 %indvar, 1 + br i1 %21, label %bb, label %return + +return: + ret void +} + +declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone + +declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll new file mode 100644 index 0000000000000..7f2b8cc8f8320 --- /dev/null +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -0,0 +1,386 @@ +; RUN: llc < %s -march=x86-64 -O3 | FileCheck %s +target datalayout = "e-p:64:64:64" +target triple = "x86_64-unknown-unknown" + +; Full strength reduction reduces register pressure from 5 to 4 here. +; Instruction selection should use the FLAGS value from the dec for +; the branch. Scheduling should push the adds upwards. + +; CHECK: full_me_0: +; CHECK: movsd (%rsi), %xmm0 +; CHECK: addq $8, %rsi +; CHECK: mulsd (%rdx), %xmm0 +; CHECK: addq $8, %rdx +; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rdi +; CHECK: decq %rcx +; CHECK: jne + +define void @full_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; Mostly-full strength reduction means we do full strength reduction on all +; except for the offsets. +; +; Given a choice between constant offsets -2048 and 2048, choose the negative +; value, because at boundary conditions it has a smaller encoding. +; TODO: That's an over-general heuristic. It would be better for the target +; to indicate what the encoding cost would be. Then using a 2048 offset +; would be better on x86-64, since the start value would be 0 instead of +; 2048. + +; CHECK: mostly_full_me_0: +; CHECK: movsd -2048(%rsi), %xmm0 +; CHECK: mulsd -2048(%rdx), %xmm0 +; CHECK: movsd %xmm0, -2048(%rdi) +; CHECK: movsd (%rsi), %xmm0 +; CHECK: addq $8, %rsi +; CHECK: divsd (%rdx), %xmm0 +; CHECK: addq $8, %rdx +; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rdi +; CHECK: decq %rcx +; CHECK: jne + +define void @mostly_full_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %j = add i64 %i, 256 + %Aj = getelementptr inbounds double* %A, i64 %j + %Bj = getelementptr inbounds double* %B, i64 %j + %Cj = getelementptr inbounds double* %C, i64 %j + %t3 = load double* %Bj + %t4 = load double* %Cj + %o = fdiv double %t3, %t4 + store double %o, double* %Aj + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; A minor variation on mostly_full_me_0. +; Prefer to start the indvar at 0. + +; CHECK: mostly_full_me_1: +; CHECK: movsd (%rsi), %xmm0 +; CHECK: mulsd (%rdx), %xmm0 +; CHECK: movsd %xmm0, (%rdi) +; CHECK: movsd -2048(%rsi), %xmm0 +; CHECK: addq $8, %rsi +; CHECK: divsd -2048(%rdx), %xmm0 +; CHECK: addq $8, %rdx +; CHECK: movsd %xmm0, -2048(%rdi) +; CHECK: addq $8, %rdi +; CHECK: decq %rcx +; CHECK: jne + +define void @mostly_full_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %j = sub i64 %i, 256 + %Aj = getelementptr inbounds double* %A, i64 %j + %Bj = getelementptr inbounds double* %B, i64 %j + %Cj = getelementptr inbounds double* %C, i64 %j + %t3 = load double* %Bj + %t4 = load double* %Cj + %o = fdiv double %t3, %t4 + store double %o, double* %Aj + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; A slightly less minor variation on mostly_full_me_0. + +; CHECK: mostly_full_me_2: +; CHECK: movsd (%rsi), %xmm0 +; CHECK: mulsd (%rdx), %xmm0 +; CHECK: movsd %xmm0, (%rdi) +; CHECK: movsd -4096(%rsi), %xmm0 +; CHECK: addq $8, %rsi +; CHECK: divsd -4096(%rdx), %xmm0 +; CHECK: addq $8, %rdx +; CHECK: movsd %xmm0, -4096(%rdi) +; CHECK: addq $8, %rdi +; CHECK: decq %rcx +; CHECK: jne + +define void @mostly_full_me_2(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %k = add i64 %i, 256 + %Ak = getelementptr inbounds double* %A, i64 %k + %Bk = getelementptr inbounds double* %B, i64 %k + %Ck = getelementptr inbounds double* %C, i64 %k + %t1 = load double* %Bk + %t2 = load double* %Ck + %m = fmul double %t1, %t2 + store double %m, double* %Ak + %j = sub i64 %i, 256 + %Aj = getelementptr inbounds double* %A, i64 %j + %Bj = getelementptr inbounds double* %B, i64 %j + %Cj = getelementptr inbounds double* %C, i64 %j + %t3 = load double* %Bj + %t4 = load double* %Cj + %o = fdiv double %t3, %t4 + store double %o, double* %Aj + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; In this test, the counting IV exit value is used, so full strength reduction +; would not reduce register pressure. IndVarSimplify ought to simplify such +; cases away, but it's useful here to verify that LSR's register pressure +; heuristics are working as expected. + +; CHECK: count_me_0: +; CHECK: movsd (%rsi,%rax,8), %xmm0 +; CHECK: mulsd (%rdx,%rax,8), %xmm0 +; CHECK: movsd %xmm0, (%rdi,%rax,8) +; CHECK: incq %rax +; CHECK: cmpq %rax, %rcx +; CHECK: jne + +define i64 @count_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + %q = phi i64 [ 0, %entry ], [ %i.next, %loop ] + ret i64 %q +} + +; In this test, the trip count value is used, so full strength reduction +; would not reduce register pressure. +; (though it would reduce register pressure inside the loop...) + +; CHECK: count_me_1: +; CHECK: movsd (%rsi,%rax,8), %xmm0 +; CHECK: mulsd (%rdx,%rax,8), %xmm0 +; CHECK: movsd %xmm0, (%rdi,%rax,8) +; CHECK: incq %rax +; CHECK: cmpq %rax, %rcx +; CHECK: jne + +define i64 @count_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + %q = phi i64 [ 0, %entry ], [ %n, %loop ] + ret i64 %q +} + +; Full strength reduction doesn't save any registers here because the +; loop tripcount is a constant. + +; CHECK: count_me_2: +; CHECK: movl $10, %eax +; CHECK: align +; CHECK: BB7_1: +; CHECK: movsd -40(%rdi,%rax,8), %xmm0 +; CHECK: addsd -40(%rsi,%rax,8), %xmm0 +; CHECK: movsd %xmm0, -40(%rdx,%rax,8) +; CHECK: movsd (%rdi,%rax,8), %xmm0 +; CHECK: subsd (%rsi,%rax,8), %xmm0 +; CHECK: movsd %xmm0, (%rdx,%rax,8) +; CHECK: incq %rax +; CHECK: cmpq $5010, %rax +; CHECK: jne + +define void @count_me_2(double* nocapture %A, double* nocapture %B, double* nocapture %C) nounwind { +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.next, %loop ] + %i5 = add i64 %i, 5 + %Ai = getelementptr double* %A, i64 %i5 + %t2 = load double* %Ai + %Bi = getelementptr double* %B, i64 %i5 + %t4 = load double* %Bi + %t5 = fadd double %t2, %t4 + %Ci = getelementptr double* %C, i64 %i5 + store double %t5, double* %Ci + %i10 = add i64 %i, 10 + %Ai10 = getelementptr double* %A, i64 %i10 + %t9 = load double* %Ai10 + %Bi10 = getelementptr double* %B, i64 %i10 + %t11 = load double* %Bi10 + %t12 = fsub double %t9, %t11 + %Ci10 = getelementptr double* %C, i64 %i10 + store double %t12, double* %Ci10 + %i.next = add i64 %i, 1 + %exitcond = icmp eq i64 %i.next, 5000 + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; This should be fully strength-reduced to reduce register pressure. + +; CHECK: full_me_1: +; CHECK: align +; CHECK: BB8_1: +; CHECK: movsd (%rdi), %xmm0 +; CHECK: addsd (%rsi), %xmm0 +; CHECK: movsd %xmm0, (%rdx) +; CHECK: movsd 40(%rdi), %xmm0 +; CHECK: addq $8, %rdi +; CHECK: subsd 40(%rsi), %xmm0 +; CHECK: addq $8, %rsi +; CHECK: movsd %xmm0, 40(%rdx) +; CHECK: addq $8, %rdx +; CHECK: decq %rcx +; CHECK: jne + +define void @full_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + br label %loop + +loop: + %i = phi i64 [ 0, %entry ], [ %i.next, %loop ] + %i5 = add i64 %i, 5 + %Ai = getelementptr double* %A, i64 %i5 + %t2 = load double* %Ai + %Bi = getelementptr double* %B, i64 %i5 + %t4 = load double* %Bi + %t5 = fadd double %t2, %t4 + %Ci = getelementptr double* %C, i64 %i5 + store double %t5, double* %Ci + %i10 = add i64 %i, 10 + %Ai10 = getelementptr double* %A, i64 %i10 + %t9 = load double* %Ai10 + %Bi10 = getelementptr double* %B, i64 %i10 + %t11 = load double* %Bi10 + %t12 = fsub double %t9, %t11 + %Ci10 = getelementptr double* %C, i64 %i10 + store double %t12, double* %Ci10 + %i.next = add i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; This is a variation on full_me_0 in which the 0,+,1 induction variable +; has a non-address use, pinning that value in a register. + +; CHECK: count_me_3: +; CHECK: call +; CHECK: movsd (%r15,%r13,8), %xmm0 +; CHECK: mulsd (%r14,%r13,8), %xmm0 +; CHECK: movsd %xmm0, (%r12,%r13,8) +; CHECK: incq %r13 +; CHECK: cmpq %r13, %rbx +; CHECK: jne + +declare void @use(i64) + +define void @count_me_3(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind { +entry: + %t0 = icmp sgt i64 %n, 0 + br i1 %t0, label %loop, label %return + +loop: + %i = phi i64 [ %i.next, %loop ], [ 0, %entry ] + call void @use(i64 %i) + %Ai = getelementptr inbounds double* %A, i64 %i + %Bi = getelementptr inbounds double* %B, i64 %i + %Ci = getelementptr inbounds double* %C, i64 %i + %t1 = load double* %Bi + %t2 = load double* %Ci + %m = fmul double %t1, %t2 + store double %m, double* %Ai + %i.next = add nsw i64 %i, 1 + %exitcond = icmp eq i64 %i.next, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} diff --git a/test/CodeGen/X86/masked-iv-safe.ll b/test/CodeGen/X86/masked-iv-safe.ll index bc493bd8f724f..0b4d73a683af9 100644 --- a/test/CodeGen/X86/masked-iv-safe.ll +++ b/test/CodeGen/X86/masked-iv-safe.ll @@ -169,7 +169,7 @@ loop: %indvar.i24 = and i64 %indvar, 16777215 %t3 = getelementptr double* %d, i64 %indvar.i24 %t4 = load double* %t3 - %t5 = fmul double %t4, 2.3 + %t5 = fdiv double %t4, 2.3 store double %t5, double* %t3 %t6 = getelementptr double* %d, i64 %indvar %t7 = load double* %t6 @@ -199,7 +199,7 @@ loop: %indvar.i24 = ashr i64 %s1, 24 %t3 = getelementptr double* %d, i64 %indvar.i24 %t4 = load double* %t3 - %t5 = fmul double %t4, 2.3 + %t5 = fdiv double %t4, 2.3 store double %t5, double* %t3 %t6 = getelementptr double* %d, i64 %indvar %t7 = load double* %t6 @@ -229,7 +229,7 @@ loop: %indvar.i24 = ashr i64 %s1, 24 %t3 = getelementptr double* %d, i64 %indvar.i24 %t4 = load double* %t3 - %t5 = fmul double %t4, 2.3 + %t5 = fdiv double %t4, 2.3 store double %t5, double* %t3 %t6 = getelementptr double* %d, i64 %indvar %t7 = load double* %t6 diff --git a/test/CodeGen/X86/nancvt.ll b/test/CodeGen/X86/nancvt.ll index 0b56644f125a4..82b73319ad149 100644 --- a/test/CodeGen/X86/nancvt.ll +++ b/test/CodeGen/X86/nancvt.ll @@ -16,6 +16,8 @@ target triple = "i686-apple-darwin8" @.str = internal constant [10 x i8] c"%08x%08x\0A\00" ; <[10 x i8]*> [#uses=2] @.str1 = internal constant [6 x i8] c"%08x\0A\00" ; <[6 x i8]*> [#uses=2] +@var = external global i32 + define i32 @main() { entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] @@ -50,7 +52,8 @@ bb: ; preds = %bb23 %tmp17 = ashr i64 %tmp16, %.cast ; <i64> [#uses=1] %tmp1718 = trunc i64 %tmp17 to i32 ; <i32> [#uses=1] %tmp19 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] - %tmp20 = call i32 (i8*, ...)* @printf( i8* %tmp19, i32 %tmp1718, i32 %tmp13 ) ; <i32> [#uses=0] + volatile store i32 %tmp1718, i32* @var + volatile store i32 %tmp13, i32* @var %tmp21 = load i32* %i, align 4 ; <i32> [#uses=1] %tmp22 = add i32 %tmp21, 1 ; <i32> [#uses=1] store i32 %tmp22, i32* %i, align 4 @@ -83,7 +86,7 @@ bb28: ; preds = %bb46 %tmp3940 = bitcast float* %tmp39 to i32* ; <i32*> [#uses=1] %tmp41 = load i32* %tmp3940, align 4 ; <i32> [#uses=1] %tmp42 = getelementptr [6 x i8]* @.str1, i32 0, i32 0 ; <i8*> [#uses=1] - %tmp43 = call i32 (i8*, ...)* @printf( i8* %tmp42, i32 %tmp41 ) ; <i32> [#uses=0] + volatile store i32 %tmp41, i32* @var %tmp44 = load i32* %i, align 4 ; <i32> [#uses=1] %tmp45 = add i32 %tmp44, 1 ; <i32> [#uses=1] store i32 %tmp45, i32* %i, align 4 @@ -124,7 +127,8 @@ bb52: ; preds = %bb78 %tmp72 = ashr i64 %tmp70, %.cast71 ; <i64> [#uses=1] %tmp7273 = trunc i64 %tmp72 to i32 ; <i32> [#uses=1] %tmp74 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] - %tmp75 = call i32 (i8*, ...)* @printf( i8* %tmp74, i32 %tmp7273, i32 %tmp66 ) ; <i32> [#uses=0] + volatile store i32 %tmp7273, i32* @var + volatile store i32 %tmp66, i32* @var %tmp76 = load i32* %i, align 4 ; <i32> [#uses=1] %tmp77 = add i32 %tmp76, 1 ; <i32> [#uses=1] store i32 %tmp77, i32* %i, align 4 @@ -157,7 +161,7 @@ bb84: ; preds = %bb101 %tmp9495 = bitcast float* %tmp94 to i32* ; <i32*> [#uses=1] %tmp96 = load i32* %tmp9495, align 4 ; <i32> [#uses=1] %tmp97 = getelementptr [6 x i8]* @.str1, i32 0, i32 0 ; <i8*> [#uses=1] - %tmp98 = call i32 (i8*, ...)* @printf( i8* %tmp97, i32 %tmp96 ) ; <i32> [#uses=0] + volatile store i32 %tmp96, i32* @var %tmp99 = load i32* %i, align 4 ; <i32> [#uses=1] %tmp100 = add i32 %tmp99, 1 ; <i32> [#uses=1] store i32 %tmp100, i32* %i, align 4 @@ -177,5 +181,3 @@ return: ; preds = %bb106 %retval107 = load i32* %retval ; <i32> [#uses=1] ret i32 %retval107 } - -declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll index 5acf04cc06c10..ce57e8fce6f2a 100644 --- a/test/CodeGen/X86/personality.ll +++ b/test/CodeGen/X86/personality.ll @@ -39,7 +39,7 @@ declare void @__gxx_personality_v0() declare void @__cxa_end_catch() ; X64: Leh_frame_common_begin: -; X64: .long ___gxx_personality_v0@GOTPCREL+4 +; X64: .long (___gxx_personality_v0@GOTPCREL)+4 ; X32: Leh_frame_common_begin: ; X32: .long L___gxx_personality_v0$non_lazy_ptr- diff --git a/test/CodeGen/X86/phi-immediate-factoring.ll b/test/CodeGen/X86/phi-immediate-factoring.ll new file mode 100644 index 0000000000000..9f9f92115c797 --- /dev/null +++ b/test/CodeGen/X86/phi-immediate-factoring.ll @@ -0,0 +1,54 @@ +; PR1296 +; RUN: llc < %s -march=x86 | grep {movl \$1} | count 1 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-apple-darwin8" + +define i32 @foo(i32 %A, i32 %B, i32 %C) { +entry: + switch i32 %A, label %out [ + i32 1, label %bb + i32 0, label %bb13 + i32 2, label %bb35 + ] + +bb: ; preds = %cond_next, %entry + %i.144.1 = phi i32 [ 0, %entry ], [ %tmp7, %cond_next ] ; <i32> [#uses=2] + %tmp4 = and i32 %i.144.1, %B ; <i32> [#uses=1] + icmp eq i32 %tmp4, 0 ; <i1>:0 [#uses=1] + br i1 %0, label %cond_next, label %out + +cond_next: ; preds = %bb + %tmp7 = add i32 %i.144.1, 1 ; <i32> [#uses=2] + icmp slt i32 %tmp7, 1000 ; <i1>:1 [#uses=1] + br i1 %1, label %bb, label %out + +bb13: ; preds = %cond_next18, %entry + %i.248.1 = phi i32 [ 0, %entry ], [ %tmp20, %cond_next18 ] ; <i32> [#uses=2] + %tmp16 = and i32 %i.248.1, %C ; <i32> [#uses=1] + icmp eq i32 %tmp16, 0 ; <i1>:2 [#uses=1] + br i1 %2, label %cond_next18, label %out + +cond_next18: ; preds = %bb13 + %tmp20 = add i32 %i.248.1, 1 ; <i32> [#uses=2] + icmp slt i32 %tmp20, 1000 ; <i1>:3 [#uses=1] + br i1 %3, label %bb13, label %out + +bb27: ; preds = %bb35 + %tmp30 = and i32 %i.3, %C ; <i32> [#uses=1] + icmp eq i32 %tmp30, 0 ; <i1>:4 [#uses=1] + br i1 %4, label %cond_next32, label %out + +cond_next32: ; preds = %bb27 + %indvar.next = add i32 %i.3, 1 ; <i32> [#uses=1] + br label %bb35 + +bb35: ; preds = %entry, %cond_next32 + %i.3 = phi i32 [ %indvar.next, %cond_next32 ], [ 0, %entry ] ; <i32> [#uses=3] + icmp slt i32 %i.3, 1000 ; <i1>:5 [#uses=1] + br i1 %5, label %bb27, label %out + +out: ; preds = %bb27, %bb35, %bb13, %cond_next18, %bb, %cond_next, %entry + %result.0 = phi i32 [ 0, %entry ], [ 1, %bb ], [ 0, %cond_next ], [ 1, %bb13 ], [ 0, %cond_next18 ], [ 1, %bb27 ], [ 0, %bb35 ] ; <i32> [#uses=1] + ret i32 %result.0 +} diff --git a/test/CodeGen/X86/phys-reg-local-regalloc.ll b/test/CodeGen/X86/phys-reg-local-regalloc.ll index e5e2d4bb230d5..045841e7245b1 100644 --- a/test/CodeGen/X86/phys-reg-local-regalloc.ll +++ b/test/CodeGen/X86/phys-reg-local-regalloc.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s +; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s +; CHECKed instructions should be the same with or without -O0. @.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index e886ba06b7089..d3c28a055aee7 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -190,7 +190,7 @@ bb12: ; LINUX: .L8$pb: ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref8-.L8$pb), ; LINUX: addl .LJTI8_0@GOTOFF( -; LINUX: jmpl *%ecx +; LINUX: jmpl * ; LINUX: .LJTI8_0: ; LINUX: .long .LBB8_2@GOTOFF diff --git a/test/CodeGen/X86/pr1505b.ll b/test/CodeGen/X86/pr1505b.ll index 12736cda4cd28..6a08dae51f8ae 100644 --- a/test/CodeGen/X86/pr1505b.ll +++ b/test/CodeGen/X86/pr1505b.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mcpu=i486 | grep fstpl | count 4 -; RUN: llc < %s -mcpu=i486 | grep fstps | count 3 +; RUN: llc < %s -mcpu=i486 | grep fstpl | count 5 +; RUN: llc < %s -mcpu=i486 | grep fstps | count 2 ; PR1505 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/X86/pr3495.ll b/test/CodeGen/X86/pr3495.ll index 1795970d353ee..e84a84f59bb76 100644 --- a/test/CodeGen/X86/pr3495.ll +++ b/test/CodeGen/X86/pr3495.ll @@ -1,8 +1,7 @@ ; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2 ; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1 -; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 38 +; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 34 ; PR3495 -; The loop reversal kicks in once here, resulting in one fewer instruction. target triple = "i386-pc-linux-gnu" @x = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/pre-split8.ll b/test/CodeGen/X86/pre-split8.ll index ea4b9496b3c37..0684bd036ce24 100644 --- a/test/CodeGen/X86/pre-split8.ll +++ b/test/CodeGen/X86/pre-split8.ll @@ -20,7 +20,7 @@ bb: ; preds = %bb9.i, %entry bb9.i: ; preds = %bb %2 = fsub double %.rle4, %0 ; <double> [#uses=0] - %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=0] + %3 = tail call double @asin(double %.rle4) nounwind readonly ; <double> [#uses=0] %4 = fmul double 0.000000e+00, %0 ; <double> [#uses=1] %5 = tail call double @tan(double 0.000000e+00) nounwind readonly ; <double> [#uses=0] %6 = fmul double %4, 0.000000e+00 ; <double> [#uses=1] diff --git a/test/CodeGen/X86/pre-split9.ll b/test/CodeGen/X86/pre-split9.ll index c27d925d43e4b..86dda33533f73 100644 --- a/test/CodeGen/X86/pre-split9.ll +++ b/test/CodeGen/X86/pre-split9.ll @@ -22,7 +22,7 @@ bb: ; preds = %bb9.i, %entry bb9.i: ; preds = %bb %2 = fsub double %.rle4, %0 ; <double> [#uses=0] - %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=0] + %3 = tail call double @asin(double %.rle4) nounwind readonly ; <double> [#uses=0] %4 = tail call double @sin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1] %5 = fmul double %4, %0 ; <double> [#uses=1] %6 = tail call double @tan(double 0.000000e+00) nounwind readonly ; <double> [#uses=0] diff --git a/test/CodeGen/X86/ptrtoint-constexpr.ll b/test/CodeGen/X86/ptrtoint-constexpr.ll index 7e33e7916c89c..dd9790568abee 100644 --- a/test/CodeGen/X86/ptrtoint-constexpr.ll +++ b/test/CodeGen/X86/ptrtoint-constexpr.ll @@ -6,3 +6,9 @@ ; CHECK: .quad r&4294967295 @r = global %union.x { i64 ptrtoint (%union.x* @r to i64) }, align 4 + +; CHECK: .globl x +; CHECK: x: +; CHECK: .quad 3 + +@x = global i64 mul (i64 3, i64 ptrtoint (i2* getelementptr (i2* null, i64 1) to i64)) diff --git a/test/CodeGen/X86/scalar_widen_div.ll b/test/CodeGen/X86/scalar_widen_div.ll index fc67e4417c4a8..77f320f1056e7 100644 --- a/test/CodeGen/X86/scalar_widen_div.ll +++ b/test/CodeGen/X86/scalar_widen_div.ll @@ -152,3 +152,32 @@ define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) { %rem.r = urem <5 x i64> %num, %rem ret <5 x i64> %rem.r } + +define void @test_int_div(<3 x i32>* %dest, <3 x i32>* %old, i32 %n) { +; CHECK: idivl +; CHECK: idivl +; CHECK: idivl +; CHECK-NOT: idivl +; CHECK: ret +entry: + %cmp13 = icmp sgt i32 %n, 0 + br i1 %cmp13, label %bb.nph, label %for.end + +bb.nph: + br label %for.body + +for.body: + %i.014 = phi i32 [ 0, %bb.nph ], [ %inc, %for.body ] + %arrayidx11 = getelementptr <3 x i32>* %dest, i32 %i.014 + %tmp4 = load <3 x i32>* %arrayidx11 ; <<3 x i32>> [#uses=1] + %arrayidx7 = getelementptr inbounds <3 x i32>* %old, i32 %i.014 + %tmp8 = load <3 x i32>* %arrayidx7 ; <<3 x i32>> [#uses=1] + %div = sdiv <3 x i32> %tmp4, %tmp8 + store <3 x i32> %div, <3 x i32>* %arrayidx11 + %inc = add nsw i32 %i.014, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll new file mode 100644 index 0000000000000..21c418d534e91 --- /dev/null +++ b/test/CodeGen/X86/sext-i1.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64 +; rdar://7573216 +; PR6146 + +define i32 @t1(i32 %x) nounwind readnone ssp { +entry: +; 32: t1: +; 32: cmpl $1 +; 32: sbbl + +; 64: t1: +; 64: cmpl $1 +; 64: sbbl + %0 = icmp eq i32 %x, 0 + %iftmp.0.0 = select i1 %0, i32 -1, i32 0 + ret i32 %iftmp.0.0 +} + +define i32 @t2(i32 %x) nounwind readnone ssp { +entry: +; 32: t2: +; 32: cmpl $1 +; 32: sbbl + +; 64: t2: +; 64: cmpl $1 +; 64: sbbl + %0 = icmp eq i32 %x, 0 + %iftmp.0.0 = sext i1 %0 to i32 + ret i32 %iftmp.0.0 +} + +%struct.zbookmark = type { i64, i64 } +%struct.zstream = type { } + +define i32 @t3() nounwind readonly { +entry: +; 32: t3: +; 32: cmpl $1 +; 32: sbbl +; 32: cmpl +; 32: xorl + +; 64: t3: +; 64: cmpl $1 +; 64: sbbq +; 64: cmpq +; 64: xorl + %not.tobool = icmp eq i32 undef, 0 ; <i1> [#uses=2] + %cond = sext i1 %not.tobool to i32 ; <i32> [#uses=1] + %conv = sext i1 %not.tobool to i64 ; <i64> [#uses=1] + %add13 = add i64 0, %conv ; <i64> [#uses=1] + %cmp = icmp ult i64 undef, %add13 ; <i1> [#uses=1] + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %if.end + +if.end: ; preds = %if.then, %entry + %xor27 = xor i32 undef, %cond ; <i32> [#uses=0] + ret i32 0 +} diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 5550d263389ac..b2af7c947d981 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -63,10 +63,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { ret <8 x i16> %tmp ; X64: t4: ; X64: pextrw $7, %xmm0, %eax -; X64: pshufhw $100, %xmm0, %xmm1 -; X64: pinsrw $1, %eax, %xmm1 +; X64: pshufhw $100, %xmm0, %xmm2 +; X64: pinsrw $1, %eax, %xmm2 ; X64: pextrw $1, %xmm0, %eax -; X64: movaps %xmm1, %xmm0 +; X64: movaps %xmm2, %xmm0 ; X64: pinsrw $4, %eax, %xmm0 ; X64: ret } diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll index 7d85818d46b95..42e7a394d8bc0 100644 --- a/test/CodeGen/X86/stack-color-with-reg.ll +++ b/test/CodeGen/X86/stack-color-with-reg.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t -; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 14 +; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 8 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 diff --git a/test/CodeGen/X86/stdcall.ll b/test/CodeGen/X86/stdcall.ll new file mode 100644 index 0000000000000..70204bcf47455 --- /dev/null +++ b/test/CodeGen/X86/stdcall.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s | FileCheck %s +; PR5851 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-mingw32" + +%0 = type { void (...)* } + +@B = global %0 { void (...)* bitcast (void ()* @MyFunc to void (...)*) }, align 4 +; CHECK: _B: +; CHECK: .long _MyFunc@0 + +define internal x86_stdcallcc void @MyFunc() nounwind { +entry: + ret void +} diff --git a/test/CodeGen/X86/switch-crit-edge-constant.ll b/test/CodeGen/X86/switch-crit-edge-constant.ll new file mode 100644 index 0000000000000..1f2ab0dbcbe96 --- /dev/null +++ b/test/CodeGen/X86/switch-crit-edge-constant.ll @@ -0,0 +1,52 @@ +; PR925 +; RUN: llc < %s -march=x86 | \ +; RUN: grep mov.*str1 | count 1 + +target datalayout = "e-p:32:32" +target triple = "i686-apple-darwin8.7.2" +@str1 = internal constant [5 x i8] c"bonk\00" ; <[5 x i8]*> [#uses=1] +@str2 = internal constant [5 x i8] c"bork\00" ; <[5 x i8]*> [#uses=1] +@str = internal constant [8 x i8] c"perfwap\00" ; <[8 x i8]*> [#uses=1] + +define void @foo(i32 %C) { +entry: + switch i32 %C, label %bb2 [ + i32 1, label %blahaha + i32 2, label %blahaha + i32 3, label %blahaha + i32 4, label %blahaha + i32 5, label %blahaha + i32 6, label %blahaha + i32 7, label %blahaha + i32 8, label %blahaha + i32 9, label %blahaha + i32 10, label %blahaha + ] + +bb2: ; preds = %entry + %tmp5 = and i32 %C, 123 ; <i32> [#uses=1] + %tmp = icmp eq i32 %tmp5, 0 ; <i1> [#uses=1] + br i1 %tmp, label %blahaha, label %cond_true + +cond_true: ; preds = %bb2 + br label %blahaha + +blahaha: ; preds = %cond_true, %bb2, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry + %s.0 = phi i8* [ getelementptr ([8 x i8]* @str, i32 0, i64 0), %cond_true ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str2, i32 0, i64 0), %bb2 ] ; <i8*> [#uses=13] + %tmp8 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp10 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp12 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp14 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp16 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp18 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp20 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp22 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp24 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp26 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp28 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp30 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + %tmp32 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0] + ret void +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/X86/tailcall1.ll b/test/CodeGen/X86/tailcall1.ll index 42f8cdd384130..f7ff5d5308d66 100644 --- a/test/CodeGen/X86/tailcall1.ll +++ b/test/CodeGen/X86/tailcall1.ll @@ -1,11 +1,14 @@ ; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL | count 5 +; With -tailcallopt, CodeGen guarantees a tail call optimization +; for all of these. + declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind { entry: - %tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2) - ret i32 %tmp11 + %tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2) + ret i32 %tmp11 } declare fastcc i8* @alias_callee() diff --git a/test/CodeGen/X86/tailcall2.ll b/test/CodeGen/X86/tailcall2.ll new file mode 100644 index 0000000000000..80bab619c16f7 --- /dev/null +++ b/test/CodeGen/X86/tailcall2.ll @@ -0,0 +1,197 @@ +; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -check-prefix=64 + +define void @t1(i32 %x) nounwind ssp { +entry: +; 32: t1: +; 32: jmp {{_?}}foo + +; 64: t1: +; 64: jmp {{_?}}foo + tail call void @foo() nounwind + ret void +} + +declare void @foo() + +define void @t2() nounwind ssp { +entry: +; 32: t2: +; 32: jmp {{_?}}foo2 + +; 64: t2: +; 64: jmp {{_?}}foo2 + %0 = tail call i32 @foo2() nounwind + ret void +} + +declare i32 @foo2() + +define void @t3() nounwind ssp { +entry: +; 32: t3: +; 32: jmp {{_?}}foo3 + +; 64: t3: +; 64: jmp {{_?}}foo3 + %0 = tail call i32 @foo3() nounwind + ret void +} + +declare i32 @foo3() + +define void @t4(void (i32)* nocapture %x) nounwind ssp { +entry: +; 32: t4: +; 32: call * +; FIXME: gcc can generate a tailcall for this. But it's tricky. + +; 64: t4: +; 64-NOT: call +; 64: jmpq * + tail call void %x(i32 0) nounwind + ret void +} + +define void @t5(void ()* nocapture %x) nounwind ssp { +entry: +; 32: t5: +; 32-NOT: call +; 32: jmpl * + +; 64: t5: +; 64-NOT: call +; 64: jmpq * + tail call void %x() nounwind + ret void +} + +define i32 @t6(i32 %x) nounwind ssp { +entry: +; 32: t6: +; 32: call {{_?}}t6 +; 32: jmp {{_?}}bar + +; 64: t6: +; 64: jmp {{_?}}t6 +; 64: jmp {{_?}}bar + %0 = icmp slt i32 %x, 10 + br i1 %0, label %bb, label %bb1 + +bb: + %1 = add nsw i32 %x, -1 + %2 = tail call i32 @t6(i32 %1) nounwind ssp + ret i32 %2 + +bb1: + %3 = tail call i32 @bar(i32 %x) nounwind + ret i32 %3 +} + +declare i32 @bar(i32) + +define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp { +entry: +; 32: t7: +; 32: jmp {{_?}}bar2 + +; 64: t7: +; 64: jmp {{_?}}bar2 + %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind + ret i32 %0 +} + +declare i32 @bar2(i32, i32, i32) + +define signext i16 @t8() nounwind ssp { +entry: +; 32: t8: +; 32: call {{_?}}bar3 + +; 64: t8: +; 64: callq {{_?}}bar3 + %0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1] + ret i16 %0 +} + +declare signext i16 @bar3() + +define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp { +entry: +; 32: t9: +; 32: call * + +; 64: t9: +; 64: callq * + %0 = bitcast i32 (i32)* %x to i16 (i32)* + %1 = tail call signext i16 %0(i32 0) nounwind + ret i16 %1 +} + +define void @t10() nounwind ssp { +entry: +; 32: t10: +; 32: call + +; 64: t10: +; 64: callq + %0 = tail call i32 @foo4() noreturn nounwind + unreachable +} + +declare i32 @foo4() + +define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp { +; In 32-bit mode, it's emitting a bunch of dead loads that are not being +; eliminated currently. + +; 32: t11: +; 32-NOT: subl ${{[0-9]+}}, %esp +; 32: jne +; 32-NOT: movl +; 32-NOT: addl ${{[0-9]+}}, %esp +; 32: jmp {{_?}}foo5 + +; 64: t11: +; 64-NOT: subq ${{[0-9]+}}, %esp +; 64-NOT: addq ${{[0-9]+}}, %esp +; 64: jmp {{_?}}foo5 +entry: + %0 = icmp eq i32 %x, 0 + br i1 %0, label %bb6, label %bb + +bb: + %1 = tail call i32 @foo5(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind + ret i32 %1 + +bb6: + ret i32 0 +} + +declare i32 @foo5(i32, i32, i32, i32, i32) + +%struct.t = type { i32, i32, i32, i32, i32 } + +define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp { +; 32: t12: +; 32-NOT: subl ${{[0-9]+}}, %esp +; 32-NOT: addl ${{[0-9]+}}, %esp +; 32: jmp {{_?}}foo6 + +; 64: t12: +; 64-NOT: subq ${{[0-9]+}}, %esp +; 64-NOT: addq ${{[0-9]+}}, %esp +; 64: jmp {{_?}}foo6 +entry: + %0 = icmp eq i32 %x, 0 + br i1 %0, label %bb2, label %bb + +bb: + %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind + ret i32 %1 + +bb2: + ret i32 0 +} + +declare i32 @foo6(i32, i32, %struct.t* byval align 4) diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll index be4f96cfb5e64..3841f518976b7 100644 --- a/test/CodeGen/X86/tailcallfp2.ll +++ b/test/CodeGen/X86/tailcallfp2.ll @@ -2,7 +2,7 @@ declare i32 @putchar(i32) -define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) { +define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind { %tmp1 = icmp sgt i32 %x, 0 br i1 %tmp1, label %if-then, label %if-else @@ -18,8 +18,8 @@ if-else: } -define i32 @main() { +define i32 @main() nounwind { %f = bitcast i32 (i32, i32*, i32)* @checktail to i32* %res = tail call fastcc i32 @checktail( i32 10, i32* %f,i32 10) ret i32 %res -}
\ No newline at end of file +} diff --git a/test/CodeGen/X86/twoaddr-coalesce.ll b/test/CodeGen/X86/twoaddr-coalesce.ll index d0e13f61f2d05..4c37225ce027b 100644 --- a/test/CodeGen/X86/twoaddr-coalesce.ll +++ b/test/CodeGen/X86/twoaddr-coalesce.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep mov | count 5 +; RUN: llc < %s -march=x86 | grep mov | count 4 ; rdar://6523745 @"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/vsplit-and.ll b/test/CodeGen/X86/vsplit-and.ll new file mode 100644 index 0000000000000..a247c6eb00d73 --- /dev/null +++ b/test/CodeGen/X86/vsplit-and.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=x86 -disable-mmx | FileCheck %s + + +define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly { +; CHECK: andb + %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer + %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer + %t1 = and <2 x i1> %cmp1, %cmp2 + %t2 = sext <2 x i1> %t1 to <2 x i64> + store <2 x i64> %t2, <2 x i64>* %dst + ret void +} + +define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly { +; CHECK: andb + %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer + %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer + %t1 = and <3 x i1> %cmp1, %cmp2 + %t2 = sext <3 x i1> %t1 to <3 x i64> + store <3 x i64> %t2, <3 x i64>* %dst + ret void +} diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll index e5d2c6a61e297..1e626a2f88228 100644 --- a/test/CodeGen/X86/widen_cast-2.ll +++ b/test/CodeGen/X86/widen_cast-2.ll @@ -2,10 +2,8 @@ ; CHECK: pextrd ; CHECK: pextrd ; CHECK: movd -; CHECK: pextrd -; CHECK: pextrd -; CHECK: pextrd -; CHECK: movd +; CHECK: movaps + ; bitcast v14i16 to v7i32 diff --git a/test/CodeGen/X86/widen_load-1.ll b/test/CodeGen/X86/widen_load-1.ll index 8a970bff498db..d397645f193f8 100644 --- a/test/CodeGen/X86/widen_load-1.ll +++ b/test/CodeGen/X86/widen_load-1.ll @@ -3,7 +3,7 @@ ; This load should be before the call, not after. -; CHECK: movq compl+128(%rip), %xmm0 +; CHECK: movaps compl+128(%rip), %xmm0 ; CHECK: movaps %xmm0, (%rsp) ; CHECK: callq killcommon diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll new file mode 100644 index 0000000000000..11383fa308298 --- /dev/null +++ b/test/CodeGen/X86/widen_load-2.ll @@ -0,0 +1,155 @@ +; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s + +; Test based on pr5626 to load/store +; + +%i32vec3 = type <3 x i32> +define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { +; CHECK: movaps +; CHECK: paddd +; CHECK: pextrd +; CHECK: movq + %a = load %i32vec3* %ap, align 16 + %b = load %i32vec3* %bp, align 16 + %x = add %i32vec3 %a, %b + store %i32vec3 %x, %i32vec3* %ret, align 16 + ret void +} + +define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { +; CHECK: movq +; CHECK: pinsrd +; CHECK: movq +; CHECK: pinsrd +; CHECK: paddd +; CHECK: pextrd +; CHECK: movq + %a = load %i32vec3* %ap + %b = load %i32vec3* %bp + %x = add %i32vec3 %a, %b + store %i32vec3 %x, %i32vec3* %ret + ret void +} + +%i32vec7 = type <7 x i32> +define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { +; CHECK: movaps +; CHECK: movaps +; CHECK: paddd +; CHECK: paddd +; CHECK: pextrd +; CHECK: movq +; CHECK: movaps + %a = load %i32vec7* %ap, align 16 + %b = load %i32vec7* %bp, align 16 + %x = add %i32vec7 %a, %b + store %i32vec7 %x, %i32vec7* %ret, align 16 + ret void +} + +%i32vec12 = type <12 x i32> +define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { +; CHECK: movaps +; CHECK: movaps +; CHECK: movaps +; CHECK: paddd +; CHECK: paddd +; CHECK: paddd +; CHECK: movaps +; CHECK: movaps +; CHECK: movaps + %a = load %i32vec12* %ap, align 16 + %b = load %i32vec12* %bp, align 16 + %x = add %i32vec12 %a, %b + store %i32vec12 %x, %i32vec12* %ret, align 16 + ret void +} + + +%i16vec3 = type <3 x i16> +define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { +; CHECK: movaps +; CHECK: paddw +; CHECK: movd +; CHECK: pextrw + %a = load %i16vec3* %ap, align 16 + %b = load %i16vec3* %bp, align 16 + %x = add %i16vec3 %a, %b + store %i16vec3 %x, %i16vec3* %ret, align 16 + ret void +} + +%i16vec4 = type <4 x i16> +define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { +; CHECK: movaps +; CHECK: paddw +; CHECK: movq + %a = load %i16vec4* %ap, align 16 + %b = load %i16vec4* %bp, align 16 + %x = add %i16vec4 %a, %b + store %i16vec4 %x, %i16vec4* %ret, align 16 + ret void +} + +%i16vec12 = type <12 x i16> +define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { +; CHECK: movaps +; CHECK: movaps +; CHECK: paddw +; CHECK: paddw +; CHECK: movq +; CHECK: movaps + %a = load %i16vec12* %ap, align 16 + %b = load %i16vec12* %bp, align 16 + %x = add %i16vec12 %a, %b + store %i16vec12 %x, %i16vec12* %ret, align 16 + ret void +} + +%i16vec18 = type <18 x i16> +define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { +; CHECK: movaps +; CHECK: movaps +; CHECK: movaps +; CHECK: paddw +; CHECK: paddw +; CHECK: paddw +; CHECK: movd +; CHECK: movaps +; CHECK: movaps + %a = load %i16vec18* %ap, align 16 + %b = load %i16vec18* %bp, align 16 + %x = add %i16vec18 %a, %b + store %i16vec18 %x, %i16vec18* %ret, align 16 + ret void +} + + +%i8vec3 = type <3 x i8> +define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { +; CHECK: movaps +; CHECK: paddb +; CHECK: pextrb +; CHECK: movb + %a = load %i8vec3* %ap, align 16 + %b = load %i8vec3* %bp, align 16 + %x = add %i8vec3 %a, %b + store %i8vec3 %x, %i8vec3* %ret, align 16 + ret void +} + +%i8vec31 = type <31 x i8> +define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { +; CHECK: movaps +; CHECK: movaps +; CHECK: paddb +; CHECK: paddb +; CHECK: movq +; CHECK: pextrb +; CHECK: pextrw + %a = load %i8vec31* %ap, align 16 + %b = load %i8vec31* %bp, align 16 + %x = add %i8vec31 %a, %b + store %i8vec31 %x, %i8vec31* %ret, align 16 + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/X86/zext-trunc.ll b/test/CodeGen/X86/zext-trunc.ll new file mode 100644 index 0000000000000..b9ffbe87b21b6 --- /dev/null +++ b/test/CodeGen/X86/zext-trunc.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; rdar://7570931 + +define i64 @foo(i64 %a, i64 %b) nounwind { +; CHECK: foo: +; CHECK: leal +; CHECK-NOT: movl +; CHECK: ret + %c = add i64 %a, %b + %d = trunc i64 %c to i32 + %e = zext i32 %d to i64 + ret i64 %e +} |