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authorRoman Divacky <rdivacky@FreeBSD.org>2010-03-03 17:27:15 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-03-03 17:27:15 +0000
commit67a71b3184ce20a901e874d0ee25e01397dd87ef (patch)
tree836a05cff50ca46176117b86029f061fa4db54f0 /test/CodeGen/XCore
parent6fe5c7aa327e188b7176daa5595bbf075a6b94df (diff)
Notes
Diffstat (limited to 'test/CodeGen/XCore')
-rw-r--r--test/CodeGen/XCore/2010-02-25-LSR-Crash.ll26
-rw-r--r--test/CodeGen/XCore/switch.ll24
-rw-r--r--test/CodeGen/XCore/switch_long.ll132
3 files changed, 182 insertions, 0 deletions
diff --git a/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll b/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
new file mode 100644
index 0000000000000..6ad9a73899d1d
--- /dev/null
+++ b/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=xcore
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "xcore-xmos-elf"
+
+%0 = type { i32 }
+%struct.dwarf_fde = type <{ i32, i32, [0 x i8] }>
+%struct.object = type { i8*, i8*, i8*, %union.anon, %0, %struct.object* }
+%union.anon = type { %struct.dwarf_fde* }
+
+define %struct.dwarf_fde* @search_object(%struct.object* %ob, i8* %pc) {
+entry:
+ br i1 undef, label %bb3.i15.i.i, label %bb2
+
+bb3.i15.i.i: ; preds = %bb3.i15.i.i, %entry
+ %indvar.i.i.i = phi i32 [ %indvar.next.i.i.i, %bb3.i15.i.i ], [ 0, %entry ] ; <i32> [#uses=2]
+ %tmp137 = sub i32 0, %indvar.i.i.i ; <i32> [#uses=1]
+ %scevgep13.i.i.i = getelementptr i32* undef, i32 %tmp137 ; <i32*> [#uses=2]
+ %scevgep1314.i.i.i = bitcast i32* %scevgep13.i.i.i to %struct.dwarf_fde** ; <%struct.dwarf_fde**> [#uses=1]
+ %0 = load %struct.dwarf_fde** %scevgep1314.i.i.i, align 4 ; <%struct.dwarf_fde*> [#uses=0]
+ store i32 undef, i32* %scevgep13.i.i.i
+ %indvar.next.i.i.i = add i32 %indvar.i.i.i, 1 ; <i32> [#uses=1]
+ br label %bb3.i15.i.i
+
+bb2: ; preds = %entry
+ ret %struct.dwarf_fde* undef
+}
diff --git a/test/CodeGen/XCore/switch.ll b/test/CodeGen/XCore/switch.ll
new file mode 100644
index 0000000000000..9cc27f2ffaa44
--- /dev/null
+++ b/test/CodeGen/XCore/switch.ll
@@ -0,0 +1,24 @@
+; RUN: llc -march=xcore < %s | FileCheck %s
+
+define i32 @switch(i32 %i) {
+entry:
+ switch i32 %i, label %default [
+ i32 0, label %bb0
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ ]
+; CHECK-NOT: shl
+; CHECK: bru
+; CHECK: .jmptable
+bb0:
+ ret i32 0
+bb1:
+ ret i32 1
+bb2:
+ ret i32 2
+bb3:
+ ret i32 3
+default:
+ ret i32 4
+}
diff --git a/test/CodeGen/XCore/switch_long.ll b/test/CodeGen/XCore/switch_long.ll
new file mode 100644
index 0000000000000..30c9e3db73977
--- /dev/null
+++ b/test/CodeGen/XCore/switch_long.ll
@@ -0,0 +1,132 @@
+; RUN: llc -march=xcore < %s | FileCheck %s
+
+define i32 @switch(i32 %i) {
+entry:
+ switch i32 %i, label %default [
+ i32 0, label %bb0
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ i32 4, label %bb4
+ i32 5, label %bb5
+ i32 6, label %bb6
+ i32 7, label %bb7
+ i32 8, label %bb8
+ i32 9, label %bb9
+ i32 10, label %bb10
+ i32 11, label %bb11
+ i32 12, label %bb12
+ i32 13, label %bb13
+ i32 14, label %bb14
+ i32 15, label %bb15
+ i32 16, label %bb16
+ i32 17, label %bb17
+ i32 18, label %bb18
+ i32 19, label %bb19
+ i32 20, label %bb20
+ i32 21, label %bb21
+ i32 22, label %bb22
+ i32 23, label %bb23
+ i32 24, label %bb24
+ i32 25, label %bb25
+ i32 26, label %bb26
+ i32 27, label %bb27
+ i32 28, label %bb28
+ i32 29, label %bb29
+ i32 30, label %bb30
+ i32 31, label %bb31
+ i32 32, label %bb32
+ i32 33, label %bb33
+ i32 34, label %bb34
+ i32 35, label %bb35
+ i32 36, label %bb36
+ i32 37, label %bb37
+ i32 38, label %bb38
+ i32 39, label %bb39
+ ]
+; CHECK: shl
+; CHECK: bru
+; CHECK: .jmptable
+bb0:
+ ret i32 0
+bb1:
+ ret i32 1
+bb2:
+ ret i32 2
+bb3:
+ ret i32 3
+bb4:
+ ret i32 4
+bb5:
+ ret i32 5
+bb6:
+ ret i32 6
+bb7:
+ ret i32 7
+bb8:
+ ret i32 8
+bb9:
+ ret i32 9
+bb10:
+ ret i32 0
+bb11:
+ ret i32 1
+bb12:
+ ret i32 2
+bb13:
+ ret i32 3
+bb14:
+ ret i32 4
+bb15:
+ ret i32 5
+bb16:
+ ret i32 6
+bb17:
+ ret i32 7
+bb18:
+ ret i32 8
+bb19:
+ ret i32 9
+bb20:
+ ret i32 0
+bb21:
+ ret i32 1
+bb22:
+ ret i32 2
+bb23:
+ ret i32 3
+bb24:
+ ret i32 4
+bb25:
+ ret i32 5
+bb26:
+ ret i32 6
+bb27:
+ ret i32 7
+bb28:
+ ret i32 8
+bb29:
+ ret i32 9
+bb30:
+ ret i32 0
+bb31:
+ ret i32 1
+bb32:
+ ret i32 2
+bb33:
+ ret i32 3
+bb34:
+ ret i32 4
+bb35:
+ ret i32 5
+bb36:
+ ret i32 6
+bb37:
+ ret i32 7
+bb38:
+ ret i32 8
+bb39:
+ ret i32 9
+default:
+ ret i32 0
+}