diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2011-02-26 22:03:50 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2011-02-26 22:03:50 +0000 |
| commit | d0e4e96dc17a6c1c6de3340842c80f0e187ba349 (patch) | |
| tree | ddf53b8bd9235bcb0b8aae16c5e22310dcdad665 /test/CodeGen | |
| parent | cf099d11218cb6f6c5cce947d6738e347f07fb12 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
47 files changed, 939 insertions, 280 deletions
diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll new file mode 100644 index 0000000000000..ce440e986de00 --- /dev/null +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -0,0 +1,32 @@ +; RUN: llc %s -O0 -o /dev/null -mtriple=arm-apple-darwin +; PR 5197 +; There is not any llvm instruction assocated with !5. The code generator +; should be able to handle this. + +define void @bar() nounwind ssp { +entry: + %count_ = alloca i32, align 4 ; <i32*> [#uses=2] + br label %do.body, !dbg !0 + +do.body: ; preds = %entry + call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !4) + %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1] + %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0] + br label %do.end, !dbg !0 + +do.end: ; preds = %do.body + ret void, !dbg !7 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare i32 @foo(i32) ssp + +!0 = metadata !{i32 5, i32 2, metadata !1, null} +!1 = metadata !{i32 458763, metadata !2}; [DW_TAG_lexical_block ] +!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ] +!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ] +!4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ] +!5 = metadata !{i32 458763, metadata !1}; [DW_TAG_lexical_block ] +!6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ] +!7 = metadata !{i32 6, i32 1, metadata !2, null} diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll new file mode 100644 index 0000000000000..f077d04803bdf --- /dev/null +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -0,0 +1,124 @@ +; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_fbreg +; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. + +%struct.SVal = type { i8*, i32 } + +define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { +entry: + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !23), !dbg !24 + call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !25), !dbg !24 + %0 = icmp ne i32 %i, 0, !dbg !27 ; <i1> [#uses=1] + br i1 %0, label %bb, label %bb1, !dbg !27 + +bb: ; preds = %entry + %1 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1] + %2 = load i32* %1, align 8, !dbg !29 ; <i32> [#uses=1] + %3 = add i32 %2, %i, !dbg !29 ; <i32> [#uses=1] + br label %bb2, !dbg !29 + +bb1: ; preds = %entry + %4 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1] + %5 = load i32* %4, align 8, !dbg !30 ; <i32> [#uses=1] + %6 = sub i32 %5, 1, !dbg !30 ; <i32> [#uses=1] + br label %bb2, !dbg !30 + +bb2: ; preds = %bb1, %bb + %.0 = phi i32 [ %3, %bb ], [ %6, %bb1 ] ; <i32> [#uses=1] + br label %return, !dbg !29 + +return: ; preds = %bb2 + ret i32 %.0, !dbg !29 +} + +define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { +entry: + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31), !dbg !34 + %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1] + store i8* null, i8** %0, align 8, !dbg !34 + %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1] + store i32 0, i32* %1, align 8, !dbg !34 + br label %return, !dbg !34 + +return: ; preds = %entry + ret void, !dbg !35 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define i32 @main() nounwind ssp { +entry: + %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] + %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !38), !dbg !41 + call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 + %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1] + store i32 1, i32* %1, align 8, !dbg !42 + %2 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %3 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %4 = load i8** %3, align 8, !dbg !43 ; <i8*> [#uses=1] + store i8* %4, i8** %2, align 8, !dbg !43 + %5 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %6 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %7 = load i32* %6, align 8, !dbg !43 ; <i32> [#uses=1] + store i32 %7, i32* %5, align 8, !dbg !43 + %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !44), !dbg !43 + br label %return, !dbg !45 + +return: ; preds = %entry + ret i32 0, !dbg !45 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !9, !16, !17, !20} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524307, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] +!2 = metadata !{i32 524329, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} +!5 = metadata !{i32 524301, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 524301, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] +!8 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{null, metadata !12, metadata !13} +!12 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] +!15 = metadata !{null, metadata !12} +!16 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] +!18 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] +!19 = metadata !{metadata !13, metadata !13, metadata !1} +!20 = metadata !{i32 524334, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!21 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] +!22 = metadata !{metadata !13} +!23 = metadata !{i32 524545, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 16, i32 0, metadata !17, null} +!25 = metadata !{i32 524545, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 524304, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!27 = metadata !{i32 17, i32 0, metadata !28, null} +!28 = metadata !{i32 524299, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 18, i32 0, metadata !28, null} +!30 = metadata !{i32 20, i32 0, metadata !28, null} +!31 = metadata !{i32 524545, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32} ; [ DW_TAG_arg_variable ] +!32 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] +!33 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] +!34 = metadata !{i32 11, i32 0, metadata !16, null} +!35 = metadata !{i32 11, i32 0, metadata !36, null} +!36 = metadata !{i32 524299, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 524299, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!38 = metadata !{i32 524544, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1} ; [ DW_TAG_auto_variable ] +!39 = metadata !{i32 524299, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524299, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 24, i32 0, metadata !39, null} +!42 = metadata !{i32 25, i32 0, metadata !39, null} +!43 = metadata !{i32 26, i32 0, metadata !39, null} +!44 = metadata !{i32 524544, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13} ; [ DW_TAG_auto_variable ] +!45 = metadata !{i32 27, i32 0, metadata !39, null} diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 99baad2d38d1d..94842124fb086 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -17,13 +17,12 @@ target triple = "thumbv7-apple-darwin10" ; DW_OP_constu ; offset -;CHECK: .byte 7 @ Abbrev [7] 0x1a5:0x13 DW_TAG_variable -;CHECK-NEXT: .ascii "x2" @ DW_AT_name +;CHECK: .ascii "x2" @ DW_AT_name ;CHECK-NEXT: .byte 0 -;CHECK-NEXT: .long 93 @ DW_AT_type -;CHECK-NEXT: .byte 1 @ DW_AT_decl_file -;CHECK-NEXT: .byte 6 @ DW_AT_decl_line -;CHECK-NEXT: .byte 8 @ DW_AT_location +;CHECK-NEXT: @ DW_AT_type +;CHECK-NEXT: @ DW_AT_decl_file +;CHECK-NEXT: @ DW_AT_decl_line +;CHECK-NEXT: @ DW_AT_location ;CHECK-NEXT: .byte 3 ;CHECK-NEXT: .long __MergedGlobals ;CHECK-NEXT: .byte 16 diff --git a/test/CodeGen/ARM/available_externally.ll b/test/CodeGen/ARM/available_externally.ll new file mode 100644 index 0000000000000..0f646d582e71d --- /dev/null +++ b/test/CodeGen/ARM/available_externally.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s +; rdar://9027648 + +@A = available_externally hidden constant i32 1 +@B = external hidden constant i32 + +define i32 @t1() { + %tmp = load i32* @A + store i32 %tmp, i32* @B + ret i32 %tmp +} + +; CHECK: L_A$non_lazy_ptr: +; CHECK-NEXT: .long _A +; CHECK: L_B$non_lazy_ptr: +; CHECK-NEXT: .long _B diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index 1050cd265998b..d30e3ebf50a58 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -9,9 +9,8 @@ entry: ; SOFT: bfi r0, r1, #31, #1 ; HARD: test1: -; HARD: vabs.f32 d0, d0 -; HARD: cmp r0, #0 -; HARD: vneglt.f32 s0, s0 +; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000 +; HARD: vbsl [[REG1]], d2, d0 %0 = tail call float @copysignf(float %x, float %y) nounwind ret float %0 } @@ -23,9 +22,9 @@ entry: ; SOFT: bfi r1, r2, #31, #1 ; HARD: test2: -; HARD: vabs.f64 d0, d0 -; HARD: cmp r1, #0 -; HARD: vneglt.f64 d0, d0 +; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000 +; HARD: vshl.i64 [[REG2]], [[REG2]], #32 +; HARD: vbsl [[REG2]], d1, d0 %0 = tail call double @copysign(double %x, double %y) nounwind ret double %0 } @@ -33,9 +32,9 @@ entry: define double @test3(double %x, double %y, double %z) nounwind { entry: ; SOFT: test3: -; SOFT: vabs.f64 -; SOFT: cmp {{.*}}, #0 -; SOFT: vneglt.f64 +; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000 +; SOFT: vshl.i64 [[REG3]], [[REG3]], #32 +; SOFT: vbsl [[REG3]], %0 = fmul double %x, %y %1 = tail call double @copysign(double %0, double %z) nounwind ret double %1 diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 6cc052bbeb1ca..d1bc15ad576da 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -10,6 +10,19 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { +;CHECK: vst1lanei8_update: +;CHECK: vst1.8 {d16[3]}, [r2]! + %A = load i8** %ptr + %tmp1 = load <8 x i8>* %B + %tmp2 = extractelement <8 x i8> %tmp1, i32 3 + store i8 %tmp2, i8* %A, align 8 + %tmp3 = getelementptr i8* %A, i32 1 + store i8* %tmp3, i8** %ptr + ret void +} + define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: @@ -66,6 +79,19 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { +;CHECK: vst1laneQi32_update: +;CHECK: vst1.32 {d17[1]}, [r1, :32]! + %A = load i32** %ptr + %tmp1 = load <4 x i32>* %B + %tmp2 = extractelement <4 x i32> %tmp1, i32 3 + store i32 %tmp2, i32* %A, align 8 + %tmp3 = getelementptr i32* %A, i32 1 + store i32* %tmp3, i32** %ptr + ret void +} + define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst1laneQf: ;CHECK: vst1.32 {d17[1]}, [r0] diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll index bc27e987a179f..71fdb4e0d60f4 100644 --- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll +++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll @@ -7,7 +7,7 @@ entry: ; CHECK: test ; CHECK: call bar ; CHECK-NOT: nop -; CHECK: ret +; CHECK: jmp ; CHECK-NEXT: restore %0 = tail call i32 @bar(i32 %a) nounwind ret i32 %0 @@ -18,7 +18,7 @@ entry: ; CHECK: test_jmpl ; CHECK: call ; CHECK-NOT: nop -; CHECK: ret +; CHECK: jmp ; CHECK-NEXT: restore %0 = tail call i32 %f(i32 %a, i32 %b) nounwind ret i32 %0 @@ -47,7 +47,7 @@ bb: ; preds = %entry, %bb bb5: ; preds = %bb, %entry %a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ] -;CHECK: ret +;CHECK: jmp ;CHECK-NEXT: restore ret i32 %a_addr.1.lcssa } diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll index 2f684b009c960..506d3a8f87afb 100644 --- a/test/CodeGen/SPARC/2011-01-22-SRet.ll +++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll @@ -7,7 +7,7 @@ entry: ;CHECK: make_foo ;CHECK: ld [%fp+64], {{.+}} ;CHECK: or {{.+}}, {{.+}}, %i0 -;CHECK: ret +;CHECK: jmp %i7+12 %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0 store i32 %a, i32* %0, align 4 %1 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 1 @@ -22,6 +22,7 @@ entry: ;CHECK: test ;CHECK: st {{.+}}, [%sp+64] ;CHECK: make_foo +;CHECK: unimp 12 %f = alloca %struct.foo_t, align 8 call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind %0 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 0 diff --git a/test/CodeGen/X86/2009-10-16-Scope.ll b/test/CodeGen/X86/2009-10-16-Scope.ll new file mode 100644 index 0000000000000..86c20243c8748 --- /dev/null +++ b/test/CodeGen/X86/2009-10-16-Scope.ll @@ -0,0 +1,32 @@ +; RUN: llc %s -O0 -o /dev/null -mtriple=x86_64-apple-darwin +; PR 5197 +; There is not any llvm instruction assocated with !5. The code generator +; should be able to handle this. + +define void @bar() nounwind ssp { +entry: + %count_ = alloca i32, align 4 ; <i32*> [#uses=2] + br label %do.body, !dbg !0 + +do.body: ; preds = %entry + call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !4) + %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1] + %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0] + br label %do.end, !dbg !0 + +do.end: ; preds = %do.body + ret void, !dbg !7 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare i32 @foo(i32) ssp + +!0 = metadata !{i32 5, i32 2, metadata !1, null} +!1 = metadata !{i32 458763, metadata !2}; [DW_TAG_lexical_block ] +!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ] +!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ] +!4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ] +!5 = metadata !{i32 458763, metadata !1}; [DW_TAG_lexical_block ] +!6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ] +!7 = metadata !{i32 6, i32 1, metadata !2, null} diff --git a/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll b/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll index 9b9d63609ab45..2ba12dfc56804 100644 --- a/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll +++ b/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll @@ -7,7 +7,7 @@ ; CHECK-NEXT: .byte 37 ## DW_AT_producer ; CHECK-NEXT: .byte 8 ## DW_FORM_string ; CHECK-NEXT: .byte 19 ## DW_AT_language -; CHECK-NEXT: .byte 11 ## DW_FORM_data1 +; CHECK-NEXT: .byte 5 ## DW_FORM_data2 ; CHECK-NEXT: .byte 3 ## DW_AT_name ; CHECK-NEXT: .byte 8 ## DW_FORM_string ; CHECK-NEXT: .byte 82 ## DW_AT_entry_pc diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll new file mode 100644 index 0000000000000..edfd1b8687371 --- /dev/null +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -0,0 +1,124 @@ +; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_fbreg +; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. + +%struct.SVal = type { i8*, i32 } + +define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { +entry: + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !23), !dbg !24 + call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !25), !dbg !24 + %0 = icmp ne i32 %i, 0, !dbg !27 ; <i1> [#uses=1] + br i1 %0, label %bb, label %bb1, !dbg !27 + +bb: ; preds = %entry + %1 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1] + %2 = load i32* %1, align 8, !dbg !29 ; <i32> [#uses=1] + %3 = add i32 %2, %i, !dbg !29 ; <i32> [#uses=1] + br label %bb2, !dbg !29 + +bb1: ; preds = %entry + %4 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1] + %5 = load i32* %4, align 8, !dbg !30 ; <i32> [#uses=1] + %6 = sub i32 %5, 1, !dbg !30 ; <i32> [#uses=1] + br label %bb2, !dbg !30 + +bb2: ; preds = %bb1, %bb + %.0 = phi i32 [ %3, %bb ], [ %6, %bb1 ] ; <i32> [#uses=1] + br label %return, !dbg !29 + +return: ; preds = %bb2 + ret i32 %.0, !dbg !29 +} + +define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { +entry: + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31), !dbg !34 + %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1] + store i8* null, i8** %0, align 8, !dbg !34 + %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1] + store i32 0, i32* %1, align 8, !dbg !34 + br label %return, !dbg !34 + +return: ; preds = %entry + ret void, !dbg !35 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define i32 @main() nounwind ssp { +entry: + %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] + %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !38), !dbg !41 + call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 + %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1] + store i32 1, i32* %1, align 8, !dbg !42 + %2 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %3 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %4 = load i8** %3, align 8, !dbg !43 ; <i8*> [#uses=1] + store i8* %4, i8** %2, align 8, !dbg !43 + %5 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %6 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %7 = load i32* %6, align 8, !dbg !43 ; <i32> [#uses=1] + store i32 %7, i32* %5, align 8, !dbg !43 + %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; <i32> [#uses=0] + call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !44), !dbg !43 + br label %return, !dbg !45 + +return: ; preds = %entry + ret i32 0, !dbg !45 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !9, !16, !17, !20} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524307, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] +!2 = metadata !{i32 524329, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} +!5 = metadata !{i32 524301, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 524301, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] +!8 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{null, metadata !12, metadata !13} +!12 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] +!15 = metadata !{null, metadata !12} +!16 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] +!18 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] +!19 = metadata !{metadata !13, metadata !13, metadata !1} +!20 = metadata !{i32 524334, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!21 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] +!22 = metadata !{metadata !13} +!23 = metadata !{i32 524545, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 16, i32 0, metadata !17, null} +!25 = metadata !{i32 524545, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 524304, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!27 = metadata !{i32 17, i32 0, metadata !28, null} +!28 = metadata !{i32 524299, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 18, i32 0, metadata !28, null} +!30 = metadata !{i32 20, i32 0, metadata !28, null} +!31 = metadata !{i32 524545, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32} ; [ DW_TAG_arg_variable ] +!32 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] +!33 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] +!34 = metadata !{i32 11, i32 0, metadata !16, null} +!35 = metadata !{i32 11, i32 0, metadata !36, null} +!36 = metadata !{i32 524299, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 524299, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!38 = metadata !{i32 524544, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1} ; [ DW_TAG_auto_variable ] +!39 = metadata !{i32 524299, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524299, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 24, i32 0, metadata !39, null} +!42 = metadata !{i32 25, i32 0, metadata !39, null} +!43 = metadata !{i32 26, i32 0, metadata !39, null} +!44 = metadata !{i32 524544, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13} ; [ DW_TAG_auto_variable ] +!45 = metadata !{i32 27, i32 0, metadata !39, null} diff --git a/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll b/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll new file mode 100644 index 0000000000000..f982723781ea8 --- /dev/null +++ b/test/CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -O2 -march=x86 -mtriple=i386-pc-linux-gnu -relocation-model=pic | FileCheck %s +; PR9237: Assertion in VirtRegRewriter.cpp, ResurrectConfirmedKill +; `KillOps[*SR] == KillOp && "invalid subreg kill flags"' + +%t = type { i32 } + +define i32 @foo(%t* %s) nounwind { +entry: + br label %if.then735 + +if.then735: + %call747 = call i32 undef(%t* %s, i8* null, i8* undef, i32 128, i8* undef, i32 516) nounwind + br i1 undef, label %if.then751, label %if.then758 + +if.then751: + unreachable + +if.then758: + %add761 = add i32 %call747, 4 + %add763 = add i32 %add761, %call747 + %add.ptr768 = getelementptr inbounds [516 x i8]* null, i32 0, i32 %add761 + br i1 undef, label %cond.false783, label %cond.true771 + +cond.true771: + %call782 = call i8* @__memmove_chk(i8* %add.ptr768, i8* undef, i32 %call747, i32 undef) + br label %cond.end791 + +; CHECK: calll __memmove_chk +cond.false783: + %call.i1035 = call i8* @__memmove_chk(i8* %add.ptr768, i8* undef, i32 %call747, i32 undef) nounwind + br label %cond.end791 + +cond.end791: + %conv801 = trunc i32 %call747 to i8 + %add.ptr822.sum = add i32 %call747, 3 + %arrayidx833 = getelementptr inbounds [516 x i8]* null, i32 0, i32 %add.ptr822.sum + store i8 %conv801, i8* %arrayidx833, align 1 + %cmp841 = icmp eq i8* undef, null + br i1 %cmp841, label %if.end849, label %if.then843 + +if.then843: + unreachable + +if.end849: + %call921 = call i32 undef(%t* %s, i8* undef, i8* undef, i32 %add763) nounwind + unreachable + +} + +declare i8* @__memmove_chk(i8*, i8*, i32, i32) nounwind diff --git a/test/CodeGen/X86/2011-02-23-UnfoldBug.ll b/test/CodeGen/X86/2011-02-23-UnfoldBug.ll new file mode 100644 index 0000000000000..900106aac351d --- /dev/null +++ b/test/CodeGen/X86/2011-02-23-UnfoldBug.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 +; rdar://9045024 +; PR9305 + +define void @calc_gb_rad_still_sse2_double() nounwind ssp { +entry: + br label %for.cond.outer + +for.cond.outer: ; preds = %if.end71, %entry + %theta.0.ph = phi <2 x double> [ undef, %entry ], [ %theta.1, %if.end71 ] + %mul.i97 = fmul <2 x double> %theta.0.ph, undef + %mul.i96 = fmul <2 x double> %mul.i97, fmul (<2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> undef) + br i1 undef, label %for.body, label %for.end82 + +for.body: ; preds = %for.cond.outer + br i1 undef, label %for.body33.lr.ph, label %for.end + +for.body33.lr.ph: ; preds = %for.body + %dccf.2 = select i1 undef, <2 x double> %mul.i96, <2 x double> undef + unreachable + +for.end: ; preds = %for.body + %vecins.i94 = insertelement <2 x double> undef, double 0.000000e+00, i32 0 + %cmpsd.i = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %vecins.i94, <2 x double> <double 0x3FE984B204153B34, double 0x3FE984B204153B34>, i8 2) nounwind + tail call void (...)* @_mm_movemask_pd(<2 x double> %cmpsd.i) nounwind + br i1 undef, label %if.then67, label %if.end71 + +if.then67: ; preds = %for.end + %vecins.i91 = insertelement <2 x double> %vecins.i94, double undef, i32 0 + br label %if.end71 + +if.end71: ; preds = %if.then67, %for.end + %theta.1 = phi <2 x double> [ %vecins.i91, %if.then67 ], [ %theta.0.ph, %for.end ] + br label %for.cond.outer + +for.end82: ; preds = %for.cond.outer + ret void +} + +declare void @_mm_movemask_pd(...) + +declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll index 3ec5358affb32..62c898025c80a 100644 --- a/test/CodeGen/X86/add.ll +++ b/test/CodeGen/X86/add.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64 ; The immediate can be encoded in a smaller way if the ; instruction is a sub instead of an add. @@ -43,7 +44,7 @@ overflow: ; X32-NEXT: jo ; X64: test4: -; X64: addl %esi, %edi +; X64: addl %e[[A1:si|dx]], %e[[A0:di|cx]] ; X64-NEXT: jo } @@ -66,7 +67,7 @@ carry: ; X32-NEXT: jb ; X64: test5: -; X64: addl %esi, %edi +; X64: addl %e[[A1]], %e[[A0]] ; X64-NEXT: jb } @@ -87,8 +88,8 @@ define i64 @test6(i64 %A, i32 %B) nounwind { ; X32-NEXT: ret ; X64: test6: -; X64: shlq $32, %rsi -; X64: leaq (%rsi,%rdi), %rax +; X64: shlq $32, %r[[A1]] +; X64: leaq (%r[[A1]],%r[[A0]]), %rax ; X64: ret } @@ -98,7 +99,7 @@ define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind { } ; X64: test7: -; X64: addl %esi, %eax +; X64: addl %e[[A1]], %eax ; X64-NEXT: setb %dl ; X64-NEXT: ret diff --git a/test/CodeGen/X86/break-sse-dep.ll b/test/CodeGen/X86/break-sse-dep.ll index 094cbc7bdefc0..2dee5754256a1 100644 --- a/test/CodeGen/X86/break-sse-dep.ll +++ b/test/CodeGen/X86/break-sse-dep.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s define double @t1(float* nocapture %x) nounwind readonly ssp { entry: ; CHECK: t1: -; CHECK: movss (%rdi), %xmm0 +; CHECK: movss ([[A0:%rdi|%rcx]]), %xmm0 ; CHECK: cvtss2sd %xmm0, %xmm0 %0 = load float* %x, align 4 @@ -14,7 +15,7 @@ entry: define float @t2(double* nocapture %x) nounwind readonly ssp optsize { entry: ; CHECK: t2: -; CHECK: cvtsd2ss (%rdi), %xmm0 +; CHECK: cvtsd2ss ([[A0]]), %xmm0 %0 = load double* %x, align 8 %1 = fptrunc double %0 to float ret float %1 @@ -23,7 +24,7 @@ entry: define float @squirtf(float* %x) nounwind { entry: ; CHECK: squirtf: -; CHECK: movss (%rdi), %xmm0 +; CHECK: movss ([[A0]]), %xmm0 ; CHECK: sqrtss %xmm0, %xmm0 %z = load float* %x %t = call float @llvm.sqrt.f32(float %z) @@ -33,7 +34,7 @@ entry: define double @squirt(double* %x) nounwind { entry: ; CHECK: squirt: -; CHECK: movsd (%rdi), %xmm0 +; CHECK: movsd ([[A0]]), %xmm0 ; CHECK: sqrtsd %xmm0, %xmm0 %z = load double* %x %t = call double @llvm.sqrt.f64(double %z) @@ -43,7 +44,7 @@ entry: define float @squirtf_size(float* %x) nounwind optsize { entry: ; CHECK: squirtf_size: -; CHECK: sqrtss (%rdi), %xmm0 +; CHECK: sqrtss ([[A0]]), %xmm0 %z = load float* %x %t = call float @llvm.sqrt.f32(float %z) ret float %t @@ -52,7 +53,7 @@ entry: define double @squirt_size(double* %x) nounwind optsize { entry: ; CHECK: squirt_size: -; CHECK: sqrtsd (%rdi), %xmm0 +; CHECK: sqrtsd ([[A0]]), %xmm0 %z = load double* %x %t = call double @llvm.sqrt.f64(double %z) ret double %t diff --git a/test/CodeGen/X86/codegen-dce.ll b/test/CodeGen/X86/codegen-dce.ll deleted file mode 100644 index d83efaf577661..0000000000000 --- a/test/CodeGen/X86/codegen-dce.ll +++ /dev/null @@ -1,43 +0,0 @@ -; RUN: llc < %s -march=x86 -stats |& grep {codegen-dce} | grep {Number of dead instructions deleted} - - %struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] } - %struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* } - %struct.node = type { i16, double, [3 x double], i32, i32 } - -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { -entry: - %0 = malloc %struct.anon ; <%struct.anon*> [#uses=2] - %1 = getelementptr %struct.anon* %0, i32 0, i32 2 ; <%struct.node**> [#uses=1] - br label %bb14.i - -bb14.i: ; preds = %bb14.i, %entry - %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %2, %bb14.i ] ; <i32> [#uses=1] - %2 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2] - %exitcond74.i = icmp eq i32 %2, 32 ; <i1> [#uses=1] - br i1 %exitcond74.i, label %bb32.i, label %bb14.i - -bb32.i: ; preds = %bb32.i, %bb14.i - %tmp.0.reg2mem.0.i = phi i32 [ %indvar.next63.i, %bb32.i ], [ 0, %bb14.i ] ; <i32> [#uses=1] - %indvar.next63.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2] - %exitcond64.i = icmp eq i32 %indvar.next63.i, 64 ; <i1> [#uses=1] - br i1 %exitcond64.i, label %bb47.loopexit.i, label %bb32.i - -bb.i.i: ; preds = %bb47.loopexit.i - unreachable - -stepsystem.exit.i: ; preds = %bb47.loopexit.i - store %struct.node* null, %struct.node** %1, align 4 - br label %bb.i6.i - -bb.i6.i: ; preds = %bb.i6.i, %stepsystem.exit.i - br i1 false, label %bb107.i.i, label %bb.i6.i - -bb107.i.i: ; preds = %bb107.i.i, %bb.i6.i - %q_addr.0.i.i.in = phi %struct.bnode** [ null, %bb107.i.i ], [ %3, %bb.i6.i ] ; <%struct.bnode**> [#uses=0] - br label %bb107.i.i - -bb47.loopexit.i: ; preds = %bb32.i - %3 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 0 ; <%struct.bnode**> [#uses=1] - %4 = icmp eq %struct.node* null, null ; <i1> [#uses=1] - br i1 %4, label %stepsystem.exit.i, label %bb.i.i -} diff --git a/test/CodeGen/X86/codegen-prepare-extload.ll b/test/CodeGen/X86/codegen-prepare-extload.ll index 9f57d53178f3d..14df815663e3d 100644 --- a/test/CodeGen/X86/codegen-prepare-extload.ll +++ b/test/CodeGen/X86/codegen-prepare-extload.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s ; rdar://7304838 ; CodeGenPrepare should move the zext into the block with the load ; so that SelectionDAG can select it with the load. -; CHECK: movzbl (%rdi), %eax +; CHECK: movzbl ({{%rdi|%rcx}}), %eax define void @foo(i8* %p, i32* %q) { entry: diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll index 33de5767ad65a..f979945835ffc 100644 --- a/test/CodeGen/X86/constant-pool-sharing.ll +++ b/test/CodeGen/X86/constant-pool-sharing.ll @@ -1,11 +1,12 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; llc should share constant pool entries between this integer vector ; and this floating-point vector since they have the same encoding. ; CHECK: LCPI0_0(%rip), %xmm0 -; CHECK: movaps %xmm0, (%rdi) -; CHECK: movaps %xmm0, (%rsi) +; CHECK: movaps %xmm0, ({{%rdi|%rcx}}) +; CHECK: movaps %xmm0, ({{%rsi|%rdx}}) define void @foo(<4 x i32>* %p, <4 x float>* %q, i1 %t) nounwind { entry: diff --git a/test/CodeGen/X86/ctpop-combine.ll b/test/CodeGen/X86/ctpop-combine.ll index c957d385a24a1..6406cc73e4128 100644 --- a/test/CodeGen/X86/ctpop-combine.ll +++ b/test/CodeGen/X86/ctpop-combine.ll @@ -9,7 +9,7 @@ define i32 @test1(i64 %x) nounwind readnone { %conv = zext i1 %cmp to i32 ret i32 %conv ; CHECK: test1: -; CHECK: leaq -1(%rdi) +; CHECK: leaq -1([[A0:%rdi|%rcx]]) ; CHECK-NEXT: testq ; CHECK-NEXT: setne ; CHECK: ret @@ -22,7 +22,7 @@ define i32 @test2(i64 %x) nounwind readnone { %conv = zext i1 %cmp to i32 ret i32 %conv ; CHECK: test2: -; CHECK: leaq -1(%rdi) +; CHECK: leaq -1([[A0]]) ; CHECK-NEXT: testq ; CHECK-NEXT: sete ; CHECK: ret diff --git a/test/CodeGen/X86/dbg-live-in-location.ll b/test/CodeGen/X86/dbg-live-in-location.ll deleted file mode 100644 index 9b1464d415f98..0000000000000 --- a/test/CodeGen/X86/dbg-live-in-location.ll +++ /dev/null @@ -1,84 +0,0 @@ -; RUN: llc < %s | FileCheck %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin10.0.0" - -@str = internal constant [3 x i8] c"Hi\00" - -define void @foo() nounwind ssp { -entry: - %puts = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0)) - ret void, !dbg !17 -} - -; CHECK: arg.c:5:14 - -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { -entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !9), !dbg !19 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !10), !dbg !20 - %cmp = icmp sgt i32 %argc, 1, !dbg !21 - br i1 %cmp, label %cond.end, label %for.body.lr.ph, !dbg !21 - -cond.end: ; preds = %entry - %arrayidx = getelementptr inbounds i8** %argv, i64 1, !dbg !21 - %tmp2 = load i8** %arrayidx, align 8, !dbg !21, !tbaa !22 - %call = tail call i32 (...)* @atoi(i8* %tmp2) nounwind, !dbg !21 - tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !16), !dbg !21 - tail call void @llvm.dbg.value(metadata !25, i64 0, metadata !14), !dbg !26 - %cmp57 = icmp sgt i32 %call, 0, !dbg !26 - br i1 %cmp57, label %for.body.lr.ph, label %for.end, !dbg !26 - -for.body.lr.ph: ; preds = %entry, %cond.end - %cond10 = phi i32 [ %call, %cond.end ], [ 300, %entry ] - br label %for.body - -for.body: ; preds = %for.body, %for.body.lr.ph - %i.08 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] - %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0)) nounwind - %inc = add nsw i32 %i.08, 1, !dbg !27 - %exitcond = icmp eq i32 %inc, %cond10 - br i1 %exitcond, label %for.end, label %for.body, !dbg !26 - -for.end: ; preds = %for.body, %cond.end - ret i32 0, !dbg !29 -} - -declare i32 @atoi(...) - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -declare i32 @puts(i8* nocapture) nounwind - -!llvm.dbg.sp = !{!0, !5} -!llvm.dbg.lv.main = !{!9, !10, !14, !16} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 124504)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{null} -!5 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ] -!6 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!7 = metadata !{metadata !8} -!8 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 590081, metadata !5, metadata !"argc", metadata !1, i32 5, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] -!10 = metadata !{i32 590081, metadata !5, metadata !"argv", metadata !1, i32 5, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] -!11 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] -!12 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] -!13 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 590080, metadata !15, metadata !"i", metadata !1, i32 7, metadata !8, i32 0} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 589835, metadata !5, i32 6, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 590080, metadata !15, metadata !"iterations", metadata !1, i32 8, metadata !8, i32 0} ; [ DW_TAG_auto_variable ] -!17 = metadata !{i32 4, i32 1, metadata !18, null} -!18 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!19 = metadata !{i32 5, i32 14, metadata !5, null} -!20 = metadata !{i32 5, i32 26, metadata !5, null} -!21 = metadata !{i32 8, i32 51, metadata !15, null} -!22 = metadata !{metadata !"any pointer", metadata !23} -!23 = metadata !{metadata !"omnipotent char", metadata !24} -!24 = metadata !{metadata !"Simple C/C++ TBAA", null} -!25 = metadata !{i32 0} -!26 = metadata !{i32 9, i32 2, metadata !15, null} -!27 = metadata !{i32 9, i32 30, metadata !28, null} -!28 = metadata !{i32 589835, metadata !15, i32 9, i32 2, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!29 = metadata !{i32 12, i32 9, metadata !15, null} diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll index 2449046c65fb1..87d7e910c3391 100644 --- a/test/CodeGen/X86/dbg-value-location.ll +++ b/test/CodeGen/X86/dbg-value-location.ll @@ -5,10 +5,10 @@ target triple = "x86_64-apple-darwin10.0.0" ;CHECK: .ascii "var" ## DW_AT_name ;CHECK-NEXT: .byte 0 -;CHECK-NEXT: .byte 2 ## DW_AT_decl_file -;CHECK-NEXT: .short 19509 ## DW_AT_decl_line -;CHECK-NEXT: .long 68 ## DW_AT_type -;CHECK-NEXT: .byte 1 ## DW_AT_location +;CHECK-NEXT: ## DW_AT_decl_file +;CHECK-NEXT: ## DW_AT_decl_line +;CHECK-NEXT: ## DW_AT_type +;CHECK-NEXT: ## DW_AT_location @dfm = external global i32, align 4 diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index 7ceb972f61bbf..fe335b9369cbc 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -40,7 +40,7 @@ entry: %div = sdiv i16 %x, 33 ; <i32> [#uses=1] ret i16 %div ; CHECK: test4: -; CHECK: imull $-1985, %ecx, %ecx +; CHECK: imull $1986, %eax, %eax } define i32 @test5(i32 %A) nounwind { diff --git a/test/CodeGen/X86/dll-linkage.ll b/test/CodeGen/X86/dll-linkage.ll index 913617585206b..a0c2a54a99a46 100644 --- a/test/CodeGen/X86/dll-linkage.ll +++ b/test/CodeGen/X86/dll-linkage.ll @@ -1,9 +1,14 @@ ; RUN: llc < %s -mtriple=i386-pc-mingw32 | FileCheck %s +; RUN: llc < %s -mtriple=i386-pc-mingw32 -O0 | FileCheck %s -check-prefix=FAST +; PR6275 + declare dllimport void @foo() define void @bar() nounwind { ; CHECK: calll *__imp__foo +; FAST: movl __imp__foo, [[R:%[a-z]{3}]] +; FAST: calll *[[R]] call void @foo() ret void } diff --git a/test/CodeGen/X86/fast-isel-cmp-branch.ll b/test/CodeGen/X86/fast-isel-cmp-branch.ll index 4ab1bc61c7e2c..12312e8a581c4 100644 --- a/test/CodeGen/X86/fast-isel-cmp-branch.ll +++ b/test/CodeGen/X86/fast-isel-cmp-branch.ll @@ -1,13 +1,14 @@ -; RUN: llc -O0 -march=x86-64 -asm-verbose=false < %s | FileCheck %s +; RUN: llc -O0 -mtriple=x86_64-linux -asm-verbose=false < %s | FileCheck %s +; RUN: llc -O0 -mtriple=x86_64-win32 -asm-verbose=false < %s | FileCheck %s ; rdar://8337108 ; Fast-isel shouldn't try to look through the compare because it's in a ; different basic block, so its operands aren't necessarily exported ; for cross-block usage. -; CHECK: movb %al, 7(%rsp) +; CHECK: movb %al, [[OFS:[0-9]*]](%rsp) ; CHECK: callq {{_?}}bar -; CHECK: movb 7(%rsp), %al +; CHECK: movb [[OFS]](%rsp), %al declare void @bar() diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll index 622a1ff831d03..fbe0243716bd6 100644 --- a/test/CodeGen/X86/fast-isel-gep.ll +++ b/test/CodeGen/X86/fast-isel-gep.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -O0 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -O0 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -march=x86 -O0 | FileCheck %s --check-prefix=X32 ; GEP indices are interpreted as signed integers, so they @@ -13,8 +14,8 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind { ; X32: ret ; X64: test1: -; X64: movslq %edi, %rax -; X64: movl (%rsi,%rax,4), %eax +; X64: movslq %e[[A0:di|cx]], %rax +; X64: movl (%r[[A1:si|dx]],%rax,4), %eax ; X64: ret } @@ -27,7 +28,7 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind { ; X32: ret ; X64: test2: -; X64: movl (%rsi,%rdi,4), %eax +; X64: movl (%r[[A1]],%r[[A0]],4), %eax ; X64: ret } @@ -47,7 +48,7 @@ entry: ; X32: ret ; X64: test3: -; X64: movb -2(%rdi), %al +; X64: movb -2(%r[[A0]]), %al ; X64: ret } @@ -80,9 +81,9 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { %v11 = add i64 %B, %v10 ret i64 %v11 ; X64: test5: -; X64: movslq %esi, %rax -; X64-NEXT: movq (%rdi,%rax), %rax -; X64-NEXT: addq %rdx, %rax +; X64: movslq %e[[A1]], %rax +; X64-NEXT: movq (%r[[A0]],%rax), %rax +; X64-NEXT: addq %{{rdx|r8}}, %rax ; X64-NEXT: ret } diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll index 134ee28df6c8e..4a6927f6a269b 100644 --- a/test/CodeGen/X86/gather-addresses.ll +++ b/test/CodeGen/X86/gather-addresses.ll @@ -1,20 +1,21 @@ -; RUN: llc -march=x86-64 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-win32 < %s | FileCheck %s ; rdar://7398554 ; When doing vector gather-scatter index calculation with 32-bit indices, ; bounce the vector off of cache rather than shuffling each individual ; element out of the index vector. -; CHECK: andps (%rdx), %xmm0 -; CHECK: movaps %xmm0, -24(%rsp) -; CHECK: movslq -24(%rsp), %rax -; CHECK: movsd (%rdi,%rax,8), %xmm0 -; CHECK: movslq -20(%rsp), %rax -; CHECK: movhpd (%rdi,%rax,8), %xmm0 -; CHECK: movslq -16(%rsp), %rax -; CHECK: movsd (%rdi,%rax,8), %xmm1 -; CHECK: movslq -12(%rsp), %rax -; CHECK: movhpd (%rdi,%rax,8), %xmm1 +; CHECK: andps ([[H:%rdx|%r8]]), %xmm0 +; CHECK: movaps %xmm0, {{(-24)?}}(%rsp) +; CHECK: movslq {{(-24)?}}(%rsp), %rax +; CHECK: movsd ([[P:%rdi|%rcx]],%rax,8), %xmm0 +; CHECK: movslq {{-20|4}}(%rsp), %rax +; CHECK: movhpd ([[P]],%rax,8), %xmm0 +; CHECK: movslq {{-16|8}}(%rsp), %rax +; CHECK: movsd ([[P]],%rax,8), %xmm1 +; CHECK: movslq {{-12|12}}(%rsp), %rax +; CHECK: movhpd ([[P]],%rax,8), %xmm1 define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind { %a = load <4 x i32>* %i diff --git a/test/CodeGen/X86/i128-ret.ll b/test/CodeGen/X86/i128-ret.ll index 277f4283328b6..264f07ceb4c85 100644 --- a/test/CodeGen/X86/i128-ret.ll +++ b/test/CodeGen/X86/i128-ret.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86-64 | grep {movq 8(%rdi), %rdx} -; RUN: llc < %s -march=x86-64 | grep {movq (%rdi), %rax} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK: movq ([[A0:%rdi|%rcx]]), %rax +; CHECK: movq 8([[A0]]), %rdx define i128 @test(i128 *%P) { %A = load i128* %P diff --git a/test/CodeGen/X86/lea.ll b/test/CodeGen/X86/lea.ll index 22a96448f029a..542135529f1d0 100644 --- a/test/CodeGen/X86/lea.ll +++ b/test/CodeGen/X86/lea.ll @@ -1,11 +1,12 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s define i32 @test1(i32 %x) nounwind { %tmp1 = shl i32 %x, 3 %tmp2 = add i32 %tmp1, 7 ret i32 %tmp2 ; CHECK: test1: -; CHECK: leal 7(,%rdi,8), %eax +; CHECK: leal 7(,[[A0:%rdi|%rcx]],8), %eax } @@ -27,8 +28,8 @@ bb.nph: bb2: ret i32 %x_offs ; CHECK: test2: -; CHECK: leal -5(%rdi), %eax +; CHECK: leal -5([[A0]]), %eax ; CHECK: andl $-4, %eax ; CHECK: negl %eax -; CHECK: leal -4(%rdi,%rax), %eax +; CHECK: leal -4([[A0]],%rax), %eax } diff --git a/test/CodeGen/X86/lsr-overflow.ll b/test/CodeGen/X86/lsr-overflow.ll index 0b0214c6d9f8a..5bc4f7e96a0b9 100644 --- a/test/CodeGen/X86/lsr-overflow.ll +++ b/test/CodeGen/X86/lsr-overflow.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; The comparison uses the pre-inc value, which could lead LSR to ; try to compute -INT64_MIN. ; CHECK: movabsq $-9223372036854775808, %rax -; CHECK: cmpq %rax, %rbx +; CHECK: cmpq %rax, ; CHECK: sete %al declare i64 @bar() diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index d1d714491faab..29f03d68daded 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -1,12 +1,13 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; Full strength reduction wouldn't reduce register pressure, so LSR should ; stick with indexing here. -; CHECK: movaps (%rsi,%rax,4), %xmm3 -; CHECK: movaps %xmm3, (%rdi,%rax,4) +; CHECK: movaps (%{{rsi|rdx}},%rax,4), %xmm3 +; CHECK: movaps %xmm3, (%{{rdi|rcx}},%rax,4) ; CHECK: addq $4, %rax -; CHECK: cmpl %eax, (%rdx) +; CHECK: cmpl %eax, (%{{rdx|r8}}) ; CHECK-NEXT: jg define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { diff --git a/test/CodeGen/X86/memcmp.ll b/test/CodeGen/X86/memcmp.ll index 36be1f308ccd5..f4bc1bb7015a0 100644 --- a/test/CodeGen/X86/memcmp.ll +++ b/test/CodeGen/X86/memcmp.ll @@ -1,4 +1,5 @@ -; RUN: llc %s -o - -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 @@ -20,8 +21,8 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK: memcmp2: -; CHECK: movw (%rdi), %ax -; CHECK: cmpw (%rsi), %ax +; CHECK: movw ([[A0:%rdi|%rcx]]), %ax +; CHECK: cmpw ([[A1:%rsi|%rdx]]), %ax } define void @memcmp2a(i8* %X, i32* nocapture %P) nounwind { @@ -37,7 +38,7 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK: memcmp2a: -; CHECK: cmpw $28527, (%rdi) +; CHECK: cmpw $28527, ([[A0]]) } @@ -54,8 +55,8 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK: memcmp4: -; CHECK: movl (%rdi), %eax -; CHECK: cmpl (%rsi), %eax +; CHECK: movl ([[A0]]), %eax +; CHECK: cmpl ([[A1]]), %eax } define void @memcmp4a(i8* %X, i32* nocapture %P) nounwind { @@ -71,7 +72,7 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK: memcmp4a: -; CHECK: cmpl $1869573999, (%rdi) +; CHECK: cmpl $1869573999, ([[A0]]) } define void @memcmp8(i8* %X, i8* %Y, i32* nocapture %P) nounwind { @@ -87,8 +88,8 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK: memcmp8: -; CHECK: movq (%rdi), %rax -; CHECK: cmpq (%rsi), %rax +; CHECK: movq ([[A0]]), %rax +; CHECK: cmpq ([[A1]]), %rax } define void @memcmp8a(i8* %X, i32* nocapture %P) nounwind { @@ -105,6 +106,6 @@ return: ; preds = %entry ret void ; CHECK: memcmp8a: ; CHECK: movabsq $8029759185026510694, %rax -; CHECK: cmpq %rax, (%rdi) +; CHECK: cmpq %rax, ([[A0]]) } diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll index 00190e802fc94..97b7fe70d8589 100644 --- a/test/CodeGen/X86/movgs.ll +++ b/test/CodeGen/X86/movgs.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse41 | FileCheck %s --check-prefix=X64 define i32 @test1() nounwind readonly { entry: @@ -30,7 +31,7 @@ entry: ; X32: calll *%gs:(%eax) ; X64: test2: -; X64: callq *%gs:(%rdi) +; X64: callq *%gs:([[A0:%rdi|%rcx]]) @@ -50,7 +51,7 @@ entry: ; X32: ret ; X64: pmovsxwd_1: -; X64: pmovsxwd %gs:(%rdi), %xmm0 +; X64: pmovsxwd %gs:([[A0]]), %xmm0 ; X64: ret } diff --git a/test/CodeGen/X86/non-globl-eh-frame.ll b/test/CodeGen/X86/non-globl-eh-frame.ll deleted file mode 100644 index 71349ecafeb68..0000000000000 --- a/test/CodeGen/X86/non-globl-eh-frame.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin10 -march x86 | not grep {{.globl\[\[:space:\]\]*__Z4funcv.eh}} -; RUN: llc < %s -mtriple x86_64-apple-darwin9 -march x86 | FileCheck %s -check-prefix=DARWIN9 - -%struct.__pointer_type_info_pseudo = type { %struct.__type_info_pseudo, i32, %"struct.std::type_info"* } -%struct.__type_info_pseudo = type { i8*, i8* } -%"struct.std::type_info" = type opaque - -@.str = private constant [12 x i8] c"hello world\00", align 1 -@_ZTIPc = external constant %struct.__pointer_type_info_pseudo - -define void @_Z4funcv() noreturn optsize ssp { -entry: - %0 = tail call i8* @__cxa_allocate_exception(i64 8) nounwind - %1 = bitcast i8* %0 to i8** - store i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0), i8** %1, align 8 - tail call void @__cxa_throw(i8* %0, i8* bitcast (%struct.__pointer_type_info_pseudo* @_ZTIPc to i8*), void (i8*)* null) noreturn - unreachable -} - -; DARWIN9: .globl __Z4funcv.eh - -declare i8* @__cxa_allocate_exception(i64) nounwind - -declare void @__cxa_throw(i8*, i8*, void (i8*)*) noreturn diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll index f1e3c2772ac9e..b90413d40a0f9 100644 --- a/test/CodeGen/X86/optimize-max-3.ll +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -asm-verbose=false | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 -asm-verbose=false | FileCheck %s ; LSR's OptimizeMax should eliminate the select (max). @@ -40,13 +41,13 @@ for.end: ; preds = %for.body, %entry ; CHECK: jle ; CHECK-NOT: cmov -; CHECK: xorl %edi, %edi +; CHECK: xorl {{%edi, %edi|%ecx, %ecx}} ; CHECK-NEXT: align ; CHECK-NEXT: BB1_2: ; CHECK-NEXT: callq -; CHECK-NEXT: incl %ebx -; CHECK-NEXT: cmpl %r14d, %ebx -; CHECK-NEXT: movq %rax, %rdi +; CHECK-NEXT: incl [[BX:%ebx|%esi]] +; CHECK-NEXT: cmpl [[R14:%r14d|%edi]], [[BX]] +; CHECK-NEXT: movq %rax, %r{{di|cx}} ; CHECK-NEXT: jl define void @_Z18GenerateStatusPagei(i32 %jobs_to_display) nounwind { diff --git a/test/CodeGen/X86/phi-constants.ll b/test/CodeGen/X86/phi-constants.ll new file mode 100644 index 0000000000000..da9652f734043 --- /dev/null +++ b/test/CodeGen/X86/phi-constants.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +%"class.std::bitset" = type { [8 x i8] } + +define zeroext i1 @_Z3fooPjmS_mRSt6bitsetILm32EE(i32* nocapture %a, i64 %asize, i32* nocapture %b, i64 %bsize, %"class.std::bitset"* %bits) nounwind readonly ssp noredzone { +entry: + %tmp.i.i.i.i = bitcast %"class.std::bitset"* %bits to i64* + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %conv = zext i32 %0 to i64 + %cmp = icmp eq i64 %conv, %bsize + br i1 %cmp, label %return, label %for.body + +for.body: ; preds = %for.cond + %arrayidx = getelementptr inbounds i32* %b, i64 %conv + %tmp5 = load i32* %arrayidx, align 4 + %conv6 = zext i32 %tmp5 to i64 + %rem.i.i.i.i = and i64 %conv6, 63 + %tmp3.i = load i64* %tmp.i.i.i.i, align 8 + %shl.i.i = shl i64 1, %rem.i.i.i.i + %and.i = and i64 %shl.i.i, %tmp3.i + %cmp.i = icmp eq i64 %and.i, 0 + br i1 %cmp.i, label %for.inc, label %return + +for.inc: ; preds = %for.body + %inc = add i32 %0, 1 + br label %for.cond + +return: ; preds = %for.body, %for.cond +; CHECK-NOT: and + %retval.0 = phi i1 [ true, %for.body ], [ false, %for.cond ] + ret i1 %retval.0 +} diff --git a/test/CodeGen/X86/pr9127.ll b/test/CodeGen/X86/pr9127.ll index 45b0c6c78706c..9b251f57e0e33 100644 --- a/test/CodeGen/X86/pr9127.ll +++ b/test/CodeGen/X86/pr9127.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=x86-64 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-win32 < %s | FileCheck %s define i8 @foobar(double %d, double* %x) { entry: @@ -9,4 +10,4 @@ entry: } ; test that the load is folded. -; CHECK: ucomisd (%rdi), %xmm0 +; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 diff --git a/test/CodeGen/X86/red-zone.ll b/test/CodeGen/X86/red-zone.ll index 1ffb4e3c78f67..d93697123596d 100644 --- a/test/CodeGen/X86/red-zone.ll +++ b/test/CodeGen/X86/red-zone.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; First without noredzone. ; CHECK: f0: diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll index 5fb445c9357c8..f89cd330803d8 100644 --- a/test/CodeGen/X86/remat-mov-0.ll +++ b/test/CodeGen/X86/remat-mov-0.ll @@ -1,12 +1,13 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; CodeGen should remat the zero instead of spilling it. declare void @foo(i64 %p) ; CHECK: bar: -; CHECK: xorl %edi, %edi -; CHECK: xorl %edi, %edi +; CHECK: xorl %e[[A0:di|cx]], %e +; CHECK: xorl %e[[A0]], %e[[A0]] define void @bar() nounwind { call void @foo(i64 0) call void @foo(i64 0) @@ -14,8 +15,8 @@ define void @bar() nounwind { } ; CHECK: bat: -; CHECK: movq $-1, %rdi -; CHECK: movq $-1, %rdi +; CHECK: movq $-1, %r[[A0]] +; CHECK: movq $-1, %r[[A0]] define void @bat() nounwind { call void @foo(i64 -1) call void @foo(i64 -1) @@ -23,8 +24,8 @@ define void @bat() nounwind { } ; CHECK: bau: -; CHECK: movl $1, %edi -; CHECK: movl $1, %edi +; CHECK: movl $1, %e[[A0]] +; CHECK: movl $1, %e[[A0]] define void @bau() nounwind { call void @foo(i64 1) call void @foo(i64 1) diff --git a/test/CodeGen/X86/test-shrink.ll b/test/CodeGen/X86/test-shrink.ll index 1d636930641f8..5bc28ecbc48c8 100644 --- a/test/CodeGen/X86/test-shrink.ll +++ b/test/CodeGen/X86/test-shrink.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=CHECK-64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32 ; CHECK-64: g64xh: -; CHECK-64: testb $8, %ah +; CHECK-64: testb $8, {{%ah|%ch}} ; CHECK-64: ret ; CHECK-32: g64xh: ; CHECK-32: testb $8, %ah @@ -19,7 +20,7 @@ no: ret void } ; CHECK-64: g64xl: -; CHECK-64: testb $8, %dil +; CHECK-64: testb $8, [[A0L:%dil|%cl]] ; CHECK-64: ret ; CHECK-32: g64xl: ; CHECK-32: testb $8, %al @@ -36,7 +37,7 @@ no: ret void } ; CHECK-64: g32xh: -; CHECK-64: testb $8, %ah +; CHECK-64: testb $8, {{%ah|%ch}} ; CHECK-64: ret ; CHECK-32: g32xh: ; CHECK-32: testb $8, %ah @@ -53,7 +54,7 @@ no: ret void } ; CHECK-64: g32xl: -; CHECK-64: testb $8, %dil +; CHECK-64: testb $8, [[A0L]] ; CHECK-64: ret ; CHECK-32: g32xl: ; CHECK-32: testb $8, %al @@ -70,7 +71,7 @@ no: ret void } ; CHECK-64: g16xh: -; CHECK-64: testb $8, %ah +; CHECK-64: testb $8, {{%ah|%ch}} ; CHECK-64: ret ; CHECK-32: g16xh: ; CHECK-32: testb $8, %ah @@ -87,7 +88,7 @@ no: ret void } ; CHECK-64: g16xl: -; CHECK-64: testb $8, %dil +; CHECK-64: testb $8, [[A0L]] ; CHECK-64: ret ; CHECK-32: g16xl: ; CHECK-32: testb $8, %al @@ -104,7 +105,7 @@ no: ret void } ; CHECK-64: g64x16: -; CHECK-64: testw $-32640, %di +; CHECK-64: testw $-32640, %[[A0W:di|cx]] ; CHECK-64: ret ; CHECK-32: g64x16: ; CHECK-32: testw $-32640, %ax @@ -121,7 +122,7 @@ no: ret void } ; CHECK-64: g32x16: -; CHECK-64: testw $-32640, %di +; CHECK-64: testw $-32640, %[[A0W]] ; CHECK-64: ret ; CHECK-32: g32x16: ; CHECK-32: testw $-32640, %ax @@ -138,7 +139,7 @@ no: ret void } ; CHECK-64: g64x32: -; CHECK-64: testl $268468352, %edi +; CHECK-64: testl $268468352, %e[[A0W]] ; CHECK-64: ret ; CHECK-32: g64x32: ; CHECK-32: testl $268468352, %eax diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll index c2f0c23fe1d3e..8fbbd397b8af2 100644 --- a/test/CodeGen/X86/use-add-flags.ll +++ b/test/CodeGen/X86/use-add-flags.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 -o - | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; Reuse the flags value from the add instructions instead of emitting separate ; testl instructions. @@ -6,9 +7,9 @@ ; Use the flags on the add. ; CHECK: test1: -; CHECK: addl (%rdi), %esi -; CHECK-NEXT: movl %edx, %eax -; CHECK-NEXT: cmovnsl %ecx, %eax +; CHECK: addl (%r[[A0:di|cx]]), {{%esi|%edx}} +; CHECK-NEXT: movl {{%edx|%r8d}}, %eax +; CHECK-NEXT: cmovnsl {{%ecx|%r9d}}, %eax ; CHECK-NEXT: ret define i32 @test1(i32* %x, i32 %y, i32 %a, i32 %b) nounwind { @@ -25,7 +26,7 @@ declare void @foo(i32) ; other use. A simple test is better. ; CHECK: test2: -; CHECK: testb $16, %dil +; CHECK: testb $16, {{%dil|%cl}} define void @test2(i32 %x) nounwind { %y = and i32 %x, 16 @@ -41,7 +42,7 @@ false: ; Do use the flags result of the and here, since the and has another use. ; CHECK: test3: -; CHECK: andl $16, %edi +; CHECK: andl $16, %e[[A0]] ; CHECK-NEXT: jne define void @test3(i32 %x) nounwind { diff --git a/test/CodeGen/X86/vec_anyext.ll b/test/CodeGen/X86/vec_anyext.ll new file mode 100644 index 0000000000000..d2a4c7f60dd7c --- /dev/null +++ b/test/CodeGen/X86/vec_anyext.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -march=x86-64 +; PR 9267 + +define<4 x i16> @func_16_32() { + %F = load <4 x i32>* undef + %G = trunc <4 x i32> %F to <4 x i16> + %H = load <4 x i32>* undef + %Y = trunc <4 x i32> %H to <4 x i16> + %T = add <4 x i16> %Y, %G + store <4 x i16>%T , <4 x i16>* undef + ret <4 x i16> %T +} + +define<4 x i16> @func_16_64() { + %F = load <4 x i64>* undef + %G = trunc <4 x i64> %F to <4 x i16> + %H = load <4 x i64>* undef + %Y = trunc <4 x i64> %H to <4 x i16> + %T = xor <4 x i16> %Y, %G + store <4 x i16>%T , <4 x i16>* undef + ret <4 x i16> %T +} + +define<4 x i32> @func_32_64() { + %F = load <4 x i64>* undef + %G = trunc <4 x i64> %F to <4 x i32> + %H = load <4 x i64>* undef + %Y = trunc <4 x i64> %H to <4 x i32> + %T = or <4 x i32> %Y, %G + ret <4 x i32> %T +} + +define<4 x i8> @func_8_16() { + %F = load <4 x i16>* undef + %G = trunc <4 x i16> %F to <4 x i8> + %H = load <4 x i16>* undef + %Y = trunc <4 x i16> %H to <4 x i8> + %T = add <4 x i8> %Y, %G + ret <4 x i8> %T +} + +define<4 x i8> @func_8_32() { + %F = load <4 x i32>* undef + %G = trunc <4 x i32> %F to <4 x i8> + %H = load <4 x i32>* undef + %Y = trunc <4 x i32> %H to <4 x i8> + %T = sub <4 x i8> %Y, %G + ret <4 x i8> %T +} + +define<4 x i8> @func_8_64() { + %F = load <4 x i64>* undef + %G = trunc <4 x i64> %F to <4 x i8> + %H = load <4 x i64>* undef + %Y = trunc <4 x i64> %H to <4 x i8> + %T = add <4 x i8> %Y, %G + ret <4 x i8> %T +} + +define<4 x i16> @const_16_32() { + %G = trunc <4 x i32> <i32 0, i32 3, i32 8, i32 7> to <4 x i16> + ret <4 x i16> %G +} + +define<4 x i16> @const_16_64() { + %G = trunc <4 x i64> <i64 0, i64 3, i64 8, i64 7> to <4 x i16> + ret <4 x i16> %G +} + +define void @bugOnTruncBitwidthReduce() nounwind { +meh: + %0 = xor <4 x i64> zeroinitializer, zeroinitializer + %1 = trunc <4 x i64> %0 to <4 x i32> + %2 = lshr <4 x i32> %1, <i32 18, i32 18, i32 18, i32 18> + %3 = xor <4 x i32> %2, %1 + ret void +} diff --git a/test/CodeGen/X86/vec_sext.ll b/test/CodeGen/X86/vec_sext.ll new file mode 100644 index 0000000000000..776ddec2e63bd --- /dev/null +++ b/test/CodeGen/X86/vec_sext.ll @@ -0,0 +1,69 @@ +; RUN: llc < %s -march=x86-64 +; PR 9267 + +define<4 x i32> @func_16_32() { + %F = load <4 x i16>* undef + %G = sext <4 x i16> %F to <4 x i32> + %H = load <4 x i16>* undef + %Y = sext <4 x i16> %H to <4 x i32> + %T = add <4 x i32> %Y, %G + store <4 x i32>%T , <4 x i32>* undef + ret <4 x i32> %T +} + +define<4 x i64> @func_16_64() { + %F = load <4 x i16>* undef + %G = sext <4 x i16> %F to <4 x i64> + %H = load <4 x i16>* undef + %Y = sext <4 x i16> %H to <4 x i64> + %T = xor <4 x i64> %Y, %G + store <4 x i64>%T , <4 x i64>* undef + ret <4 x i64> %T +} + +define<4 x i64> @func_32_64() { + %F = load <4 x i32>* undef + %G = sext <4 x i32> %F to <4 x i64> + %H = load <4 x i32>* undef + %Y = sext <4 x i32> %H to <4 x i64> + %T = or <4 x i64> %Y, %G + ret <4 x i64> %T +} + +define<4 x i16> @func_8_16() { + %F = load <4 x i8>* undef + %G = sext <4 x i8> %F to <4 x i16> + %H = load <4 x i8>* undef + %Y = sext <4 x i8> %H to <4 x i16> + %T = add <4 x i16> %Y, %G + ret <4 x i16> %T +} + +define<4 x i32> @func_8_32() { + %F = load <4 x i8>* undef + %G = sext <4 x i8> %F to <4 x i32> + %H = load <4 x i8>* undef + %Y = sext <4 x i8> %H to <4 x i32> + %T = sub <4 x i32> %Y, %G + ret <4 x i32> %T +} + +define<4 x i64> @func_8_64() { + %F = load <4 x i8>* undef + %G = sext <4 x i8> %F to <4 x i64> + %H = load <4 x i8>* undef + %Y = sext <4 x i8> %H to <4 x i64> + %T = add <4 x i64> %Y, %G + ret <4 x i64> %T +} + +define<4 x i32> @const_16_32() { + %G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32> + ret <4 x i32> %G +} + +define<4 x i64> @const_16_64() { + %G = sext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64> + ret <4 x i64> %G +} + diff --git a/test/CodeGen/X86/vec_shuffle-37.ll b/test/CodeGen/X86/vec_shuffle-37.ll index b09093089c5aa..2efdb14b40446 100644 --- a/test/CodeGen/X86/vec_shuffle-37.ll +++ b/test/CodeGen/X86/vec_shuffle-37.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s ; RUN: llc -O0 < %s -march=x86 -mcpu=core2 | FileCheck %s --check-prefix=CHECK_O0 define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp { entry: -; CHECK: movaps (%rdi), %xmm0 +; CHECK: movaps ({{%rdi|%rcx}}), %xmm0 ; CHECK-NEXT: movaps %xmm0, %xmm1 ; CHECK-NEXT: movlps (%rax), %xmm1 ; CHECK-NEXT: shufps $36, %xmm1, %xmm0 diff --git a/test/CodeGen/X86/vec_zext.ll b/test/CodeGen/X86/vec_zext.ll new file mode 100644 index 0000000000000..615a50b7afc33 --- /dev/null +++ b/test/CodeGen/X86/vec_zext.ll @@ -0,0 +1,69 @@ +; RUN: llc < %s -march=x86-64 +; PR 9267 + +define<4 x i32> @func_16_32() { + %F = load <4 x i16>* undef + %G = zext <4 x i16> %F to <4 x i32> + %H = load <4 x i16>* undef + %Y = zext <4 x i16> %H to <4 x i32> + %T = add <4 x i32> %Y, %G + store <4 x i32>%T , <4 x i32>* undef + ret <4 x i32> %T +} + +define<4 x i64> @func_16_64() { + %F = load <4 x i16>* undef + %G = zext <4 x i16> %F to <4 x i64> + %H = load <4 x i16>* undef + %Y = zext <4 x i16> %H to <4 x i64> + %T = xor <4 x i64> %Y, %G + store <4 x i64>%T , <4 x i64>* undef + ret <4 x i64> %T +} + +define<4 x i64> @func_32_64() { + %F = load <4 x i32>* undef + %G = zext <4 x i32> %F to <4 x i64> + %H = load <4 x i32>* undef + %Y = zext <4 x i32> %H to <4 x i64> + %T = or <4 x i64> %Y, %G + ret <4 x i64> %T +} + +define<4 x i16> @func_8_16() { + %F = load <4 x i8>* undef + %G = zext <4 x i8> %F to <4 x i16> + %H = load <4 x i8>* undef + %Y = zext <4 x i8> %H to <4 x i16> + %T = add <4 x i16> %Y, %G + ret <4 x i16> %T +} + +define<4 x i32> @func_8_32() { + %F = load <4 x i8>* undef + %G = zext <4 x i8> %F to <4 x i32> + %H = load <4 x i8>* undef + %Y = zext <4 x i8> %H to <4 x i32> + %T = sub <4 x i32> %Y, %G + ret <4 x i32> %T +} + +define<4 x i64> @func_8_64() { + %F = load <4 x i8>* undef + %G = zext <4 x i8> %F to <4 x i64> + %H = load <4 x i8>* undef + %Y = zext <4 x i8> %H to <4 x i64> + %T = add <4 x i64> %Y, %G + ret <4 x i64> %T +} + +define<4 x i32> @const_16_32() { + %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32> + ret <4 x i32> %G +} + +define<4 x i64> @const_16_64() { + %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64> + ret <4 x i64> %G +} + diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index 6c623cb155388..b90d81ac9b188 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64 ; Though it is undefined, we want xor undef,undef to produce zero. define <4 x i32> @test1() nounwind { @@ -28,9 +29,9 @@ entry: ret i32 %tmp4 ; X64: test3: -; X64: notl %esi -; X64: andl %edi, %esi -; X64: movl %esi, %eax +; X64: notl [[A1:%esi|%edx]] +; X64: andl [[A0:%edi|%ecx]], [[A1]] +; X64: movl [[A1]], %eax ; X64: shrl %eax ; X64: ret diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll new file mode 100644 index 0000000000000..4fc2f26d1b6be --- /dev/null +++ b/test/CodeGen/XCore/events.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) +declare i8* @llvm.xcore.waitevent() +declare void @llvm.xcore.clre() + +define i32 @f(i8 addrspace(1)* %r) nounwind { +; CHECK: f: +entry: +; CHECK: clre + call void @llvm.xcore.clre() + call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* blockaddress(@f, %L1)) + call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* blockaddress(@f, %L2)) + %goto_addr = call i8* @llvm.xcore.waitevent() +; CHECK: waiteu + indirectbr i8* %goto_addr, [label %L1, label %L2] +L1: + br label %ret +L2: + br label %ret +ret: + %retval = phi i32 [1, %L1], [2, %L2] + ret i32 %retval +} diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll index 3114bdcd17771..3389912b8c0b2 100644 --- a/test/CodeGen/XCore/resources.ll +++ b/test/CodeGen/XCore/resources.ll @@ -11,6 +11,14 @@ declare void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) +declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) define i8 addrspace(1)* @getr() { ; CHECK: getr: @@ -109,3 +117,60 @@ define void @setci(i8 addrspace(1)* %r) { call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2) ret void } + +define i32 @inshr(i32 %value, i8 addrspace(1)* %r) { +; CHECK: inshr: +; CHECK: inshr r0, res[r1] + %result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) + ret i32 %result +} + +define i32 @outshr(i32 %value, i8 addrspace(1)* %r) { +; CHECK: outshr: +; CHECK: outshr res[r1], r0 + %result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value) + ret i32 %result +} + +define void @setpt(i8 addrspace(1)* %r, i32 %value) { +; CHECK: setpt: +; CHECK: setpt res[r0], r1 + call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define i32 @getts(i8 addrspace(1)* %r) { +; CHECK: getts: +; CHECK: getts r0, res[r0] + %result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define void @syncr(i8 addrspace(1)* %r) { +; CHECK: syncr: +; CHECK: syncr res[r0] + call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) + ret void +} + +define void @settw(i8 addrspace(1)* %r, i32 %value) { +; CHECK: settw: +; CHECK: settw res[r0], r1 + call void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define void @setv(i8 addrspace(1)* %r, i8* %p) { +; CHECK: setv: +; CHECK: mov r11, r1 +; CHECK-NEXT: setv res[r0], r11 + call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) + ret void +} + +define void @eeu(i8 addrspace(1)* %r) { +; CHECK: eeu: +; CHECK: eeu res[r0] + call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) + ret void +} |