vendor/clang/clang-release_351-r225668

8 files changed, 222 insertions, 30 deletions

diff --git a/test/CodeGen/atomics-inlining.c b/test/CodeGen/atomics-inlining.c
index 6456e74a94ecf..ec916e1b5eef6 100644
--- a/test/CodeGen/atomics-inlining.c
+++ b/test/CodeGen/atomics-inlining.c
@@ -76,8 +76,8 @@ void test1(void) {
 // MIPS32: store atomic i32 {{.*}}, i32* @i1 seq_cst
 // MIPS32: call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*)
 // MIPS32: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64
-// MIPS32: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
-// MIPS32: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
+// MIPS32: call void @__atomic_load(i32 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
+// MIPS32: call void @__atomic_store(i32 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
 
 // MIPS64-LABEL: define void @test1
 // MIPS64: = load atomic i8* @c1 seq_cst
@@ -88,6 +88,6 @@ void test1(void) {
 // MIPS64: store atomic i32 {{.*}}, i32* @i1 seq_cst
 // MIPS64: = load atomic i64* @ll1 seq_cst
 // MIPS64: store atomic i64 {{.*}}, i64* @ll1 seq_cst
-// MIPS64: call void @__atomic_load(i64 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0)
-// MIPS64: call void @__atomic_store(i64 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
+// MIPS64: call void @__atomic_load(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0)
+// MIPS64: call void @__atomic_store(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0)
 }
diff --git a/test/CodeGen/mips-byval-arg.c b/test/CodeGen/mips-byval-arg.c
index 589e85ef9dd1f..0e3d334b27453 100644
--- a/test/CodeGen/mips-byval-arg.c
+++ b/test/CodeGen/mips-byval-arg.c
@@ -7,8 +7,8 @@ typedef struct {
 
 extern void foo2(S0);
 
-// O32-LABEL: define void @foo1(i32 %a0.coerce0, i32 %a0.coerce1, i32 %a0.coerce2)
-// N64-LABEL: define void @foo1(i64 %a0.coerce0, i32 %a0.coerce1)
+// O32-LABEL: define void @foo1(i32 inreg %a0.coerce0, i32 inreg %a0.coerce1, i32 inreg %a0.coerce2)
+// N64-LABEL: define void @foo1(i64 inreg %a0.coerce0, i32 inreg %a0.coerce1)
 
 void foo1(S0 a0) {
   foo2(a0);
diff --git a/test/CodeGen/mips-varargs.c b/test/CodeGen/mips-varargs.c
new file mode 100644
index 0000000000000..ad202ff85bf0b
--- /dev/null
+++ b/test/CodeGen/mips-varargs.c
@@ -0,0 +1,176 @@
+// RUN: %clang_cc1 -triple mips-unknown-linux -o - -O1 -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+// RUN: %clang_cc1 -triple mipsel-unknown-linux -o - -O1 -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -O1 -emit-llvm  -target-abi n32 %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 -check-prefix=NEW
+// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -O1 -emit-llvm  -target-abi n32 %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 -check-prefix=NEW
+// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -O1 -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NEW
+// RUN: %clang_cc1 -triple mips64el-unknown-linux -o - -O1 -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NEW
+
+#include <stdarg.h>
+
+typedef int v4i32 __attribute__ ((__vector_size__ (16)));
+
+int test_i32(char *fmt, ...) {
+  va_list va;
+
+  va_start(va, fmt);
+  int v = va_arg(va, int);
+  va_end(va);
+
+  return v;
+}
+
+// ALL-LABEL: define i32 @test_i32(i8*{{.*}} %fmt, ...)
+//
+// O32:   %va = alloca i8*, align [[PTRALIGN:4]]
+// N32:   %va = alloca i8*, align [[PTRALIGN:4]]
+// N64:   %va = alloca i8*, align [[PTRALIGN:8]]
+//
+// ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
+// ALL:   call void @llvm.va_start(i8* [[VA1]])
+//
+// ALL:   [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[TMP0:%.+]] = bitcast i8* [[AP_CUR]] to i32*
+// NEW:   [[TMP0:%.+]] = bitcast i8* [[AP_CUR]] to i64*
+//
+// O32:   [[AP_NEXT:%.+]] = getelementptr i8* [[AP_CUR]], i32 4
+// NEW:   [[AP_NEXT:%.+]] = getelementptr i8* [[AP_CUR]], {{i32|i64}} 8
+//
+// ALL:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[ARG1:%.+]] = load i32* [[TMP0]], align 4
+// NEW:   [[TMP2:%.+]] = load i64* [[TMP0]], align 8
+// NEW:   [[ARG1:%.+]] = trunc i64 [[TMP2]] to i32
+//
+// ALL:   call void @llvm.va_end(i8* [[VA1]])
+// ALL:   ret i32 [[ARG1]]
+// ALL: }
+
+int test_i32_2args(char *fmt, ...) {
+  va_list va;
+
+  va_start(va, fmt);
+  int v1 = va_arg(va, int);
+  int v2 = va_arg(va, int);
+  va_end(va);
+
+  return v1 + v2;
+}
+
+// ALL-LABEL: define i32 @test_i32_2args(i8*{{.*}} %fmt, ...)
+//
+// ALL:   %va = alloca i8*, align [[PTRALIGN]]
+// ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
+// ALL:   call void @llvm.va_start(i8* [[VA1]])
+//
+// ALL:   [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[TMP0:%.+]] = bitcast i8* [[AP_CUR]] to i32*
+// NEW:   [[TMP0:%.+]] = bitcast i8* [[AP_CUR]] to i64*
+//
+// O32:   [[AP_NEXT:%.+]] = getelementptr i8* [[AP_CUR]], i32 4
+// NEW:   [[AP_NEXT:%.+]] = getelementptr i8* [[AP_CUR]], [[INTPTR_T:i32|i64]] 8
+//
+// O32:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
+// FIXME: N32 optimised this store out. Why only for this ABI?
+// N64:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[ARG1:%.+]] = load i32* [[TMP0]], align 4
+// NEW:   [[TMP3:%.+]] = load i64* [[TMP0]], align 8
+// NEW:   [[ARG1:%.+]] = trunc i64 [[TMP3]] to i32
+//
+// O32:   [[TMP1:%.+]] = bitcast i8* [[AP_NEXT]] to i32*
+// NEW:   [[TMP1:%.+]] = bitcast i8* [[AP_NEXT]] to i64*
+//
+// O32:   [[AP_NEXT3:%.+]] = getelementptr i8* [[AP_CUR]], i32 8
+// NEW:   [[AP_NEXT3:%.+]] = getelementptr i8* [[AP_CUR]], [[INTPTR_T]] 16
+//
+// ALL:   store i8* [[AP_NEXT3]], i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[ARG2:%.+]] = load i32* [[TMP1]], align 4
+// NEW:   [[TMP4:%.+]] = load i64* [[TMP1]], align 8
+// NEW:   [[ARG2:%.+]] = trunc i64 [[TMP4]] to i32
+//
+// ALL:   call void @llvm.va_end(i8* [[VA1]])
+// ALL:   [[ADD:%.+]] = add nsw i32 [[ARG2]], [[ARG1]]
+// ALL:   ret i32 [[ADD]]
+// ALL: }
+
+long long test_i64(char *fmt, ...) {
+  va_list va;
+
+  va_start(va, fmt);
+  long long v = va_arg(va, long long);
+  va_end(va);
+
+  return v;
+}
+
+// ALL-LABEL: define i64 @test_i64(i8*{{.*}} %fmt, ...)
+//
+// ALL:   %va = alloca i8*, align [[PTRALIGN]]
+// ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
+// ALL:   call void @llvm.va_start(i8* [[VA1]])
+//
+// ALL:   [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]]
+//
+// NEW:   [[TMP0:%.+]] = bitcast i8* [[AP_CUR]] to i64*
+//
+// i64 is 8-byte aligned, while this is within O32's stack alignment there's no
+// guarantee that the offset is still 8-byte aligned after earlier reads.
+// O32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
+// O32:   [[PTR1:%.+]] = add i32 [[PTR0]], 7
+// O32:   [[PTR2:%.+]] = and i32 [[PTR1]], -8
+// O32:   [[PTR3:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i64*
+// O32:   [[PTR4:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i8*
+//
+// O32:   [[AP_NEXT:%.+]] = getelementptr i8* [[PTR4]], [[INTPTR_T]] 8
+// NEW:   [[AP_NEXT:%.+]] = getelementptr i8* [[AP_CUR]], [[INTPTR_T]] 8
+//
+// ALL:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[ARG1:%.+]] = load i64* [[PTR3]], align 8
+// NEW:   [[ARG1:%.+]] = load i64* [[TMP0]], align 8
+//
+// ALL:   call void @llvm.va_end(i8* [[VA1]])
+// ALL:   ret i64 [[ARG1]]
+// ALL: }
+
+int test_v4i32(char *fmt, ...) {
+  va_list va;
+
+  va_start(va, fmt);
+  v4i32 v = va_arg(va, v4i32);
+  va_end(va);
+
+  return v[0];
+}
+
+// ALL-LABEL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...)
+//
+// ALL:   %va = alloca i8*, align [[PTRALIGN]]
+// ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
+// ALL:   call void @llvm.va_start(i8* [[VA1]])
+// ALL:   [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]]
+//
+// O32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
+// N32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
+// N64:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i64]]
+//
+// Vectors are 16-byte aligned, however the O32 ABI has a maximum alignment of
+// 8-bytes since the base of the stack is 8-byte aligned.
+// O32:   [[PTR1:%.+]] = add i32 [[PTR0]], 7
+// O32:   [[PTR2:%.+]] = and i32 [[PTR1]], -8
+//
+// NEW:   [[PTR1:%.+]] = add [[INTPTR_T]] [[PTR0]], 15
+// NEW:   [[PTR2:%.+]] = and [[INTPTR_T]] [[PTR1]], -16
+//
+// ALL:   [[PTR3:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to <4 x i32>*
+// ALL:   [[PTR4:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i8*
+// ALL:   [[AP_NEXT:%.+]] = getelementptr i8* [[PTR4]], [[INTPTR_T]] 16
+// ALL:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
+// ALL:   [[PTR5:%.+]] = load <4 x i32>* [[PTR3]], align 16
+// ALL:   call void @llvm.va_end(i8* [[VA1]])
+// ALL:   [[VECEXT:%.+]] = extractelement <4 x i32> [[PTR5]], i32 0
+// ALL:   ret i32 [[VECEXT]]
+// ALL: }
diff --git a/test/CodeGen/mips-vector-arg.c b/test/CodeGen/mips-vector-arg.c
index 6ffb043188185..f8c89dfff5483 100644
--- a/test/CodeGen/mips-vector-arg.c
+++ b/test/CodeGen/mips-vector-arg.c
@@ -8,19 +8,19 @@
 typedef float  v4sf __attribute__ ((__vector_size__ (16)));
 typedef int v4i32 __attribute__ ((__vector_size__ (16)));
 
-// O32: define void @test_v4sf(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW:#[0-9]+]]
-// O32: declare i32 @test_v4sf_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
-// N64: define void @test_v4sf(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW:#[0-9]+]]
-// N64: declare i32 @test_v4sf_2(i64, i64, i32, i64, i64, i64)
+// O32: define void @test_v4sf(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) [[NUW:#[0-9]+]]
+// O32: declare i32 @test_v4sf_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
+// N64: define void @test_v4sf(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) [[NUW:#[0-9]+]]
+// N64: declare i32 @test_v4sf_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg)
 extern test_v4sf_2(v4sf, int, v4sf);
 void test_v4sf(v4sf a1, int a2, v4sf a3) {
   test_v4sf_2(a3, a2, a1);
 }
 
-// O32: define void @test_v4i32(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW]]
-// O32: declare i32 @test_v4i32_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
-// N64: define void @test_v4i32(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW]]
-// N64: declare i32 @test_v4i32_2(i64, i64, i32, i64, i64, i64)
+// O32: define void @test_v4i32(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) [[NUW]]
+// O32: declare i32 @test_v4i32_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
+// N64: define void @test_v4i32(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) [[NUW]]
+// N64: declare i32 @test_v4i32_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg)
 extern test_v4i32_2(v4i32, int, v4i32);
 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
   test_v4i32_2(a3, a2, a1);
diff --git a/test/CodeGen/mips-vector-return.c b/test/CodeGen/mips-vector-return.c
index a7c8ce157c841..8af4998cdf7c9 100644
--- a/test/CodeGen/mips-vector-return.c
+++ b/test/CodeGen/mips-vector-return.c
@@ -9,7 +9,7 @@ typedef double v4df __attribute__ ((__vector_size__ (32)));
 typedef int v4i32 __attribute__ ((__vector_size__ (16)));
 
 // O32-LABEL: define void @test_v4sf(<4 x float>* noalias nocapture sret
-// N64: define { i64, i64 } @test_v4sf
+// N64: define inreg { i64, i64 } @test_v4sf
 v4sf test_v4sf(float a) {
   return (v4sf){0.0f, a, 0.0f, 0.0f};
 }
@@ -23,8 +23,8 @@ v4df test_v4df(double a) {
 // O32 returns integer vectors whose size is equal to or smaller than 16-bytes
 // in integer registers.
 //
-// O32: define { i32, i32, i32, i32 } @test_v4i32
-// N64: define { i64, i64 } @test_v4i32
+// O32: define inreg { i32, i32, i32, i32 } @test_v4i32
+// N64: define inreg { i64, i64 } @test_v4i32
 v4i32 test_v4i32(int a) {
   return (v4i32){0, a, 0, 0};
 }
diff --git a/test/CodeGen/mips-zero-sized-struct.c b/test/CodeGen/mips-zero-sized-struct.c
new file mode 100644
index 0000000000000..afff3b41d833c
--- /dev/null
+++ b/test/CodeGen/mips-zero-sized-struct.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target mips-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang -target mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
+// RUN: %clang -target mips64-unknown-linux-gnu -S -emit-llvm -o - %s -mabi=n32 | FileCheck -check-prefix=N32 %s
+// RUN: %clang -target mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -mabi=n32 | FileCheck -check-prefix=N32 %s
+// RUN: %clang -target mips64-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
+// RUN: %clang -target mips64el-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
+
+// O32: define void @fn28(%struct.T2* noalias sret %agg.result, i8 signext %arg0)
+// N32: define void @fn28(i8 signext %arg0)
+// N64: define void @fn28(i8 signext %arg0)
+
+typedef struct T2 {  } T2;
+T2 T2_retval;
+T2 fn28(char arg0) {
+  return T2_retval;
+}
diff --git a/test/CodeGen/mips64-class-return.cpp b/test/CodeGen/mips64-class-return.cpp
index a473c13195507..57fa8ef5109b7 100644
--- a/test/CodeGen/mips64-class-return.cpp
+++ b/test/CodeGen/mips64-class-return.cpp
@@ -24,22 +24,22 @@ extern D0 gd0;
 extern D1 gd1;
 extern D2 gd2;
 
-// CHECK: define { i64, i64 } @_Z4foo1v() 
+// CHECK: define inreg { i64, i64 } @_Z4foo1v()
 D0 foo1(void) {
   return gd0;
 }
 
-// CHECK: define { double, float } @_Z4foo2v() 
+// CHECK: define inreg { double, float } @_Z4foo2v()
 D1 foo2(void) {
   return gd1;
 }
 
-// CHECK-LABEL: define void @_Z4foo32D2(i64 %a0.coerce0, double %a0.coerce1) 
+// CHECK-LABEL: define void @_Z4foo32D2(i64 inreg %a0.coerce0, double inreg %a0.coerce1)
 void foo3(D2 a0) {
   gd2 = a0;
 }
 
-// CHECK-LABEL: define void @_Z4foo42D0(i64 %a0.coerce0, i64 %a0.coerce1)
+// CHECK-LABEL: define void @_Z4foo42D0(i64 inreg %a0.coerce0, i64 inreg %a0.coerce1)
 void foo4(D0 a0) {
   gd0 = a0;
 }
diff --git a/test/CodeGen/mips64-padding-arg.c b/test/CodeGen/mips64-padding-arg.c
index 49a29c1efb312..b92098f45a4e6 100644
--- a/test/CodeGen/mips64-padding-arg.c
+++ b/test/CodeGen/mips64-padding-arg.c
@@ -9,9 +9,9 @@ typedef struct {
 
 // Insert padding to ensure arguments of type S0 are aligned to 16-byte boundaries.
 
-// N64-LABEL: define void @foo1(i32 %a0, i64, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 %b, i64, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
-// N64: tail call void @foo2(i32 1, i32 2, i32 %a0, i64 undef, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 3, i64 undef, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
-// N64: declare void @foo2(i32, i32, i32, i64, double, i64, i64, i64, double, i64, i64, i64, i32, i64, double, i64, i64, i64)
+// N64-LABEL: define void @foo1(i32 signext %a0, i64, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext %b, i64, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3)
+// N64: tail call void @foo2(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext 3, i64 undef, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3)
+// N64: declare void @foo2(i32 signext, i32 signext, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg, double inreg, i64 inreg, i64 inreg, i64 inreg, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg)
 
 extern void foo2(int, int, int, S0, S0, int, S0);
 
@@ -21,9 +21,9 @@ void foo1(int a0, S0 a1, S0 a2, int b, S0 a3) {
 
 // Insert padding before long double argument.
 //
-// N64-LABEL: define void @foo3(i32 %a0, i64, fp128 %a1)
-// N64: tail call void @foo4(i32 1, i32 2, i32 %a0, i64 undef, fp128 %a1)
-// N64: declare void @foo4(i32, i32, i32, i64, fp128)
+// N64-LABEL: define void @foo3(i32 signext %a0, i64, fp128 %a1)
+// N64: tail call void @foo4(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, fp128 %a1)
+// N64: declare void @foo4(i32 signext, i32 signext, i32 signext, i64, fp128)
 
 extern void foo4(int, int, int, long double);
 
@@ -34,8 +34,8 @@ void foo3(int a0, long double a1) {
 // Insert padding after hidden argument.
 //
 // N64-LABEL: define void @foo5(%struct.S0* noalias sret %agg.result, i64, fp128 %a0)
-// N64: call void @foo6(%struct.S0* sret %agg.result, i32 1, i32 2, i64 undef, fp128 %a0)
-// N64: declare void @foo6(%struct.S0* sret, i32, i32, i64, fp128)
+// N64: call void @foo6(%struct.S0* sret %agg.result, i32 signext 1, i32 signext 2, i64 undef, fp128 %a0)
+// N64: declare void @foo6(%struct.S0* sret, i32 signext, i32 signext, i64, fp128)
 
 extern S0 foo6(int, int, long double);
 
@@ -55,7 +55,7 @@ void foo7(float a0, double a1) {
 }
 
 // O32-LABEL: define void @foo9()
-// O32: declare void @foo10(i32, i32
+// O32: declare void @foo10(i32 signext, i32
 
 typedef struct __attribute__((aligned(16))) {
   int a;