diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
| commit | 58b69754af0cbff56b1cfce9be9392e4451f6628 (patch) | |
| tree | eacfc83d988e4b9d11114387ae7dc41243f2a363 /test/MC | |
| parent | 0378662f5bd3dbe8305a485b0282bceb8b52f465 (diff) | |
Notes
Diffstat (limited to 'test/MC')
152 files changed, 3817 insertions, 1288 deletions
diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s index 74dfb99ef2a7e..99eb3c539416b 100644 --- a/test/MC/ARM/arm_fixups.s +++ b/test/MC/ARM/arm_fixups.s @@ -15,3 +15,8 @@ @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3] @ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16 + + mov r2, fred + +@ CHECK: movw r2, fred @ encoding: [A,0x20'A',0b0000AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: fred, kind: fixup_arm_movw_lo16 diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 186954cafa56f..ce7e036b3be43 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -74,3 +74,6 @@ @ CHECK: cpsie none, #0 @ encoding: [0x00,0x00,0x0a,0xf1] cpsie none, #0 +@ CHECK: strh r3, [r2, #-0] @ encoding: [0xb0,0x30,0x42,0xe1] + strh r3, [r2, #-0] + diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 4788ac731b199..5c2a214598d15 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s .syntax unified .globl _func @@ -141,6 +141,14 @@ Lforward: @ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2] @ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2] + adr r1, #-0x0 + adr r1, #-0x12000000 + adr r1, #0x12000000 + +@ CHECK: adr r1, #-0 @ encoding: [0x00,0x10,0x4f,0xe2] +@ CHECK: adr r1, #-301989888 @ encoding: [0x12,0x14,0x4f,0xe2] +@ CHECK: adr r1, #301989888 @ encoding: [0x12,0x14,0x8f,0xe2] + @------------------------------------------------------------------------------ @ ADD @@ -206,6 +214,11 @@ Lforward: @ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2] @ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2] + @ Test right shift by 32, which is encoded as 0 + add r3, r1, r2, lsr #32 + add r3, r1, r2, asr #32 +@ CHECK: add r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x81,0xe0] +@ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0] @------------------------------------------------------------------------------ @ AND @@ -265,6 +278,12 @@ Lforward: @ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0] @ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0] + @ Test right shift by 32, which is encoded as 0 + and r3, r1, r2, lsr #32 + and r3, r1, r2, asr #32 +@ CHECK: and r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x01,0xe0] +@ CHECK: and r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x01,0xe0] + @------------------------------------------------------------------------------ @ ASR @------------------------------------------------------------------------------ @@ -368,6 +387,12 @@ Lforward: @ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1] @ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1] + @ Test right shift by 32, which is encoded as 0 + bic r3, r1, r2, lsr #32 + bic r3, r1, r2, asr #32 +@ CHECK: bic r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0xc1,0xe1] +@ CHECK: bic r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0xc1,0xe1] + @------------------------------------------------------------------------------ @ BKPT @------------------------------------------------------------------------------ @@ -542,6 +567,23 @@ Lforward: @------------------------------------------------------------------------------ @ DMB @------------------------------------------------------------------------------ + dmb #0xf + dmb #0xe + dmb #0xd + dmb #0xc + dmb #0xb + dmb #0xa + dmb #0x9 + dmb #0x8 + dmb #0x7 + dmb #0x6 + dmb #0x5 + dmb #0x4 + dmb #0x3 + dmb #0x2 + dmb #0x1 + dmb #0x0 + dmb sy dmb st dmb sh @@ -558,6 +600,23 @@ Lforward: @ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] @ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] +@ CHECK: dmb #0xd @ encoding: [0x5d,0xf0,0x7f,0xf5] +@ CHECK: dmb #0xc @ encoding: [0x5c,0xf0,0x7f,0xf5] +@ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] +@ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x9 @ encoding: [0x59,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x8 @ encoding: [0x58,0xf0,0x7f,0xf5] +@ CHECK: dmb nsh @ encoding: [0x57,0xf0,0x7f,0xf5] +@ CHECK: dmb nshst @ encoding: [0x56,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x5 @ encoding: [0x55,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x4 @ encoding: [0x54,0xf0,0x7f,0xf5] +@ CHECK: dmb osh @ encoding: [0x53,0xf0,0x7f,0xf5] +@ CHECK: dmb oshst @ encoding: [0x52,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x1 @ encoding: [0x51,0xf0,0x7f,0xf5] +@ CHECK: dmb #0x0 @ encoding: [0x50,0xf0,0x7f,0xf5] + +@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] +@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] @ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] @ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] @ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] @@ -573,6 +632,26 @@ Lforward: @------------------------------------------------------------------------------ @ DSB @------------------------------------------------------------------------------ + dsb #0xf + dsb #0xe + dsb #0xd + dsb #0xc + dsb #0xb + dsb #0xa + dsb #0x9 + dsb #0x8 + dsb #0x7 + dsb #0x6 + dsb #0x5 + dsb #0x4 + dsb #0x3 + dsb #0x2 + dsb #0x1 + dsb #0x0 + + dsb 8 + dsb 7 + dsb sy dsb st dsb sh @@ -589,6 +668,26 @@ Lforward: @ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] @ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] +@ CHECK: dsb #0xd @ encoding: [0x4d,0xf0,0x7f,0xf5] +@ CHECK: dsb #0xc @ encoding: [0x4c,0xf0,0x7f,0xf5] +@ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] +@ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x9 @ encoding: [0x49,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x8 @ encoding: [0x48,0xf0,0x7f,0xf5] +@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] +@ CHECK: dsb nshst @ encoding: [0x46,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x5 @ encoding: [0x45,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x4 @ encoding: [0x44,0xf0,0x7f,0xf5] +@ CHECK: dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5] +@ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x1 @ encoding: [0x41,0xf0,0x7f,0xf5] +@ CHECK: dsb #0x0 @ encoding: [0x40,0xf0,0x7f,0xf5] + +@ CHECK: dsb #0x8 @ encoding: [0x48,0xf0,0x7f,0xf5] +@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] + +@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] +@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] @ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] @ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] @ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] @@ -601,6 +700,12 @@ Lforward: @ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] @ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] +@ With capitals + dsb SY + dsb OSHST + +@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] +@ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] @------------------------------------------------------------------------------ @ EOR @------------------------------------------------------------------------------ @@ -658,6 +763,11 @@ Lforward: @ CHECK: eor r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x26,0xe0] @ CHECK: eor r4, r4, r5, rrx @ encoding: [0x65,0x40,0x24,0xe0] + @ Test right shift by 32, which is encoded as 0 + eor r3, r1, r2, lsr #32 + eor r3, r1, r2, asr #32 +@ CHECK: eor r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x21,0xe0] +@ CHECK: eor r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x21,0xe0] @------------------------------------------------------------------------------ @ ISB @@ -1205,6 +1315,12 @@ Lforward: @ CHECK: orrslt r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x96,0xb1] @ CHECK: orrsgt r4, r4, r5, rrx @ encoding: [0x65,0x40,0x94,0xc1] + @ Test right shift by 32, which is encoded as 0 + orr r3, r1, r2, lsr #32 + orr r3, r1, r2, asr #32 +@ CHECK: orr r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x81,0xe1] +@ CHECK: orr r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe1] + @------------------------------------------------------------------------------ @ PKH @------------------------------------------------------------------------------ @@ -2210,6 +2326,11 @@ Lforward: @ CHECK: sub r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x46,0xe0] @ CHECK: sub r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x46,0xe0] + @ Test right shift by 32, which is encoded as 0 + sub r3, r1, r2, lsr #32 + sub r3, r1, r2, asr #32 +@ CHECK: sub r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x41,0xe0] +@ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0] @------------------------------------------------------------------------------ @ SVC @@ -2711,10 +2832,22 @@ Lforward: wfilt yield yieldne - -@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] -@ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83] -@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] -@ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3] -@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] -@ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13] + hint #5 + hint #4 + hint #3 + hint #2 + hint #1 + hint #0 + +@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] +@ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83] +@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] +@ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3] +@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] +@ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13] +@ CHECK: hint #5 @ encoding: [0x05,0xf0,0x20,0xe3] +@ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3] +@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] +@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] +@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] +@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index bc2605c16ec91..4ee34ce6b4c81 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -169,9 +169,9 @@ _func: bl _bar blx _baz -@ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xf8'A'] +@ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xd0'A'] @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl -@ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xe8'A'] +@ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xc0'A'] @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx @@ -635,13 +635,3 @@ _func: @ CHECK: uxth r1, r4 @ encoding: [0xa1,0xb2] -@------------------------------------------------------------------------------ -@ WFE/WFI/YIELD -@------------------------------------------------------------------------------ - wfe - wfi - yield - -@ CHECK: wfe @ encoding: [0x20,0xbf] -@ CHECK: wfi @ encoding: [0x30,0xbf] -@ CHECK: yield @ encoding: [0x10,0xbf] diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index d2e208bc53b52..23d9f5977a296 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s .syntax unified .globl _func @@ -48,6 +48,7 @@ _func: adcs r0, r1, r3, lsl #7 adc.w r0, r1, r3, lsr #31 adcs.w r0, r1, r3, asr #32 + add r2, sp, ip @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04] @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04] @@ -57,6 +58,7 @@ _func: @ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] @ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70] @ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00] +@ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02] @------------------------------------------------------------------------------ @@ -78,6 +80,12 @@ _func: adds r2, r2, #56 adds r2, #56 + adds.w r2, #-16 + adds.w r2, r2, #-16 + addw r2, #-16 + addw r2, #-16 + addw r2, r2, #-16 + @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35] @@ -94,6 +102,12 @@ _func: @ CHECK: adds r2, #56 @ encoding: [0x38,0x32] @ CHECK: adds r2, #56 @ encoding: [0x38,0x32] +@ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02] +@ CHECK: subs.w r2, r2, #16 @ encoding: [0xb2,0xf1,0x10,0x02] +@ CHECK: subw r2, r2, #16 @ encoding: [0xa2,0xf2,0x10,0x02] +@ CHECK: subw r2, r2, #16 @ encoding: [0xa2,0xf2,0x10,0x02] +@ CHECK: subw r2, r2, #16 @ encoding: [0xa2,0xf2,0x10,0x02] + @------------------------------------------------------------------------------ @ ADD (register) @@ -121,9 +135,11 @@ _func: subw r11, pc, #3270 adr.w r11, #-826 + adr.w r1, #-0x0 @ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b] @ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b] +@ CHECK: adr.w r1, #-0 @ encoding: [0xaf,0xf2,0x00,0x01] @------------------------------------------------------------------------------ @ AND (immediate) @@ -401,6 +417,23 @@ _func: @------------------------------------------------------------------------------ @ DMB @------------------------------------------------------------------------------ + dmb #0xf + dmb #0xe + dmb #0xd + dmb #0xc + dmb #0xb + dmb #0xa + dmb #0x9 + dmb #0x8 + dmb #0x7 + dmb #0x6 + dmb #0x5 + dmb #0x4 + dmb #0x3 + dmb #0x2 + dmb #0x1 + dmb #0x0 + dmb sy dmb st dmb sh @@ -417,6 +450,23 @@ _func: @ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] @ CHECK: dmb st @ encoding: [0xbf,0xf3,0x5e,0x8f] +@ CHECK: dmb #0xd @ encoding: [0xbf,0xf3,0x5d,0x8f] +@ CHECK: dmb #0xc @ encoding: [0xbf,0xf3,0x5c,0x8f] +@ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] +@ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] +@ CHECK: dmb #0x9 @ encoding: [0xbf,0xf3,0x59,0x8f] +@ CHECK: dmb #0x8 @ encoding: [0xbf,0xf3,0x58,0x8f] +@ CHECK: dmb nsh @ encoding: [0xbf,0xf3,0x57,0x8f] +@ CHECK: dmb nshst @ encoding: [0xbf,0xf3,0x56,0x8f] +@ CHECK: dmb #0x5 @ encoding: [0xbf,0xf3,0x55,0x8f] +@ CHECK: dmb #0x4 @ encoding: [0xbf,0xf3,0x54,0x8f] +@ CHECK: dmb osh @ encoding: [0xbf,0xf3,0x53,0x8f] +@ CHECK: dmb oshst @ encoding: [0xbf,0xf3,0x52,0x8f] +@ CHECK: dmb #0x1 @ encoding: [0xbf,0xf3,0x51,0x8f] +@ CHECK: dmb #0x0 @ encoding: [0xbf,0xf3,0x50,0x8f] + +@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] +@ CHECK: dmb st @ encoding: [0xbf,0xf3,0x5e,0x8f] @ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] @ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] @ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] @@ -433,6 +483,23 @@ _func: @------------------------------------------------------------------------------ @ DSB @------------------------------------------------------------------------------ + dsb #0xf + dsb #0xe + dsb #0xd + dsb #0xc + dsb #0xb + dsb #0xa + dsb #0x9 + dsb #0x8 + dsb #0x7 + dsb #0x6 + dsb #0x5 + dsb #0x4 + dsb #0x3 + dsb #0x2 + dsb #0x1 + dsb #0x0 + dsb sy dsb st dsb sh @@ -449,6 +516,23 @@ _func: @ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] @ CHECK: dsb st @ encoding: [0xbf,0xf3,0x4e,0x8f] +@ CHECK: dsb #0xd @ encoding: [0xbf,0xf3,0x4d,0x8f] +@ CHECK: dsb #0xc @ encoding: [0xbf,0xf3,0x4c,0x8f] +@ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] +@ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] +@ CHECK: dsb #0x9 @ encoding: [0xbf,0xf3,0x49,0x8f] +@ CHECK: dsb #0x8 @ encoding: [0xbf,0xf3,0x48,0x8f] +@ CHECK: dsb nsh @ encoding: [0xbf,0xf3,0x47,0x8f] +@ CHECK: dsb nshst @ encoding: [0xbf,0xf3,0x46,0x8f] +@ CHECK: dsb #0x5 @ encoding: [0xbf,0xf3,0x45,0x8f] +@ CHECK: dsb #0x4 @ encoding: [0xbf,0xf3,0x44,0x8f] +@ CHECK: dsb osh @ encoding: [0xbf,0xf3,0x43,0x8f] +@ CHECK: dsb oshst @ encoding: [0xbf,0xf3,0x42,0x8f] +@ CHECK: dsb #0x1 @ encoding: [0xbf,0xf3,0x41,0x8f] +@ CHECK: dsb #0x0 @ encoding: [0xbf,0xf3,0x40,0x8f] + +@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] +@ CHECK: dsb st @ encoding: [0xbf,0xf3,0x4e,0x8f] @ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] @ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] @ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] @@ -509,6 +593,19 @@ _func: @ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] +@ Should also work for UPPER CASE condition codes. + + ITEET EQ + ADDEQ R0, R1, R2 + NOPNE + SUBNE R5, R6, R7 + ADDEQ R1, R2, #4 + +@ CHECK: iteet eq @ encoding: [0x0d,0xbf] +@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18] +@ CHECK: nopne @ encoding: [0x00,0xbf] +@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] +@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @------------------------------------------------------------------------------ @ LDC{L}/LDC2{L} @@ -755,6 +852,9 @@ _func: ldrd r3, r5, [r6], #-8 ldrd r3, r5, [r6] ldrd r8, r1, [r3, #0] + ldrd r0, r1, [r2, #-0] + ldrd r0, r1, [r2, #-0]! + ldrd r0, r1, [r2], #-0 @ CHECK: ldrd r3, r5, [r6, #24] @ encoding: [0xd6,0xe9,0x06,0x35] @ CHECK: ldrd r3, r5, [r6, #24]! @ encoding: [0xf6,0xe9,0x06,0x35] @@ -762,6 +862,9 @@ _func: @ CHECK: ldrd r3, r5, [r6], #-8 @ encoding: [0x76,0xe8,0x02,0x35] @ CHECK: ldrd r3, r5, [r6] @ encoding: [0xd6,0xe9,0x00,0x35] @ CHECK: ldrd r8, r1, [r3] @ encoding: [0xd3,0xe9,0x00,0x81] +@ CHECK: ldrd r0, r1, [r2, #-0] @ encoding: [0x52,0xe9,0x00,0x01] +@ CHECK: ldrd r0, r1, [r2, #-0]! @ encoding: [0x72,0xe9,0x00,0x01] +@ CHECK: ldrd r0, r1, [r2], #-0 @ encoding: [0x72,0xe8,0x00,0x01] @------------------------------------------------------------------------------ @@ -2539,6 +2642,9 @@ _func: strd r3, r5, [r6], #-8 strd r3, r5, [r6] strd r8, r1, [r3, #0] + strd r0, r1, [r2, #-0] + strd r0, r1, [r2, #-0]! + strd r0, r1, [r2], #-0 @ CHECK: strd r3, r5, [r6, #24] @ encoding: [0xc6,0xe9,0x06,0x35] @ CHECK: strd r3, r5, [r6, #24]! @ encoding: [0xe6,0xe9,0x06,0x35] @@ -2546,6 +2652,9 @@ _func: @ CHECK: strd r3, r5, [r6], #-8 @ encoding: [0x66,0xe8,0x02,0x35] @ CHECK: strd r3, r5, [r6] @ encoding: [0xc6,0xe9,0x00,0x35] @ CHECK: strd r8, r1, [r3] @ encoding: [0xc3,0xe9,0x00,0x81] +@ CHECK: strd r0, r1, [r2, #-0] @ encoding: [0x42,0xe9,0x00,0x01] +@ CHECK: strd r0, r1, [r2, #-0]! @ encoding: [0x62,0xe9,0x00,0x01] +@ CHECK: strd r0, r1, [r2], #-0 @ encoding: [0x62,0xe8,0x00,0x01] @------------------------------------------------------------------------------ @@ -3342,7 +3451,7 @@ _func: @ CHECK: uxth.w r7, r8 @ encoding: [0x1f,0xfa,0x88,0xf7] @------------------------------------------------------------------------------ -@ WFE/WFI/YIELD +@ WFE/WFI/YIELD/HINT @------------------------------------------------------------------------------ wfe wfi @@ -3351,6 +3460,13 @@ _func: wfelt wfige yieldlt + hint #5 + hint.w #5 + hint.w #4 + hint #3 + hint #2 + hint #1 + hint #0 @ CHECK: wfe @ encoding: [0x20,0xbf] @ CHECK: wfi @ encoding: [0x30,0xbf] @@ -3359,6 +3475,13 @@ _func: @ CHECK: wfelt @ encoding: [0x20,0xbf] @ CHECK: wfige @ encoding: [0x30,0xbf] @ CHECK: yieldlt @ encoding: [0x10,0xbf] +@ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80] +@ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80] +@ CHECK: sev.w @ encoding: [0xaf,0xf3,0x04,0x80] +@ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80] +@ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80] +@ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80] +@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 7da79c31dc35c..499e0550135e5 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -70,8 +70,8 @@ dbg #-1 dbg #16 -@ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] @ Double-check that we're synced up with the right diagnostics. @ CHECK-ERRORS: dbg #16 @@ -86,8 +86,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] @ Out of range immediate for MOV @@ -115,8 +115,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] @ Shifter operand validation for PKH instructions. pkhbt r2, r2, r3, lsl #-1 @@ -315,3 +315,9 @@ @ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255] @ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 } @ CHECK-ERRORS: ^ + + @ Bad CPS instruction format. + cps f,#1 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: cps f,#1 +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index 6899d92b50f8c..c98026b6a0437 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -61,7 +61,7 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind ;; OBJ: Relocation 1 -;; OBJ-NEXT: 'r_offset', +;; OBJ-NEXT: 'r_offset', ;; OBJ-NEXT: 'r_sym', 0x000002 ;; OBJ-NEXT: 'r_type', 0x2b diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s index dcc62d33c2f0a..08b4ecc9c7454 100644 --- a/test/MC/ARM/elf-reloc-condcall.s +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -4,6 +4,8 @@ bleq some_label bl some_label blx some_label + beq some_label + b some_label // OBJ: .rel.text // OBJ: 'r_offset', 0x00000000 @@ -18,6 +20,14 @@ // OBJ-NEXT: 'r_sym', 0x000004 // OBJ-NEXT: 'r_type', 0x1c +// OBJ: 'r_offset', 0x0000000c +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1d + +// OBJ: 'r_offset', 0x00000010 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1d + // OBJ: .symtab // OBJ: Symbol 4 -// OBJ-NEXT: some_label
\ No newline at end of file +// OBJ-NEXT: some_label diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index 2ce9bccf6727b..e8c1dd6348671 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -30,11 +30,16 @@ vbic q8, q8, q9 vbic.i32 d16, #0xFF000000 vbic.i32 q8, #0xFF000000 + vbic q10, q11 + vbic d9, d1 @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] @ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] @ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] +@ CHECK: vbic q10, q10, q11 @ encoding: [0xf6,0x41,0x54,0xf2] +@ CHECK: vbic d9, d9, d1 @ encoding: [0x11,0x91,0x19,0xf2] + vorn d16, d17, d16 vorn q8, q8, q9 @@ -232,32 +237,38 @@ @ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] @ Two-operand aliases + vand q6, q5 vand.s8 q6, q5 vand.s16 q7, q1 vand.s32 q8, q2 vand.f64 q8, q2 + veor q6, q5 veor.8 q6, q5 veor.p16 q7, q1 veor.u32 q8, q2 veor.d q8, q2 + veor q6, q5 veor.i8 q6, q5 veor.16 q7, q1 veor.f q8, q2 veor.i64 q8, q2 @ CHECK: vand q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf2] +@ CHECK: vand q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf2] @ CHECK: vand q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf2] @ CHECK: vand q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf2] @ CHECK: vand q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf2] @ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] +@ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] @ CHECK: veor q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] @ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] +@ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] @ CHECK: veor q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] diff --git a/test/MC/ARM/neon-shiftaccum-encoding.s b/test/MC/ARM/neon-shiftaccum-encoding.s new file mode 100644 index 0000000000000..92ca7a34095ba --- /dev/null +++ b/test/MC/ARM/neon-shiftaccum-encoding.s @@ -0,0 +1,209 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + + vsra.s8 d17, d16, #8 + vsra.s16 d15, d14, #16 + vsra.s32 d13, d12, #32 + vsra.s64 d11, d10, #64 + vsra.s8 q7, q2, #8 + vsra.s16 q3, q6, #16 + vsra.s32 q9, q5, #32 + vsra.s64 q8, q4, #64 + vsra.u8 d17, d16, #8 + vsra.u16 d11, d14, #11 + vsra.u32 d12, d15, #22 + vsra.u64 d13, d16, #54 + vsra.u8 q1, q7, #8 + vsra.u16 q2, q7, #6 + vsra.u32 q3, q6, #21 + vsra.u64 q4, q5, #25 + + @ Two-operand syntax variant. + vsra.s8 d16, #8 + vsra.s16 d14, #16 + vsra.s32 d12, #32 + vsra.s64 d10, #64 + vsra.s8 q2, #8 + vsra.s16 q6, #16 + vsra.s32 q5, #32 + vsra.s64 q4, #64 + vsra.u8 d16, #8 + vsra.u16 d14, #11 + vsra.u32 d15, #22 + vsra.u64 d16, #54 + vsra.u8 q7, #8 + vsra.u16 q7, #6 + vsra.u32 q6, #21 + vsra.u64 q5, #25 + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf2] +@ CHECK: vsra.s16 d15, d14, #16 @ encoding: [0x1e,0xf1,0x90,0xf2] +@ CHECK: vsra.s32 d13, d12, #32 @ encoding: [0x1c,0xd1,0xa0,0xf2] +@ CHECK: vsra.s64 d11, d10, #64 @ encoding: [0x9a,0xb1,0x80,0xf2] +@ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x54,0xe1,0x88,0xf2] +@ CHECK: vsra.s16 q3, q6, #16 @ encoding: [0x5c,0x61,0x90,0xf2] +@ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0x5a,0x21,0xe0,0xf2] +@ CHECK: vsra.s64 q8, q4, #64 @ encoding: [0xd8,0x01,0xc0,0xf2] +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf3] +@ CHECK: vsra.u16 d11, d14, #11 @ encoding: [0x1e,0xb1,0x95,0xf3] +@ CHECK: vsra.u32 d12, d15, #22 @ encoding: [0x1f,0xc1,0xaa,0xf3] +@ CHECK: vsra.u64 d13, d16, #54 @ encoding: [0xb0,0xd1,0x8a,0xf3] +@ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x5e,0x21,0x88,0xf3] +@ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x5e,0x41,0x9a,0xf3] +@ CHECK: vsra.u32 q3, q6, #21 @ encoding: [0x5c,0x61,0xab,0xf3] +@ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xda,0x81,0xa7,0xf3] + +@ CHECK: vsra.s8 d16, d16, #8 @ encoding: [0x30,0x01,0xc8,0xf2] +@ CHECK: vsra.s16 d14, d14, #16 @ encoding: [0x1e,0xe1,0x90,0xf2] +@ CHECK: vsra.s32 d12, d12, #32 @ encoding: [0x1c,0xc1,0xa0,0xf2] +@ CHECK: vsra.s64 d10, d10, #64 @ encoding: [0x9a,0xa1,0x80,0xf2] +@ CHECK: vsra.s8 q2, q2, #8 @ encoding: [0x54,0x41,0x88,0xf2] +@ CHECK: vsra.s16 q6, q6, #16 @ encoding: [0x5c,0xc1,0x90,0xf2] +@ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0x5a,0xa1,0xa0,0xf2] +@ CHECK: vsra.s64 q4, q4, #64 @ encoding: [0xd8,0x81,0x80,0xf2] +@ CHECK: vsra.u8 d16, d16, #8 @ encoding: [0x30,0x01,0xc8,0xf3] +@ CHECK: vsra.u16 d14, d14, #11 @ encoding: [0x1e,0xe1,0x95,0xf3] +@ CHECK: vsra.u32 d15, d15, #22 @ encoding: [0x1f,0xf1,0xaa,0xf3] +@ CHECK: vsra.u64 d16, d16, #54 @ encoding: [0xb0,0x01,0xca,0xf3] +@ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x5e,0xe1,0x88,0xf3] +@ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x5e,0xe1,0x9a,0xf3] +@ CHECK: vsra.u32 q6, q6, #21 @ encoding: [0x5c,0xc1,0xab,0xf3] +@ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xda,0xa1,0xa7,0xf3] + + vrsra.s8 d5, d26, #8 + vrsra.s16 d6, d25, #16 + vrsra.s32 d7, d24, #32 + vrsra.s64 d14, d23, #64 + vrsra.u8 d15, d22, #8 + vrsra.u16 d16, d21, #16 + vrsra.u32 d17, d20, #32 + vrsra.u64 d18, d19, #64 + vrsra.s8 q1, q2, #8 + vrsra.s16 q2, q3, #16 + vrsra.s32 q3, q4, #32 + vrsra.s64 q4, q5, #64 + vrsra.u8 q5, q6, #8 + vrsra.u16 q6, q7, #16 + vrsra.u32 q7, q8, #32 + vrsra.u64 q8, q9, #64 + + @ Two-operand syntax variant. + vrsra.s8 d26, #8 + vrsra.s16 d25, #16 + vrsra.s32 d24, #32 + vrsra.s64 d23, #64 + vrsra.u8 d22, #8 + vrsra.u16 d21, #16 + vrsra.u32 d20, #32 + vrsra.u64 d19, #64 + vrsra.s8 q2, #8 + vrsra.s16 q3, #16 + vrsra.s32 q4, #32 + vrsra.s64 q5, #64 + vrsra.u8 q6, #8 + vrsra.u16 q7, #16 + vrsra.u32 q8, #32 + vrsra.u64 q9, #64 + +@ CHECK: vrsra.s8 d5, d26, #8 @ encoding: [0x3a,0x53,0x88,0xf2] +@ CHECK: vrsra.s16 d6, d25, #16 @ encoding: [0x39,0x63,0x90,0xf2] +@ CHECK: vrsra.s32 d7, d24, #32 @ encoding: [0x38,0x73,0xa0,0xf2] +@ CHECK: vrsra.s64 d14, d23, #64 @ encoding: [0xb7,0xe3,0x80,0xf2] +@ CHECK: vrsra.u8 d15, d22, #8 @ encoding: [0x36,0xf3,0x88,0xf3] +@ CHECK: vrsra.u16 d16, d21, #16 @ encoding: [0x35,0x03,0xd0,0xf3] +@ CHECK: vrsra.u32 d17, d20, #32 @ encoding: [0x34,0x13,0xe0,0xf3] +@ CHECK: vrsra.u64 d18, d19, #64 @ encoding: [0xb3,0x23,0xc0,0xf3] +@ CHECK: vrsra.s8 q1, q2, #8 @ encoding: [0x54,0x23,0x88,0xf2] +@ CHECK: vrsra.s16 q2, q3, #16 @ encoding: [0x56,0x43,0x90,0xf2] +@ CHECK: vrsra.s32 q3, q4, #32 @ encoding: [0x58,0x63,0xa0,0xf2] +@ CHECK: vrsra.s64 q4, q5, #64 @ encoding: [0xda,0x83,0x80,0xf2] +@ CHECK: vrsra.u8 q5, q6, #8 @ encoding: [0x5c,0xa3,0x88,0xf3] +@ CHECK: vrsra.u16 q6, q7, #16 @ encoding: [0x5e,0xc3,0x90,0xf3] +@ CHECK: vrsra.u32 q7, q8, #32 @ encoding: [0x70,0xe3,0xa0,0xf3] +@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf3] + +@ CHECK: vrsra.s8 d26, d26, #8 @ encoding: [0x3a,0xa3,0xc8,0xf2] +@ CHECK: vrsra.s16 d25, d25, #16 @ encoding: [0x39,0x93,0xd0,0xf2] +@ CHECK: vrsra.s32 d24, d24, #32 @ encoding: [0x38,0x83,0xe0,0xf2] +@ CHECK: vrsra.s64 d23, d23, #64 @ encoding: [0xb7,0x73,0xc0,0xf2] +@ CHECK: vrsra.u8 d22, d22, #8 @ encoding: [0x36,0x63,0xc8,0xf3] +@ CHECK: vrsra.u16 d21, d21, #16 @ encoding: [0x35,0x53,0xd0,0xf3] +@ CHECK: vrsra.u32 d20, d20, #32 @ encoding: [0x34,0x43,0xe0,0xf3] +@ CHECK: vrsra.u64 d19, d19, #64 @ encoding: [0xb3,0x33,0xc0,0xf3] +@ CHECK: vrsra.s8 q2, q2, #8 @ encoding: [0x54,0x43,0x88,0xf2] +@ CHECK: vrsra.s16 q3, q3, #16 @ encoding: [0x56,0x63,0x90,0xf2] +@ CHECK: vrsra.s32 q4, q4, #32 @ encoding: [0x58,0x83,0xa0,0xf2] +@ CHECK: vrsra.s64 q5, q5, #64 @ encoding: [0xda,0xa3,0x80,0xf2] +@ CHECK: vrsra.u8 q6, q6, #8 @ encoding: [0x5c,0xc3,0x88,0xf3] +@ CHECK: vrsra.u16 q7, q7, #16 @ encoding: [0x5e,0xe3,0x90,0xf3] +@ CHECK: vrsra.u32 q8, q8, #32 @ encoding: [0x70,0x03,0xe0,0xf3] +@ CHECK: vrsra.u64 q9, q9, #64 @ encoding: [0xf2,0x23,0xc0,0xf3] + + + vsli.8 d11, d12, #7 + vsli.16 d12, d13, #15 + vsli.32 d13, d14, #31 + vsli.64 d14, d15, #63 + vsli.8 q1, q8, #7 + vsli.16 q2, q7, #15 + vsli.32 q3, q4, #31 + vsli.64 q4, q5, #63 + vsri.8 d28, d11, #8 + vsri.16 d26, d12, #16 + vsri.32 d24, d13, #32 + vsri.64 d21, d14, #64 + vsri.8 q1, q8, #8 + vsri.16 q5, q2, #16 + vsri.32 q7, q4, #32 + vsri.64 q9, q6, #64 + + @ Two-operand syntax variant. + vsli.8 d12, #7 + vsli.16 d13, #15 + vsli.32 d14, #31 + vsli.64 d15, #63 + vsli.8 q8, #7 + vsli.16 q7, #15 + vsli.32 q4, #31 + vsli.64 q5, #63 + vsri.8 d11, #8 + vsri.16 d12, #16 + vsri.32 d13, #32 + vsri.64 d14, #64 + vsri.8 q8, #8 + vsri.16 q2, #16 + vsri.32 q4, #32 + vsri.64 q6, #64 + +@ CHECK: vsli.8 d11, d12, #7 @ encoding: [0x1c,0xb5,0x8f,0xf3] +@ CHECK: vsli.16 d12, d13, #15 @ encoding: [0x1d,0xc5,0x9f,0xf3] +@ CHECK: vsli.32 d13, d14, #31 @ encoding: [0x1e,0xd5,0xbf,0xf3] +@ CHECK: vsli.64 d14, d15, #63 @ encoding: [0x9f,0xe5,0xbf,0xf3] +@ CHECK: vsli.8 q1, q8, #7 @ encoding: [0x70,0x25,0x8f,0xf3] +@ CHECK: vsli.16 q2, q7, #15 @ encoding: [0x5e,0x45,0x9f,0xf3] +@ CHECK: vsli.32 q3, q4, #31 @ encoding: [0x58,0x65,0xbf,0xf3] +@ CHECK: vsli.64 q4, q5, #63 @ encoding: [0xda,0x85,0xbf,0xf3] +@ CHECK: vsri.8 d28, d11, #8 @ encoding: [0x1b,0xc4,0xc8,0xf3] +@ CHECK: vsri.16 d26, d12, #16 @ encoding: [0x1c,0xa4,0xd0,0xf3] +@ CHECK: vsri.32 d24, d13, #32 @ encoding: [0x1d,0x84,0xe0,0xf3] +@ CHECK: vsri.64 d21, d14, #64 @ encoding: [0x9e,0x54,0xc0,0xf3] +@ CHECK: vsri.8 q1, q8, #8 @ encoding: [0x70,0x24,0x88,0xf3] +@ CHECK: vsri.16 q5, q2, #16 @ encoding: [0x54,0xa4,0x90,0xf3] +@ CHECK: vsri.32 q7, q4, #32 @ encoding: [0x58,0xe4,0xa0,0xf3] +@ CHECK: vsri.64 q9, q6, #64 @ encoding: [0xdc,0x24,0xc0,0xf3] + +@ CHECK: vsli.8 d12, d12, #7 @ encoding: [0x1c,0xc5,0x8f,0xf3] +@ CHECK: vsli.16 d13, d13, #15 @ encoding: [0x1d,0xd5,0x9f,0xf3] +@ CHECK: vsli.32 d14, d14, #31 @ encoding: [0x1e,0xe5,0xbf,0xf3] +@ CHECK: vsli.64 d15, d15, #63 @ encoding: [0x9f,0xf5,0xbf,0xf3] +@ CHECK: vsli.8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf3] +@ CHECK: vsli.16 q7, q7, #15 @ encoding: [0x5e,0xe5,0x9f,0xf3] +@ CHECK: vsli.32 q4, q4, #31 @ encoding: [0x58,0x85,0xbf,0xf3] +@ CHECK: vsli.64 q5, q5, #63 @ encoding: [0xda,0xa5,0xbf,0xf3] +@ CHECK: vsri.8 d11, d11, #8 @ encoding: [0x1b,0xb4,0x88,0xf3] +@ CHECK: vsri.16 d12, d12, #16 @ encoding: [0x1c,0xc4,0x90,0xf3] +@ CHECK: vsri.32 d13, d13, #32 @ encoding: [0x1d,0xd4,0xa0,0xf3] +@ CHECK: vsri.64 d14, d14, #64 @ encoding: [0x9e,0xe4,0x80,0xf3] +@ CHECK: vsri.8 q8, q8, #8 @ encoding: [0x70,0x04,0xc8,0xf3] +@ CHECK: vsri.16 q2, q2, #16 @ encoding: [0x54,0x44,0x90,0xf3] +@ CHECK: vsri.32 q4, q4, #32 @ encoding: [0x58,0x84,0xa0,0xf3] +@ CHECK: vsri.64 q6, q6, #64 @ encoding: [0xdc,0xc4,0x80,0xf3] diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s index 8eb38a5f71187..be67aa8da6ff9 100644 --- a/test/MC/ARM/neon-sub-encoding.s +++ b/test/MC/ARM/neon-sub-encoding.s @@ -158,3 +158,18 @@ @ CHECK: vhsub.u8 q4, q4, q9 @ encoding: [0x62,0x82,0x08,0xf3] @ CHECK: vhsub.u16 q5, q5, q8 @ encoding: [0x60,0xa2,0x1a,0xf3] @ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3] + + + vsubw.s8 q6, d5 + vsubw.s16 q7, d1 + vsubw.s32 q8, d2 + vsubw.u8 q6, d5 + vsubw.u16 q7, d1 + vsubw.u32 q8, d2 + +@ CHECK: vsubw.s8 q6, q6, d5 @ encoding: [0x05,0xc3,0x8c,0xf2] +@ CHECK: vsubw.s16 q7, q7, d1 @ encoding: [0x01,0xe3,0x9e,0xf2] +@ CHECK: vsubw.s32 q8, q8, d2 @ encoding: [0x82,0x03,0xe0,0xf2] +@ CHECK: vsubw.u8 q6, q6, d5 @ encoding: [0x05,0xc3,0x8c,0xf3] +@ CHECK: vsubw.u16 q7, q7, d1 @ encoding: [0x01,0xe3,0x9e,0xf3] +@ CHECK: vsubw.u32 q8, q8, d2 @ encoding: [0x82,0x03,0xe0,0xf3] diff --git a/test/MC/ARM/neont2-absdiff-encoding.s b/test/MC/ARM/neont2-absdiff-encoding.s index 431348392f481..ac2f9e7f4e748 100644 --- a/test/MC/ARM/neont2-absdiff-encoding.s +++ b/test/MC/ARM/neont2-absdiff-encoding.s @@ -1,4 +1,4 @@ -@RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck %s +@RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s .code 16 diff --git a/test/MC/ARM/neont2-dup-encoding.s b/test/MC/ARM/neont2-dup-encoding.s index bf25d70b5cf49..d6db496d4f886 100644 --- a/test/MC/ARM/neont2-dup-encoding.s +++ b/test/MC/ARM/neont2-dup-encoding.s @@ -1,4 +1,4 @@ -@RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck %s +@RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s .code 16 diff --git a/test/MC/ARM/neont2-shiftaccum-encoding.s b/test/MC/ARM/neont2-shiftaccum-encoding.s index a3a18fcee87e0..3229b43da2327 100644 --- a/test/MC/ARM/neont2-shiftaccum-encoding.s +++ b/test/MC/ARM/neont2-shiftaccum-encoding.s @@ -2,99 +2,211 @@ .code 16 -@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x11] - vsra.s8 d17, d16, #8 -@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x11] - vsra.s16 d17, d16, #16 -@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x11] - vsra.s32 d17, d16, #32 -@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x11] - vsra.s64 d17, d16, #64 -@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0xc8,0xef,0x72,0x01] - vsra.s8 q8, q9, #8 -@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0xd0,0xef,0x72,0x01] - vsra.s16 q8, q9, #16 -@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0xe0,0xef,0x72,0x01] - vsra.s32 q8, q9, #32 -@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xc0,0xef,0xf2,0x01] - vsra.s64 q8, q9, #64 -@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x11] - vsra.u8 d17, d16, #8 -@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x11] - vsra.u16 d17, d16, #16 -@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x11] - vsra.u32 d17, d16, #32 -@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x11] - vsra.u64 d17, d16, #64 -@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0xc8,0xff,0x72,0x01] - vsra.u8 q8, q9, #8 -@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0xd0,0xff,0x72,0x01] - vsra.u16 q8, q9, #16 -@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0xe0,0xff,0x72,0x01] - vsra.u32 q8, q9, #32 -@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xc0,0xff,0xf2,0x01] - vsra.u64 q8, q9, #64 -@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x13] - vrsra.s8 d17, d16, #8 -@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x13] - vrsra.s16 d17, d16, #16 -@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x13] - vrsra.s32 d17, d16, #32 -@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x13] - vrsra.s64 d17, d16, #64 -@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x13] - vrsra.u8 d17, d16, #8 -@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x13] - vrsra.u16 d17, d16, #16 -@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x13] - vrsra.u32 d17, d16, #32 -@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x13] - vrsra.u64 d17, d16, #64 -@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0xc8,0xef,0x72,0x03] - vrsra.s8 q8, q9, #8 -@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0xd0,0xef,0x72,0x03] - vrsra.s16 q8, q9, #16 -@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0xe0,0xef,0x72,0x03] - vrsra.s32 q8, q9, #32 -@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xc0,0xef,0xf2,0x03] - vrsra.s64 q8, q9, #64 -@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0xc8,0xff,0x72,0x03] - vrsra.u8 q8, q9, #8 -@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0xd0,0xff,0x72,0x03] - vrsra.u16 q8, q9, #16 -@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0xe0,0xff,0x72,0x03] - vrsra.u32 q8, q9, #32 + vsra.s8 d17, d16, #8 + vsra.s16 d15, d14, #16 + vsra.s32 d13, d12, #32 + vsra.s64 d11, d10, #64 + vsra.s8 q7, q2, #8 + vsra.s16 q3, q6, #16 + vsra.s32 q9, q5, #32 + vsra.s64 q8, q4, #64 + vsra.u8 d17, d16, #8 + vsra.u16 d11, d14, #11 + vsra.u32 d12, d15, #22 + vsra.u64 d13, d16, #54 + vsra.u8 q1, q7, #8 + vsra.u16 q2, q7, #6 + vsra.u32 q3, q6, #21 + vsra.u64 q4, q5, #25 + + @ Two-operand syntax variant. + vsra.s8 d16, #8 + vsra.s16 d14, #16 + vsra.s32 d12, #32 + vsra.s64 d10, #64 + vsra.s8 q2, #8 + vsra.s16 q6, #16 + vsra.s32 q5, #32 + vsra.s64 q4, #64 + vsra.u8 d16, #8 + vsra.u16 d14, #11 + vsra.u32 d15, #22 + vsra.u64 d16, #54 + vsra.u8 q7, #8 + vsra.u16 q7, #6 + vsra.u32 q6, #21 + vsra.u64 q5, #25 + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x11] +@ CHECK: vsra.s16 d15, d14, #16 @ encoding: [0x90,0xef,0x1e,0xf1] +@ CHECK: vsra.s32 d13, d12, #32 @ encoding: [0xa0,0xef,0x1c,0xd1] +@ CHECK: vsra.s64 d11, d10, #64 @ encoding: [0x80,0xef,0x9a,0xb1] +@ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x88,0xef,0x54,0xe1] +@ CHECK: vsra.s16 q3, q6, #16 @ encoding: [0x90,0xef,0x5c,0x61] +@ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0xe0,0xef,0x5a,0x21] +@ CHECK: vsra.s64 q8, q4, #64 @ encoding: [0xc0,0xef,0xd8,0x01] +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x11] +@ CHECK: vsra.u16 d11, d14, #11 @ encoding: [0x95,0xff,0x1e,0xb1] +@ CHECK: vsra.u32 d12, d15, #22 @ encoding: [0xaa,0xff,0x1f,0xc1] +@ CHECK: vsra.u64 d13, d16, #54 @ encoding: [0x8a,0xff,0xb0,0xd1] +@ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x88,0xff,0x5e,0x21] +@ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x9a,0xff,0x5e,0x41] +@ CHECK: vsra.u32 q3, q6, #21 @ encoding: [0xab,0xff,0x5c,0x61] +@ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xa7,0xff,0xda,0x81] + +@ CHECK: vsra.s8 d16, d16, #8 @ encoding: [0xc8,0xef,0x30,0x01] +@ CHECK: vsra.s16 d14, d14, #16 @ encoding: [0x90,0xef,0x1e,0xe1] +@ CHECK: vsra.s32 d12, d12, #32 @ encoding: [0xa0,0xef,0x1c,0xc1] +@ CHECK: vsra.s64 d10, d10, #64 @ encoding: [0x80,0xef,0x9a,0xa1] +@ CHECK: vsra.s8 q2, q2, #8 @ encoding: [0x88,0xef,0x54,0x41] +@ CHECK: vsra.s16 q6, q6, #16 @ encoding: [0x90,0xef,0x5c,0xc1] +@ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0xa0,0xef,0x5a,0xa1] +@ CHECK: vsra.s64 q4, q4, #64 @ encoding: [0x80,0xef,0xd8,0x81] +@ CHECK: vsra.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x01] +@ CHECK: vsra.u16 d14, d14, #11 @ encoding: [0x95,0xff,0x1e,0xe1] +@ CHECK: vsra.u32 d15, d15, #22 @ encoding: [0xaa,0xff,0x1f,0xf1] +@ CHECK: vsra.u64 d16, d16, #54 @ encoding: [0xca,0xff,0xb0,0x01] +@ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x88,0xff,0x5e,0xe1] +@ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x9a,0xff,0x5e,0xe1] +@ CHECK: vsra.u32 q6, q6, #21 @ encoding: [0xab,0xff,0x5c,0xc1] +@ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xa7,0xff,0xda,0xa1] + + + vrsra.s8 d5, d26, #8 + vrsra.s16 d6, d25, #16 + vrsra.s32 d7, d24, #32 + vrsra.s64 d14, d23, #64 + vrsra.u8 d15, d22, #8 + vrsra.u16 d16, d21, #16 + vrsra.u32 d17, d20, #32 + vrsra.u64 d18, d19, #64 + vrsra.s8 q1, q2, #8 + vrsra.s16 q2, q3, #16 + vrsra.s32 q3, q4, #32 + vrsra.s64 q4, q5, #64 + vrsra.u8 q5, q6, #8 + vrsra.u16 q6, q7, #16 + vrsra.u32 q7, q8, #32 + vrsra.u64 q8, q9, #64 + + @ Two-operand syntax variant. + vrsra.s8 d26, #8 + vrsra.s16 d25, #16 + vrsra.s32 d24, #32 + vrsra.s64 d23, #64 + vrsra.u8 d22, #8 + vrsra.u16 d21, #16 + vrsra.u32 d20, #32 + vrsra.u64 d19, #64 + vrsra.s8 q2, #8 + vrsra.s16 q3, #16 + vrsra.s32 q4, #32 + vrsra.s64 q5, #64 + vrsra.u8 q6, #8 + vrsra.u16 q7, #16 + vrsra.u32 q8, #32 + vrsra.u64 q9, #64 + +@ CHECK: vrsra.s8 d5, d26, #8 @ encoding: [0x88,0xef,0x3a,0x53] +@ CHECK: vrsra.s16 d6, d25, #16 @ encoding: [0x90,0xef,0x39,0x63] +@ CHECK: vrsra.s32 d7, d24, #32 @ encoding: [0xa0,0xef,0x38,0x73] +@ CHECK: vrsra.s64 d14, d23, #64 @ encoding: [0x80,0xef,0xb7,0xe3] +@ CHECK: vrsra.u8 d15, d22, #8 @ encoding: [0x88,0xff,0x36,0xf3] +@ CHECK: vrsra.u16 d16, d21, #16 @ encoding: [0xd0,0xff,0x35,0x03] +@ CHECK: vrsra.u32 d17, d20, #32 @ encoding: [0xe0,0xff,0x34,0x13] +@ CHECK: vrsra.u64 d18, d19, #64 @ encoding: [0xc0,0xff,0xb3,0x23] +@ CHECK: vrsra.s8 q1, q2, #8 @ encoding: [0x88,0xef,0x54,0x23] +@ CHECK: vrsra.s16 q2, q3, #16 @ encoding: [0x90,0xef,0x56,0x43] +@ CHECK: vrsra.s32 q3, q4, #32 @ encoding: [0xa0,0xef,0x58,0x63] +@ CHECK: vrsra.s64 q4, q5, #64 @ encoding: [0x80,0xef,0xda,0x83] +@ CHECK: vrsra.u8 q5, q6, #8 @ encoding: [0x88,0xff,0x5c,0xa3] +@ CHECK: vrsra.u16 q6, q7, #16 @ encoding: [0x90,0xff,0x5e,0xc3] +@ CHECK: vrsra.u32 q7, q8, #32 @ encoding: [0xa0,0xff,0x70,0xe3] @ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xc0,0xff,0xf2,0x03] - vrsra.u64 q8, q9, #64 -@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0xcf,0xff,0x30,0x15] - vsli.8 d17, d16, #7 -@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0xdf,0xff,0x30,0x15] - vsli.16 d17, d16, #15 -@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0xff,0xff,0x30,0x15] - vsli.32 d17, d16, #31 -@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xff,0xff,0xb0,0x15] - vsli.64 d17, d16, #63 -@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0xcf,0xff,0x70,0x25] - vsli.8 q9, q8, #7 -@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0xdf,0xff,0x70,0x25] - vsli.16 q9, q8, #15 -@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0xff,0xff,0x70,0x25] - vsli.32 q9, q8, #31 -@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xff,0xff,0xf0,0x25] - vsli.64 q9, q8, #63 -@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x14] - vsri.8 d17, d16, #8 -@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x14] - vsri.16 d17, d16, #16 -@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x14] - vsri.32 d17, d16, #32 -@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x14] - vsri.64 d17, d16, #64 -@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0xc8,0xff,0x70,0x24] - vsri.8 q9, q8, #8 -@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0xd0,0xff,0x70,0x24] - vsri.16 q9, q8, #16 -@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0xe0,0xff,0x70,0x24] - vsri.32 q9, q8, #32 -@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xc0,0xff,0xf0,0x24] - vsri.64 q9, q8, #64 + +@ CHECK: vrsra.s8 d26, d26, #8 @ encoding: [0xc8,0xef,0x3a,0xa3] +@ CHECK: vrsra.s16 d25, d25, #16 @ encoding: [0xd0,0xef,0x39,0x93] +@ CHECK: vrsra.s32 d24, d24, #32 @ encoding: [0xe0,0xef,0x38,0x83] +@ CHECK: vrsra.s64 d23, d23, #64 @ encoding: [0xc0,0xef,0xb7,0x73] +@ CHECK: vrsra.u8 d22, d22, #8 @ encoding: [0xc8,0xff,0x36,0x63] +@ CHECK: vrsra.u16 d21, d21, #16 @ encoding: [0xd0,0xff,0x35,0x53] +@ CHECK: vrsra.u32 d20, d20, #32 @ encoding: [0xe0,0xff,0x34,0x43] +@ CHECK: vrsra.u64 d19, d19, #64 @ encoding: [0xc0,0xff,0xb3,0x33] +@ CHECK: vrsra.s8 q2, q2, #8 @ encoding: [0x88,0xef,0x54,0x43] +@ CHECK: vrsra.s16 q3, q3, #16 @ encoding: [0x90,0xef,0x56,0x63] +@ CHECK: vrsra.s32 q4, q4, #32 @ encoding: [0xa0,0xef,0x58,0x83] +@ CHECK: vrsra.s64 q5, q5, #64 @ encoding: [0x80,0xef,0xda,0xa3] +@ CHECK: vrsra.u8 q6, q6, #8 @ encoding: [0x88,0xff,0x5c,0xc3] +@ CHECK: vrsra.u16 q7, q7, #16 @ encoding: [0x90,0xff,0x5e,0xe3] +@ CHECK: vrsra.u32 q8, q8, #32 @ encoding: [0xe0,0xff,0x70,0x03] +@ CHECK: vrsra.u64 q9, q9, #64 @ encoding: [0xc0,0xff,0xf2,0x23] + + + vsli.8 d11, d12, #7 + vsli.16 d12, d13, #15 + vsli.32 d13, d14, #31 + vsli.64 d14, d15, #63 + vsli.8 q1, q8, #7 + vsli.16 q2, q7, #15 + vsli.32 q3, q4, #31 + vsli.64 q4, q5, #63 + vsri.8 d28, d11, #8 + vsri.16 d26, d12, #16 + vsri.32 d24, d13, #32 + vsri.64 d21, d14, #64 + vsri.8 q1, q8, #8 + vsri.16 q5, q2, #16 + vsri.32 q7, q4, #32 + vsri.64 q9, q6, #64 + + @ Two-operand syntax variant. + vsli.8 d12, #7 + vsli.16 d13, #15 + vsli.32 d14, #31 + vsli.64 d15, #63 + vsli.8 q8, #7 + vsli.16 q7, #15 + vsli.32 q4, #31 + vsli.64 q5, #63 + vsri.8 d11, #8 + vsri.16 d12, #16 + vsri.32 d13, #32 + vsri.64 d14, #64 + vsri.8 q8, #8 + vsri.16 q2, #16 + vsri.32 q4, #32 + vsri.64 q6, #64 + +@ CHECK: vsli.8 d11, d12, #7 @ encoding: [0x8f,0xff,0x1c,0xb5] +@ CHECK: vsli.16 d12, d13, #15 @ encoding: [0x9f,0xff,0x1d,0xc5] +@ CHECK: vsli.32 d13, d14, #31 @ encoding: [0xbf,0xff,0x1e,0xd5] +@ CHECK: vsli.64 d14, d15, #63 @ encoding: [0xbf,0xff,0x9f,0xe5] +@ CHECK: vsli.8 q1, q8, #7 @ encoding: [0x8f,0xff,0x70,0x25] +@ CHECK: vsli.16 q2, q7, #15 @ encoding: [0x9f,0xff,0x5e,0x45] +@ CHECK: vsli.32 q3, q4, #31 @ encoding: [0xbf,0xff,0x58,0x65] +@ CHECK: vsli.64 q4, q5, #63 @ encoding: [0xbf,0xff,0xda,0x85] +@ CHECK: vsri.8 d28, d11, #8 @ encoding: [0xc8,0xff,0x1b,0xc4] +@ CHECK: vsri.16 d26, d12, #16 @ encoding: [0xd0,0xff,0x1c,0xa4] +@ CHECK: vsri.32 d24, d13, #32 @ encoding: [0xe0,0xff,0x1d,0x84] +@ CHECK: vsri.64 d21, d14, #64 @ encoding: [0xc0,0xff,0x9e,0x54] +@ CHECK: vsri.8 q1, q8, #8 @ encoding: [0x88,0xff,0x70,0x24] +@ CHECK: vsri.16 q5, q2, #16 @ encoding: [0x90,0xff,0x54,0xa4] +@ CHECK: vsri.32 q7, q4, #32 @ encoding: [0xa0,0xff,0x58,0xe4] +@ CHECK: vsri.64 q9, q6, #64 @ encoding: [0xc0,0xff,0xdc,0x24] + +@ CHECK: vsli.8 d12, d12, #7 @ encoding: [0x8f,0xff,0x1c,0xc5] +@ CHECK: vsli.16 d13, d13, #15 @ encoding: [0x9f,0xff,0x1d,0xd5] +@ CHECK: vsli.32 d14, d14, #31 @ encoding: [0xbf,0xff,0x1e,0xe5] +@ CHECK: vsli.64 d15, d15, #63 @ encoding: [0xbf,0xff,0x9f,0xf5] +@ CHECK: vsli.8 q8, q8, #7 @ encoding: [0xcf,0xff,0x70,0x05] +@ CHECK: vsli.16 q7, q7, #15 @ encoding: [0x9f,0xff,0x5e,0xe5] +@ CHECK: vsli.32 q4, q4, #31 @ encoding: [0xbf,0xff,0x58,0x85] +@ CHECK: vsli.64 q5, q5, #63 @ encoding: [0xbf,0xff,0xda,0xa5] +@ CHECK: vsri.8 d11, d11, #8 @ encoding: [0x88,0xff,0x1b,0xb4] +@ CHECK: vsri.16 d12, d12, #16 @ encoding: [0x90,0xff,0x1c,0xc4] +@ CHECK: vsri.32 d13, d13, #32 @ encoding: [0xa0,0xff,0x1d,0xd4] +@ CHECK: vsri.64 d14, d14, #64 @ encoding: [0x80,0xff,0x9e,0xe4] +@ CHECK: vsri.8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x04] +@ CHECK: vsri.16 q2, q2, #16 @ encoding: [0x90,0xff,0x54,0x44] +@ CHECK: vsri.32 q4, q4, #32 @ encoding: [0xa0,0xff,0x58,0x84] +@ CHECK: vsri.64 q6, q6, #64 @ encoding: [0x80,0xff,0xdc,0xc4] diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index b592f1ee499d4..2a226205a086d 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -1,124 +1,121 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + vadd.f64 d16, d17, d16 + vadd.f32 s0, s1, s0 @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] - vadd.f64 d16, d17, d16 - @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] - vadd.f32 s0, s1, s0 + vsub.f64 d16, d17, d16 + vsub.f32 s0, s1, s0 @ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee] - vsub.f64 d16, d17, d16 - @ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee] - vsub.f32 s0, s1, s0 -@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] - vdiv.f64 d16, d17, d16 + vdiv.f64 d16, d17, d16 + vdiv.f32 s0, s1, s0 + vdiv.f32 s5, s7 + vdiv.f64 d5, d7 -@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] - vdiv.f32 s0, s1, s0 +@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] +@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] +@ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee] +@ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee] -@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] - vmul.f64 d16, d17, d16 -@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] + vmul.f64 d16, d17, d16 vmul.f64 d20, d17 + vmul.f32 s0, s1, s0 + vmul.f32 s11, s21 -@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] - vmul.f32 s0, s1, s0 -@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] - vmul.f32 s11, s21 +@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] +@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] +@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] +@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] -@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] vnmul.f64 d16, d17, d16 + vnmul.f32 s0, s1, s0 +@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] - vnmul.f32 s0, s1, s0 -@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] vcmpe.f64 d17, d16 + vcmpe.f32 s1, s0 +@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] @ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] - vcmpe.f32 s1, s0 -@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] vcmpe.f64 d16, #0 + vcmpe.f32 s0, #0 +@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] @ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] - vcmpe.f32 s0, #0 -@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] vabs.f64 d16, d16 + vabs.f32 s0, s0 +@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] @ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] - vabs.f32 s0, s0 -@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 + vcvt.f64.f32 d16, s0 +@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee] - vcvt.f64.f32 d16, s0 -@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] vneg.f64 d16, d16 + vneg.f32 s0, s0 +@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] @ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee] - vneg.f32 s0, s0 -@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] vsqrt.f64 d16, d16 + vsqrt.f32 s0, s0 +@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] @ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee] - vsqrt.f32 s0, s0 -@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] vcvt.f64.s32 d16, s0 - -@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] vcvt.f32.s32 s0, s0 - -@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] vcvt.f64.u32 d16, s0 - -@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] vcvt.f32.u32 s0, s0 - -@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] vcvt.s32.f64 s0, d16 - -@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] vcvt.s32.f32 s0, s0 - -@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] vcvt.u32.f64 s0, d16 + vcvt.u32.f32 s0, s0 +@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] +@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] +@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] +@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] +@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] +@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] +@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] @ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee] - vcvt.u32.f32 s0, s0 -@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] + vmla.f64 d16, d18, d17 + vmla.f32 s1, s2, s0 +@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] @ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] - vmla.f32 s1, s2, s0 -@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] vmls.f64 d16, d18, d17 + vmls.f32 s1, s2, s0 +@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] @ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] - vmls.f32 s1, s2, s0 -@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] vnmla.f64 d16, d18, d17 + vnmla.f32 s1, s2, s0 +@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] @ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] - vnmla.f32 s1, s2, s0 -@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] vnmls.f64 d16, d18, d17 + vnmls.f32 s1, s2, s0 +@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] - vnmls.f32 s1, s2, s0 vmrs APSR_nzcv, fpscr vmrs apsr_nzcv, fpscr @@ -199,6 +196,27 @@ @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 +@ Between two single precision registers and two core registers + vmov s3, s4, r1, r2 + vmov s2, s3, r1, r2 + vmov r1, r2, s3, s4 + vmov r1, r2, s2, s3 +@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec] +@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec] +@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec] +@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec] + +@ Between one double precision register and two core registers + vmov d15, r1, r2 + vmov d16, r1, r2 + vmov r1, r2, d15 + vmov r1, r2, d16 +@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec] +@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec] +@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec] +@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec] + + @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed] @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed] diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index 99d7e38c7ed49..6f822d1c8e8ad 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -67,7 +67,7 @@ error: invalid operand for instruction @ Invalid writeback and register lists for STM stm r1, {r2, r6} stm r1!, {r2, r9} -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: stm r1, {r2, r6} @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: registers must be in range r0-r7 @@ -95,13 +95,13 @@ error: invalid operand for instruction str r2, [r7, #-1] str r5, [r1, #3] str r3, [r7, #128] -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r2, [r7, #-1] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r5, [r1, #3] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r3, [r7, #128] @ CHECK-ERRORS: ^ @@ -111,7 +111,7 @@ error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: svc #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: arm-mode @ CHECK-ERRORS: svc #256 @ CHECK-ERRORS: ^ @@ -121,15 +121,38 @@ error: invalid operand for instruction add sp, #3 add sp, sp, #512 add r2, sp, #1024 -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, #3 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, sp, #512 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: error: instruction requires: arm-mode @ CHECK-ERRORS: add r2, sp, #1024 @ CHECK-ERRORS: ^ + + add r2, sp, ip +@ CHECK-ERRORS: error: source register must be the same as destination +@ CHECK-ERRORS: add r2, sp, ip +@ CHECK-ERRORS: ^ + +@------------------------------------------------------------------------------ +@ WFE/WFI/YIELD - are not supported pre v6T2 +@------------------------------------------------------------------------------ + wfe + wfi + yield + +@ CHECK-ERRORS: error: instruction requires: thumb2 +@ CHECK-ERRORS: wfe +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires: thumb2 +@ CHECK-ERRORS: wfi +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires: thumb2 +@ CHECK-ERRORS: yield +@ CHECK-ERRORS: ^ + diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s index 625882c737fb5..2223bdcd46735 100644 --- a/test/MC/ARM/thumb.s +++ b/test/MC/ARM/thumb.s @@ -44,13 +44,6 @@ nop @ CHECK: nop @ encoding: [0xc0,0x46] - wfe - wfi - yield -@ CHECK: wfe @ encoding: [0x20,0xbf] -@ CHECK: wfi @ encoding: [0x30,0xbf] -@ CHECK: yield @ encoding: [0x10,0xbf] - cpsie aif @ CHECK: cpsie aif @ encoding: [0x67,0xb6] diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s index e38f53c6cfdc8..d94c686e2f83f 100644 --- a/test/MC/ARM/thumb2-diagnostics.s +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -40,5 +40,5 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] diff --git a/test/MC/ARM/thumb2-mclass.s b/test/MC/ARM/thumb2-mclass.s index 10460f9145096..b7af7236207d5 100644 --- a/test/MC/ARM/thumb2-mclass.s +++ b/test/MC/ARM/thumb2-mclass.s @@ -44,9 +44,21 @@ @------------------------------------------------------------------------------ msr apsr, r0 + msr apsr_nzcvq, r0 + msr apsr_g, r0 + msr apsr_nzcvqg, r0 msr iapsr, r0 + msr iapsr_nzcvq, r0 + msr iapsr_g, r0 + msr iapsr_nzcvqg, r0 msr eapsr, r0 + msr eapsr_nzcvq, r0 + msr eapsr_g, r0 + msr eapsr_nzcvqg, r0 msr xpsr, r0 + msr xpsr_nzcvq, r0 + msr xpsr_g, r0 + msr xpsr_nzcvqg, r0 msr ipsr, r0 msr epsr, r0 msr iepsr, r0 @@ -58,17 +70,29 @@ msr faultmask, r0 msr control, r0 -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80] -@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80] -@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80] -@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80] -@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80] -@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80] -@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80] -@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80] -@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80] -@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80] -@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80] +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] +@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] +@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] +@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] +@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] +@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88] +@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88] +@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88] +@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88] +@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88] +@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88] +@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88] +@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88] +@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88] +@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88] diff --git a/test/MC/ARM/thumb2-narrow-dp.ll b/test/MC/ARM/thumb2-narrow-dp.ll new file mode 100644 index 0000000000000..ae2ba355d41ff --- /dev/null +++ b/test/MC/ARM/thumb2-narrow-dp.ll @@ -0,0 +1,807 @@ +// RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s + +// Test each of the Thumb1 data-processing instructions +// The assembly syntax for these instructions allows an optional Rd register +// OP{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm> +// Assemblers should chose the narrow thumb encoding when possible, i.e. +// - Rd == Rn +// - Rd, Rn and Rm are < r8 +// In addition, some operations are commutative, allowing the transormation +// when: +// - Rd == Rn || Rd == Rm +// - Rd, Rn and Rm are < r8 + +// AND (commutative) + ANDS r0, r2, r1 // Must be wide - 3 distinct registers + ANDS r2, r2, r1 // Should choose narrow + ANDS r2, r1, r2 // Should choose narrow - commutative + ANDS.W r0, r0, r1 // Explicitly wide + ANDS.W r3, r1, r3 + AND r0, r1, r0 // Must use wide encoding as not flag-setting + ANDS r7, r7, r1 // Should use narrow + ANDS r7, r1, r7 // Commutative + ANDS r8, r1, r8 // high registers so must use wide encoding + ANDS r8, r8, r1 + ANDS r0, r8, r0 + ANDS r1, r1, r8 + ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register + ANDS r0, r1, r0, lsr #1 +// CHECK: ands.w r0, r2, r1 @ encoding: [0x12,0xea,0x01,0x00] +// CHECK: ands r2, r1 @ encoding: [0x0a,0x40] +// CHECK: ands r2, r1 @ encoding: [0x0a,0x40] +// CHECK: ands.w r0, r0, r1 @ encoding: [0x10,0xea,0x01,0x00] +// CHECK: ands.w r3, r1, r3 @ encoding: [0x11,0xea,0x03,0x03] +// CHECK: and.w r0, r1, r0 @ encoding: [0x01,0xea,0x00,0x00] +// CHECK: ands r7, r1 @ encoding: [0x0f,0x40] +// CHECK: ands r7, r1 @ encoding: [0x0f,0x40] +// CHECK: ands.w r8, r1, r8 @ encoding: [0x11,0xea,0x08,0x08] +// CHECK: ands.w r8, r8, r1 @ encoding: [0x18,0xea,0x01,0x08] +// CHECK: ands.w r0, r8, r0 @ encoding: [0x18,0xea,0x00,0x00] +// CHECK: ands.w r1, r1, r8 @ encoding: [0x11,0xea,0x08,0x01] +// CHECK: ands.w r2, r2, r1, lsl #1 @ encoding: [0x12,0xea,0x41,0x02] +// CHECK: ands.w r0, r1, r0, lsr #1 @ encoding: [0x11,0xea,0x50,0x00] + + IT EQ + ANDEQ r0, r2, r1 // Must be wide - 3 distinct registers + IT EQ + ANDEQ r3, r3, r1 // Should choose narrow + IT EQ + ANDEQ r3, r1, r3 // Should choose narrow - commutative + IT EQ + ANDEQ.W r0, r0, r1 // Explicitly wide + IT EQ + ANDEQ.W r2, r1, r2 + IT EQ + ANDSEQ r0, r1, r0 // Must use wide encoding as flag-setting + IT EQ + ANDEQ r7, r7, r1 // Should use narrow + IT EQ + ANDEQ r7, r1, r7 // Commutative + IT EQ + ANDEQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + ANDEQ r8, r8, r1 + IT EQ + ANDEQ r4, r8, r4 + IT EQ + ANDEQ r4, r4, r8 + IT EQ + ANDEQ r0, r0, r1, lsl #1 // Must use wide - shifted register + IT EQ + ANDEQ r5, r1, r5, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r0, r2, r1 @ encoding: [0x02,0xea,0x01,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq r3, r1 @ encoding: [0x0b,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq r3, r1 @ encoding: [0x0b,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r0, r0, r1 @ encoding: [0x00,0xea,0x01,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r2, r1, r2 @ encoding: [0x01,0xea,0x02,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andseq.w r0, r1, r0 @ encoding: [0x11,0xea,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq r7, r1 @ encoding: [0x0f,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq r7, r1 @ encoding: [0x0f,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r8, r1, r8 @ encoding: [0x01,0xea,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r8, r8, r1 @ encoding: [0x08,0xea,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r4, r8, r4 @ encoding: [0x08,0xea,0x04,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r4, r4, r8 @ encoding: [0x04,0xea,0x08,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r0, r0, r1, lsl #1 @ encoding: [0x00,0xea,0x41,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: andeq.w r5, r1, r5, lsr #1 @ encoding: [0x01,0xea,0x55,0x05] + +// EOR (commutative) + EORS r0, r2, r1 // Must be wide - 3 distinct registers + EORS r5, r5, r1 // Should choose narrow + EORS r5, r1, r5 // Should choose narrow - commutative + EORS.W r0, r0, r1 // Explicitly wide + EORS.W r2, r1, r2 + EOR r1, r1, r1 // Must use wide encoding as not flag-setting + EORS r7, r7, r1 // Should use narrow + EORS r7, r1, r7 // Commutative + EORS r8, r1, r8 // high registers so must use wide encoding + EORS r8, r8, r1 + EORS r6, r8, r6 + EORS r0, r0, r8 + EORS r2, r2, r1, lsl #1 // Must use wide - shifted register + EORS r0, r1, r0, lsr #1 +// CHECK: eors.w r0, r2, r1 @ encoding: [0x92,0xea,0x01,0x00] +// CHECK: eors r5, r1 @ encoding: [0x4d,0x40] +// CHECK: eors r5, r1 @ encoding: [0x4d,0x40] +// CHECK: eors.w r0, r0, r1 @ encoding: [0x90,0xea,0x01,0x00] +// CHECK: eors.w r2, r1, r2 @ encoding: [0x91,0xea,0x02,0x02] +// CHECK: eor.w r1, r1, r1 @ encoding: [0x81,0xea,0x01,0x01] +// CHECK: eors r7, r1 @ encoding: [0x4f,0x40] +// CHECK: eors r7, r1 @ encoding: [0x4f,0x40] +// CHECK: eors.w r8, r1, r8 @ encoding: [0x91,0xea,0x08,0x08] +// CHECK: eors.w r8, r8, r1 @ encoding: [0x98,0xea,0x01,0x08] +// CHECK: eors.w r6, r8, r6 @ encoding: [0x98,0xea,0x06,0x06] +// CHECK: eors.w r0, r0, r8 @ encoding: [0x90,0xea,0x08,0x00] +// CHECK: eors.w r2, r2, r1, lsl #1 @ encoding: [0x92,0xea,0x41,0x02] +// CHECK: eors.w r0, r1, r0, lsr #1 @ encoding: [0x91,0xea,0x50,0x00] + + IT EQ + EOREQ r3, r2, r1 // Must be wide - 3 distinct registers + IT EQ + EOREQ r0, r0, r1 // Should choose narrow + IT EQ + EOREQ r2, r1, r2 // Should choose narrow - commutative + IT EQ + EOREQ.W r3, r3, r1 // Explicitly wide + IT EQ + EOREQ.W r0, r1, r0 + IT EQ + EORSEQ r1, r1, r1 // Must use wide encoding as flag-setting + IT EQ + EOREQ r7, r7, r1 // Should use narrow + IT EQ + EOREQ r7, r1, r7 // Commutative + IT EQ + EOREQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + EOREQ r8, r8, r1 + IT EQ + EOREQ r0, r8, r0 + IT EQ + EOREQ r3, r3, r8 + IT EQ + EOREQ r4, r4, r1, lsl #1 // Must use wide - shifted register + IT EQ + EOREQ r0, r1, r0, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r3, r2, r1 @ encoding: [0x82,0xea,0x01,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq r0, r1 @ encoding: [0x48,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq r2, r1 @ encoding: [0x4a,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r3, r3, r1 @ encoding: [0x83,0xea,0x01,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r0, r1, r0 @ encoding: [0x81,0xea,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eorseq.w r1, r1, r1 @ encoding: [0x91,0xea,0x01,0x01] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq r7, r1 @ encoding: [0x4f,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq r7, r1 @ encoding: [0x4f,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r8, r1, r8 @ encoding: [0x81,0xea,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r8, r8, r1 @ encoding: [0x88,0xea,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r0, r8, r0 @ encoding: [0x88,0xea,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r3, r3, r8 @ encoding: [0x83,0xea,0x08,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r4, r4, r1, lsl #1 @ encoding: [0x84,0xea,0x41,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: eoreq.w r0, r1, r0, lsr #1 @ encoding: [0x81,0xea,0x50,0x00] + +// LSL + LSLS r0, r2, r1 // Must be wide - 3 distinct registers + LSLS r2, r2, r1 // Should choose narrow + LSLS r2, r1, r2 // Should choose wide - not commutative + LSLS.W r0, r0, r1 // Explicitly wide + LSLS.W r4, r1, r4 + LSL r4, r1, r4 // Must use wide encoding as not flag-setting + LSLS r7, r7, r1 // Should use narrow + LSLS r8, r1, r8 // high registers so must use wide encoding + LSLS r8, r8, r1 + LSLS r3, r8, r3 + LSLS r5, r5, r8 +// CHECK: lsls.w r0, r2, r1 @ encoding: [0x12,0xfa,0x01,0xf0] +// CHECK: lsls r2, r1 @ encoding: [0x8a,0x40] +// CHECK: lsls.w r2, r1, r2 @ encoding: [0x11,0xfa,0x02,0xf2] +// CHECK: lsls.w r0, r0, r1 @ encoding: [0x10,0xfa,0x01,0xf0] +// CHECK: lsls.w r4, r1, r4 @ encoding: [0x11,0xfa,0x04,0xf4] +// CHECK: lsl.w r4, r1, r4 @ encoding: [0x01,0xfa,0x04,0xf4] +// CHECK: lsls r7, r1 @ encoding: [0x8f,0x40] +// CHECK: lsls.w r8, r1, r8 @ encoding: [0x11,0xfa,0x08,0xf8] +// CHECK: lsls.w r8, r8, r1 @ encoding: [0x18,0xfa,0x01,0xf8] +// CHECK: lsls.w r3, r8, r3 @ encoding: [0x18,0xfa,0x03,0xf3] +// CHECK: lsls.w r5, r5, r8 @ encoding: [0x15,0xfa,0x08,0xf5] + + IT EQ + LSLEQ r0, r2, r1 // Must be wide - 3 distinct registers + IT EQ + LSLEQ r2, r2, r1 // Should choose narrow + IT EQ + LSLEQ r2, r1, r2 // Should choose wide - not commutative + IT EQ + LSLEQ.W r0, r0, r1 // Explicitly wide + IT EQ + LSLEQ.W r3, r1, r3 + IT EQ + LSLSEQ r4, r1, r4 // Must use wide encoding as flag-setting + IT EQ + LSLEQ r7, r7, r1 // Should use narrow + IT EQ + LSLEQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + LSLEQ r8, r8, r1 + IT EQ + LSLEQ r0, r8, r0 + IT EQ + LSLEQ r3, r3, r8 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r0, r2, r1 @ encoding: [0x02,0xfa,0x01,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq r2, r1 @ encoding: [0x8a,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r2, r1, r2 @ encoding: [0x01,0xfa,0x02,0xf2] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r0, r0, r1 @ encoding: [0x00,0xfa,0x01,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r3, r1, r3 @ encoding: [0x01,0xfa,0x03,0xf3] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lslseq.w r4, r1, r4 @ encoding: [0x11,0xfa,0x04,0xf4] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq r7, r1 @ encoding: [0x8f,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r8, r1, r8 @ encoding: [0x01,0xfa,0x08,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r8, r8, r1 @ encoding: [0x08,0xfa,0x01,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r0, r8, r0 @ encoding: [0x08,0xfa,0x00,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsleq.w r3, r3, r8 @ encoding: [0x03,0xfa,0x08,0xf3] + +// LSR + LSRS r6, r2, r1 // Must be wide - 3 distinct registers + LSRS r2, r2, r1 // Should choose narrow + LSRS r2, r1, r2 // Should choose wide - not commutative + LSRS.W r2, r2, r1 // Explicitly wide + LSRS.W r3, r1, r3 + LSR r4, r1, r4 // Must use wide encoding as not flag-setting + LSRS r7, r7, r1 // Should use narrow + LSRS r8, r1, r8 // high registers so must use wide encoding + LSRS r8, r8, r1 + LSRS r2, r8, r2 + LSRS r5, r5, r8 +// CHECK: lsrs.w r6, r2, r1 @ encoding: [0x32,0xfa,0x01,0xf6] +// CHECK: lsrs r2, r1 @ encoding: [0xca,0x40] +// CHECK: lsrs.w r2, r1, r2 @ encoding: [0x31,0xfa,0x02,0xf2] +// CHECK: lsrs.w r2, r2, r1 @ encoding: [0x32,0xfa,0x01,0xf2] +// CHECK: lsrs.w r3, r1, r3 @ encoding: [0x31,0xfa,0x03,0xf3] +// CHECK: lsr.w r4, r1, r4 @ encoding: [0x21,0xfa,0x04,0xf4] +// CHECK: lsrs r7, r1 @ encoding: [0xcf,0x40] +// CHECK: lsrs.w r8, r1, r8 @ encoding: [0x31,0xfa,0x08,0xf8] +// CHECK: lsrs.w r8, r8, r1 @ encoding: [0x38,0xfa,0x01,0xf8] +// CHECK: lsrs.w r2, r8, r2 @ encoding: [0x38,0xfa,0x02,0xf2] +// CHECK: lsrs.w r5, r5, r8 @ encoding: [0x35,0xfa,0x08,0xf5] + + IT EQ + LSREQ r6, r2, r1 // Must be wide - 3 distinct registers + IT EQ + LSREQ r7, r7, r1 // Should choose narrow + IT EQ + LSREQ r7, r1, r7 // Should choose wide - not commutative + IT EQ + LSREQ.W r7, r7, r1 // Explicitly wide + IT EQ + LSREQ.W r2, r1, r2 + IT EQ + LSRSEQ r0, r1, r0 // Must use wide encoding as flag-setting + IT EQ + LSREQ r7, r7, r1 // Should use narrow + IT EQ + LSREQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + LSREQ r8, r8, r1 + IT EQ + LSREQ r1, r8, r1 + IT EQ + LSREQ r4, r4, r8 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r6, r2, r1 @ encoding: [0x22,0xfa,0x01,0xf6] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq r7, r1 @ encoding: [0xcf,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r7, r1, r7 @ encoding: [0x21,0xfa,0x07,0xf7] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r7, r7, r1 @ encoding: [0x27,0xfa,0x01,0xf7] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r2, r1, r2 @ encoding: [0x21,0xfa,0x02,0xf2] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsrseq.w r0, r1, r0 @ encoding: [0x31,0xfa,0x00,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq r7, r1 @ encoding: [0xcf,0x40] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r8, r1, r8 @ encoding: [0x21,0xfa,0x08,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r8, r8, r1 @ encoding: [0x28,0xfa,0x01,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r1, r8, r1 @ encoding: [0x28,0xfa,0x01,0xf1] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: lsreq.w r4, r4, r8 @ encoding: [0x24,0xfa,0x08,0xf4] + +// ASR + ASRS r7, r6, r5 // Must be wide - 3 distinct registers + ASRS r0, r0, r1 // Should choose narrow + ASRS r0, r1, r0 // Should choose wide - not commutative + ASRS.W r3, r3, r1 // Explicitly wide + ASRS.W r1, r1, r1 + ASR r0, r1, r0 // Must use wide encoding as not flag-setting + ASRS r7, r7, r1 // Should use narrow + ASRS r8, r1, r8 // high registers so must use wide encoding + ASRS r8, r8, r1 + ASRS r5, r8, r5 + ASRS r5, r5, r8 +// CHECK: asrs.w r7, r6, r5 @ encoding: [0x56,0xfa,0x05,0xf7] +// CHECK: asrs r0, r1 @ encoding: [0x08,0x41] +// CHECK: asrs.w r0, r1, r0 @ encoding: [0x51,0xfa,0x00,0xf0] +// CHECK: asrs.w r3, r3, r1 @ encoding: [0x53,0xfa,0x01,0xf3] +// CHECK: asrs.w r1, r1, r1 @ encoding: [0x51,0xfa,0x01,0xf1] +// CHECK: asr.w r0, r1, r0 @ encoding: [0x41,0xfa,0x00,0xf0] +// CHECK: asrs r7, r1 @ encoding: [0x0f,0x41] +// CHECK: asrs.w r8, r1, r8 @ encoding: [0x51,0xfa,0x08,0xf8] +// CHECK: asrs.w r8, r8, r1 @ encoding: [0x58,0xfa,0x01,0xf8] +// CHECK: asrs.w r5, r8, r5 @ encoding: [0x58,0xfa,0x05,0xf5] +// CHECK: asrs.w r5, r5, r8 @ encoding: [0x55,0xfa,0x08,0xf5] + + IT EQ + ASREQ r0, r2, r1 // Must be wide - 3 distinct registers + IT EQ + ASREQ r2, r2, r1 // Should choose narrow + IT EQ + ASREQ r1, r2, r1 // Should choose wide - not commutative + IT EQ + ASREQ.W r4, r4, r1 // Explicitly wide + IT EQ + ASREQ.W r6, r1, r6 + IT EQ + ASRSEQ r3, r1, r3 // Must use wide encoding as flag-setting + IT EQ + ASREQ r7, r7, r1 // Should use narrow + IT EQ + ASREQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + ASREQ r8, r8, r1 + IT EQ + ASREQ r1, r8, r1 + IT EQ + ASREQ r3, r3, r8 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r0, r2, r1 @ encoding: [0x42,0xfa,0x01,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq r2, r1 @ encoding: [0x0a,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r1, r2, r1 @ encoding: [0x42,0xfa,0x01,0xf1] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r4, r4, r1 @ encoding: [0x44,0xfa,0x01,0xf4] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r6, r1, r6 @ encoding: [0x41,0xfa,0x06,0xf6] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asrseq.w r3, r1, r3 @ encoding: [0x51,0xfa,0x03,0xf3] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq r7, r1 @ encoding: [0x0f,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r8, r1, r8 @ encoding: [0x41,0xfa,0x08,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r8, r8, r1 @ encoding: [0x48,0xfa,0x01,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r1, r8, r1 @ encoding: [0x48,0xfa,0x01,0xf1] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: asreq.w r3, r3, r8 @ encoding: [0x43,0xfa,0x08,0xf3] + +// ADC (commutative) + ADCS r5, r2, r1 // Must be wide - 3 distinct registers + ADCS r5, r5, r1 // Should choose narrow + ADCS r3, r1, r3 // Should choose narrow - commutative + ADCS.W r2, r2, r1 // Explicitly wide + ADCS.W r3, r1, r3 + ADC r0, r1, r0 // Must use wide encoding as not flag-setting + ADCS r7, r7, r1 // Should use narrow + ADCS r7, r1, r7 // Commutative + ADCS r8, r1, r8 // high registers so must use wide encoding + ADCS r8, r8, r1 + ADCS r5, r8, r5 + ADCS r2, r2, r8 + ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register + ADCS r4, r1, r4, lsr #1 +// CHECK: adcs.w r5, r2, r1 @ encoding: [0x52,0xeb,0x01,0x05] +// CHECK: adcs r5, r1 @ encoding: [0x4d,0x41] +// CHECK: adcs r3, r1 @ encoding: [0x4b,0x41] +// CHECK: adcs.w r2, r2, r1 @ encoding: [0x52,0xeb,0x01,0x02] +// CHECK: adcs.w r3, r1, r3 @ encoding: [0x51,0xeb,0x03,0x03] +// CHECK: adc.w r0, r1, r0 @ encoding: [0x41,0xeb,0x00,0x00] +// CHECK: adcs r7, r1 @ encoding: [0x4f,0x41] +// CHECK: adcs r7, r1 @ encoding: [0x4f,0x41] +// CHECK: adcs.w r8, r1, r8 @ encoding: [0x51,0xeb,0x08,0x08] +// CHECK: adcs.w r8, r8, r1 @ encoding: [0x58,0xeb,0x01,0x08] +// CHECK: adcs.w r5, r8, r5 @ encoding: [0x58,0xeb,0x05,0x05] +// CHECK: adcs.w r2, r2, r8 @ encoding: [0x52,0xeb,0x08,0x02] +// CHECK: adcs.w r3, r3, r1, lsl #1 @ encoding: [0x53,0xeb,0x41,0x03] +// CHECK: adcs.w r4, r1, r4, lsr #1 @ encoding: [0x51,0xeb,0x54,0x04] + + IT EQ + ADCEQ r1, r2, r3 // Must be wide - 3 distinct registers + IT EQ + ADCEQ r1, r1, r1 // Should choose narrow + IT EQ + ADCEQ r3, r1, r3 // Should choose narrow - commutative + IT EQ + ADCEQ.W r3, r3, r1 // Explicitly wide + IT EQ + ADCEQ.W r0, r1, r0 + IT EQ + ADCSEQ r3, r1, r3 // Must use wide encoding as flag-setting + IT EQ + ADCEQ r7, r7, r1 // Should use narrow + IT EQ + ADCEQ r7, r1, r7 // Commutative + IT EQ + ADCEQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + ADCEQ r8, r8, r1 + IT EQ + ADCEQ r3, r8, r3 + IT EQ + ADCEQ r1, r1, r8 + IT EQ + ADCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register + IT EQ + ADCEQ r1, r1, r1, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r1, r2, r3 @ encoding: [0x42,0xeb,0x03,0x01] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq r1, r1 @ encoding: [0x49,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq r3, r1 @ encoding: [0x4b,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r3, r3, r1 @ encoding: [0x43,0xeb,0x01,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r0, r1, r0 @ encoding: [0x41,0xeb,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adcseq.w r3, r1, r3 @ encoding: [0x51,0xeb,0x03,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq r7, r1 @ encoding: [0x4f,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq r7, r1 @ encoding: [0x4f,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r8, r1, r8 @ encoding: [0x41,0xeb,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r8, r8, r1 @ encoding: [0x48,0xeb,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r3, r8, r3 @ encoding: [0x48,0xeb,0x03,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r1, r1, r8 @ encoding: [0x41,0xeb,0x08,0x01] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r2, r2, r1, lsl #1 @ encoding: [0x42,0xeb,0x41,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: adceq.w r1, r1, r1, lsr #1 @ encoding: [0x41,0xeb,0x51,0x01] + +// SBC + SBCS r3, r2, r1 // Must be wide - 3 distinct registers + SBCS r4, r4, r1 // Should choose narrow + SBCS r1, r4, r1 // Should choose wide - not commutative + SBCS.W r4, r4, r1 // Explicitly wide + SBCS.W r2, r1, r2 + SBC r0, r1, r0 // Must use wide encoding as not flag-setting + SBCS r7, r7, r1 // Should use narrow + SBCS r8, r1, r8 // high registers so must use wide encoding + SBCS r8, r8, r1 + SBCS r4, r8, r4 + SBCS r3, r3, r8 + SBCS r2, r2, r1, lsl #1 // Must use wide - shifted register + SBCS r5, r1, r5, lsr #1 +// CHECK: sbcs.w r3, r2, r1 @ encoding: [0x72,0xeb,0x01,0x03] +// CHECK: sbcs r4, r1 @ encoding: [0x8c,0x41] +// CHECK: sbcs.w r1, r4, r1 @ encoding: [0x74,0xeb,0x01,0x01] +// CHECK: sbcs.w r4, r4, r1 @ encoding: [0x74,0xeb,0x01,0x04] +// CHECK: sbcs.w r2, r1, r2 @ encoding: [0x71,0xeb,0x02,0x02] +// CHECK: sbc.w r0, r1, r0 @ encoding: [0x61,0xeb,0x00,0x00] +// CHECK: sbcs r7, r1 @ encoding: [0x8f,0x41] +// CHECK: sbcs.w r8, r1, r8 @ encoding: [0x71,0xeb,0x08,0x08] +// CHECK: sbcs.w r8, r8, r1 @ encoding: [0x78,0xeb,0x01,0x08] +// CHECK: sbcs.w r4, r8, r4 @ encoding: [0x78,0xeb,0x04,0x04] +// CHECK: sbcs.w r3, r3, r8 @ encoding: [0x73,0xeb,0x08,0x03] +// CHECK: sbcs.w r2, r2, r1, lsl #1 @ encoding: [0x72,0xeb,0x41,0x02] +// CHECK: sbcs.w r5, r1, r5, lsr #1 @ encoding: [0x71,0xeb,0x55,0x05] + + IT EQ + SBCEQ r5, r2, r1 // Must be wide - 3 distinct registers + IT EQ + SBCEQ r5, r5, r1 // Should choose narrow + IT EQ + SBCEQ r1, r5, r1 // Should choose narrow + IT EQ + SBCEQ.W r5, r5, r1 // Explicitly wide + IT EQ + SBCEQ.W r0, r1, r0 + IT EQ + SBCSEQ r2, r1, r2 // Must use wide encoding as flag-setting + IT EQ + SBCEQ r7, r7, r1 // Should use narrow + IT EQ + SBCEQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + SBCEQ r8, r8, r1 + IT EQ + SBCEQ r7, r8, r7 + IT EQ + SBCEQ r7, r7, r8 + IT EQ + SBCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register + IT EQ + SBCEQ r5, r1, r5, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r5, r2, r1 @ encoding: [0x62,0xeb,0x01,0x05] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq r5, r1 @ encoding: [0x8d,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r1, r5, r1 @ encoding: [0x65,0xeb,0x01,0x01] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r5, r5, r1 @ encoding: [0x65,0xeb,0x01,0x05] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r0, r1, r0 @ encoding: [0x61,0xeb,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbcseq.w r2, r1, r2 @ encoding: [0x71,0xeb,0x02,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq r7, r1 @ encoding: [0x8f,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r8, r1, r8 @ encoding: [0x61,0xeb,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r8, r8, r1 @ encoding: [0x68,0xeb,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r7, r8, r7 @ encoding: [0x68,0xeb,0x07,0x07] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r7, r7, r8 @ encoding: [0x67,0xeb,0x08,0x07] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r2, r2, r1, lsl #1 @ encoding: [0x62,0xeb,0x41,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: sbceq.w r5, r1, r5, lsr #1 @ encoding: [0x61,0xeb,0x55,0x05] + +// ROR + RORS r3, r2, r1 // Must be wide - 3 distinct registers + RORS r0, r0, r1 // Should choose narrow + RORS r1, r0, r1 // Should choose wide - not commutative + RORS.W r2, r2, r1 // Explicitly wide + RORS.W r2, r1, r2 + ROR r5, r1, r5 // Must use wide encoding as not flag-setting + RORS r7, r7, r1 // Should use narrow + RORS r8, r1, r8 // high registers so must use wide encoding + RORS r8, r8, r1 + RORS r6, r8, r6 + RORS r6, r6, r8 +// CHECK: rors.w r3, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf3] +// CHECK: rors r0, r1 @ encoding: [0xc8,0x41] +// CHECK: rors.w r1, r0, r1 @ encoding: [0x70,0xfa,0x01,0xf1] +// CHECK: rors.w r2, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf2] +// CHECK: rors.w r2, r1, r2 @ encoding: [0x71,0xfa,0x02,0xf2] +// CHECK: ror.w r5, r1, r5 @ encoding: [0x61,0xfa,0x05,0xf5] +// CHECK: rors r7, r1 @ encoding: [0xcf,0x41] +// CHECK: rors.w r8, r1, r8 @ encoding: [0x71,0xfa,0x08,0xf8] +// CHECK: rors.w r8, r8, r1 @ encoding: [0x78,0xfa,0x01,0xf8] +// CHECK: rors.w r6, r8, r6 @ encoding: [0x78,0xfa,0x06,0xf6] +// CHECK: rors.w r6, r6, r8 @ encoding: [0x76,0xfa,0x08,0xf6] + + IT EQ + ROREQ r4, r2, r1 // Must be wide - 3 distinct registers + IT EQ + ROREQ r4, r4, r1 // Should choose narrow + IT EQ + ROREQ r1, r4, r1 // Should choose wide - not commutative + IT EQ + ROREQ.W r4, r4, r1 // Explicitly wide + IT EQ + ROREQ.W r0, r1, r0 + IT EQ + RORSEQ r0, r1, r0 // Must use wide encoding as flag-setting + IT EQ + ROREQ r7, r7, r1 // Should use narrow + IT EQ + ROREQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + ROREQ r8, r8, r1 + IT EQ + ROREQ r3, r8, r3 + IT EQ + ROREQ r1, r1, r8 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r4, r2, r1 @ encoding: [0x62,0xfa,0x01,0xf4] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq r4, r1 @ encoding: [0xcc,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r1, r4, r1 @ encoding: [0x64,0xfa,0x01,0xf1] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r4, r4, r1 @ encoding: [0x64,0xfa,0x01,0xf4] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r0, r1, r0 @ encoding: [0x61,0xfa,0x00,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: rorseq.w r0, r1, r0 @ encoding: [0x71,0xfa,0x00,0xf0] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq r7, r1 @ encoding: [0xcf,0x41] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r8, r1, r8 @ encoding: [0x61,0xfa,0x08,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r8, r8, r1 @ encoding: [0x68,0xfa,0x01,0xf8] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r3, r8, r3 @ encoding: [0x68,0xfa,0x03,0xf3] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: roreq.w r1, r1, r8 @ encoding: [0x61,0xfa,0x08,0xf1] + +// TST - only two register version available +// RSB - only two register version available +// CMP - only two register version available +// CMN - only two register version available + +// ORR (commutative) + ORRS r7, r2, r1 // Must be wide - 3 distinct registers + ORRS r2, r2, r1 // Should choose narrow + ORRS r3, r1, r3 // Should choose narrow - commutative + ORRS.W r4, r4, r1 // Explicitly wide + ORRS.W r5, r1, r5 + ORR r2, r1, r2 // Must use wide encoding as not flag-setting + ORRS r7, r7, r1 // Should use narrow + ORRS r7, r1, r7 // Commutative + ORRS r8, r1, r8 // high registers so must use wide encoding + ORRS r8, r8, r1 + ORRS r1, r8, r1 + ORRS r0, r0, r8 + ORRS r1, r1, r1, lsl #1 // Must use wide - shifted register + ORRS r0, r1, r0, lsr #1 +// CHECK: orrs.w r7, r2, r1 @ encoding: [0x52,0xea,0x01,0x07] +// CHECK: orrs r2, r1 @ encoding: [0x0a,0x43] +// CHECK: orrs r3, r1 @ encoding: [0x0b,0x43] +// CHECK: orrs.w r4, r4, r1 @ encoding: [0x54,0xea,0x01,0x04] +// CHECK: orrs.w r5, r1, r5 @ encoding: [0x51,0xea,0x05,0x05] +// CHECK: orr.w r2, r1, r2 @ encoding: [0x41,0xea,0x02,0x02] +// CHECK: orrs r7, r1 @ encoding: [0x0f,0x43] +// CHECK: orrs r7, r1 @ encoding: [0x0f,0x43] +// CHECK: orrs.w r8, r1, r8 @ encoding: [0x51,0xea,0x08,0x08] +// CHECK: orrs.w r8, r8, r1 @ encoding: [0x58,0xea,0x01,0x08] +// CHECK: orrs.w r1, r8, r1 @ encoding: [0x58,0xea,0x01,0x01] +// CHECK: orrs.w r0, r0, r8 @ encoding: [0x50,0xea,0x08,0x00] +// CHECK: orrs.w r1, r1, r1, lsl #1 @ encoding: [0x51,0xea,0x41,0x01] +// CHECK: orrs.w r0, r1, r0, lsr #1 @ encoding: [0x51,0xea,0x50,0x00] + + IT EQ + ORREQ r0, r2, r1 // Must be wide - 3 distinct registers + IT EQ + ORREQ r5, r5, r1 // Should choose narrow + IT EQ + ORREQ r5, r1, r5 // Should choose narrow - commutative + IT EQ + ORREQ.W r2, r2, r1 // Explicitly wide + IT EQ + ORREQ.W r3, r1, r3 + IT EQ + ORRSEQ r4, r1, r4 // Must use wide encoding as flag-setting + IT EQ + ORREQ r7, r7, r1 // Should use narrow + IT EQ + ORREQ r7, r1, r7 // Commutative + IT EQ + ORREQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + ORREQ r8, r8, r1 + IT EQ + ORREQ r0, r8, r0 + IT EQ + ORREQ r0, r0, r8 + IT EQ + ORREQ r2, r2, r1, lsl #1 // Must use wide - shifted register + IT EQ + ORREQ r2, r1, r2, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r0, r2, r1 @ encoding: [0x42,0xea,0x01,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq r5, r1 @ encoding: [0x0d,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq r5, r1 @ encoding: [0x0d,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r2, r2, r1 @ encoding: [0x42,0xea,0x01,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r3, r1, r3 @ encoding: [0x41,0xea,0x03,0x03] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orrseq.w r4, r1, r4 @ encoding: [0x51,0xea,0x04,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq r7, r1 @ encoding: [0x0f,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq r7, r1 @ encoding: [0x0f,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r8, r1, r8 @ encoding: [0x41,0xea,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r8, r8, r1 @ encoding: [0x48,0xea,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r0, r8, r0 @ encoding: [0x48,0xea,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r0, r0, r8 @ encoding: [0x40,0xea,0x08,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r2, r2, r1, lsl #1 @ encoding: [0x42,0xea,0x41,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: orreq.w r2, r1, r2, lsr #1 @ encoding: [0x41,0xea,0x52,0x02] + +// MUL - not affected by this change + +// BIC + BICS r3, r2, r1 // Must be wide - 3 distinct registers + BICS r2, r2, r1 // Should choose narrow + BICS r1, r2, r1 // Should choose wide - not commutative + BICS.W r2, r2, r1 // Explicitly wide + BICS.W r0, r1, r0 + BIC r0, r1, r0 // Must use wide encoding as not flag-setting + BICS r7, r7, r1 // Should use narrow + BICS r8, r1, r8 // high registers so must use wide encoding + BICS r8, r8, r1 + BICS r7, r8, r7 + BICS r5, r5, r8 + BICS r3, r3, r1, lsl #1 // Must use wide - shifted register + BICS r4, r1, r4, lsr #1 +// CHECK: bics.w r3, r2, r1 @ encoding: [0x32,0xea,0x01,0x03] +// CHECK: bics r2, r1 @ encoding: [0x8a,0x43] +// CHECK: bics.w r1, r2, r1 @ encoding: [0x32,0xea,0x01,0x01] +// CHECK: bics.w r2, r2, r1 @ encoding: [0x32,0xea,0x01,0x02] +// CHECK: bics.w r0, r1, r0 @ encoding: [0x31,0xea,0x00,0x00] +// CHECK: bic.w r0, r1, r0 @ encoding: [0x21,0xea,0x00,0x00] +// CHECK: bics r7, r1 @ encoding: [0x8f,0x43] +// CHECK: bics.w r8, r1, r8 @ encoding: [0x31,0xea,0x08,0x08] +// CHECK: bics.w r8, r8, r1 @ encoding: [0x38,0xea,0x01,0x08] +// CHECK: bics.w r7, r8, r7 @ encoding: [0x38,0xea,0x07,0x07] +// CHECK: bics.w r5, r5, r8 @ encoding: [0x35,0xea,0x08,0x05] +// CHECK: bics.w r3, r3, r1, lsl #1 @ encoding: [0x33,0xea,0x41,0x03] +// CHECK: bics.w r4, r1, r4, lsr #1 @ encoding: [0x31,0xea,0x54,0x04] + + IT EQ + BICEQ r0, r2, r1 // Must be wide - 3 distinct registers + IT EQ + BICEQ r5, r5, r1 // Should choose narrow + IT EQ + BICEQ r1, r5, r1 // Should choose wide - not commutative + IT EQ + BICEQ.W r4, r4, r1 // Explicitly wide + IT EQ + BICEQ.W r2, r1, r2 + IT EQ + BICSEQ r5, r1, r5 // Must use wide encoding as flag-setting + IT EQ + BICEQ r7, r7, r1 // Should use narrow + IT EQ + BICEQ r8, r1, r8 // high registers so must use wide encoding + IT EQ + BICEQ r8, r8, r1 + IT EQ + BICEQ r0, r8, r0 + IT EQ + BICEQ r2, r2, r8 + IT EQ + BICEQ r4, r4, r1, lsl #1 // Must use wide - shifted register + IT EQ + BICEQ r5, r1, r5, lsr #1 +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r0, r2, r1 @ encoding: [0x22,0xea,0x01,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq r5, r1 @ encoding: [0x8d,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r1, r5, r1 @ encoding: [0x25,0xea,0x01,0x01] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r4, r4, r1 @ encoding: [0x24,0xea,0x01,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r2, r1, r2 @ encoding: [0x21,0xea,0x02,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: bicseq.w r5, r1, r5 @ encoding: [0x31,0xea,0x05,0x05] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq r7, r1 @ encoding: [0x8f,0x43] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r8, r1, r8 @ encoding: [0x21,0xea,0x08,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r8, r8, r1 @ encoding: [0x28,0xea,0x01,0x08] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r0, r8, r0 @ encoding: [0x28,0xea,0x00,0x00] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r2, r2, r8 @ encoding: [0x22,0xea,0x08,0x02] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r4, r4, r1, lsl #1 @ encoding: [0x24,0xea,0x41,0x04] +// CHECK: it eq @ encoding: [0x08,0xbf] +// CHECK: biceq.w r5, r1, r5, lsr #1 @ encoding: [0x21,0xea,0x55,0x05] + +// CMN - only two register version available diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s index cc87a38112ba5..0a1fe92abd87d 100644 --- a/test/MC/ARM/vfp4.s +++ b/test/MC/ARM/vfp4.s @@ -1,5 +1,6 @@ @ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM @ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB +@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 | FileCheck %s --check-prefix=THUMB_V7EM @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] @@ -7,6 +8,7 @@ vfma.f64 d16, d18, d17 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee] @ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] +@ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] vfma.f32 s2, s4, s0 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @@ -23,6 +25,7 @@ vfnma.f64 d16, d18, d17 @ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee] @ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] +@ THUMB_V7EM: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] vfnma.f32 s2, s4, s0 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @@ -31,6 +34,7 @@ vfms.f64 d16, d18, d17 @ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee] @ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] +@ THUMB_V7EM: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] vfms.f32 s2, s4, s0 @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] diff --git a/test/MC/ARM/vpush-vpop.s b/test/MC/ARM/vpush-vpop.s index 4fb4decd11e24..31f55244b6fa5 100644 --- a/test/MC/ARM/vpush-vpop.s +++ b/test/MC/ARM/vpush-vpop.s @@ -1,5 +1,5 @@ -@ RUN: llvm-mc -triple armv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-ARM %s -@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-THUMB %s +@ RUN: llvm-mc -triple armv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck --check-prefix=CHECK-ARM %s +@ RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a8 -show-encoding < %s | FileCheck --check-prefix=CHECK-THUMB %s foo: @ CHECK: foo diff --git a/test/MC/AsmParser/extern.s b/test/MC/AsmParser/extern.s new file mode 100644 index 0000000000000..461f843c69286 --- /dev/null +++ b/test/MC/AsmParser/extern.s @@ -0,0 +1,4 @@ +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s + +# CHECK-NOT: foo +.extern foo diff --git a/test/MC/AsmParser/ifb.s b/test/MC/AsmParser/ifb.s new file mode 100644 index 0000000000000..48d69f4fc2b3e --- /dev/null +++ b/test/MC/AsmParser/ifb.s @@ -0,0 +1,67 @@ +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s + +defined: + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifb + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifb defined + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifb undefined + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifb "" + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnb + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnb defined + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnb undefined + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnb "" + .byte 1 +.else + .byte 0 +.endif diff --git a/test/MC/AsmParser/ifc.s b/test/MC/AsmParser/ifc.s new file mode 100644 index 0000000000000..20e55c0a24fc2 --- /dev/null +++ b/test/MC/AsmParser/ifc.s @@ -0,0 +1,65 @@ +# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifc foo, foo + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifc "foo space", "foo space" + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifc foo space, foo space + .byte 1 +.else + .byte 0 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifc unequal, unEqual + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnc foo, foo + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnc "foo space", "foo space" + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnc foo space, foo space + .byte 0 +.else + .byte 1 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +.ifnc unequal, unEqual + .byte 1 +.else + .byte 0 +.endif diff --git a/test/MC/AsmParser/macro-args.s b/test/MC/AsmParser/macro-args.s index 13b197a55a819..6d084213e40b6 100644 --- a/test/MC/AsmParser/macro-args.s +++ b/test/MC/AsmParser/macro-args.s @@ -42,3 +42,15 @@ top bar, 42 // CHECK-NOT: fred // CHECK: _bar // CHECK-NEXT: fred = 42 + + +.macro foo +foo_$0_$1_$2_$3: + nop +.endm + +foo 1, 2, 3, 4 +foo 1, , 3, 4 + +// CHECK: foo_1_2_3_4: +// CHECK: foo_1__3_4: diff --git a/test/MC/AsmParser/macro-err1.s b/test/MC/AsmParser/macro-err1.s new file mode 100644 index 0000000000000..924deb0cf6e16 --- /dev/null +++ b/test/MC/AsmParser/macro-err1.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t +// RUN: FileCheck < %t %s + +.macro foo bar + .long \bar +.endm + +foo 42, 42 + +// CHECK: Too many arguments diff --git a/test/MC/AsmParser/macro-irp.s b/test/MC/AsmParser/macro-irp.s new file mode 100644 index 0000000000000..a368b7446dc0f --- /dev/null +++ b/test/MC/AsmParser/macro-irp.s @@ -0,0 +1,8 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s + +.irp reg,%eax,%ebx + pushl \reg +.endr + +// CHECK: pushl %eax +// CHECK: pushl %ebx diff --git a/test/MC/AsmParser/macro-irpc.s b/test/MC/AsmParser/macro-irpc.s new file mode 100644 index 0000000000000..ea5efbfb2452f --- /dev/null +++ b/test/MC/AsmParser/macro-irpc.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s + +.irpc foo,123 + .long \foo +.endr + +// CHECK: long 1 +// CHECK: long 2 +// CHECK: long 3 diff --git a/test/MC/AsmParser/macro-rept-err1.s b/test/MC/AsmParser/macro-rept-err1.s new file mode 100644 index 0000000000000..db92856a1d6d2 --- /dev/null +++ b/test/MC/AsmParser/macro-rept-err1.s @@ -0,0 +1,6 @@ +// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t +// RUN: FileCheck < %t %s + +.endr + +// CHECK: unexpected '.endr' directive, no current .rept diff --git a/test/MC/AsmParser/macro-rept-err2.s b/test/MC/AsmParser/macro-rept-err2.s new file mode 100644 index 0000000000000..678b4c7eeee02 --- /dev/null +++ b/test/MC/AsmParser/macro-rept-err2.s @@ -0,0 +1,7 @@ +// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t +// RUN: FileCheck < %t %s + +.rept 3 +.long + +// CHECK: no matching '.endr' in definition diff --git a/test/MC/AsmParser/macro-rept.s b/test/MC/AsmParser/macro-rept.s new file mode 100644 index 0000000000000..1dc8060e1d871 --- /dev/null +++ b/test/MC/AsmParser/macro-rept.s @@ -0,0 +1,22 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s + +.rept 2 + .long 1 +.endr + +.rept 3 +.rept 2 + .long 0 +.endr +.endr + +// CHECK: .long 1 +// CHECK: .long 1 + +// CHECK: .long 0 +// CHECK: .long 0 +// CHECK: .long 0 + +// CHECK: .long 0 +// CHECK: .long 0 +// CHECK: .long 0 diff --git a/test/MC/AsmParser/macros-parsing.s b/test/MC/AsmParser/macros-parsing.s index 65f64546cc130..75aaac036ed10 100644 --- a/test/MC/AsmParser/macros-parsing.s +++ b/test/MC/AsmParser/macros-parsing.s @@ -5,7 +5,7 @@ .endmacro .macros_off -// CHECK-ERRORS: 9:1: warning: ignoring directive for now +// CHECK-ERRORS: 9:1: error: unknown directive .test0 .macros_on diff --git a/test/MC/AsmParser/macros.s b/test/MC/AsmParser/macros.s index 214274d9aa845..2957592992389 100644 --- a/test/MC/AsmParser/macros.s +++ b/test/MC/AsmParser/macros.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err | FileCheck %s +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err .macro .test0 @@ -9,7 +9,7 @@ .endmacro .test1 -// CHECK-ERRORS: <instantiation>:1:1: warning: ignoring directive for now +// CHECK-ERRORS: <instantiation>:1:1: error: unknown directive // CHECK-ERRORS-NEXT: macrobody0 // CHECK-ERRORS-NEXT: ^ // CHECK-ERRORS: <instantiation>:1:1: note: while in macro instantiation diff --git a/test/MC/AsmParser/purgem.s b/test/MC/AsmParser/purgem.s new file mode 100644 index 0000000000000..c76c1c6d27db8 --- /dev/null +++ b/test/MC/AsmParser/purgem.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc -triple i386-unknown-unknown %s 2>&1 | FileCheck %s + +.macro foo +.err +.endm + +.purgem bar +# CHECK: error: macro 'bar' is not defined + +.purgem foo +foo +# CHECK: error: invalid instruction mnemonic 'foo' diff --git a/test/MC/COFF/seh.s b/test/MC/COFF/seh.s index 8cafcb3ab15fa..3f728056005b7 100644 --- a/test/MC/COFF/seh.s +++ b/test/MC/COFF/seh.s @@ -14,7 +14,6 @@ // CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA // CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES // CHECK-NEXT: IMAGE_SCN_MEM_READ -// CHECK-NEXT: IMAGE_SCN_MEM_WRITE // CHECK-NEXT: SectionData // CHECK-NEXT: 09 12 08 03 00 03 0F 30 - 0E 88 00 00 09 64 02 00 // CHECK-NEXT: 04 22 00 1A 00 00 00 00 - 00 00 00 00 21 00 00 00 diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 471076a19bd77..0c9aaab38c7e4 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: addpl r4, pc, #318767104 0x4c 0x45 0x8f 0x52 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index fc7eda537aba2..1100ce64a947b 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -169,9 +169,15 @@ #------------------------------------------------------------------------------ # CHECK: add r2, pc, #3 # CHECK: sub r2, pc, #3 +# CHECK: sub r1, pc, #0 +# CHECK: sub r1, pc, #301989888 +# CHECK: add r1, pc, #301989888 0x03 0x20 0x8f 0xe2 0x03 0x20 0x4f 0xe2 +0x00 0x10 0x4f 0xe2 +0x12 0x14 0x4f 0xe2 +0x12 0x14 0x8f 0xe2 #------------------------------------------------------------------------------ # AND @@ -469,47 +475,77 @@ #------------------------------------------------------------------------------ # DMB #------------------------------------------------------------------------------ -# CHECK: dmb sy -# CHECK: dmb st -# CHECK: dmb ish -# CHECK: dmb ishst -# CHECK: dmb nsh -# CHECK: dmb nshst -# CHECK: dmb osh + +# CHECK: dmb #0x0 +# CHECK: dmb #0x1 # CHECK: dmb oshst -# CHECK: dmb +# CHECK: dmb osh +# CHECK: dmb #0x4 +# CHECK: dmb #0x5 +# CHECK: dmb nshst +# CHECK: dmb nsh +# CHECK: dmb #0x8 +# CHECK: dmb #0x9 +# CHECK: dmb ishst +# CHECK: dmb ish +# CHECK: dmb #0xc +# CHECK: dmb #0xd +# CHECK: dmb st +# CHECK: dmb sy -0x5f 0xf0 0x7f 0xf5 -0x5e 0xf0 0x7f 0xf5 -0x5b 0xf0 0x7f 0xf5 -0x5a 0xf0 0x7f 0xf5 -0x57 0xf0 0x7f 0xf5 -0x56 0xf0 0x7f 0xf5 -0x53 0xf0 0x7f 0xf5 +0x50 0xf0 0x7f 0xf5 +0x51 0xf0 0x7f 0xf5 0x52 0xf0 0x7f 0xf5 +0x53 0xf0 0x7f 0xf5 +0x54 0xf0 0x7f 0xf5 +0x55 0xf0 0x7f 0xf5 +0x56 0xf0 0x7f 0xf5 +0x57 0xf0 0x7f 0xf5 +0x58 0xf0 0x7f 0xf5 +0x59 0xf0 0x7f 0xf5 +0x5a 0xf0 0x7f 0xf5 +0x5b 0xf0 0x7f 0xf5 +0x5c 0xf0 0x7f 0xf5 +0x5d 0xf0 0x7f 0xf5 +0x5e 0xf0 0x7f 0xf5 0x5f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ # DSB #------------------------------------------------------------------------------ -# CHECK: dsb sy -# CHECK: dsb st -# CHECK: dsb ish -# CHECK: dsb ishst -# CHECK: dsb nsh -# CHECK: dsb nshst -# CHECK: dsb osh -# CHECK: dsb oshst -# CHECK: dsb -0x4f 0xf0 0x7f 0xf5 -0x4e 0xf0 0x7f 0xf5 -0x4b 0xf0 0x7f 0xf5 -0x4a 0xf0 0x7f 0xf5 -0x47 0xf0 0x7f 0xf5 -0x46 0xf0 0x7f 0xf5 -0x43 0xf0 0x7f 0xf5 +# CHECK: dsb #0x0 +# CHECK: dsb #0x1 +# CHECK: dsb oshst +# CHECK: dsb osh +# CHECK: dsb #0x4 +# CHECK: dsb #0x5 +# CHECK: dsb nshst +# CHECK: dsb nsh +# CHECK: dsb #0x8 +# CHECK: dsb #0x9 +# CHECK: dsb ishst +# CHECK: dsb ish +# CHECK: dsb #0xc +# CHECK: dsb #0xd +# CHECK: dsb st +# CHECK: dsb sy + +0x40 0xf0 0x7f 0xf5 +0x41 0xf0 0x7f 0xf5 0x42 0xf0 0x7f 0xf5 +0x43 0xf0 0x7f 0xf5 +0x44 0xf0 0x7f 0xf5 +0x45 0xf0 0x7f 0xf5 +0x46 0xf0 0x7f 0xf5 +0x47 0xf0 0x7f 0xf5 +0x48 0xf0 0x7f 0xf5 +0x49 0xf0 0x7f 0xf5 +0x4a 0xf0 0x7f 0xf5 +0x4b 0xf0 0x7f 0xf5 +0x4c 0xf0 0x7f 0xf5 +0x4d 0xf0 0x7f 0xf5 +0x4e 0xf0 0x7f 0xf5 0x4f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt index 9095b84ce18b9..8dedf808c180d 100644 --- a/test/MC/Disassembler/ARM/fp-encoding.txt +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s 0xa0 0x0b 0x71 0xee # CHECK: vadd.f64 d16, d17, d16 @@ -203,6 +203,33 @@ # CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} # CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} +0x05 0x9a 0xc0 0x0c +0x0c 0x0b 0xc7 0x0c +0x06 0x9a 0x93 0x0c +0x0a 0x5b 0xd2 0x0c +# CHECK: vstmiaeq r0, {s19, s20, s21, s22, s23} +# CHECK: vstmiaeq r7, {d16, d17, d18, d19, d20, d21} +# CHECK: vldmiaeq r3, {s18, s19, s20, s21, s22, s23} +# CHECK: vldmiaeq r2, {d21, d22, d23, d24, d25} + +0x04 0xca 0x6c 0x0d +0x06 0x1b 0x69 0x0d +0x03 0xaa 0x75 0x0d +0x08 0xeb 0x37 0x0d +# CHECK: vstmdbeq r12!, {s25, s26, s27, s28} +# CHECK: vstmdbeq r9!, {d17, d18, d19} +# CHECK: vldmdbeq r5!, {s21, s22, s23} +# CHECK: vldmdbeq r7!, {d14, d15, d16, d17} + +0x04 0x7a 0xa6 0x0c +0x0c 0xfb 0xa4 0x0c +0x03 0xaa 0xf8 0x0c +0x0a 0x3b 0xfb 0x0c +# CHECK: vstmiaeq r6!, {s14, s15, s16, s17} +# CHECK: vstmiaeq r4!, {d15, d16, d17, d18, d19, d20} +# CHECK: vldmiaeq r8!, {s21, s22, s23} +# CHECK: vldmiaeq r11!, {d19, d20, d21, d22, d23} + 0x40 0x0b 0xbd 0xee 0x60 0x0a 0xbd 0xee 0x40 0x0b 0xbc 0xee diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt index a0d5944a053f0..f7acce9fc0155 100644 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt index d2d424c1de491..356c376fedeae 100644 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt index 10748e9b1269d..bc8b7e10b91d8 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # invalid imod value (0b01) 0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 8146b5cb44613..842a52b72928f 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # invalid (imod, M, iflags) combination 0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt index b4414859c91f3..83961569bd1a2 100644 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt index de042a97c6ef9..2c6e6a7fa265f 100644 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt index 6174e92c4726a..4297c016e86bd 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # CBZ / CBNZ not allowed in IT block. diff --git a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt index 17e25ead42f12..733895d6af6bd 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep und # rdar://10841671 0xe3 0xbf diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt index 9b571b33f5fc7..1a8ff48cd99d9 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt @@ -1,3 +1,3 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding" 0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt index 0b0426b2dabe4..6cff09e719609 100644 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt index a42b24880e562..7d8c492649ac1 100644 --- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Writeback is not allowed is Rn is in the target register list. diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt index 6b695b95b2b31..68d22debb0e85 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt index 7ea1b46795707..4df5309b1366c 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index eef2c45db522f..0cff28ad2b2b0 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt index e42e0de9b9d10..30cb727ece8ff 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt index 23a0b85f36157..7b7286af123fa 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # LDR (register) has encoding Inst{4} = 0. 0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt index 8343d549e1b06..bb4b06c90a626 100644 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt index 235952fc35884..528563acb3fc9 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt index 01c1466a280d7..41ec53f3c70ba 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt index 757d167594472..e5f2a5ecbc154 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt index ba488776c0d69..3f4c1e5ff96bc 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt index aaae6ce2e40a3..c20ce542a6b2a 100644 --- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: invalid instruction encoding 0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt index 3765b1f5c025e..901667ab90751 100644 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt index cffd86dc1ad8d..499aa868f904e 100644 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt index 9e1653605256a..7bc97d5260d43 100644 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt index 91f3d58b4c4a5..fe4f43aadd7e1 100644 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt index fc5c711a2300d..eedd05cea624c 100644 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt index ca16724c7ad5b..3d5235de55d77 100644 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt index 400d44ce8c38c..f67f38e28e020 100644 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt index c7cbd844871a3..f57c48f0e22b5 100644 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt index 12da8690f160a..5ba7d618bfd7c 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt index bab32ca1711f5..58def05f27834 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt index 887b983eddb39..54fcadb2a4f7c 100644 --- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # core registers out of range 0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index a53f9405025f7..f961c64f7d998 100644 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt index 8ff3a2b9bd592..2d2a62811ae9c 100644 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt index a12ca9548a521..07a1c7aac699f 100644 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt index df0a642f440c4..c9f1cf12d197d 100644 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt index e1f841b86de31..eb415f755ebf2 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt index 7c0efab3834d4..6c13560a31279 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt index a63d1214f27c9..7f84e0813096b 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt index f126ff04fb1ca..e44cf952cd36e 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt index b3daa9a429f4d..8c0d48bd56c0c 100644 --- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # SP and PC are not allowed in the register list on STM instructions in Thumb2. diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt index 2198efc2d2577..64ba3685cd9bc 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt index 3f406d49487bd..243c11d56137c 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt index 0f9a16ee54dd2..7a7c4a5c54f57 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt index 548ad056e6c0d..2ad3e7df9ce32 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt index bb87ade7869b7..f2fff3f21c4ab 100644 --- a/test/MC/Disassembler/ARM/ldrd-armv4.txt +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -1,5 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 -# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V5TE # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index f44c2a02cf060..a7b6b1ccb408f 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index c5dbee3aa8933..649424af22fd0 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0x20 0x03 0xf1 0xf3 # CHECK: vabs.s8 d16, d16 @@ -1734,6 +1734,25 @@ 0xcf 0x1a 0xe0 0xf4 # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0x0f 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0x0d 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0x25 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0x6f 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0x4d 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0x65 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0x8f 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0x8d 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 +0xa5 0x0e 0xa4 0xf4 + 0x3f 0x03 0xe0 0xf4 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0x4f 0x07 0xe0 0xf4 @@ -1745,6 +1764,30 @@ 0x4f 0x1b 0xe0 0xf4 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0x0f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0x3f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0x1d 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0x35 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0x4f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0x7f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0x5d 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0x75 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0x8f 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xbf 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xdd 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xf5 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 0x1f 0x07 0x40 0xf4 @@ -1852,7 +1895,26 @@ # CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! 0x3d 0x2a 0x5e 0x6c -# CHECK: vmovvs r2, lr, s29, s30 +# CHECK: vmovvs r2, lr, s27, s28 + +0x31 0x1a 0x42 0xec +0x11 0x1a 0x42 0xec +0x31 0x1a 0x52 0xec +0x11 0x1a 0x52 0xec +# CHECK: vmov s3, s4, r1, r2 +# CHECK: vmov s2, s3, r1, r2 +# CHECK: vmov r1, r2, s3, s4 +# CHECK: vmov r1, r2, s2, s3 + +0x1f 0x1b 0x42 0xec +0x30 0x1b 0x42 0xec +0x1f 0x1b 0x52 0xec +0x30 0x1b 0x52 0xec +# CHECK: vmov d15, r1, r2 +# CHECK: vmov d16, r1, r2 +# CHECK: vmov r1, r2, d15 +# CHECK: vmov r1, r2, d16 + 0xe9 0x1a 0xb2 0x4e # CHECK: vcvttmi.f32.f16 s2, s19 @@ -1869,14 +1931,6 @@ # CHECK: vmov.f32 d0, #1.600000e+01 # CHECK: vmov.f32 q0, #1.600000e+01 -# rdar://10798451 -0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 -0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! -0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16] - # rdar://11034702 0x0d 0x87 0x04 0xf4 # CHECK: vst1.8 {d8}, [r4]! diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 65cd2304149de..7d7010febb5e0 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0xf1 0xff 0x20 0x03 # CHECK: vabs.s8 d16, d16 @@ -1475,6 +1475,25 @@ 0xe0 0xf9 0xcf 0x1a # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +0xa4 0xf9 0x0f 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x0d 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x25 0x0e +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x6f 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0xa4 0xf9 0x4d 0x0e +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x65 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x8f 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x8d 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0xa5 0x0e +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 + 0xe0 0xf9 0x3f 0x03 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0xe0 0xf9 0x4f 0x07 @@ -1486,6 +1505,31 @@ 0xe0 0xf9 0x4f 0x1b # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0xa4 0xf9 0x0f 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x3f 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0xa4 0xf9 0x1d 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0xa4 0xf9 0x35 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0xa4 0xf9 0x4f 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x7f 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0x5d 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0xa4 0xf9 0x75 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0xa4 0xf9 0x8f 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0xbf 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0xdd 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xa4 0xf9 0xf5 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 + 0x40 0xf9 0x1f 0x07 # CHECK: vst1.8 {d16}, [r0, :64] 0x40 0xf9 0x4f 0x07 @@ -1998,3 +2042,13 @@ # CHECK: vld2.16 {d0[], d2[]}, [r3], r4 0xa3 0xf9 0xa4 0x0d # CHECK: vld2.32 {d0[], d2[]}, [r3], r4 + + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16] + diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 18b8f4701da6c..c08585a371976 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: add r5, sp, #68 0x11 0xad @@ -301,3 +301,11 @@ # CHECK: mrs r0, apsr 0xef 0xf3 0x00 0x80 + +# rdar://11313994 +# CHECK: blx #2313244 +0x34 0xf2 0x0e 0xee + +# rdar://11324693 +# CHECK: bl #-12303196 +0x44 0xf4 0x52 0xda diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index 17c4bad239ef7..5b7026231096c 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble -show-encoding < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (register) @@ -83,6 +83,15 @@ 0xb1 0x43 #------------------------------------------------------------------------------ +# B +#------------------------------------------------------------------------------ +# CHECK: bls #128 @ encoding: [0x40,0xd9] +# CHECK: beq #-256 @ encoding: [0x80,0xd0] + +0x40 0xd9 +0x80 0xd0 + +#------------------------------------------------------------------------------ # BKPT #------------------------------------------------------------------------------ # CHECK: bkpt #0 @@ -516,15 +525,3 @@ 0xd7 0xb2 0xa1 0xb2 - - -#------------------------------------------------------------------------------ -# WFE/WFI/YIELD -#------------------------------------------------------------------------------ -# CHECK: wfe -# CHECK: wfi -# CHECK: yield - -0x20 0xbf -0x30 0xbf -0x10 0xbf diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index ed8d9886cdbba..42ebe58207b3c 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -92,9 +92,11 @@ #------------------------------------------------------------------------------ # CHECK: subw r11, pc, #3270 # CHECK: subw r11, pc, #826 +# CHECK: subw r1, pc, #0 0xaf 0xf6 0xc6 0x4b 0xaf 0xf2 0x3a 0x3b +0xaf 0xf2 0x00 0x01 #------------------------------------------------------------------------------ # AND (immediate) @@ -344,23 +346,37 @@ #------------------------------------------------------------------------------ #CHECK: dmb sy #CHECK: dmb st +#CHECK: dmb #0xd +#CHECK: dmb #0xc #CHECK: dmb ish #CHECK: dmb ishst +#CHECK: dmb #0x9 +#CHECK: dmb #0x8 #CHECK: dmb nsh #CHECK: dmb nshst +#CHECK: dmb #0x5 +#CHECK: dmb #0x4 #CHECK: dmb osh #CHECK: dmb oshst -#CHECK: dmb +#CHECK: dmb #0x1 +#CHECK: dmb #0x0 0xbf 0xf3 0x5f 0x8f 0xbf 0xf3 0x5e 0x8f +0xbf 0xf3 0x5d 0x8f +0xbf 0xf3 0x5c 0x8f 0xbf 0xf3 0x5b 0x8f 0xbf 0xf3 0x5a 0x8f +0xbf 0xf3 0x59 0x8f +0xbf 0xf3 0x58 0x8f 0xbf 0xf3 0x57 0x8f 0xbf 0xf3 0x56 0x8f +0xbf 0xf3 0x55 0x8f +0xbf 0xf3 0x54 0x8f 0xbf 0xf3 0x53 0x8f 0xbf 0xf3 0x52 0x8f -0xbf 0xf3 0x5f 0x8f +0xbf 0xf3 0x51 0x8f +0xbf 0xf3 0x50 0x8f #------------------------------------------------------------------------------ @@ -368,21 +384,37 @@ #------------------------------------------------------------------------------ #CHECK: dsb sy #CHECK: dsb st +#CHECK: dsb #0xd +#CHECK: dsb #0xc #CHECK: dsb ish #CHECK: dsb ishst +#CHECK: dsb #0x9 +#CHECK: dsb #0x8 #CHECK: dsb nsh #CHECK: dsb nshst +#CHECK: dsb #0x5 +#CHECK: dsb #0x4 #CHECK: dsb osh #CHECK: dsb oshst +#CHECK: dsb #0x1 +#CHECK: dsb #0x0 0xbf 0xf3 0x4f 0x8f 0xbf 0xf3 0x4e 0x8f +0xbf 0xf3 0x4d 0x8f +0xbf 0xf3 0x4c 0x8f 0xbf 0xf3 0x4b 0x8f 0xbf 0xf3 0x4a 0x8f +0xbf 0xf3 0x49 0x8f +0xbf 0xf3 0x48 0x8f 0xbf 0xf3 0x47 0x8f 0xbf 0xf3 0x46 0x8f +0xbf 0xf3 0x45 0x8f +0xbf 0xf3 0x44 0x8f 0xbf 0xf3 0x43 0x8f 0xbf 0xf3 0x42 0x8f +0xbf 0xf3 0x41 0x8f +0xbf 0xf3 0x40 0x8f #------------------------------------------------------------------------------ @@ -609,6 +641,9 @@ # CHECK: ldrd r3, r5, [r6], #-8 # CHECK: ldrd r3, r5, [r6] # CHECK: ldrd r8, r1, [r3] +# CHECK: ldrd r0, r1, [r2], #-0 +# CHECK: ldrd r0, r1, [r2, #-0]! +# CHECK: ldrd r0, r1, [r2, #-0] 0xd6 0xe9 0x06 0x35 0xf6 0xe9 0x06 0x35 @@ -616,6 +651,9 @@ 0x76 0xe8 0x02 0x35 0xd6 0xe9 0x00 0x35 0xd3 0xe9 0x00 0x81 +0x72 0xe8 0x00 0x01 +0x72 0xe9 0x00 0x01 +0x52 0xe9 0x00 0x01 #------------------------------------------------------------------------------ @@ -1790,12 +1828,16 @@ # STRD (immediate) #------------------------------------------------------------------------------ # CHECK: strd r6, r3, [r5], #-8 -# CHECK: strd r8, r5, [r5]{{$}} +# CHECK: strd r8, r5, [r5], #-0 # CHECK: strd r7, r4, [r5], #-4 +# CHECK: strd r0, r1, [r2, #-0]! +# CHECK: strd r0, r1, [r2, #-0] 0x65 0xe8 0x02 0x63 0x65 0xe8 0x00 0x85 0x65 0xe8 0x01 0x74 +0x62 0xe9 0x00 0x01 +0x42 0xe9 0x00 0x01 #------------------------------------------------------------------------------ # STREX/STREXB/STREXH/STREXD diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt index 275bae2fa28ed..d5c8cbba9d365 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x1f 0x12 0xb0 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt index 635b66ea43f0e..d251eb4a303ca 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xd1 0xf1 0x5f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt new file mode 100644 index 0000000000000..d0cb520e32d0d --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt @@ -0,0 +1,62 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=CHECK-WARN +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x03 0xaf 0x06 +# CHECK: sxtb +0x74 0x03 0xaf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xbf 0x06 +# CHECK: sxth +0x74 0x3f 0xbf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xa6 0x06 +# CHECK: sxtab +0x74 0x3f 0xa6 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xb7 0x06 +# CHECK: sxtah +0x74 0x3f 0xb7 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x8f 0x06 +# CHECK: sxtb16 +0x74 0x3f 0x8f 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x86 0x06 +# CHECK: sxtab16 +0x74 0x3f 0x86 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xef 0x06 +# CHECK: uxtb +0x74 0x3f 0xef 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xff 0x06 +# CHECK: uxth +0x74 0x3f 0xff 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xcf 0x06 +# CHECK: uxtb16 +0x74 0x3f 0xcf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xe4 0x06 +# CHECK: uxtab +0x74 0x3f 0xe4 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xf2 0x06 +# CHECK: uxtah +0x74 0x3f 0xf2 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xc4 0x06 +# CHECK: uxtab16 +0x74 0x3f 0xc4 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt index dac4390cde8c8..554ae53076211 100644 --- a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x01 0x10 0x50 0x03 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt index ed5e350c13c85..66073a81be521 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xff 0x00 0xb9 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index a8f54f7127f24..572d84474ccba 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index f7d6bc6edcf6b..9c269537dea2f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt index 26b286dbf4eac..439aaed09780a 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x00 0x10 0x51 0xfc diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt index 3e472cdbfb144..d7853410d9d7f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: 0x00 0xf0 0x0f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt index 3db86cc44fb62..472868fff66bf 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x93 0x12 0x01 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 5b1361094990c..fdfda6df838fa 100644 --- a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt new file mode 100644 index 0000000000000..a2a87703d08c5 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xb4 0x38 0x80 0x06 +0xb4 0x38 0x80 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt index 8ec49cad34994..741d0590abf87 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: shadd16 r5, r7, r0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index 874378ed024c9..832aa3ffa30f7 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index fef6125d283dc..5e62802a3a40b 100644 --- a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index 4c4c9abed2fcb..85b52dd6aa601 100644 --- a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt index 64bb171bf8132..eef5d9fa97282 100644 --- a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x9f 0x10 0x03 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictables-thumb.txt b/test/MC/Disassembler/ARM/unpredictables-thumb.txt index e7645f0a59e3e..925dcd38b6ab3 100644 --- a/test/MC/Disassembler/ARM/unpredictables-thumb.txt +++ b/test/MC/Disassembler/ARM/unpredictables-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7 2>&1 | FileCheck %s 0x01 0x47 # CHECK: 3:1: warning: potentially undefined diff --git a/test/MC/Disassembler/Mips/lit.local.cfg b/test/MC/Disassembler/Mips/lit.local.cfg new file mode 100644 index 0000000000000..9b698b2e6c411 --- /dev/null +++ b/test/MC/Disassembler/Mips/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'Mips' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 591d8c444af4e..a1933190b1412 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -1,421 +1,406 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x05 -# CHECK: abs.d $f12,$f14 -0x46 0x20 0x39 0x85 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x46 0x00 0x39 0x85 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x00 0xc7 0x48 0x20 -# CHECK: add.d $f18,$f12,$f14 -0x46 0x27 0x32 0x40 +# CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x00 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x46 0x07 0x32 0x40 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x20 0xc9 0x45 0x67 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x24 0xc9 0xc5 0x67 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x00 0xc7 0x48 0x21 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x00 0xc7 0x48 0x24 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x30 0xc9 0x45 0x67 -# CHECK: b 00000534 +# CHECK: b 1332 0x10 0x00 0x01 0x4c -# CHECK: bal 00000534 -0x04 0x11 0x01 0x4c - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x45 0x00 0x01 0x4c -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x45 0x01 0x01 0x4c -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x04 0xc1 0x01 0x4c -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x04 0xd1 0x01 0x4c -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x1c 0xc0 0x01 0x4c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x18 0xc0 0x01 0x4c -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x15 0x26 0x01 0x4c -# CHECK: c.eq.d $f12,$f14 -0x46 0x27 0x30 0x32 +# CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x32 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x46 0x07 0x30 0x32 -# CHECK: c.f.d $f12,$f14 -0x46 0x27 0x30 0x30 +# CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x30 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x46 0x07 0x30 0x30 -# CHECK: c.le.d $f12,$f14 -0x46 0x27 0x30 0x3e +# CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3e -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3e -# CHECK: c.lt.d $f12,$f14 -0x46 0x27 0x30 0x3c +# CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3c -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x46 0x07 0x30 0x3c -# CHECK: c.nge.d $f12,$f14 -0x46 0x27 0x30 0x3d +# CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3d -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x46 0x07 0x30 0x3d -# CHECK: c.ngl.d $f12,$f14 -0x46 0x27 0x30 0x3b +# CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3b -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3b -# CHECK: c.ngle.d $f12,$f14 -0x46 0x27 0x30 0x39 +# CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x39 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x46 0x07 0x30 0x39 -# CHECK: c.ngt.d $f12,$f14 -0x46 0x27 0x30 0x3f +# CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x60 0x3f -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x46 0x07 0x30 0x3f -# CHECK: c.ole.d $f12,$f14 -0x46 0x27 0x30 0x36 +# CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x36 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x46 0x07 0x30 0x36 -# CHECK: c.olt.d $f12,$f14 -0x46 0x27 0x30 0x34 +# CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x34 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x46 0x07 0x30 0x34 -# CHECK: c.seq.d $f12,$f14 -0x46 0x27 0x30 0x3a +# CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3a -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a -# CHECK: c.sf.d $f12,$f14 -0x46 0x27 0x30 0x38 +# CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x38 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 -# CHECK: c.ueq.d $f12,$f14 -0x46 0x27 0x30 0x33 +# CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x33 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 -# CHECK: c.ule.d $f12,$f14 -0x46 0x27 0x30 0x37 +# CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x37 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x46 0x07 0x30 0x37 -# CHECK: c.ult.d $f12,$f14 -0x46 0x27 0x30 0x35 +# CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x35 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 -# CHECK: c.un.d $f12,$f14 -0x46 0x27 0x30 0x31 +# CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x31 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 -# CHECK: ceil.w.d $f12,$f14 -0x46 0x20 0x39 0x8e +# CHECK: ceil.w.d $f12, $f14 +0x46 0x20 0x73 0x0e -# CHECK: ceil.w.s $f6,$f7 +# CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x44 0xc6 0x38 0x00 -# CHECK: cvt.d.s $f6,$f7 -0x46 0x00 0x38 0xa1 - -# CHECK: cvt.d.w $f12,$f14 -0x46 0x80 0x38 0xa1 - -# CHECK: cvt.l.d $f12,$f14 -0x46 0x20 0x39 0xa5 +# CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa1 -# CHECK: cvt.l.s $f6,$f7 -0x46 0x00 0x39 0xa5 +# CHECK: cvt.d.w $f12, $f14 +0x46 0x80 0x73 0x21 -# CHECK: cvt.s.d $f12,$f14 -0x46 0x20 0x39 0xa0 +# CHECK: cvt.s.d $f12, $f14 +0x46 0x20 0x73 0x20 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 -# CHECK: cvt.w.d $f12,$f14 -0x46 0x20 0x39 0xa4 +# CHECK: cvt.w.d $f12, $f14 +0x46 0x20 0x73 0x24 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 -# CHECK: floor.w.d $f12,$f14 -0x46 0x20 0x39 0x8f +# CHECK: floor.w.d $f12, $f14 +0x46 0x20 0x73 0x0f -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f -# CHECK: j 00000530 +# CHECK: j 1328 0x08 0x00 0x01 0x4c -# CHECK: jal 00000530 +# CHECK: jal 1328 0x0c 0x00 0x01 0x4c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x00 0xe0 0xf8 0x09 -# CHECK: jr a3 +# CHECK: jr $7 0x00 0xe0 0x00 0x08 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0x80 0xa4 0x23 0xc6 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x90 0xa4 0x00 0x06 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xd4 0xe9 0x23 0xc6 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: li v1,17767 -0x24 0x03 0x45 0x67 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc0 0xe9 0x23 0xc6 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x3c 0x06 0x45 0x67 -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x8c 0xa4 0x00 0x18 -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc4 0xe9 0x23 0xc6 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x88 0x82 0x00 0x03 + +# CHECK: lwr $3, 16($5) +0x98 0xa3 0x00 0x10 + +# CHECK: madd $6, $7 0x70 0xc7 0x00 0x00 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x70 0xc7 0x00 0x01 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x44 0x06 0x38 0x00 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x00 0x00 0x28 0x10 -# CHECK: mflo a1 +# CHECK: mflo $5 0x00 0x00 0x28 0x12 -# CHECK: mov.d $f6,$f7 -0x46 0x20 0x39 0x86 +# CHECK: mov.d $f6, $f8 +0x46 0x20 0x41 0x86 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 -# CHECK: move a2,a1 -0x00 0xa0 0x30 0x21 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x70 0xc7 0x00 0x05 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x44 0x86 0x38 0x00 -# CHECK: mthi a3 +# CHECK: mthi $7 0x00 0xe0 0x00 0x11 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x00 0xe0 0x00 0x13 -# CHECK: mul.d $f9,$f12,$f14 -0x46 0x27 0x32 0x42 +# CHECK: mul.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x46 0x07 0x32 0x42 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x70 0xc7 0x48 0x02 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x00 0x65 0x00 0x18 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x00 0x65 0x00 0x19 -# CHECK: neg.d $f12,$f14 -0x46 0x20 0x39 0x87 +# CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x07 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 -# CHECK: neg v1,a1 -0x00 0x05 0x18 0x22 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x00 0xc7 0x48 0x27 -# CHECK: not v1,a1 -0x00 0xa0 0x18 0x27 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x00 0x65 0x18 0x25 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x34 0xc9 0x45 0x67 -# CHECK: rdhwr a2,$29 -0x7c 0x06 0xe8 0x3b +# CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0c -# CHECK: round.w.d $f12,$f14 -0x46 0x20 0x39 0x8c - -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xa0 0xa4 0x23 0xc6 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0xa0 0xa4 0x00 0x06 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xe0 0xe9 0x23 0xc6 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xf4 0xe9 0x23 0xc6 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xa4 0xa4 0x23 0xc6 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0x00 0x03 0x21 0xc0 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x00 0xa3 0x10 0x04 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x00 0x65 0x18 0x2a -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x28 0x63 0x00 0x67 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x2c 0x63 0x00 0x67 -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x00 0x65 0x18 0x2b -# CHECK: sqrt.d $f12,$f14 -0x46 0x20 0x39 0x84 +# CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x04 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x46 0x00 0x39 0x84 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0x00 0x03 0x21 0xc3 -# CHECK: sra a0,v1,0x7 -0x00 0x03 0x21 0xc3 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x00 0xa3 0x10 0x07 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0x00 0x03 0x21 0xc2 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x00 0xa3 0x10 0x06 -# CHECK: sub.d $f9,$f12,$f14 -0x46 0x27 0x32 0x41 +# CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x46 0x07 0x32 0x41 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x22 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x00 0x65 0x20 0x23 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0xac 0xa4 0x00 0x18 -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xe4 0xe9 0x23 0xc6 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0xa8 0xa4 0x00 0x10 + +# CHECK: swr $6, 16($7) +0xb8 0xe6 0x00 0x10 + +# CHECK: sync 7 0x00 0x00 0x01 0xcf -# CHECK: trunc.w.d $f12,$f14 -0x46 0x20 0x39 0x8d +# CHECK: trunc.w.d $f12, $f14 +0x46 0x20 0x73 0x0d -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x00 0x65 0x18 0x26 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index a5a3cfd095df4..08b36726baf3e 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -1,424 +1,406 @@ -# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x05 0x73 0x20 0x46 -# CHECK: abs.d $f12,$f14 -0x85 0x39 0x20 0x46 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x85 0x39 0x00 0x46 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x20 0x48 0xc7 0x00 -# CHECK: add.d $f18,$f12,$f14 -0x40 0x32 0x27 0x46 +# CHECK: add.d $f8, $f12, $f14 +0x00 0x62 0x2e 0x46 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x40 0x32 0x07 0x46 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x67 0x45 0xc9 0x20 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x67 0xc5 0xc9 0x24 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x21 0x48 0xc7 0x00 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x24 0x48 0xc7 0x00 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x67 0x45 0xc9 0x30 -# CHECK: b 00000534 +# CHECK: b 1332 0x4c 0x01 0x00 0x10 -# CHECK: bal 00000534 -0x4c 0x01 0x11 0x04 - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x4c 0x01 0xc1 0x04 -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x4c 0x01 0xd1 0x04 -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x4c 0x01 0xc0 0x1c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x4c 0x01 0xc0 0x18 -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x4c 0x01 0x26 0x15 -# CHECK: c.eq.d $f12,$f14 -0x32 0x30 0x27 0x46 +# CHECK: c.eq.d $f12, $f14 +0x32 0x60 0x2e 0x46 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x32 0x30 0x07 0x46 -# CHECK: c.f.d $f12,$f14 -0x30 0x30 0x27 0x46 +# CHECK: c.f.d $f12, $f14 +0x30 0x60 0x2e 0x46 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x30 0x30 0x07 0x46 -# CHECK: c.le.d $f12,$f14 -0x3e 0x30 0x27 0x46 +# CHECK: c.le.d $f12, $f14 +0x3e 0x60 0x2e 0x46 -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x3e 0x30 0x07 0x46 -# CHECK: c.lt.d $f12,$f14 -0x3c 0x30 0x27 0x46 +# CHECK: c.lt.d $f12, $f14 +0x3c 0x60 0x2e 0x46 -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x3c 0x30 0x07 0x46 -# CHECK: c.nge.d $f12,$f14 -0x3d 0x30 0x27 0x46 +# CHECK: c.nge.d $f12, $f14 +0x3d 0x60 0x2e 0x46 -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x3d 0x30 0x07 0x46 -# CHECK: c.ngl.d $f12,$f14 -0x3b 0x30 0x27 0x46 +# CHECK: c.ngl.d $f12, $f14 +0x3b 0x60 0x2e 0x46 -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x3b 0x30 0x07 0x46 -# CHECK: c.ngle.d $f12,$f14 -0x39 0x30 0x27 0x46 +# CHECK: c.ngle.d $f12, $f14 +0x39 0x60 0x2e 0x46 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x39 0x30 0x07 0x46 -# CHECK: c.ngt.d $f12,$f14 -0x3f 0x30 0x27 0x46 +# CHECK: c.ngt.d $f12, $f14 +0x3f 0x60 0x2e 0x46 -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x3f 0x30 0x07 0x46 -# CHECK: c.ole.d $f12,$f14 -0x36 0x30 0x27 0x46 +# CHECK: c.ole.d $f12, $f14 +0x36 0x60 0x2e 0x46 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x36 0x30 0x07 0x46 -# CHECK: c.olt.d $f12,$f14 -0x34 0x30 0x27 0x46 +# CHECK: c.olt.d $f12, $f14 +0x34 0x60 0x2e 0x46 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x34 0x30 0x07 0x46 -# CHECK: c.seq.d $f12,$f14 -0x3a 0x30 0x27 0x46 +# CHECK: c.seq.d $f12, $f14 +0x3a 0x60 0x2e 0x46 -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x3a 0x30 0x07 0x46 -# CHECK: c.sf.d $f12,$f14 -0x38 0x30 0x27 0x46 +# CHECK: c.sf.d $f12, $f14 +0x38 0x60 0x2e 0x46 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x38 0x30 0x07 0x46 -# CHECK: c.ueq.d $f12,$f14 -0x33 0x30 0x27 0x46 +# CHECK: c.ueq.d $f12, $f14 +0x33 0x60 0x2e 0x46 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x33 0xe0 0x12 0x46 -# CHECK: c.ule.d $f12,$f14 -0x37 0x30 0x27 0x46 +# CHECK: c.ule.d $f12, $f14 +0x37 0x60 0x2e 0x46 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x37 0x30 0x07 0x46 -# CHECK: c.ult.d $f12,$f14 -0x35 0x30 0x27 0x46 +# CHECK: c.ult.d $f12, $f14 +0x35 0x60 0x2e 0x46 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 -# CHECK: c.un.d $f12,$f14 -0x31 0x30 0x27 0x46 +# CHECK: c.un.d $f12, $f14 +0x31 0x60 0x2e 0x46 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 -# CHECK: ceil.w.d $f12,$f14 -0x8e 0x38 0x20 0x46 +# CHECK: ceil.w.d $f12, $f14 +0x0e 0x73 0x20 0x46 -# CHECK: ceil.w.s $f6,$f7 -0x8e 0x38 0x00 0x46 +# CHECK: ceil.w.s $f6, $f7 +0x8e 0x39 0x00 0x46 -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x00 0x38 0x46 0x44 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x00 0x38 0xc6 0x44 -# CHECK: cvt.d.s $f6,$f7 +# CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 -# CHECK: cvt.d.w $f12,$f14 -0xa1 0x39 0x80 0x46 - -# CHECK: cvt.l.d $f12,$f14 -0xa5 0x39 0x20 0x46 - -# CHECK: cvt.l.s $f6,$f7 -0xa5 0x39 0x00 0x46 +# CHECK: cvt.d.w $f12, $f14 +0x21 0x73 0x80 0x46 -# CHECK: cvt.s.d $f12,$f14 -0xa0 0x39 0x20 0x46 +# CHECK: cvt.s.d $f12, $f14 +0x20 0x73 0x20 0x46 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 -# CHECK: cvt.w.d $f12,$f14 -0xa4 0x39 0x20 0x46 +# CHECK: cvt.w.d $f12, $f14 +0x24 0x73 0x20 0x46 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 -# CHECK: floor.w.d $f12,$f14 -0x8f 0x39 0x20 0x46 +# CHECK: floor.w.d $f12, $f14 +0x0f 0x73 0x20 0x46 -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 -# CHECK: j 00000530 +# CHECK: j 1328 0x4c 0x01 0x00 0x08 -# CHECK: jal 00000530 +# CHECK: jal 1328 0x4c 0x01 0x00 0x0c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x09 0xf8 0xe0 0x00 -# CHECK: jr a3 +# CHECK: jr $7 0x08 0x00 0xe0 0x00 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0xc6 0x23 0xa4 0x80 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x06 0x00 0xa4 0x90 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xd4 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: li v1,17767 -0x67 0x45 0x03 0x24 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc6 0x23 0xe9 0xc0 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x67 0x45 0x06 0x3c -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x18 0x00 0xa4 0x8c -# CHECK lw at,-18316(v0) -0x74 0xb8 0x41 0x8c - -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xc4 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x03 0x00 0x82 0x88 + +# CHECK: lwr $3, 16($5) +0x10 0x00 0xa3 0x98 + +# CHECK: madd $6, $7 0x00 0x00 0xc7 0x70 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x10 0x28 0x00 0x00 -# CHECK: mflo a1 +# CHECK: mflo $5 0x12 0x28 0x00 0x00 -# CHECK: mov.d $f12,$f14 -0x86 0x39 0x20 0x46 +# CHECK: mov.d $f6, $f8 +0x86 0x41 0x20 0x46 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x86 0x39 0x00 0x46 -# CHECK: move a2,a1 -0x21 0x30 0xa0 0x00 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 -# CHECK: mthi a3 +# CHECK: mthi $7 0x11 0x00 0xe0 0x00 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x13 0x00 0xe0 0x00 -# CHECK: mul.d $f9,$f12,$f14 -0x42 0x32 0x27 0x46 +# CHECK: mul.d $f8, $f12, $f14 +0x02 0x62 0x2e 0x46 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x42 0x32 0x07 0x46 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x02 0x48 0xc7 0x70 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x18 0x00 0x65 0x00 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x19 0x00 0x65 0x00 -# CHECK: neg.d $f12,$f14 -0x87 0x39 0x20 0x46 +# CHECK: neg.d $f12, $f14 +0x07 0x73 0x20 0x46 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 -# CHECK: neg v1,a1 -0x22 0x18 0x05 0x00 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 -# CHECK: not v1,a1 -0x27 0x18 0xa0 0x00 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 -# CHECK: rdhwr a2,$29 -0x3b 0xe8 0x06 0x7c - -# CHECK: round.w.d $f12,$f14 -0x8c 0x39 0x20 0x46 +# CHECK: round.w.d $f12, $f14 +0x0c 0x73 0x20 0x46 -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0xc0 0x21 0x03 0x00 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x04 0x10 0xa3 0x00 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x2a 0x18 0x65 0x00 -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x67 0x00 0x63 0x28 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x67 0x00 0x63 0x2c -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x2b 0x18 0x65 0x00 -# CHECK: sqrt.d $f12,$f14 -0x84 0x39 0x20 0x46 +# CHECK: sqrt.d $f12, $f14 +0x04 0x73 0x20 0x46 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x84 0x39 0x00 0x46 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0xc3 0x21 0x03 0x00 -# CHECK: sra a0,v1,0x7 -0xc3 0x21 0x03 0x00 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x07 0x10 0xa3 0x00 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0xc2 0x21 0x03 0x00 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x06 0x10 0xa3 0x00 -# CHECK: sub.d $f9,$f12,$f14 -0x41 0x32 0x27 0x46 +# CHECK: sub.d $f8, $f12, $f14 +0x01 0x62 0x2e 0x46 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x41 0x32 0x07 0x46 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x22 0x48 0xc7 0x00 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xe4 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0x10 0x00 0xa4 0xa8 + +# CHECK: swr $6, 16($7) +0x10 0x00 0xe6 0xb8 + +# CHECK: sync 7 0xcf 0x01 0x00 0x00 -# CHECK: trunc.w.d $f12,$f14 -0x8d 0x39 0x20 0x46 +# CHECK: trunc.w.d $f12, $f14 +0x0d 0x73 0x20 0x46 -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x8d 0x39 0x00 0x46 -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x26 0x18 0x65 0x00 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 295ffd0389598..3b70db3bc29d1 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -1,439 +1,430 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x05 -# CHECK: abs.d $f12,$f14 -0x46 0x20 0x39 0x85 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x46 0x00 0x39 0x85 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x00 0xc7 0x48 0x20 -# CHECK: add.d $f18,$f12,$f14 -0x46 0x27 0x32 0x40 +# CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x00 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x46 0x07 0x32 0x40 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x20 0xc9 0x45 0x67 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x24 0xc9 0xc5 0x67 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x00 0xc7 0x48 0x21 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x00 0xc7 0x48 0x24 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x30 0xc9 0x45 0x67 -# CHECK: b 00000534 +# CHECK: b 1332 0x10 0x00 0x01 0x4c -# CHECK: bal 00000534 -0x04 0x11 0x01 0x4c - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x45 0x00 0x01 0x4c -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x45 0x01 0x01 0x4c -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x04 0xc1 0x01 0x4c -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x04 0xd1 0x01 0x4c -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x1c 0xc0 0x01 0x4c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x18 0xc0 0x01 0x4c -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x15 0x26 0x01 0x4c -# CHECK: c.eq.d $f12,$f14 -0x46 0x27 0x30 0x32 +# CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x32 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x46 0x07 0x30 0x32 -# CHECK: c.f.d $f12,$f14 -0x46 0x27 0x30 0x30 +# CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x30 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x46 0x07 0x30 0x30 -# CHECK: c.le.d $f12,$f14 -0x46 0x27 0x30 0x3e +# CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3e -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3e -# CHECK: c.lt.d $f12,$f14 -0x46 0x27 0x30 0x3c +# CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3c -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x46 0x07 0x30 0x3c -# CHECK: c.nge.d $f12,$f14 -0x46 0x27 0x30 0x3d +# CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3d -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x46 0x07 0x30 0x3d -# CHECK: c.ngl.d $f12,$f14 -0x46 0x27 0x30 0x3b +# CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3b -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3b -# CHECK: c.ngle.d $f12,$f14 -0x46 0x27 0x30 0x39 +# CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x39 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x46 0x07 0x30 0x39 -# CHECK: c.ngt.d $f12,$f14 -0x46 0x27 0x30 0x3f +# CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x60 0x3f -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x46 0x07 0x30 0x3f -# CHECK: c.ole.d $f12,$f14 -0x46 0x27 0x30 0x36 +# CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x36 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x46 0x07 0x30 0x36 -# CHECK: c.olt.d $f12,$f14 -0x46 0x27 0x30 0x34 +# CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x34 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x46 0x07 0x30 0x34 -# CHECK: c.seq.d $f12,$f14 -0x46 0x27 0x30 0x3a +# CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3a -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a -# CHECK: c.sf.d $f12,$f14 -0x46 0x27 0x30 0x38 +# CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x38 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 -# CHECK: c.ueq.d $f12,$f14 -0x46 0x27 0x30 0x33 +# CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x33 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 -# CHECK: c.ule.d $f12,$f14 -0x46 0x27 0x30 0x37 +# CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x37 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x46 0x07 0x30 0x37 -# CHECK: c.ult.d $f12,$f14 -0x46 0x27 0x30 0x35 +# CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x35 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 -# CHECK: c.un.d $f12,$f14 -0x46 0x27 0x30 0x31 +# CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x31 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 -# CHECK: ceil.w.d $f12,$f14 -0x46 0x20 0x39 0x8e +# CHECK: ceil.w.d $f12, $f14 +0x46 0x20 0x73 0x0e -# CHECK: ceil.w.s $f6,$f7 +# CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x44 0xc6 0x38 0x00 -# CHECK: cvt.d.s $f6,$f7 -0x46 0x00 0x38 0xa1 +# CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa1 -# CHECK: cvt.d.w $f12,$f14 -0x46 0x80 0x38 0xa1 +# CHECK: cvt.d.w $f12, $f14 +0x46 0x80 0x73 0x21 -# CHECK: cvt.l.d $f12,$f14 -0x46 0x20 0x39 0xa5 +# CHECK: cvt.l.d $f12, $f14 +0x46 0x20 0x73 0x25 -# CHECK: cvt.l.s $f6,$f7 +# CHECK: cvt.l.s $f6, $f7 0x46 0x00 0x39 0xa5 -# CHECK: cvt.s.d $f12,$f14 -0x46 0x20 0x39 0xa0 +# CHECK: cvt.s.d $f12, $f14 +0x46 0x20 0x73 0x20 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 -# CHECK: cvt.w.d $f12,$f14 -0x46 0x20 0x39 0xa4 +# CHECK: cvt.w.d $f12, $f14 +0x46 0x20 0x73 0x24 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 -# CHECK: floor.w.d $f12,$f14 -0x46 0x20 0x39 0x8f +# CHECK: floor.w.d $f12, $f14 +0x46 0x20 0x73 0x0f -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f -# CHECK: ins s3,t1,0x6,0x7 +# CHECK: ins $19, $9, 6, 7 0x7d 0x33 0x61 0x84 -# CHECK: j 00000530 +# CHECK: j 1328 0x08 0x00 0x01 0x4c -# CHECK: jal 00000530 +# CHECK: jal 1328 0x0c 0x00 0x01 0x4c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x00 0xe0 0xf8 0x09 -# CHECK: jr a3 +# CHECK: jr $7 0x00 0xe0 0x00 0x08 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0x80 0xa4 0x23 0xc6 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x90 0xa4 0x00 0x06 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xd4 0xe9 0x23 0xc6 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: li v1,17767 -0x24 0x03 0x45 0x67 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc0 0xe9 0x23 0xc6 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x3c 0x06 0x45 0x67 -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x8c 0xa4 0x00 0x18 -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc4 0xe9 0x23 0xc6 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x88 0x82 0x00 0x03 + +# CHECK: lwr $3, 16($5) +0x98 0xa3 0x00 0x10 + +# CHECK: madd $6, $7 0x70 0xc7 0x00 0x00 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x70 0xc7 0x00 0x01 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x44 0x06 0x38 0x00 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x00 0x00 0x28 0x10 -# CHECK: mflo a1 +# CHECK: mflo $5 0x00 0x00 0x28 0x12 -# CHECK: mov.d $f6,$f7 -0x46 0x20 0x39 0x86 +# CHECK: mov.d $f6, $f8 +0x46 0x20 0x41 0x86 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 -# CHECK: move a2,a1 -0x00 0xa0 0x30 0x21 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x70 0xc7 0x00 0x05 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x44 0x86 0x38 0x00 -# CHECK: mthi a3 +# CHECK: mthi $7 0x00 0xe0 0x00 0x11 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x00 0xe0 0x00 0x13 -# CHECK: mul.d $f9,$f12,$f14 -0x46 0x27 0x32 0x42 +# CHECK: mul.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x46 0x07 0x32 0x42 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x70 0xc7 0x48 0x02 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x00 0x65 0x00 0x18 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x00 0x65 0x00 0x19 -# CHECK: neg.d $f12,$f14 -0x46 0x20 0x39 0x87 +# CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x07 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 -# CHECK: neg v1,a1 -0x00 0x05 0x18 0x22 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x00 0xc7 0x48 0x27 -# CHECK: not v1,a1 -0x00 0xa0 0x18 0x27 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x00 0x65 0x18 0x25 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x34 0xc9 0x45 0x67 -# CHECK: rdhwr a2,$29 -0x7c 0x06 0xe8 0x3b - -# CHECK: ror t1,a2,0x7 +# CHECK: rotr $9, $6, 7 0x00 0x26 0x49 0xc2 -# CHECK: rorv t1,a2,a3 +# CHECK: rotrv $9, $6, $7 0x00 0xe6 0x48 0x46 -# CHECK: round.w.d $f12,$f14 -0x46 0x20 0x39 0x8c +# CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0c -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xa0 0xa4 0x23 0xc6 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0xa0 0xa4 0x00 0x06 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xe0 0xe9 0x23 0xc6 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xf4 0xe9 0x23 0xc6 -# CHECK: seb a2,a3 +# CHECK: seb $6, $7 0x7c 0x07 0x34 0x20 -# CHECK: seh a2,a3 +# CHECK: seh $6, $7 0x7c 0x07 0x36 0x20 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xa4 0xa4 0x23 0xc6 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0x00 0x03 0x21 0xc0 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x00 0xa3 0x10 0x04 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x00 0x65 0x18 0x2a -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x28 0x63 0x00 0x67 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x2c 0x63 0x00 0x67 -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x00 0x65 0x18 0x2b -# CHECK: sqrt.d $f12,$f14 -0x46 0x20 0x39 0x84 +# CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x04 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x46 0x00 0x39 0x84 -# CHECK: sra a0,v1,0x7 -0x00 0x03 0x21 0xc3 - -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0x00 0x03 0x21 0xc3 -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x00 0xa3 0x10 0x07 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0x00 0x03 0x21 0xc2 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x00 0xa3 0x10 0x06 -# CHECK: sub.d $f9,$f12,$f14 -0x46 0x27 0x32 0x41 +# CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x46 0x07 0x32 0x41 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x22 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x00 0x65 0x20 0x23 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0xac 0xa4 0x00 0x18 -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xe4 0xe9 0x23 0xc6 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0xa8 0xa4 0x00 0x10 + +# CHECK: swr $6, 16($7) +0xb8 0xe6 0x00 0x10 + +# CHECK: sync 7 0x00 0x00 0x01 0xcf -# CHECK: trunc.w.d $f12,$f14 -0x46 0x20 0x39 0x8d +# CHECK: trunc.w.d $f12, $f14 +0x46 0x20 0x73 0x0d -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d -# CHECK: wsbh a2,a3 +# CHECK: wsbh $6, $7 0x7c 0x07 0x30 0xa0 -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x00 0x65 0x18 0x26 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index 6d8be790f148d..ecfde7a39c4fb 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -1,442 +1,430 @@ -# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x05 0x73 0x20 0x46 -# CHECK: abs.d $f12,$f14 -0x85 0x39 0x20 0x46 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x85 0x39 0x00 0x46 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x20 0x48 0xc7 0x00 -# CHECK: add.d $f18,$f12,$f14 -0x40 0x32 0x27 0x46 +# CHECK: add.d $f8, $f12, $f14 +0x00 0x62 0x2e 0x46 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x40 0x32 0x07 0x46 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x67 0x45 0xc9 0x20 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x67 0xc5 0xc9 0x24 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x21 0x48 0xc7 0x00 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x24 0x48 0xc7 0x00 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x67 0x45 0xc9 0x30 -# CHECK: b 00000534 +# CHECK: b 1332 0x4c 0x01 0x00 0x10 -# CHECK: bal 00000534 -0x4c 0x01 0x11 0x04 - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x4c 0x01 0xc1 0x04 -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x4c 0x01 0xd1 0x04 -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x4c 0x01 0xc0 0x1c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x4c 0x01 0xc0 0x18 -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x4c 0x01 0x26 0x15 -# CHECK: c.eq.d $f12,$f14 -0x32 0x30 0x27 0x46 +# CHECK: c.eq.d $f12, $f14 +0x32 0x60 0x2e 0x46 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x32 0x30 0x07 0x46 -# CHECK: c.f.d $f12,$f14 -0x30 0x30 0x27 0x46 +# CHECK: c.f.d $f12, $f14 +0x30 0x60 0x2e 0x46 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x30 0x30 0x07 0x46 -# CHECK: c.le.d $f12,$f14 -0x3e 0x30 0x27 0x46 +# CHECK: c.le.d $f12, $f14 +0x3e 0x60 0x2e 0x46 -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x3e 0x30 0x07 0x46 -# CHECK: c.lt.d $f12,$f14 -0x3c 0x30 0x27 0x46 +# CHECK: c.lt.d $f12, $f14 +0x3c 0x60 0x2e 0x46 -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x3c 0x30 0x07 0x46 -# CHECK: c.nge.d $f12,$f14 -0x3d 0x30 0x27 0x46 +# CHECK: c.nge.d $f12, $f14 +0x3d 0x60 0x2e 0x46 -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x3d 0x30 0x07 0x46 -# CHECK: c.ngl.d $f12,$f14 -0x3b 0x30 0x27 0x46 +# CHECK: c.ngl.d $f12, $f14 +0x3b 0x60 0x2e 0x46 -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x3b 0x30 0x07 0x46 -# CHECK: c.ngle.d $f12,$f14 -0x39 0x30 0x27 0x46 +# CHECK: c.ngle.d $f12, $f14 +0x39 0x60 0x2e 0x46 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x39 0x30 0x07 0x46 -# CHECK: c.ngt.d $f12,$f14 -0x3f 0x30 0x27 0x46 +# CHECK: c.ngt.d $f12, $f14 +0x3f 0x60 0x2e 0x46 -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x3f 0x30 0x07 0x46 -# CHECK: c.ole.d $f12,$f14 -0x36 0x30 0x27 0x46 +# CHECK: c.ole.d $f12, $f14 +0x36 0x60 0x2e 0x46 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x36 0x30 0x07 0x46 -# CHECK: c.olt.d $f12,$f14 -0x34 0x30 0x27 0x46 +# CHECK: c.olt.d $f12, $f14 +0x34 0x60 0x2e 0x46 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x34 0x30 0x07 0x46 -# CHECK: c.seq.d $f12,$f14 -0x3a 0x30 0x27 0x46 +# CHECK: c.seq.d $f12, $f14 +0x3a 0x60 0x2e 0x46 -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x3a 0x30 0x07 0x46 -# CHECK: c.sf.d $f12,$f14 -0x38 0x30 0x27 0x46 +# CHECK: c.sf.d $f12, $f14 +0x38 0x60 0x2e 0x46 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x38 0x30 0x07 0x46 -# CHECK: c.ueq.d $f12,$f14 -0x33 0x30 0x27 0x46 +# CHECK: c.ueq.d $f12, $f14 +0x33 0x60 0x2e 0x46 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x33 0xe0 0x12 0x46 -# CHECK: c.ule.d $f12,$f14 -0x37 0x30 0x27 0x46 +# CHECK: c.ule.d $f12, $f14 +0x37 0x60 0x2e 0x46 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x37 0x30 0x07 0x46 -# CHECK: c.ult.d $f12,$f14 -0x35 0x30 0x27 0x46 +# CHECK: c.ult.d $f12, $f14 +0x35 0x60 0x2e 0x46 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 -# CHECK: c.un.d $f12,$f14 -0x31 0x30 0x27 0x46 +# CHECK: c.un.d $f12, $f14 +0x31 0x60 0x2e 0x46 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 -# CHECK: ceil.w.d $f12,$f14 -0x8e 0x38 0x20 0x46 +# CHECK: ceil.w.d $f12, $f14 +0x0e 0x73 0x20 0x46 -# CHECK: ceil.w.s $f6,$f7 -0x8e 0x38 0x00 0x46 +# CHECK: ceil.w.s $f6, $f7 +0x8e 0x39 0x00 0x46 -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x00 0x38 0x46 0x44 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x00 0x38 0xc6 0x44 -# CHECK: cvt.d.s $f6,$f7 +# CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 -# CHECK: cvt.d.w $f12,$f14 -0xa1 0x39 0x80 0x46 +# CHECK: cvt.d.w $f12, $f14 +0x21 0x73 0x80 0x46 -# CHECK: cvt.l.d $f12,$f14 -0xa5 0x39 0x20 0x46 +# CHECK: cvt.l.d $f12, $f14 +0x25 0x73 0x20 0x46 -# CHECK: cvt.l.s $f6,$f7 +# CHECK: cvt.l.s $f6, $f7 0xa5 0x39 0x00 0x46 -# CHECK: cvt.s.d $f12,$f14 -0xa0 0x39 0x20 0x46 +# CHECK: cvt.s.d $f12, $f14 +0x20 0x73 0x20 0x46 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 -# CHECK: cvt.w.d $f12,$f14 -0xa4 0x39 0x20 0x46 +# CHECK: cvt.w.d $f12, $f14 +0x24 0x73 0x20 0x46 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 -# CHECK: floor.w.d $f12,$f14 -0x8f 0x39 0x20 0x46 +# CHECK: floor.w.d $f12, $f14 +0x0f 0x73 0x20 0x46 -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 -# CHECK: ins s3,t1,0x6,0x7 +# CHECK: ins $19, $9, 6, 7 0x84 0x61 0x33 0x7d -# CHECK: j 00000530 +# CHECK: j 1328 0x4c 0x01 0x00 0x08 -# CHECK: jal 00000530 +# CHECK: jal 1328 0x4c 0x01 0x00 0x0c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x09 0xf8 0xe0 0x00 -# CHECK: jr a3 +# CHECK: jr $7 0x08 0x00 0xe0 0x00 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0xc6 0x23 0xa4 0x80 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x06 0x00 0xa4 0x90 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xd4 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: li v1,17767 -0x67 0x45 0x03 0x24 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc6 0x23 0xe9 0xc0 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x67 0x45 0x06 0x3c -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x18 0x00 0xa4 0x8c -# CHECK lw at,-18316(v0) -0x74 0xb8 0x41 0x8c - -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xc4 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x03 0x00 0x82 0x88 + +# CHECK: lwr $3, 16($5) +0x10 0x00 0xa3 0x98 + +# CHECK: madd $6, $7 0x00 0x00 0xc7 0x70 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x10 0x28 0x00 0x00 -# CHECK: mflo a1 +# CHECK: mflo $5 0x12 0x28 0x00 0x00 -# CHECK: mov.d $f12,$f14 -0x86 0x39 0x20 0x46 +# CHECK: mov.d $f6, $f8 +0x86 0x41 0x20 0x46 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x86 0x39 0x00 0x46 -# CHECK: move a2,a1 -0x21 0x30 0xa0 0x00 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 -# CHECK: mthi a3 +# CHECK: mthi $7 0x11 0x00 0xe0 0x00 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x13 0x00 0xe0 0x00 -# CHECK: mul.d $f9,$f12,$f14 -0x42 0x32 0x27 0x46 +# CHECK: mul.d $f8, $f12, $f14 +0x02 0x62 0x2e 0x46 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x42 0x32 0x07 0x46 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x02 0x48 0xc7 0x70 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x18 0x00 0x65 0x00 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x19 0x00 0x65 0x00 -# CHECK: neg.d $f12,$f14 -0x87 0x39 0x20 0x46 +# CHECK: neg.d $f12, $f14 +0x07 0x73 0x20 0x46 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 -# CHECK: neg v1,a1 -0x22 0x18 0x05 0x00 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 -# CHECK: not v1,a1 -0x27 0x18 0xa0 0x00 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 -# CHECK: rdhwr a2,$29 -0x3b 0xe8 0x06 0x7c - -# CHECK: ror t1,a2,0x7 +# CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 -# CHECK: rorv t1,a2,a3 +# CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 -# CHECK: round.w.d $f12,$f14 -0x8c 0x39 0x20 0x46 +# CHECK: round.w.d $f12, $f14 +0x0c 0x73 0x20 0x46 -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 -# CHECK: seb a2,a3 +# CHECK: seb $6, $7 0x20 0x34 0x07 0x7c -# CHECK: seh a2,a3 +# CHECK: seh $6, $7 0x20 0x36 0x07 0x7c -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0xc0 0x21 0x03 0x00 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x04 0x10 0xa3 0x00 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x2a 0x18 0x65 0x00 -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x67 0x00 0x63 0x28 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x67 0x00 0x63 0x2c -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x2b 0x18 0x65 0x00 -# CHECK: sqrt.d $f12,$f14 -0x84 0x39 0x20 0x46 +# CHECK: sqrt.d $f12, $f14 +0x04 0x73 0x20 0x46 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x84 0x39 0x00 0x46 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0xc3 0x21 0x03 0x00 -# CHECK: sra a0,v1,0x7 -0xc3 0x21 0x03 0x00 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x07 0x10 0xa3 0x00 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0xc2 0x21 0x03 0x00 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x06 0x10 0xa3 0x00 -# CHECK: sub.d $f9,$f12,$f14 -0x41 0x32 0x27 0x46 +# CHECK: sub.d $f8, $f12, $f14 +0x01 0x62 0x2e 0x46 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x41 0x32 0x07 0x46 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x22 0x48 0xc7 0x00 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xe4 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0x10 0x00 0xa4 0xa8 + +# CHECK: swr $6, 16($7) +0x10 0x00 0xe6 0xb8 + +# CHECK: sync 7 0xcf 0x01 0x00 0x00 -# CHECK: trunc.w.d $f12,$f14 -0x8d 0x39 0x20 0x46 +# CHECK: trunc.w.d $f12, $f14 +0x0d 0x73 0x20 0x46 -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x8d 0x39 0x00 0x46 -# CHECK: wsbh a2,a3 +# CHECK: wsbh $6, $7 0xa0 0x30 0x07 0x7c -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x26 0x18 0x65 0x00 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index 1c7447a815fcb..095ed181ba819 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0x67 0x4b 0x7c 0xcd
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x00 0x2b 0xd0 0x2d
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x01 0x38 0x00 0x1f
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x44 0x22 0x70 0x00
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x44 0xb7 0x28 0x00
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x01 0x7a 0x00 0x1c
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x00 0x18 0x1c 0x78
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0x00 0x01 0x0f 0xbb
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x03 0xc1 0x08 0x17
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x00 0x1c 0x56 0x3a
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0x8c 0x3b 0xc4 0xcd
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x3c 0x01 0x00 0x01
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x9c 0x63 0xf9 0x2e
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x3c 0x1f 0x00 0x01
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xac 0x3a 0xc4 0xc9
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0xdc 0x1a 0x0f 0x76
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0xfc 0x06 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index dd87522b083f8..c4e5591da4f95 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0xcd 0x7c 0x4b 0x67
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x2d 0xd0 0x2b 0x00
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x1e 0x00 0x56 0x03
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x1f 0x00 0x38 0x01
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x00 0x70 0x22 0x44
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x00 0x28 0xb7 0x44
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x1c 0x00 0x7a 0x01
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x1d 0x00 0xed 0x02
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x78 0x1c 0x18 0x00
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x14 0xe0 0x1b 0x03
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0xbb 0x0f 0x01 0x00
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x17 0x08 0xc1 0x03
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x3a 0x56 0x1c 0x00
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x16 0xe0 0xea 0x02
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x2f 0xe0 0x78 0x03
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0xcd 0xc4 0x3b 0x8c
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x01 0x00 0x01 0x3c
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x2e 0xf9 0x63 0x9c
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x01 0x00 0x1f 0x3c
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xc9 0xc4 0x3a 0xac
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0x76 0x0f 0x1a 0xdc
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0x67 0x45 0x06 0xfc
diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt index 26bc94d65b55e..41808c724e247 100644 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0x67 0x4b 0x7c 0xcd
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x00 0x2b 0xd0 0x2d
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x01 0x38 0x00 0x1f
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x44 0x22 0x70 0x00
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x44 0xb7 0x28 0x00
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x01 0x7a 0x00 0x1c
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x00 0x18 0x1c 0x78
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0x00 0x01 0x0f 0xbb
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x03 0xc1 0x08 0x17
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x00 0x1c 0x56 0x3a
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0x8c 0x3b 0xc4 0xcd
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x3c 0x01 0x00 0x01
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x9c 0x63 0xf9 0x2e
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x3c 0x1f 0x00 0x01
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xac 0x3a 0xc4 0xc9
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0xdc 0x1a 0x0f 0x76
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0xfc 0x06 0x45 0x67
-# CHECK: dclo t1,t8
+# CHECK: dclo $9, $24
0x73 0x09 0x48 0x25
-# CHECK: dclz k0,t1
+# CHECK: dclz $26, $9
0x71 0x3a 0xd0 0x24
-# CHECK: dext a3,gp,0x1d,0x1f
+# CHECK: dext $7, $gp, 29, 31
0x7f 0x87 0xf7 0x43
-# CHECK: dins s4,gp,0xf,0x1
+# CHECK: dins $20, $gp, 15, 1
0x7f 0x94 0x7b 0xc7
-# CHECK: dsbh a3,gp
+# CHECK: dsbh $7, $gp
0x7c 0x1c 0x38 0xa4
-# CHECK: dshd v1,t6
+# CHECK: dshd $3, $14
0x7c 0x0e 0x19 0x64
-# CHECK: drotr s4,k1,0x6
+# CHECK: drotr $20, $27, 6
0x00 0x3b 0xa1 0xba
-# CHECK: drotrv t8,s7,a1
+# CHECK: drotrv $24, $23, $5
0x00 0xb7 0xc0 0x56
diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt index 81a7c66d1a210..4987f80af9d84 100644 --- a/test/MC/Disassembler/Mips/mips64r2_le.txt +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0xcd 0x7c 0x4b 0x67
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x2d 0xd0 0x2b 0x00
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x1e 0x00 0x56 0x03
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x1f 0x00 0x38 0x01
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x00 0x70 0x22 0x44
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x00 0x28 0xb7 0x44
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x1c 0x00 0x7a 0x01
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x1d 0x00 0xed 0x02
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x78 0x1c 0x18 0x00
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x14 0xe0 0x1b 0x03
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0xbb 0x0f 0x01 0x00
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x17 0x08 0xc1 0x03
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x3a 0x56 0x1c 0x00
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x16 0xe0 0xea 0x02
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x2f 0xe0 0x78 0x03
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0xcd 0xc4 0x3b 0x8c
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x01 0x00 0x01 0x3c
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x2e 0xf9 0x63 0x9c
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x01 0x00 0x1f 0x3c
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xc9 0xc4 0x3a 0xac
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0x76 0x0f 0x1a 0xdc
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0x67 0x45 0x06 0xfc
-# CHECK: dclo t1,t8
+# CHECK: dclo $9, $24
0x25 0x48 0x09 0x73
-# CHECK: dclz k0,t1
+# CHECK: dclz $26, $9
0x24 0xd0 0x3a 0x71
-# CHECK: dext a3,gp,0x1d,0x1f
+# CHECK: dext $7, $gp, 29, 31
0x43 0xf7 0x87 0x7f
-# CHECK: dins s4,gp,0xf,0x1
+# CHECK: dins $20, $gp, 15, 1
0xc7 0x7b 0x94 0x7f
-# CHECK: dsbh a3,gp
+# CHECK: dsbh $7, $gp
0xa4 0x38 0x1c 0x7c
-# CHECK: dshd v1,t6
+# CHECK: dshd $3, $14
0x64 0x19 0x0e 0x7c
-# CHECK: drotr s4,k1,0x6
+# CHECK: drotr $20, $27, 6
0xba 0xa1 0x3b 0x00
-# CHECK: drotrv t8,s7,a1
+# CHECK: drotrv $24, $23, $5
0x56 0xc0 0xb7 0x00
diff --git a/test/MC/Disassembler/X86/enhanced.txt b/test/MC/Disassembler/X86/enhanced.txt index 752ab179af669..deff735b69dbc 100644 --- a/test/MC/Disassembler/X86/enhanced.txt +++ b/test/MC/Disassembler/X86/enhanced.txt @@ -1,10 +1,10 @@ -# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s -# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606 +# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/112](pc)=18446744073709551606 0x0f 0x85 0xf6 0xff 0xff 0xff -# CHECK: [o:movq][w: ][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8 +# CHECK: [o:movq][w: ][1-r:%gs=r64][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r109] <mov> 0:[RCX/109]=0 1:[GS/64]=8 0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00 -# CHECK: [o:xorps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +# CHECK: [o:xorps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 0x0f 0x57 0xd1 -# CHECK: [o:andps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +# CHECK: [o:andps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 0x0f 0x54 0xd1 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index a5dbcf29b9647..27694cd014461 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -105,3 +105,8 @@ # CHECK: retf 0x66 0xcb +# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0 +0xc4 0xe2 0xfd 0x91 0x14 0x4f + +# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 +0xc4 0x02 0x39 0x90 0x14 0x4f diff --git a/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt index 9feb54c517e4f..31a3804decccf 100644 --- a/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt +++ b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding" # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s. 0xc5 0xf0 0x50 0xc0 diff --git a/test/MC/Disassembler/X86/invalid-cmp-imm.txt b/test/MC/Disassembler/X86/invalid-cmp-imm.txt index bf8699b24f268..7b2ea2aa06c78 100644 --- a/test/MC/Disassembler/X86/invalid-cmp-imm.txt +++ b/test/MC/Disassembler/X86/invalid-cmp-imm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding" # This instruction would decode as cmpordps if the immediate byte was less than 8. 0x0f 0xc2 0xc7 0x08 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index c0e77d0698bd0..672d239243216 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -123,10 +123,10 @@ # CHECK: vcvtss2sil %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %rax +# CHECK: vcvtsd2siq %xmm0, %rax 0xc4 0xe1 0xfb 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) @@ -437,10 +437,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %rax +# CHECK: vcvtsd2siq %xmm0, %rax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -725,6 +725,30 @@ # CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21 +# CHECK: vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2 +0xc4 0xe2 0xf9 0x92 0x14 0x4f + +# CHECK: vgatherdpd %ymm0, (%rdi,%xmm1,2), %ymm2 +0xc4 0xe2 0xfd 0x92 0x14 0x4f + +# CHECK: vgatherqps %xmm8, (%r15,%xmm9,2), %xmm10 +0xc4 0x02 0x39 0x93 0x14 0x4f + +# CHECK: vgatherqps %xmm8, (%r15,%ymm9,2), %xmm10 +0xc4 0x02 0x3d 0x93 0x14 0x4f + +# CHECK: vpgatherdq %xmm0, (%rdi,%xmm1,2), %xmm2 +0xc4 0xe2 0xf9 0x90 0x14 0x4f + +# CHECK: vpgatherdq %ymm0, (%rdi,%xmm1,2), %ymm2 +0xc4 0xe2 0xfd 0x90 0x14 0x4f + +# CHECK: vpgatherqd %xmm8, (%r15,%xmm9,2), %xmm10 +0xc4 0x02 0x39 0x91 0x14 0x4f + +# CHECK: vpgatherqd %xmm8, (%r15,%ymm9,2), %xmm10 +0xc4 0x02 0x3d 0x91 0x14 0x4f + # rdar://8812056 lldb doesn't print the x86 lock prefix when disassembling # CHECK: lock # CHECK-NEXT: xaddq %rcx, %rbx diff --git a/test/MC/Disassembler/X86/truncated-input.txt b/test/MC/Disassembler/X86/truncated-input.txt index 34cf0382a74c4..83be1ca5db153 100644 --- a/test/MC/Disassembler/X86/truncated-input.txt +++ b/test/MC/Disassembler/X86/truncated-input.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning 0x00 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 739fa6a843f9d..899657b0d4a33 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -159,10 +159,10 @@ # CHECK: vcvtss2sil %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7b 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%eax) @@ -460,10 +460,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -612,3 +612,21 @@ # CHECK: shrxl %esi, %ebx, %edx 0xc4 0xe2 0x0b 0xf7 0xd3 + +# CHECK: extrq $2, $3, %xmm0 +0x66 0x0f 0x78 0xc0 0x03 0x02 + +# CHECK: extrq %xmm1, %xmm0 +0x66 0x0f 0x79 0xc1 + +# CHECK: insertq $6, $5, %xmm1, %xmm0 +0xf2 0x0f 0x78 0xc1 0x05 0x06 + +# CHECK: insertq %xmm1, %xmm0 +0xf2 0x0f 0x79 0xc1 + +# CHECK: movntsd %xmm0, (%edi) +0xf2 0x0f 0x2b 0x07 + +# CHECK: movntss %xmm0, (%edi) +0xf3 0x0f 0x2b 0x07 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index f4b8f46fa2e58..df449a403b895 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -61,3 +61,21 @@ # CHECK: cmpordsd 0xf2 0x0f 0xc2 0xc7 0x07 + +# CHECK: extrq $2, $3, %xmm0 +0x66 0x0f 0x78 0xc0 0x03 0x02 + +# CHECK: extrq %xmm1, %xmm0 +0x66 0x0f 0x79 0xc1 + +# CHECK: insertq $6, $5, %xmm1, %xmm0 +0xf2 0x0f 0x78 0xc1 0x05 0x06 + +# CHECK: insertq %xmm1, %xmm0 +0xf2 0x0f 0x79 0xc1 + +# CHECK: movntsd %xmm0, (%rdi) +0xf2 0x0f 0x2b 0x07 + +# CHECK: movntss %xmm0, (%rdi) +0xf3 0x0f 0x2b 0x07 diff --git a/test/MC/ELF/fde.s b/test/MC/ELF/fde.s new file mode 100644 index 0000000000000..52ee33f16fbc5 --- /dev/null +++ b/test/MC/ELF/fde.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc -filetype=obj %s -o %t.o -triple x86_64-pc-linux-gnu && llvm-objdump -s %t.o +# PR13581 + +# CHECK: Contents of section .debug_frame: +# CHECK-NEXT: 0000 14000000 ffffffff 01000178 100c0708 ...........x.... +# CHECK-NEXT: 0010 90010000 00000000 1c000000 00000000 ................ +# CHECK-NEXT: 0020 00000000 00000000 11000000 00000000 ................ +# CHECK-NEXT: 0030 410e1086 02430d06 A....C.. + +__cxx_global_var_init: # @__cxx_global_var_init + .cfi_startproc +.Lfunc_begin0: +# BB#0: # %entry + pushq %rbp +.Ltmp2: + .cfi_def_cfa_offset 16 +.Ltmp3: + .cfi_offset %rbp, -16 + movq %rsp, %rbp +.Ltmp4: + .cfi_def_cfa_register %rbp +.Ltmp5: + callq _Z2rsv@PLT + movl %eax, _ZL1i(%rip) + popq %rbp + ret + .cfi_endproc + .cfi_sections .debug_frame diff --git a/test/MC/ELF/version.s b/test/MC/ELF/version.s new file mode 100644 index 0000000000000..31e952afeb40b --- /dev/null +++ b/test/MC/ELF/version.s @@ -0,0 +1,17 @@ +// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +.version "1234" +.version "123" + +// CHECK: (('sh_name', 0x0000000c) # '.note' +// CHECK-NEXT: ('sh_type', 0x00000007) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000034) +// CHECK-NEXT: ('sh_size', 0x00000024) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000004) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '05000000 00000000 01000000 31323334 00000000 04000000 00000000 01000000 31323300') +// CHECK-NEXT: ), diff --git a/test/MC/MachO/ARM/data-in-code.s b/test/MC/MachO/ARM/data-in-code.s new file mode 100644 index 0000000000000..bbcb9aabde5c2 --- /dev/null +++ b/test/MC/MachO/ARM/data-in-code.s @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -triple armv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s + .text +_foo: +@ CHECK: # DICE 0 +@ CHECK: ('offset', 0) +@ CHECK: ('length', 4) +@ CHECK: ('kind', 1) +@ CHECK: # DICE 1 +@ CHECK: ('offset', 4) +@ CHECK: ('length', 4) +@ CHECK: ('kind', 4) +@ CHECK: # DICE 2 +@ CHECK: ('offset', 8) +@ CHECK: ('length', 2) +@ CHECK: ('kind', 3) +@ CHECK: # DICE 3 +@ CHECK: ('offset', 10) +@ CHECK: ('length', 1) +@ CHECK: ('kind', 2) + +.data_region + .long 10 +.end_data_region +.data_region jt32 + .long 1 +.end_data_region +.data_region jt16 + .short 2 +.end_data_region +.data_region jt8 + .byte 3 +.end_data_region + diff --git a/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s b/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s new file mode 100644 index 0000000000000..7fcec529947f2 --- /dev/null +++ b/test/MC/MachO/ARM/llvm-objdump-macho-stripped.s @@ -0,0 +1,5 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d -macho -triple=thumbv7-apple-ios - | FileCheck %s + nop +# CHECK: 0: 00 bf nop +# We are checking that disassembly happens when there are no symbols. +# rdar://11460289 diff --git a/test/MC/MachO/ARM/llvm-objdump-macho.s b/test/MC/MachO/ARM/llvm-objdump-macho.s new file mode 100644 index 0000000000000..c8aec932ad6c9 --- /dev/null +++ b/test/MC/MachO/ARM/llvm-objdump-macho.s @@ -0,0 +1,20 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-ios -filetype=obj -o - < %s | llvm-objdump -d -macho -triple=thumbv7-apple-ios - | FileCheck %s +.thumb +.thumb_func _fib +_fib: + push {r7, lr} + pop {r7, pc} +.thumb_func _main +_main: + push {r7, lr} + pop {r7, pc} + nop +# CHECK: _fib: +# CHECK: 0: 80 b5 push {r7, lr} +# CHECK: 2: 80 bd pop {r7, pc} +# CHECK: _main: +# CHECK: 4: 80 b5 push {r7, lr} +# CHECK: 6: 80 bd pop {r7, pc} +# CHECK: 8: 00 bf nop +# We are checking that second function is fully disassembled. +# rdar://11426465 diff --git a/test/MC/MachO/ARM/thumb-bl-jbits.s b/test/MC/MachO/ARM/thumb-bl-jbits.s new file mode 100644 index 0000000000000..9657968db5e4c --- /dev/null +++ b/test/MC/MachO/ARM/thumb-bl-jbits.s @@ -0,0 +1,19 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -filetype=obj -o - < %s | macho-dump --dump-section-data | FileCheck %s +.thumb +.thumb_func t +t: nop + +.data +.space 4441096 - 4 - 2 + +.section __TEXT, __branch, regular, pure_instructions +.thumb +.thumb_func b +b: + bl t +# CHECK: '_section_data', 'c3f7fcf5' +# We are checking that the branch and link instruction which is: +# bl #-4441096 +# has it displacement encoded correctly with respect to the J1 and J2 bits when +# the branch is assembled with a label not a displacement. +# rdar://10149689 diff --git a/test/MC/MachO/ARM/thumb2-movw-fixup.s b/test/MC/MachO/ARM/thumb2-movw-fixup.s new file mode 100644 index 0000000000000..57973a874467f --- /dev/null +++ b/test/MC/MachO/ARM/thumb2-movw-fixup.s @@ -0,0 +1,44 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s + +@ rdar://10038370 + + .syntax unified + .text + .align 2 + .code 16 + .thumb_func _foo + movw r2, :lower16:L1 + movt r2, :upper16:L1 + movw r12, :lower16:L2 + movt r12, :upper16:L2 + .space 70000 + + .data +L1: .long 0 +L2: .long 0 + +@ CHECK: ('_relocations', [ +@ CHECK: # Relocation 0 +@ CHECK: (('word-0', 0xc), +@ CHECK: ('word-1', 0x86000002)), +@ CHECK: # Relocation 1 +@ CHECK: (('word-0', 0x1184), +@ CHECK: ('word-1', 0x16ffffff)), +@ CHECK: # Relocation 2 +@ CHECK: (('word-0', 0x8), +@ CHECK: ('word-1', 0x84000002)), +@ CHECK: # Relocation 3 +@ CHECK: (('word-0', 0x1), +@ CHECK: ('word-1', 0x14ffffff)), +@ CHECK: # Relocation 4 +@ CHECK: (('word-0', 0x4), +@ CHECK: ('word-1', 0x86000002)), +@ CHECK: # Relocation 5 +@ CHECK: (('word-0', 0x1180), +@ CHECK: ('word-1', 0x16ffffff)), +@ CHECK: # Relocation 6 +@ CHECK: (('word-0', 0x0), +@ CHECK: ('word-1', 0x84000002)), +@ CHECK: # Relocation 7 +@ CHECK: (('word-0', 0x1), +@ CHECK: ('word-1', 0x14ffffff)), diff --git a/test/MC/MachO/previous.s b/test/MC/MachO/previous.s new file mode 100644 index 0000000000000..41077cd0c0d13 --- /dev/null +++ b/test/MC/MachO/previous.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - | FileCheck %s + +.text +// CHECK: .section __TEXT,__text + +.data +// CHECK: .section __DATA,__data + +.previous +// CHECK: .section __TEXT,__text + +.previous +// CHECK: .section __DATA,__data diff --git a/test/MC/MachO/pushsection.s b/test/MC/MachO/pushsection.s new file mode 100644 index 0000000000000..6881323a4df5b --- /dev/null +++ b/test/MC/MachO/pushsection.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - | FileCheck %s + +.text +// CHECK: .section __TEXT,__text + +.pushsection __DATA, __data +// CHECK: .section __DATA,__data + +.pushsection __TEXT, initcode +// CHECK: .section __TEXT,initcode + +.popsection +// CHECK: .section __DATA,__data + +.popsection +// CHECK: .section __TEXT,__text diff --git a/test/MC/Mips/elf-N64.ll b/test/MC/Mips/elf-N64.ll new file mode 100644 index 0000000000000..23ec53a2e26da --- /dev/null +++ b/test/MC/Mips/elf-N64.ll @@ -0,0 +1,39 @@ +; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check for N64 relocation production. +; +; ModuleID = '../hello.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v64:64:64-n32" +target triple = "mips64el-unknown-linux" + +@str = private unnamed_addr constant [12 x i8] c"hello world\00" + +define i32 @main() nounwind { +entry: +; Check that the appropriate relocations were created. + +; R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 +; CHECK: ('r_type3', 0x05) +; CHECK-NEXT: ('r_type2', 0x18) +; CHECK-NEXT: ('r_type', 0x07) + +; R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 +; CHECK: ('r_type3', 0x06) +; CHECK-NEXT: ('r_type2', 0x18) +; CHECK-NEXT: ('r_type', 0x07) + +; R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE +; CHECK: ('r_type3', 0x00) +; CHECK-NEXT: ('r_type2', 0x00) +; CHECK-NEXT: ('r_type', 0x14) + +; R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE +; CHECK: ('r_type3', 0x00) +; CHECK-NEXT: ('r_type2', 0x00) +; CHECK-NEXT: ('r_type', 0x15) + + %puts = tail call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @str, i64 0, i64 0)) + ret i32 0 + +} +declare i32 @puts(i8* nocapture) nounwind diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll index 71c69bb7afa71..7111debd11b18 100644 --- a/test/MC/Mips/elf-bigendian.ll +++ b/test/MC/Mips/elf-bigendian.ll @@ -1,4 +1,6 @@ -; RUN: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; DISABLE: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: false +; XFAIL: * ; Check that this is big endian. ; CHECK: ('e_indent[EI_DATA]', 0x02) diff --git a/test/MC/Mips/elf-objdump.s b/test/MC/Mips/elf-objdump.s new file mode 100644 index 0000000000000..6a5c2a5bf6faa --- /dev/null +++ b/test/MC/Mips/elf-objdump.s @@ -0,0 +1,11 @@ +// 32 bit big endian +// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s +// 32 bit little endian +// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s +// 64 bit big endian +// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s +// 64 bit little endian +// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s + +// We just want to see if llvm-objdump works at all. +// CHECK: .text diff --git a/test/MC/Mips/elf_basic.s b/test/MC/Mips/elf_basic.s index 7a79fa066be48..ffc3b112e502d 100644 --- a/test/MC/Mips/elf_basic.s +++ b/test/MC/Mips/elf_basic.s @@ -30,3 +30,6 @@ // CHECK-LE64: ('e_indent[EI_CLASS]', 0x02) // This is little endian. // CHECK-LE64: ('e_indent[EI_DATA]', 0x01) + +// Check that we are setting EI_OSABI to ELFOSABI_LINUX. +// CHECK-LE64: ('e_indent[EI_OSABI]', 0x03) diff --git a/test/MC/Mips/higher_highest.ll b/test/MC/Mips/higher_highest.ll new file mode 100644 index 0000000000000..81a89e3040e3d --- /dev/null +++ b/test/MC/Mips/higher_highest.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that the R_MIPS_HIGHER and R_MIPS_HIGHEST relocations were created. + +; CHECK: ('r_type', 0x1d) +; CHECK: ('r_type', 0x1d) +; CHECK: ('r_type', 0x1c) +; CHECK: ('r_type', 0x1c) + +@g0 = external global i32 + +define void @foo1(i32 %s) nounwind { +entry: + + %tobool = icmp eq i32 %s, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i32* @g0, align 4 + %add = add nsw i32 %0, 12 + store i32 %add, i32* @g0, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + diff --git a/test/MC/Mips/lea_64.ll b/test/MC/Mips/lea_64.ll new file mode 100644 index 0000000000000..2e7a37befc84a --- /dev/null +++ b/test/MC/Mips/lea_64.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \ +; RUN: | llvm-objdump -disassemble -triple mips64el - \ +; RUN: | FileCheck %s + +@p = external global i32* + +define void @f1() nounwind { +entry: +; CHECK: .text: +; CHECK-NOT: addiu {{[0-9,a-f]+}}, {{[0-9,a-f]+}}, {{[0-9]+}} + + %a = alloca [10 x i32], align 4 + %arraydecay = getelementptr inbounds [10 x i32]* %a, i64 0, i64 0 + store i32* %arraydecay, i32** @p, align 8 + ret void + +; CHECK: jr $ra +} diff --git a/test/MC/Mips/mips64shift.ll b/test/MC/Mips/mips64shift.ll new file mode 100644 index 0000000000000..7817b96fa594c --- /dev/null +++ b/test/MC/Mips/mips64shift.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s + + +define i64 @f3(i64 %a0) nounwind readnone { +entry: +; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shl = shl i64 %a0, 10 + ret i64 %shl +} + +define i64 @f4(i64 %a0) nounwind readnone { +entry: +; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shr = ashr i64 %a0, 10 + ret i64 %shr +} + +define i64 @f5(i64 %a0) nounwind readnone { +entry: +; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shr = lshr i64 %a0, 10 + ret i64 %shr +} + +define i64 @f6(i64 %a0) nounwind readnone { +entry: +; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shl = shl i64 %a0, 40 + ret i64 %shl +} + +define i64 @f7(i64 %a0) nounwind readnone { +entry: +; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shr = ashr i64 %a0, 40 + ret i64 %shr +} + +define i64 @f8(i64 %a0) nounwind readnone { +entry: +; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shr = lshr i64 %a0, 40 + ret i64 %shr +} + diff --git a/test/MC/Mips/multi-64bit-func.ll b/test/MC/Mips/multi-64bit-func.ll new file mode 100644 index 0000000000000..6e0d784e07f64 --- /dev/null +++ b/test/MC/Mips/multi-64bit-func.ll @@ -0,0 +1,23 @@ +; There is no real check here. If the test doesn't +; assert it passes. +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s +; Run it again without extra nop in delay slot +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -enable-mips-delay-filler < %s + +define i32 @bosco1(i32 %x) nounwind readnone { +entry: + %inc = add i32 %x, 1 + ret i32 %inc +} + +define i32 @bosco2(i32 %x) nounwind readnone { +entry: + %inc = add i32 %x, 1 + ret i32 %inc +} + +define i32 @bosco3(i32 %x) nounwind readnone { +entry: + %inc = add i32 %x, 1 + ret i32 %inc +} diff --git a/test/MC/Mips/r-mips-got-disp.ll b/test/MC/Mips/r-mips-got-disp.ll new file mode 100644 index 0000000000000..73396ac5139dd --- /dev/null +++ b/test/MC/Mips/r-mips-got-disp.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that the R_MIPS_GOT_DISP relocations were created. + +; CHECK: ('r_type', 0x13) + +@shl = global i64 1, align 8 +@.str = private unnamed_addr constant [8 x i8] c"0x%llx\0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i64* @shl, align 8 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i64 %0) nounwind + ret i32 0 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + diff --git a/test/MC/Mips/sext_64_32.ll b/test/MC/Mips/sext_64_32.ll new file mode 100644 index 0000000000000..e5c57b8c41d8c --- /dev/null +++ b/test/MC/Mips/sext_64_32.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s + +; Sign extend from 32 to 64 was creating nonsense opcodes + +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + +define i64 @foo(i32 %ival) nounwind readnone { +entry: + %conv = sext i32 %ival to i64 + ret i64 %conv +} + +; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 0 + +define i64 @foo_2(i32 %ival_2) nounwind readnone { +entry: + %conv_2 = zext i32 %ival_2 to i64 + ret i64 %conv_2 +} + diff --git a/test/MC/Mips/sym-offset.ll b/test/MC/Mips/sym-offset.ll index 59399358394bf..5162c913ad068 100644 --- a/test/MC/Mips/sym-offset.ll +++ b/test/MC/Mips/sym-offset.ll @@ -1,4 +1,6 @@ -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; DISABLED: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: false +; XFAIL: * ; FIXME: use assembler instead of llc when it becomes available. diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s index 7cd56777b0e9c..7edd26a1382f3 100644 --- a/test/MC/X86/intel-syntax.s +++ b/test/MC/X86/intel-syntax.s @@ -63,4 +63,6 @@ _main: mov ECX, DWORD PTR [4*ECX + _fnan] // CHECK: movq %fs:320, %rax mov RAX, QWORD PTR FS:[320] +// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1 + vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 ret diff --git a/test/MC/X86/x86-32-avx.s b/test/MC/X86/x86-32-avx.s index e13a8712f7d6e..586f3fe73c57b 100644 --- a/test/MC/X86/x86-32-avx.s +++ b/test/MC/X86/x86-32-avx.s @@ -2603,11 +2603,11 @@ // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] vcvttpd2dq %xmm1, %xmm5 -// CHECK: vcvttpd2dq %ymm2, %xmm5 +// CHECK: vcvttpd2dqy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0xe6,0xea] vcvttpd2dq %ymm2, %xmm5 -// CHECK: vcvttpd2dqx %xmm1, %xmm5 +// CHECK: vcvttpd2dq %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] vcvttpd2dqx %xmm1, %xmm5 @@ -2623,11 +2623,11 @@ // CHECK: encoding: [0xc5,0xfd,0xe6,0x08] vcvttpd2dqy (%eax), %xmm1 -// CHECK: vcvtpd2ps %ymm2, %xmm5 +// CHECK: vcvtpd2psy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0x5a,0xea] vcvtpd2ps %ymm2, %xmm5 -// CHECK: vcvtpd2psx %xmm1, %xmm5 +// CHECK: vcvtpd2ps %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xf9,0x5a,0xe9] vcvtpd2psx %xmm1, %xmm5 @@ -2643,7 +2643,7 @@ // CHECK: encoding: [0xc5,0xfd,0x5a,0x08] vcvtpd2psy (%eax), %xmm1 -// CHECK: vcvtpd2dq %ymm2, %xmm5 +// CHECK: vcvtpd2dqy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xff,0xe6,0xea] vcvtpd2dq %ymm2, %xmm5 @@ -2655,7 +2655,7 @@ // CHECK: encoding: [0xc5,0xff,0xe6,0x08] vcvtpd2dqy (%eax), %xmm1 -// CHECK: vcvtpd2dqx %xmm1, %xmm5 +// CHECK: vcvtpd2dq %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xfb,0xe6,0xe9] vcvtpd2dqx %xmm1, %xmm5 @@ -3103,21 +3103,21 @@ // CHECK: encoding: [0xc5,0xf8,0x77] vzeroupper -// CHECK: vcvtsd2si %xmm4, %ecx +// CHECK: vcvtsd2sil %xmm4, %ecx // CHECK: encoding: [0xc5,0xfb,0x2d,0xcc] - vcvtsd2si %xmm4, %ecx + vcvtsd2sil %xmm4, %ecx -// CHECK: vcvtsd2si (%ecx), %ecx +// CHECK: vcvtsd2sil (%ecx), %ecx // CHECK: encoding: [0xc5,0xfb,0x2d,0x09] - vcvtsd2si (%ecx), %ecx + vcvtsd2sil (%ecx), %ecx -// CHECK: vcvtsi2sdl (%ebp), %xmm0, %xmm7 +// CHECK: vcvtsi2sd (%ebp), %xmm0, %xmm7 // CHECK: encoding: [0xc5,0xfb,0x2a,0x7d,0x00] - vcvtsi2sdl (%ebp), %xmm0, %xmm7 + vcvtsi2sd (%ebp), %xmm0, %xmm7 -// CHECK: vcvtsi2sdl (%esp), %xmm0, %xmm7 +// CHECK: vcvtsi2sd (%esp), %xmm0, %xmm7 // CHECK: encoding: [0xc5,0xfb,0x2a,0x3c,0x24] - vcvtsi2sdl (%esp), %xmm0, %xmm7 + vcvtsi2sd (%esp), %xmm0, %xmm7 // CHECK: vlddqu (%eax), %ymm2 // CHECK: encoding: [0xc5,0xff,0xf0,0x10] diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s index 6c27b8590b524..0824916519277 100644 --- a/test/MC/X86/x86-32-coverage.s +++ b/test/MC/X86/x86-32-coverage.s @@ -19626,3 +19626,29 @@ dppd $0x81, %xmm2, %xmm1 // CHECK: insertps $129, %xmm2, %xmm1 insertps $0x81, %xmm2, %xmm1 + +// PR13253 handle implicit optional third argument that must always be xmm0 +// CHECK: pblendvb %xmm2, %xmm1 +pblendvb %xmm2, %xmm1 +// CHECK: pblendvb %xmm2, %xmm1 +pblendvb %xmm0, %xmm2, %xmm1 +// CHECK: pblendvb (%eax), %xmm1 +pblendvb (%eax), %xmm1 +// CHECK: pblendvb (%eax), %xmm1 +pblendvb %xmm0, (%eax), %xmm1 +// CHECK: blendvpd %xmm2, %xmm1 +blendvpd %xmm2, %xmm1 +// CHECK: blendvpd %xmm2, %xmm1 +blendvpd %xmm0, %xmm2, %xmm1 +// CHECK: blendvpd (%eax), %xmm1 +blendvpd (%eax), %xmm1 +// CHECK: blendvpd (%eax), %xmm1 +blendvpd %xmm0, (%eax), %xmm1 +// CHECK: blendvps %xmm2, %xmm1 +blendvps %xmm2, %xmm1 +// CHECK: blendvps %xmm2, %xmm1 +blendvps %xmm0, %xmm2, %xmm1 +// CHECK: blendvps (%eax), %xmm1 +blendvps (%eax), %xmm1 +// CHECK: blendvps (%eax), %xmm1 +blendvps %xmm0, (%eax), %xmm1 diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s index bd5559a52810b..46ff9ead39bfc 100644 --- a/test/MC/X86/x86_64-avx-encoding.s +++ b/test/MC/X86/x86_64-avx-encoding.s @@ -3368,11 +3368,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] vcvttpd2dq %xmm11, %xmm10 -// CHECK: vcvttpd2dq %ymm12, %xmm10 +// CHECK: vcvttpd2dqy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xd4] vcvttpd2dq %ymm12, %xmm10 -// CHECK: vcvttpd2dqx %xmm11, %xmm10 +// CHECK: vcvttpd2dq %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] vcvttpd2dqx %xmm11, %xmm10 @@ -3388,11 +3388,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0xe6,0x18] vcvttpd2dqy (%rax), %xmm11 -// CHECK: vcvtpd2ps %ymm12, %xmm10 +// CHECK: vcvtpd2psy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xd4] vcvtpd2ps %ymm12, %xmm10 -// CHECK: vcvtpd2psx %xmm11, %xmm10 +// CHECK: vcvtpd2ps %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xd3] vcvtpd2psx %xmm11, %xmm10 @@ -3408,7 +3408,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0x5a,0x18] vcvtpd2psy (%rax), %xmm11 -// CHECK: vcvtpd2dq %ymm12, %xmm10 +// CHECK: vcvtpd2dqy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xd4] vcvtpd2dq %ymm12, %xmm10 @@ -3420,7 +3420,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7f,0xe6,0x18] vcvtpd2dqy (%rax), %xmm11 -// CHECK: vcvtpd2dqx %xmm11, %xmm10 +// CHECK: vcvtpd2dq %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xd3] vcvtpd2dqx %xmm11, %xmm10 @@ -3860,29 +3860,29 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc4,0x63,0x2d,0x06,0x18,0x07] vperm2f128 $7, (%rax), %ymm10, %ymm11 -// CHECK: vcvtsd2si %xmm8, %r8d +// CHECK: vcvtsd2sil %xmm8, %r8d // CHECK: encoding: [0xc4,0x41,0x7b,0x2d,0xc0] - vcvtsd2si %xmm8, %r8d + vcvtsd2sil %xmm8, %r8d -// CHECK: vcvtsd2si (%rcx), %ecx +// CHECK: vcvtsd2sil (%rcx), %ecx // CHECK: encoding: [0xc5,0xfb,0x2d,0x09] - vcvtsd2si (%rcx), %ecx + vcvtsd2sil (%rcx), %ecx -// CHECK: vcvtss2si %xmm4, %rcx +// CHECK: vcvtss2siq %xmm4, %rcx // CHECK: encoding: [0xc4,0xe1,0xfa,0x2d,0xcc] - vcvtss2si %xmm4, %rcx + vcvtss2siq %xmm4, %rcx -// CHECK: vcvtss2si (%rcx), %r8 +// CHECK: vcvtss2siq (%rcx), %r8 // CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0x01] - vcvtss2si (%rcx), %r8 + vcvtss2siq (%rcx), %r8 -// CHECK: vcvtsi2sdl %r8d, %xmm8, %xmm15 +// CHECK: vcvtsi2sd %r8d, %xmm8, %xmm15 // CHECK: encoding: [0xc4,0x41,0x3b,0x2a,0xf8] - vcvtsi2sdl %r8d, %xmm8, %xmm15 + vcvtsi2sd %r8d, %xmm8, %xmm15 -// CHECK: vcvtsi2sdl (%rbp), %xmm8, %xmm15 +// CHECK: vcvtsi2sd (%rbp), %xmm8, %xmm15 // CHECK: encoding: [0xc5,0x3b,0x2a,0x7d,0x00] - vcvtsi2sdl (%rbp), %xmm8, %xmm15 + vcvtsi2sd (%rbp), %xmm8, %xmm15 // CHECK: vcvtsi2sdq %rcx, %xmm4, %xmm6 // CHECK: encoding: [0xc4,0xe1,0xdb,0x2a,0xf1] @@ -3900,21 +3900,21 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc4,0xe1,0xda,0x2a,0x31] vcvtsi2ssq (%rcx), %xmm4, %xmm6 -// CHECK: vcvttsd2si %xmm4, %rcx +// CHECK: vcvttsd2siq %xmm4, %rcx // CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0xcc] - vcvttsd2si %xmm4, %rcx + vcvttsd2siq %xmm4, %rcx -// CHECK: vcvttsd2si (%rcx), %rcx +// CHECK: vcvttsd2siq (%rcx), %rcx // CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0x09] - vcvttsd2si (%rcx), %rcx + vcvttsd2siq (%rcx), %rcx -// CHECK: vcvttss2si %xmm4, %rcx +// CHECK: vcvttss2siq %xmm4, %rcx // CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0xcc] - vcvttss2si %xmm4, %rcx + vcvttss2siq %xmm4, %rcx -// CHECK: vcvttss2si (%rcx), %rcx +// CHECK: vcvttss2siq (%rcx), %rcx // CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0x09] - vcvttss2si (%rcx), %rcx + vcvttss2siq (%rcx), %rcx // CHECK: vlddqu (%rax), %ymm12 // CHECK: encoding: [0xc5,0x7f,0xf0,0x20] @@ -4121,3 +4121,67 @@ _foo: _foo2: nop vblendvps %ymm1, _foo2(%rip), %ymm0, %ymm0 + +// CHECK: vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0xf9,0x92,0x14,0x4f] + vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2 + +// CHECK: vgatherqpd %xmm0, (%rdi,%xmm1,2), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0xf9,0x93,0x14,0x4f] + vgatherqpd %xmm0, (%rdi,%xmm1,2), %xmm2 + +// CHECK: vgatherdpd %ymm0, (%rdi,%xmm1,2), %ymm2 +// CHECK: encoding: [0xc4,0xe2,0xfd,0x92,0x14,0x4f] + vgatherdpd %ymm0, (%rdi,%xmm1,2), %ymm2 + +// CHECK: vgatherqpd %ymm0, (%rdi,%ymm1,2), %ymm2 +// CHECK: encoding: [0xc4,0xe2,0xfd,0x93,0x14,0x4f] + vgatherqpd %ymm0, (%rdi,%ymm1,2), %ymm2 + +// CHECK: vgatherdps %xmm8, (%r15,%xmm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x39,0x92,0x14,0x4f] + vgatherdps %xmm8, (%r15,%xmm9,2), %xmm10 + +// CHECK: vgatherqps %xmm8, (%r15,%xmm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x39,0x93,0x14,0x4f] + vgatherqps %xmm8, (%r15,%xmm9,2), %xmm10 + +// CHECK: vgatherdps %ymm8, (%r15,%ymm9,2), %ymm10 +// CHECK: encoding: [0xc4,0x02,0x3d,0x92,0x14,0x4f] + vgatherdps %ymm8, (%r15,%ymm9,2), %ymm10 + +// CHECK: vgatherqps %xmm8, (%r15,%ymm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x3d,0x93,0x14,0x4f] + vgatherqps %xmm8, (%r15,%ymm9,2), %xmm10 + +// CHECK: vpgatherdq %xmm0, (%rdi,%xmm1,2), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0xf9,0x90,0x14,0x4f] + vpgatherdq %xmm0, (%rdi,%xmm1,2), %xmm2 + +// CHECK: vpgatherqq %xmm0, (%rdi,%xmm1,2), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0xf9,0x91,0x14,0x4f] + vpgatherqq %xmm0, (%rdi,%xmm1,2), %xmm2 + +// CHECK: vpgatherdq %ymm0, (%rdi,%xmm1,2), %ymm2 +// CHECK: encoding: [0xc4,0xe2,0xfd,0x90,0x14,0x4f] + vpgatherdq %ymm0, (%rdi,%xmm1,2), %ymm2 + +// CHECK: vpgatherqq %ymm0, (%rdi,%ymm1,2), %ymm2 +// CHECK: encoding: [0xc4,0xe2,0xfd,0x91,0x14,0x4f] + vpgatherqq %ymm0, (%rdi,%ymm1,2), %ymm2 + +// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x39,0x90,0x14,0x4f] + vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm10 + +// CHECK: vpgatherqd %xmm8, (%r15,%xmm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x39,0x91,0x14,0x4f] + vpgatherqd %xmm8, (%r15,%xmm9,2), %xmm10 + +// CHECK: vpgatherdd %ymm8, (%r15,%ymm9,2), %ymm10 +// CHECK: encoding: [0xc4,0x02,0x3d,0x90,0x14,0x4f] + vpgatherdd %ymm8, (%r15,%ymm9,2), %ymm10 + +// CHECK: vpgatherqd %xmm8, (%r15,%ymm9,2), %xmm10 +// CHECK: encoding: [0xc4,0x02,0x3d,0x91,0x14,0x4f] + vpgatherqd %xmm8, (%r15,%ymm9,2), %xmm10 diff --git a/test/MC/X86/x86_64-sse4a.s b/test/MC/X86/x86_64-sse4a.s new file mode 100644 index 0000000000000..e5ed69e5b2c3c --- /dev/null +++ b/test/MC/X86/x86_64-sse4a.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +extrq $2, $3, %xmm0 +# CHECK: extrq $2, $3, %xmm0 +# CHECK: encoding: [0x66,0x0f,0x78,0xc0,0x03,0x02] + +extrq %xmm1, %xmm0 +# CHECK: extrq %xmm1, %xmm0 +# CHECK: encoding: [0x66,0x0f,0x79,0xc1] + +insertq $6, $5, %xmm1, %xmm0 +# CHECK: insertq $6, $5, %xmm1, %xmm0 +# CHECK: encoding: [0xf2,0x0f,0x78,0xc1,0x05,0x06] + +insertq %xmm1, %xmm0 +# CHECK: insertq %xmm1, %xmm0 +# CHECK: encoding: [0xf2,0x0f,0x79,0xc1] + +movntsd %xmm0, (%rdi) +# CHECK: movntsd %xmm0, (%rdi) +# CHECK: encoding: [0xf2,0x0f,0x2b,0x07] + +movntss %xmm0, (%rdi) +# CHECK: movntss %xmm0, (%rdi) +# CHECK: encoding: [0xf3,0x0f,0x2b,0x07] |