diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-07-05 14:21:36 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-07-05 14:21:36 +0000 |
| commit | 1a82d4c088707c791c792f6822f611b47a12bdfe (patch) | |
| tree | 7c411f9b5d807f7f204fdd16965d8925a82b6d18 /test | |
| parent | 3a0822f094b578157263e04114075ad7df81db41 (diff) | |
Notes
Diffstat (limited to 'test')
300 files changed, 28089 insertions, 7723 deletions
diff --git a/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll b/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll new file mode 100644 index 0000000000000..01782e0f2c47c --- /dev/null +++ b/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll @@ -0,0 +1,26 @@ +; RUN: opt -S -disable-output -passes=print-cg < %s 2>&1 | FileCheck %s + +declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) +declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) + +define private void @f() { + ret void +} + +define void @calls_statepoint(i8 addrspace(1)* %arg) gc "statepoint-example" { +; CHECK: Call edges in function: calls_statepoint +; CHECK-NEXT: -> f +entry: + %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)* + %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @f, i32 0, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg) + ret void +} + +define void @calls_patchpoint() { +; CHECK: Call edges in function: calls_patchpoint +; CHECK-NEXT: -> f +entry: + %c = bitcast void()* @f to i8* + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %c, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1) + ret void +} diff --git a/test/Analysis/LoopAccessAnalysis/non-wrapping-pointer.ll b/test/Analysis/LoopAccessAnalysis/non-wrapping-pointer.ll new file mode 100644 index 0000000000000..0de1cd1bea6de --- /dev/null +++ b/test/Analysis/LoopAccessAnalysis/non-wrapping-pointer.ll @@ -0,0 +1,41 @@ +; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s + +; For this loop: +; for (int i = 0; i < n; i++) +; A[2 * i] = A[2 * i] + B[i]; +; +; , SCEV is unable to prove that A[2 * i] does not overflow. However, +; analyzing the IR helps us to conclude it and in turn allow dependence +; analysis. + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; CHECK: Memory dependences are safe{{$}} + +define void @f(i16* noalias %a, + i16* noalias %b, i64 %N) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %ind = phi i64 [ 0, %entry ], [ %inc, %for.body ] + + %mul = mul nuw nsw i64 %ind, 2 + + %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %mul + %loadA = load i16, i16* %arrayidxA, align 2 + + %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %ind + %loadB = load i16, i16* %arrayidxB, align 2 + + %add = mul i16 %loadA, %loadB + + store i16 %add, i16* %arrayidxA, align 2 + + %inc = add nuw nsw i64 %ind, 1 + %exitcond = icmp eq i64 %inc, %N + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/Assembler/dimodule.ll b/test/Assembler/dimodule.ll new file mode 100644 index 0000000000000..994bc12b68182 --- /dev/null +++ b/test/Assembler/dimodule.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s + +; CHECK: !named = !{!0, !1, !2, !1} +!named = !{!0, !1, !2, !3} + +!0 = distinct !{} + +; CHECK: !1 = !DIModule(scope: !0, name: "Module") +!1 = !DIModule(scope: !0, name: "Module") + +; CHECK: !2 = !DIModule(scope: !0, name: "Module", configMacros: "-DNDEBUG", includePath: "/usr/include", isysroot: "/") +!2 = !DIModule(scope: !0, name: "Module", configMacros: "-DNDEBUG", includePath: "/usr/include", isysroot: "/") + +!3 = !DIModule(scope: !0, name: "Module", configMacros: "") diff --git a/test/Bindings/llvm-c/disassemble.test b/test/Bindings/llvm-c/ARM/disassemble.test index bb7a9a01ab9a2..ffa7ebfe12052 100644 --- a/test/Bindings/llvm-c/disassemble.test +++ b/test/Bindings/llvm-c/ARM/disassemble.test @@ -19,25 +19,3 @@ arm-linux-android NULL 44 26 1f e5 0c 10 4b e2 02 20 81 e0 ;CHECK: sub r1, r11, #12 ;CHECK: 02 20 81 e0 ;CHECK: add r2, r1, r2 - -x86_64-linux-unknown NULL 48 83 c4 38 5b 5d 41 5c 41 5d 41 5e 41 5f c3 -;CHECK: triple: x86_64-linux-unknown, features: NULL -;CHECK: addq $56, %rsp -;CHECK: popq %rbx -;CHECK: popq %rbp -;CHECK: popq %r12 -;CHECK: popq %r13 -;CHECK: popq %r14 -;CHECK: popq %r15 -;CHECK: ret - -i686-apple-darwin NULL 0f b7 4c 24 0a e8 29 ce ff ff -;CHECK: triple: i686-apple-darwin, features: NULL -;CHECK: movzwl 10(%esp), %ecx -;CHECK: calll -12759 - -i686-linux-unknown NULL dd 44 24 04 d9 e1 c3 -;CHECK: triple: i686-linux-unknown, features: NULL -;CHECK: fldl 4(%esp) -;CHECK: fabs -;CHECK: ret diff --git a/test/Bindings/llvm-c/lit.local.cfg b/test/Bindings/llvm-c/ARM/lit.local.cfg index 75b22c06fb2f2..7c23e4f980130 100644 --- a/test/Bindings/llvm-c/lit.local.cfg +++ b/test/Bindings/llvm-c/ARM/lit.local.cfg @@ -1,4 +1,2 @@ -if not "X86" in config.root.targets: - config.unsupported = True if not "ARM" in config.root.targets: config.unsupported = True diff --git a/test/Bindings/llvm-c/X86/disassemble.test b/test/Bindings/llvm-c/X86/disassemble.test new file mode 100644 index 0000000000000..465b370a94fdc --- /dev/null +++ b/test/Bindings/llvm-c/X86/disassemble.test @@ -0,0 +1,23 @@ +; RUN: llvm-c-test --disassemble < %s | FileCheck %s + +x86_64-linux-unknown NULL 48 83 c4 38 5b 5d 41 5c 41 5d 41 5e 41 5f c3 +;CHECK: triple: x86_64-linux-unknown, features: NULL +;CHECK: addq $56, %rsp +;CHECK: popq %rbx +;CHECK: popq %rbp +;CHECK: popq %r12 +;CHECK: popq %r13 +;CHECK: popq %r14 +;CHECK: popq %r15 +;CHECK: ret + +i686-apple-darwin NULL 0f b7 4c 24 0a e8 29 ce ff ff +;CHECK: triple: i686-apple-darwin, features: NULL +;CHECK: movzwl 10(%esp), %ecx +;CHECK: calll -12759 + +i686-linux-unknown NULL dd 44 24 04 d9 e1 c3 +;CHECK: triple: i686-linux-unknown, features: NULL +;CHECK: fldl 4(%esp) +;CHECK: fabs +;CHECK: ret diff --git a/test/Bindings/llvm-c/X86/lit.local.cfg b/test/Bindings/llvm-c/X86/lit.local.cfg new file mode 100644 index 0000000000000..42bf50dcc13c3 --- /dev/null +++ b/test/Bindings/llvm-c/X86/lit.local.cfg @@ -0,0 +1,2 @@ +if not "X86" in config.root.targets: + config.unsupported = True diff --git a/test/Bitcode/Inputs/PR23310.bc b/test/Bitcode/Inputs/PR23310.bc Binary files differnew file mode 100644 index 0000000000000..cd1202f69f339 --- /dev/null +++ b/test/Bitcode/Inputs/PR23310.bc diff --git a/test/Bitcode/PR23310.test b/test/Bitcode/PR23310.test new file mode 100644 index 0000000000000..6b794716c3fe2 --- /dev/null +++ b/test/Bitcode/PR23310.test @@ -0,0 +1 @@ +RUN: llvm-dis -disable-output %p/Inputs/PR23310.bc diff --git a/test/CodeGen/AArch64/aarch-multipart.ll b/test/CodeGen/AArch64/aarch-multipart.ll new file mode 100644 index 0000000000000..fd42d6e8cd8eb --- /dev/null +++ b/test/CodeGen/AArch64/aarch-multipart.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -o - | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-os" + +declare <4 x double> @user_func(<4 x double>) #1 + +; Make sure we are not crashing on this code. +; CHECK-LABEL: caller_function +; CHECK: ret +define void @caller_function(<4 x double>, <4 x double>, <4 x double>, <4 x double>, <4 x double>) #1 { +entry: + %r = call <4 x double> @user_func(<4 x double> %4) + ret void +} + +attributes #1 = { nounwind readnone } + diff --git a/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll b/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll new file mode 100644 index 0000000000000..ea3b8fa557328 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll @@ -0,0 +1,197 @@ +; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic -lower-interleaved-accesses=true < %s | FileCheck %s + +; CHECK-LABEL: load_factor2: +; CHECK: ld2 { v0.8b, v1.8b }, [x0] +define <8 x i8> @load_factor2(<16 x i8>* %ptr) { + %wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4 + %strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %add = add nsw <8 x i8> %strided.v0, %strided.v1 + ret <8 x i8> %add +} + +; CHECK-LABEL: load_factor3: +; CHECK: ld3 { v0.4s, v1.4s, v2.4s }, [x0] +define <4 x i32> @load_factor3(i32* %ptr) { + %base = bitcast i32* %ptr to <12 x i32>* + %wide.vec = load <12 x i32>, <12 x i32>* %base, align 4 + %strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> + %strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> + %add = add nsw <4 x i32> %strided.v2, %strided.v1 + ret <4 x i32> %add +} + +; CHECK-LABEL: load_factor4: +; CHECK: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0] +define <4 x i32> @load_factor4(i32* %ptr) { + %base = bitcast i32* %ptr to <16 x i32>* + %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 + %strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> + %strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> + %add = add nsw <4 x i32> %strided.v0, %strided.v2 + ret <4 x i32> %add +} + +; CHECK-LABEL: store_factor2: +; CHECK: st2 { v0.8b, v1.8b }, [x0] +define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) { + %interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> + store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4 + ret void +} + +; CHECK-LABEL: store_factor3: +; CHECK: st3 { v0.4s, v1.4s, v2.4s }, [x0] +define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { + %base = bitcast i32* %ptr to <12 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> + store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_factor4: +; CHECK: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0] +define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { + %base = bitcast i32* %ptr to <16 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> + store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4 + ret void +} + +; The following cases test that interleaved access of pointer vectors can be +; matched to ldN/stN instruction. + +; CHECK-LABEL: load_ptrvec_factor2: +; CHECK: ld2 { v0.2d, v1.2d }, [x0] +define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) { + %base = bitcast i32** %ptr to <4 x i32*>* + %wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4 + %strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2> + ret <2 x i32*> %strided.v0 +} + +; CHECK-LABEL: load_ptrvec_factor3: +; CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] +define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { + %base = bitcast i32** %ptr to <6 x i32*>* + %wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4 + %strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5> + store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1 + %strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4> + store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2 + ret void +} + +; CHECK-LABEL: load_ptrvec_factor4: +; CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { + %base = bitcast i32** %ptr to <8 x i32*>* + %wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4 + %strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5> + %strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7> + store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1 + store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor2: +; CHECK: st2 { v0.2d, v1.2d }, [x0] +define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) { + %base = bitcast i32** %ptr to <4 x i32*>* + %interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> + store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor3: +; CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] +define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) { + %base = bitcast i32** %ptr to <6 x i32*>* + %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + %interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> + store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor4: +; CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] +define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) { + %base = bitcast i32* %ptr to <8 x i32*>* + %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> + store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4 + ret void +} + +; Following cases check that shuffle maskes with undef indices can be matched +; into ldN/stN instruction. + +; CHECK-LABEL: load_undef_mask_factor2: +; CHECK: ld2 { v0.4s, v1.4s }, [x0] +define <4 x i32> @load_undef_mask_factor2(i32* %ptr) { + %base = bitcast i32* %ptr to <8 x i32>* + %wide.vec = load <8 x i32>, <8 x i32>* %base, align 4 + %strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6> + %strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7> + %add = add nsw <4 x i32> %strided.v0, %strided.v1 + ret <4 x i32> %add +} + +; CHECK-LABEL: load_undef_mask_factor3: +; CHECK: ld3 { v0.4s, v1.4s, v2.4s }, [x0] +define <4 x i32> @load_undef_mask_factor3(i32* %ptr) { + %base = bitcast i32* %ptr to <12 x i32>* + %wide.vec = load <12 x i32>, <12 x i32>* %base, align 4 + %strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> + %strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> + %add = add nsw <4 x i32> %strided.v2, %strided.v1 + ret <4 x i32> %add +} + +; CHECK-LABEL: load_undef_mask_factor4: +; CHECK: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0] +define <4 x i32> @load_undef_mask_factor4(i32* %ptr) { + %base = bitcast i32* %ptr to <16 x i32>* + %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 + %strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef> + %strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef> + %add = add nsw <4 x i32> %strided.v0, %strided.v2 + ret <4 x i32> %add +} + +; CHECK-LABEL: store_undef_mask_factor2: +; CHECK: st2 { v0.4s, v1.4s }, [x0] +define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) { + %base = bitcast i32* %ptr to <8 x i32>* + %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7> + store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_undef_mask_factor3: +; CHECK: st3 { v0.4s, v1.4s, v2.4s }, [x0] +define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { + %base = bitcast i32* %ptr to <12 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> + store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_undef_mask_factor4: +; CHECK: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0] +define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { + %base = bitcast i32* %ptr to <16 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> + store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/commute-shifts.ll b/test/CodeGen/AMDGPU/commute-shifts.ll new file mode 100644 index 0000000000000..f88cf6470c4f0 --- /dev/null +++ b/test/CodeGen/AMDGPU/commute-shifts.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +; GCN-LABEL: {{^}}main: +; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1 + +define void @main() #0 { +main_body: + %0 = fptosi float undef to i32 + %1 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> undef, <32 x i8> undef, i32 2) + %2 = extractelement <4 x i32> %1, i32 0 + %3 = and i32 %0, 7 + %4 = shl i32 1, %3 + %5 = and i32 %2, %4 + %6 = icmp eq i32 %5, 0 + %.10 = select i1 %6, float 0.000000e+00, float undef + %7 = call i32 @llvm.SI.packf16(float undef, float %.10) + %8 = bitcast i32 %7 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %8, float undef, float %8) + ret void +} + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.SI.packf16(float, float) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/elf.ll b/test/CodeGen/AMDGPU/elf.ll index d0fd06a343798..90af6782c4b45 100644 --- a/test/CodeGen/AMDGPU/elf.ll +++ b/test/CodeGen/AMDGPU/elf.ll @@ -1,14 +1,16 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s -; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -march=amdgcn -mcpu=carrizo -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s ; Test that we don't try to produce a COFF file on windows -; RUN: llc < %s -mtriple=amdgcn-pc-mingw -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -mtriple=amdgcn-pc-mingw -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s -; ELF: Format: ELF32 +; ELF: Format: ELF64 +; ELF: OS/ABI: AMDGPU_HSA (0x40) +; ELF: Machine: EM_AMDGPU (0xE0) ; ELF: Name: .AMDGPU.config ; ELF: Type: SHT_PROGBITS diff --git a/test/CodeGen/AMDGPU/hsa.ll b/test/CodeGen/AMDGPU/hsa.ll index f9113399afe8a..653a6bb1b6098 100644 --- a/test/CodeGen/AMDGPU/hsa.ll +++ b/test/CodeGen/AMDGPU/hsa.ll @@ -1,10 +1,31 @@ -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -s -sd | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF + +; The SHT_NOTE section contains the output from the .hsa_code_object_* +; directives. + +; ELF: SHT_NOTE +; ELF: 0000: 04000000 08000000 01000000 414D4400 +; ELF: 0010: 01000000 00000000 04000000 1B000000 +; ELF: 0020: 03000000 414D4400 04000700 07000000 +; ELF: 0030: 00000000 00000000 414D4400 414D4447 +; ELF: 0040: 50550000 + +; HSA: .hsa_code_object_version 1,0 +; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" +; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" -; HSA: .section .hsa.version -; HSA-NEXT: .ascii "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0" ; HSA: {{^}}simple: +; HSA: .amd_kernel_code_t +; HSA: .end_amd_kernel_code_t +; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0 + ; Make sure we are setting the ATC bit: -; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000 +; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000 +; On VI+ we also need to set MTYPE = 2 +; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000 ; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0 define void @simple(i32 addrspace(1)* %out) { diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll index bcb7f870f1f42..f948c987b0385 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s +; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s ; FIXME: Enable for VI. diff --git a/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll new file mode 100644 index 0000000000000..ac9bedb2f8b5b --- /dev/null +++ b/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @@ -0,0 +1,37 @@ +; RUN: llc -march=amdgcn -mcpu=SI -o - %s | FileCheck %s +; Don't crash when the use of an undefined value is only detected by the +; register coalescer because it is hidden with subregister insert/extract. +target triple="amdgcn--" + +; CHECK-LABEL: foobar: +; CHECK: s_load_dword s2, s[0:1], 0x9 +; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, s2 +; CHECK-NEXT: s_and_saveexec_b64 s[2:3], s[0:1] +; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; BB0_1: +; CHECK: s_load_dword s6, s[0:1], 0xa +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, s6 +; BB0_2: +; CHECK: s_or_b64 exec, exec, s[2:3] +; CHECK-NEXT: s_mov_b32 s7, 0xf000 +; CHECK-NEXT: s_mov_b32 s6, -1 +; CHECK-NEXT: buffer_store_dword v1, s[4:7], 0 +; CHECK-NEXT: s_endpgm +define void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind { +entry: + %v0 = insertelement <4 x float> undef, float %a0, i32 0 + br i1 undef, label %ift, label %ife + +ift: + %v1 = insertelement <4 x float> undef, float %a1, i32 0 + br label %ife + +ife: + %val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ] + %v2 = extractelement <4 x float> %val, i32 1 + store float %v2, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/ARM/arm-interleaved-accesses.ll b/test/CodeGen/ARM/arm-interleaved-accesses.ll new file mode 100644 index 0000000000000..9a9885ccdd0c7 --- /dev/null +++ b/test/CodeGen/ARM/arm-interleaved-accesses.ll @@ -0,0 +1,204 @@ +; RUN: llc -mtriple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s + +; CHECK-LABEL: load_factor2: +; CHECK: vld2.8 {d16, d17}, [r0] +define <8 x i8> @load_factor2(<16 x i8>* %ptr) { + %wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4 + %strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %add = add nsw <8 x i8> %strided.v0, %strided.v1 + ret <8 x i8> %add +} + +; CHECK-LABEL: load_factor3: +; CHECK: vld3.32 {d16, d17, d18}, [r0] +define <2 x i32> @load_factor3(i32* %ptr) { + %base = bitcast i32* %ptr to <6 x i32>* + %wide.vec = load <6 x i32>, <6 x i32>* %base, align 4 + %strided.v2 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 2, i32 5> + %strided.v1 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 1, i32 4> + %add = add nsw <2 x i32> %strided.v2, %strided.v1 + ret <2 x i32> %add +} + +; CHECK-LABEL: load_factor4: +; CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! +; CHECK: vld4.32 {d17, d19, d21, d23}, [r0] +define <4 x i32> @load_factor4(i32* %ptr) { + %base = bitcast i32* %ptr to <16 x i32>* + %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 + %strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> + %strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> + %add = add nsw <4 x i32> %strided.v0, %strided.v2 + ret <4 x i32> %add +} + +; CHECK-LABEL: store_factor2: +; CHECK: vst2.8 {d16, d17}, [r0] +define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) { + %interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> + store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4 + ret void +} + +; CHECK-LABEL: store_factor3: +; CHECK: vst3.32 {d16, d18, d20}, [r0]! +; CHECK: vst3.32 {d17, d19, d21}, [r0] +define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { + %base = bitcast i32* %ptr to <12 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> + store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_factor4: +; CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! +; CHECK: vst4.32 {d17, d19, d21, d23}, [r0] +define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { + %base = bitcast i32* %ptr to <16 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> + store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4 + ret void +} + +; The following cases test that interleaved access of pointer vectors can be +; matched to ldN/stN instruction. + +; CHECK-LABEL: load_ptrvec_factor2: +; CHECK: vld2.32 {d16, d17}, [r0] +define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) { + %base = bitcast i32** %ptr to <4 x i32*>* + %wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4 + %strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2> + ret <2 x i32*> %strided.v0 +} + +; CHECK-LABEL: load_ptrvec_factor3: +; CHECK: vld3.32 {d16, d17, d18}, [r0] +define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { + %base = bitcast i32** %ptr to <6 x i32*>* + %wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4 + %strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5> + store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1 + %strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4> + store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2 + ret void +} + +; CHECK-LABEL: load_ptrvec_factor4: +; CHECK: vld4.32 {d16, d17, d18, d19}, [r0] +define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { + %base = bitcast i32** %ptr to <8 x i32*>* + %wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4 + %strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5> + %strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7> + store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1 + store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor2: +; CHECK: vst2.32 {d16, d17}, [r0] +define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) { + %base = bitcast i32** %ptr to <4 x i32*>* + %interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> + store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor3: +; CHECK: vst3.32 {d16, d17, d18}, [r0] +define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) { + %base = bitcast i32** %ptr to <6 x i32*>* + %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + %interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> + store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_ptrvec_factor4: +; CHECK: vst4.32 {d16, d17, d18, d19}, [r0] +define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) { + %base = bitcast i32* %ptr to <8 x i32*>* + %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> + store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4 + ret void +} + +; Following cases check that shuffle maskes with undef indices can be matched +; into ldN/stN instruction. + +; CHECK-LABEL: load_undef_mask_factor2: +; CHECK: vld2.32 {d16, d17, d18, d19}, [r0] +define <4 x i32> @load_undef_mask_factor2(i32* %ptr) { + %base = bitcast i32* %ptr to <8 x i32>* + %wide.vec = load <8 x i32>, <8 x i32>* %base, align 4 + %strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6> + %strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7> + %add = add nsw <4 x i32> %strided.v0, %strided.v1 + ret <4 x i32> %add +} + +; CHECK-LABEL: load_undef_mask_factor3: +; CHECK: vld3.32 {d16, d18, d20}, [r0]! +; CHECK: vld3.32 {d17, d19, d21}, [r0] +define <4 x i32> @load_undef_mask_factor3(i32* %ptr) { + %base = bitcast i32* %ptr to <12 x i32>* + %wide.vec = load <12 x i32>, <12 x i32>* %base, align 4 + %strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> + %strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> + %add = add nsw <4 x i32> %strided.v2, %strided.v1 + ret <4 x i32> %add +} + +; CHECK-LABEL: load_undef_mask_factor4: +; CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! +; CHECK: vld4.32 {d17, d19, d21, d23}, [r0] +define <4 x i32> @load_undef_mask_factor4(i32* %ptr) { + %base = bitcast i32* %ptr to <16 x i32>* + %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 + %strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef> + %strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef> + %add = add nsw <4 x i32> %strided.v0, %strided.v2 + ret <4 x i32> %add +} + +; CHECK-LABEL: store_undef_mask_factor2: +; CHECK: vst2.32 {d16, d17, d18, d19}, [r0] +define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) { + %base = bitcast i32* %ptr to <8 x i32>* + %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7> + store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_undef_mask_factor3: +; CHECK: vst3.32 {d16, d18, d20}, [r0]! +; CHECK: vst3.32 {d17, d19, d21}, [r0] +define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { + %base = bitcast i32* %ptr to <12 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> + store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4 + ret void +} + +; CHECK-LABEL: store_undef_mask_factor4: +; CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! +; CHECK: vst4.32 {d17, d19, d21, d23}, [r0] +define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { + %base = bitcast i32* %ptr to <16 x i32>* + %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> + store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4 + ret void +} diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 0cc4f230f2845..29c702304a3f1 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -51,6 +51,13 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST + +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16 + ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST @@ -1049,7 +1056,7 @@ ; CORTEX-R4F: .eabi_attribute 23, 3 ; CORTEX-R4F: .eabi_attribute 24, 1 ; CORTEX-R4F: .eabi_attribute 25, 1 -; CORTEX-R4F: .eabi_attribute 27, 1 +; CORTEX-R4F-NOT: .eabi_attribute 27, 1 ; CORTEX-R4F-NOT: .eabi_attribute 28 ; CORTEX-R4F-NOT: .eabi_attribute 36 ; CORTEX-R4F: .eabi_attribute 38, 1 @@ -1071,7 +1078,7 @@ ; CORTEX-R5: .eabi_attribute 23, 3 ; CORTEX-R5: .eabi_attribute 24, 1 ; CORTEX-R5: .eabi_attribute 25, 1 -; CORTEX-R5: .eabi_attribute 27, 1 +; CORTEX-R5-NOT: .eabi_attribute 27, 1 ; CORTEX-R5-NOT: .eabi_attribute 28 ; CORTEX-R5-NOT: .eabi_attribute 36 ; CORTEX-R5: .eabi_attribute 38, 1 @@ -1091,7 +1098,7 @@ ; CORTEX-R7: .eabi_attribute 7, 82 ; CORTEX-R7: .eabi_attribute 8, 1 ; CORTEX-R7: .eabi_attribute 9, 2 -; CORTEX-R7: .fpu vfpv3-d16 +; CORTEX-R7: .fpu vfpv3xd ; CORTEX-R7-NOT: .eabi_attribute 19 ;; We default to IEEE 754 compliance ; CORTEX-R7: .eabi_attribute 20, 1 @@ -1205,6 +1212,12 @@ ; CORTEX-A72-FAST-NOT: .eabi_attribute 22 ; CORTEX-A72-FAST: .eabi_attribute 23, 1 +; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16 +; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16 +; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd +; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16 +; GENERIC-FPU-NEON-FP16: .fpu neon-fp16 + ; GENERIC-ARMV8_1-A: .eabi_attribute 6, 14 ; GENERIC-ARMV8_1-A: .eabi_attribute 7, 65 ; GENERIC-ARMV8_1-A: .eabi_attribute 8, 1 diff --git a/test/CodeGen/ARM/fnattr-trap.ll b/test/CodeGen/ARM/fnattr-trap.ll new file mode 100644 index 0000000000000..492e31b4b9d16 --- /dev/null +++ b/test/CodeGen/ARM/fnattr-trap.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=arm-unknown-unknown | FileCheck %s -check-prefix=NOOPTION +; RUN: llc < %s -mtriple=arm-unknown-unknown -trap-func=trap_llc | FileCheck %s -check-prefix=TRAP + +; NOOPTION-LABEL: {{\_?}}foo0: +; NOOPTION: trap{{$}} + +; TRAP-LABEL: {{\_?}}foo0: +; TRAP: bl {{\_?}}trap_llc + +define void @foo0() { + call void @llvm.trap() + unreachable +} + +; NOOPTION-LABEL: {{\_?}}foo1: +; NOOPTION: bl {{\_?}}trap_func_attr0 + +; TRAP-LABEL: {{\_?}}foo1: +; TRAP: bl {{\_?}}trap_llc + +define void @foo1() { + call void @llvm.trap() #0 + unreachable +} + +; NOOPTION-LABEL: {{\_?}}foo2: +; NOOPTION: bl {{\_?}}trap_func_attr1 + +; TRAP-LABEL: {{\_?}}foo2: +; TRAP: bl {{\_?}}trap_llc + +define void @foo2() { + call void @llvm.trap() #1 + unreachable +} + +declare void @llvm.trap() nounwind + +attributes #0 = { "trap-func-name"="trap_func_attr0" } +attributes #1 = { "trap-func-name"="trap_func_attr1" } diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index a8070ea68aa2b..f3e13671ac37a 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -6,23 +6,24 @@ ; Magic ARM pair hints works best with linearscan / fast. -; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base -; register when interrupted or faulted. - @b = external global i64* -define i64 @t(i64 %a) nounwind readonly { -entry: -; A8-LABEL: t: -; A8: ldrd r2, r3, [r2] - -; M3-LABEL: t: -; M3-NOT: ldrd +; We use the following two to force values into specific registers. +declare i64* @get_ptr() +declare void @use_i64(i64 %v) - %0 = load i64*, i64** @b, align 4 - %1 = load i64, i64* %0, align 4 - %2 = mul i64 %1, %a - ret i64 %2 +define void @test_ldrd(i64 %a) nounwind readonly { +; CHECK-LABEL: test_ldrd: +; CHECK: bl{{x?}} _get_ptr +; A8: ldrd r0, r1, [r0] +; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base +; register when interrupted or faulted. +; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]] +; CHECK: bl{{x?}} _use_i64 + %ptr = call i64* @get_ptr() + %v = load i64, i64* %ptr, align 8 + call void @use_i64(i64 %v) + ret void } ; rdar://10435045 mixed LDRi8/LDRi12 diff --git a/test/CodeGen/ARM/load-store-flags.ll b/test/CodeGen/ARM/load-store-flags.ll new file mode 100644 index 0000000000000..5825a30109d08 --- /dev/null +++ b/test/CodeGen/ARM/load-store-flags.ll @@ -0,0 +1,43 @@ +; RUN: llc -mtriple=thumbv7-apple-ios7.0 -o - %s -verify-machineinstrs | FileCheck %s + +; The base register for the store is killed by the last instruction, but is +; actually also used during as part of the store itself. If an extra ADD is +; inserted, it should not kill the base. +define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) { +; CHECK-LABEL: test_base_kill: +; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4 +; CHECK: stm.w [[NEWBASE]], {r0, r1, r2} + + %addr.1 = getelementptr i32, i32* %addr, i32 1 + store i32 %v0, i32* %addr.1 + + %addr.2 = getelementptr i32, i32* %addr, i32 2 + store i32 %v1, i32* %addr.2 + + %addr.3 = getelementptr i32, i32* %addr, i32 3 + %val = ptrtoint i32* %addr to i32 + store i32 %val, i32* %addr.3 + + ret void +} + +; Similar, but it's not sufficient to look at just the last instruction (where +; liveness of the base is determined). An intervening instruction might be moved +; past it to form the STM. +define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) { +; CHECK-LABEL: test_base_kill_mid: +; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4 +; CHECK: stm.w [[NEWBASE]], {r0, r1, r2} + + %addr.1 = getelementptr i32, i32* %addr, i32 1 + store i32 %v0, i32* %addr.1 + + %addr.2 = getelementptr i32, i32* %addr, i32 2 + %val = ptrtoint i32* %addr to i32 + store i32 %val, i32* %addr.2 + + %addr.3 = getelementptr i32, i32* %addr, i32 3 + store i32 %v1, i32* %addr.3 + + ret void +} diff --git a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll index 4b274d2aedc2c..96c5fb8961ef7 100644 --- a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll +++ b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a9 -O1 -filetype=obj %s -o - | llvm-objdump -arch thumb -mcpu=cortex-a9 -d - | FileCheck %s +; RUN: llc -mtriple=thumbv7-- -mcpu=cortex-a9 -O1 -filetype=obj %s -o - | llvm-objdump -triple=thumbv7-- -mcpu=cortex-a9 -d - | FileCheck %s target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7--linux-gnueabi" diff --git a/test/CodeGen/Generic/vector-casts.ll b/test/CodeGen/Generic/vector-casts.ll index fee72b6b65855..0afbb8cfadc59 100644 --- a/test/CodeGen/Generic/vector-casts.ll +++ b/test/CodeGen/Generic/vector-casts.ll @@ -2,44 +2,44 @@ ; PR2671 define void @a(<2 x double>* %p, <2 x i8>* %q) { - %t = load <2 x double>, <2 x double>* %p - %r = fptosi <2 x double> %t to <2 x i8> - store <2 x i8> %r, <2 x i8>* %q - ret void + %t = load <2 x double>, <2 x double>* %p + %r = fptosi <2 x double> %t to <2 x i8> + store <2 x i8> %r, <2 x i8>* %q + ret void } define void @b(<2 x double>* %p, <2 x i8>* %q) { - %t = load <2 x double>, <2 x double>* %p - %r = fptoui <2 x double> %t to <2 x i8> - store <2 x i8> %r, <2 x i8>* %q - ret void + %t = load <2 x double>, <2 x double>* %p + %r = fptoui <2 x double> %t to <2 x i8> + store <2 x i8> %r, <2 x i8>* %q + ret void } define void @c(<2 x i8>* %p, <2 x double>* %q) { - %t = load <2 x i8>, <2 x i8>* %p - %r = sitofp <2 x i8> %t to <2 x double> - store <2 x double> %r, <2 x double>* %q - ret void + %t = load <2 x i8>, <2 x i8>* %p + %r = sitofp <2 x i8> %t to <2 x double> + store <2 x double> %r, <2 x double>* %q + ret void } define void @d(<2 x i8>* %p, <2 x double>* %q) { - %t = load <2 x i8>, <2 x i8>* %p - %r = uitofp <2 x i8> %t to <2 x double> - store <2 x double> %r, <2 x double>* %q - ret void + %t = load <2 x i8>, <2 x i8>* %p + %r = uitofp <2 x i8> %t to <2 x double> + store <2 x double> %r, <2 x double>* %q + ret void } define void @e(<2 x i8>* %p, <2 x i16>* %q) { - %t = load <2 x i8>, <2 x i8>* %p - %r = sext <2 x i8> %t to <2 x i16> - store <2 x i16> %r, <2 x i16>* %q - ret void + %t = load <2 x i8>, <2 x i8>* %p + %r = sext <2 x i8> %t to <2 x i16> + store <2 x i16> %r, <2 x i16>* %q + ret void } define void @f(<2 x i8>* %p, <2 x i16>* %q) { - %t = load <2 x i8>, <2 x i8>* %p - %r = zext <2 x i8> %t to <2 x i16> - store <2 x i16> %r, <2 x i16>* %q - ret void + %t = load <2 x i8>, <2 x i8>* %p + %r = zext <2 x i8> %t to <2 x i16> + store <2 x i16> %r, <2 x i16>* %q + ret void } define void @g(<2 x i16>* %p, <2 x i8>* %q) { - %t = load <2 x i16>, <2 x i16>* %p - %r = trunc <2 x i16> %t to <2 x i8> - store <2 x i8> %r, <2 x i8>* %q - ret void + %t = load <2 x i16>, <2 x i16>* %p + %r = trunc <2 x i16> %t to <2 x i8> + store <2 x i8> %r, <2 x i8>* %q + ret void } diff --git a/test/CodeGen/MIR/X86/expected-machine-operand.mir b/test/CodeGen/MIR/X86/expected-machine-operand.mir new file mode 100644 index 0000000000000..3725c93cd3ead --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-machine-operand.mir @@ -0,0 +1,21 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:24: expected a machine operand + - '%eax = XOR32rr =' + - 'RETQ %eax' +... + diff --git a/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/test/CodeGen/MIR/X86/expected-number-after-bb.mir new file mode 100644 index 0000000000000..f4248a76be461 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-number-after-bb.mir @@ -0,0 +1,37 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32* %p) { + entry: + %a = load i32, i32* %p + %b = icmp sle i32 %a, 10 + br i1 %b, label %yes, label %nah + + yes: + ret i32 0 + + nah: + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + - 'CMP32ri8 %eax, 10' + # CHECK: [[@LINE+1]]:18: expected a number after '%bb.' + - 'JG_1 %bb.nah' + - id: 1 + name: yes + instructions: + - '%eax = MOV32r0' + - id: 2 + name: nah + instructions: + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/global-value-operands.mir b/test/CodeGen/MIR/X86/global-value-operands.mir new file mode 100644 index 0000000000000..4aa88fe96cebe --- /dev/null +++ b/test/CodeGen/MIR/X86/global-value-operands.mir @@ -0,0 +1,49 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses global value operands correctly. + +--- | + + @G = external global i32 + @0 = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + + define i32 @inc2() { + entry: + %a = load i32, i32* @0 + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +# CHECK: name: inc +name: inc +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _' + - '%rax = MOV64rm %rip, 1, _, @G, _' + - '%eax = MOV32rm %rax, 1, _, 0, _' + - '%eax = INC32r %eax' + - 'RETQ %eax' +... +--- +# CHECK: name: inc2 +name: inc2 +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _' + - '%rax = MOV64rm %rip, 1, _, @0, _' + - '%eax = MOV32rm %rax, 1, _, 0, _' + - '%eax = INC32r %eax' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/immediate-operands.mir b/test/CodeGen/MIR/X86/immediate-operands.mir new file mode 100644 index 0000000000000..5d4956f539ddc --- /dev/null +++ b/test/CodeGen/MIR/X86/immediate-operands.mir @@ -0,0 +1,40 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses immediate machine operands. + +--- | + + define i32 @foo() { + entry: + ret i32 42 + } + + define i32 @bar() { + entry: + ret i32 -11 + } + +... +--- +# CHECK: name: foo +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%eax = MOV32ri 42' + # CHECK-NEXT: - 'RETQ %eax' + - '%eax = MOV32ri 42' + - 'RETQ %eax' +... +--- +# CHECK: name: bar +name: bar +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%eax = MOV32ri -11' + # CHECK-NEXT: - 'RETQ %eax' + - '%eax = MOV32ri -11' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/large-index-number-error.mir b/test/CodeGen/MIR/X86/large-index-number-error.mir new file mode 100644 index 0000000000000..61a5bdfe2edb6 --- /dev/null +++ b/test/CodeGen/MIR/X86/large-index-number-error.mir @@ -0,0 +1,35 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32* %p) { + entry: + %a = load i32, i32* %p + %b = icmp sle i32 %a, 10 + br i1 %b, label %0, label %1 + + ; <label>:0 + ret i32 0 + + ; <label>:1 + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + - 'CMP32ri8 %eax, 10' + # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large) + - 'JG_1 %bb.123456789123456' + - id: 1 + instructions: + - '%eax = MOV32r0' + - id: 2 + instructions: + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/lit.local.cfg b/test/CodeGen/MIR/X86/lit.local.cfg new file mode 100644 index 0000000000000..c8625f4d9d248 --- /dev/null +++ b/test/CodeGen/MIR/X86/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'X86' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir new file mode 100644 index 0000000000000..9d1bd0bd58adc --- /dev/null +++ b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -0,0 +1,75 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses machine basic block operands. + +--- | + + define i32 @foo(i32* %p) { + entry: + %a = load i32, i32* %p + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + + define i32 @bar(i32* %p) { + entry: + %a = load i32, i32* %p + %b = icmp sle i32 %a, 10 + br i1 %b, label %0, label %1 + + ; <label>:0 + ret i32 0 + + ; <label>:1 + ret i32 %a + } + +... +--- +# CHECK: name: foo +name: foo +body: + # CHECK: name: entry + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + # CHECK: - 'CMP32ri8 %eax, 10 + # CHECK-NEXT: - 'JG_1 %bb.2.exit + - 'CMP32ri8 %eax, 10' + - 'JG_1 %bb.2.exit' + # CHECK: name: less + - id: 1 + name: less + instructions: + - '%eax = MOV32r0' + - id: 2 + name: exit + instructions: + - 'RETQ %eax' +... +--- +# CHECK: name: bar +name: bar +body: + # CHECK: name: entry + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + # CHECK: - 'CMP32ri8 %eax, 10 + # CHECK-NEXT: - 'JG_1 %bb.2 + - 'CMP32ri8 %eax, 10' + - 'JG_1 %bb.3' + - id: 1 + instructions: + - '%eax = MOV32r0' + - id: 3 + instructions: + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/machine-instructions.mir b/test/CodeGen/MIR/X86/machine-instructions.mir new file mode 100644 index 0000000000000..b743198cf2707 --- /dev/null +++ b/test/CodeGen/MIR/X86/machine-instructions.mir @@ -0,0 +1,25 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses X86 machine instructions +# correctly. + +--- | + + define i32 @inc(i32 %a) { + entry: + %b = mul i32 %a, 11 + ret i32 %b + } + +... +--- +# CHECK: name: inc +name: inc +body: + - id: 0 + name: entry + instructions: + # CHECK: - IMUL32rri8 + # CHECK-NEXT: - RETQ + - IMUL32rri8 + - ' RETQ ' +... diff --git a/test/CodeGen/MIR/X86/missing-comma.mir b/test/CodeGen/MIR/X86/missing-comma.mir new file mode 100644 index 0000000000000..54c67ac6c9117 --- /dev/null +++ b/test/CodeGen/MIR/X86/missing-comma.mir @@ -0,0 +1,21 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:29: expected ',' before the next machine operand + - '%eax = XOR32rr %eax %eflags' + - 'RETQ %eax' +... + diff --git a/test/CodeGen/MIR/X86/missing-instruction.mir b/test/CodeGen/MIR/X86/missing-instruction.mir new file mode 100644 index 0000000000000..8d11ab5eaabe7 --- /dev/null +++ b/test/CodeGen/MIR/X86/missing-instruction.mir @@ -0,0 +1,19 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @foo() { + entry: + ret void + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:9: expected a machine instruction + - '' +... diff --git a/test/CodeGen/MIR/X86/named-registers.mir b/test/CodeGen/MIR/X86/named-registers.mir new file mode 100644 index 0000000000000..5defb8489e1e7 --- /dev/null +++ b/test/CodeGen/MIR/X86/named-registers.mir @@ -0,0 +1,23 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses X86 registers correctly. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +# CHECK: name: foo +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%eax = MOV32r0 + # CHECK-NEXT: - 'RETQ %eax + - '%eax = MOV32r0' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/null-register-operands.mir b/test/CodeGen/MIR/X86/null-register-operands.mir new file mode 100644 index 0000000000000..55c0ceb3a60a3 --- /dev/null +++ b/test/CodeGen/MIR/X86/null-register-operands.mir @@ -0,0 +1,24 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses null register operands correctly. + +--- | + + define i32 @deref(i32* %p) { + entry: + %a = load i32, i32* %p + ret i32 %a + } + +... +--- +# CHECK: name: deref +name: deref +body: + - id: 0 + name: entry + instructions: + # CHECK: - '%eax = MOV32rm %rdi, 1, _, 0, _' + # CHECK-NEXT: - 'RETQ %eax' + - '%eax = MOV32rm %rdi, 1, _, 0, %noreg' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/register-mask-operands.mir b/test/CodeGen/MIR/X86/register-mask-operands.mir new file mode 100644 index 0000000000000..ecaedeae4dbda --- /dev/null +++ b/test/CodeGen/MIR/X86/register-mask-operands.mir @@ -0,0 +1,43 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses register mask operands correctly. + +--- | + + define i32 @compute(i32 %a) #0 { + body: + %c = mul i32 %a, 11 + ret i32 %c + } + + define i32 @foo(i32 %a) #0 { + entry: + %b = call i32 @compute(i32 %a) + ret i32 %b + } + + attributes #0 = { "no-frame-pointer-elim"="false" } + +... +--- +name: compute +body: + - id: 0 + name: body + instructions: + - '%eax = IMUL32rri8 %edi, 11' + - 'RETQ %eax' +... +--- +# CHECK: name: foo +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: - 'PUSH64r %rax + # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, %rsp, %edi, %rsp, %eax' + - 'PUSH64r %rax' + - 'CALL64pcrel32 @compute, csr_64, %rsp, %edi, %rsp, %eax' + - '%rdx = POP64r' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/undefined-global-value.mir b/test/CodeGen/MIR/X86/undefined-global-value.mir new file mode 100644 index 0000000000000..e41dc0454d2cb --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-global-value.mir @@ -0,0 +1,28 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an invalid global value index +# is used. + +--- | + + @0 = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @0 + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:37: use of undefined global value '@2' + - '%rax = MOV64rm %rip, 1, _, @2, _' + - '%eax = MOV32rm %rax, 1, _, 0, _' + - '%eax = INC32r %eax' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/test/CodeGen/MIR/X86/undefined-named-global-value.mir new file mode 100644 index 0000000000000..b40c2ce43b5f8 --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-named-global-value.mir @@ -0,0 +1,28 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an undefined global value is +# used. + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:37: use of undefined global value '@GG' + - '%rax = MOV64rm %rip, 1, _, @GG, _' + - '%eax = MOV32rm %rax, 1, _, 0, _' + - '%eax = INC32r %eax' + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/unknown-instruction.mir b/test/CodeGen/MIR/X86/unknown-instruction.mir new file mode 100644 index 0000000000000..4e58ca6bad402 --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-instruction.mir @@ -0,0 +1,21 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an unknown instruction is +# encountered. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:8: unknown machine instruction name 'retJust0' + - retJust0 +... diff --git a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir new file mode 100644 index 0000000000000..5bc979a83eafd --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir @@ -0,0 +1,38 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an invalid machine basic +# block index is used. + + +--- | + + define i32 @foo(i32* %p) { + entry: + %a = load i32, i32* %p + %b = icmp sle i32 %a, 10 + br i1 %b, label %0, label %1 + + ; <label>:0 + ret i32 0 + + ; <label>:1 + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + - 'CMP32ri8 %eax, 10' + # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4 + - 'JG_1 %bb.4' + - id: 1 + instructions: + - '%eax = MOV32r0' + - id: 2 + instructions: + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir new file mode 100644 index 0000000000000..cd8c5402256fb --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir @@ -0,0 +1,39 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an unknown named machine +# basic block is encountered. + +--- | + + define i32 @foo(i32* %p) { + entry: + %a = load i32, i32* %p + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + - '%eax = MOV32rm %rdi, 1, _, 0, _' + - 'CMP32ri8 %eax, 10' + # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit' + - 'JG_1 %bb.2.hit' + - id: 1 + name: less + instructions: + - '%eax = MOV32r0' + - id: 2 + name: exit + instructions: + - 'RETQ %eax' +... diff --git a/test/CodeGen/MIR/X86/unknown-register.mir b/test/CodeGen/MIR/X86/unknown-register.mir new file mode 100644 index 0000000000000..ce40ee809bf3f --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-register.mir @@ -0,0 +1,22 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an unknown register is +# encountered. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:9: unknown register name 'xax' + - '%xax = MOV32r0' + - 'RETQ %xax' +... diff --git a/test/CodeGen/MIR/X86/unrecognized-character.mir b/test/CodeGen/MIR/X86/unrecognized-character.mir new file mode 100644 index 0000000000000..3b4fb1a9fc6eb --- /dev/null +++ b/test/CodeGen/MIR/X86/unrecognized-character.mir @@ -0,0 +1,19 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @foo() { + entry: + ret void + } + +... +--- +name: foo +body: + - id: 0 + name: entry + instructions: + # CHECK: [[@LINE+1]]:9: unexpected character '`' + - '` RETQ' +... diff --git a/test/CodeGen/MIR/basic-blocks.mir b/test/CodeGen/MIR/basic-blocks.mir index 43d87507d5d31..17313047576b4 100644 --- a/test/CodeGen/MIR/basic-blocks.mir +++ b/test/CodeGen/MIR/basic-blocks.mir @@ -17,27 +17,33 @@ --- # CHECK: name: foo # CHECK: body: -# CHECK-NEXT: - name: entry +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: name: entry # CHECK-NEXT: alignment: 0 # CHECK-NEXT: isLandingPad: false # CHECK-NEXT: addressTaken: false name: foo body: - - name: entry + - id: 0 + name: entry ... --- # CHECK: name: bar # CHECK: body: -# CHECK-NEXT: - name: start +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: name: start # CHECK-NEXT: alignment: 4 # CHECK-NEXT: isLandingPad: false # CHECK-NEXT: addressTaken: false -# CHECK-NEXT: - alignment: 0 +# CHECK-NEXT: - id: 1 +# CHECK-NEXT: alignment: 0 # CHECK-NEXT: isLandingPad: false # CHECK-NEXT: addressTaken: true name: bar body: - - name: start + - id: 0 + name: start alignment: 4 - - addressTaken: true + - id: 1 + addressTaken: true ... diff --git a/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir b/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir new file mode 100644 index 0000000000000..25ae511929717 --- /dev/null +++ b/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir @@ -0,0 +1,29 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + # CHECK: [[@LINE+1]]:46: expected end of string after the machine basic block reference + successors: [ '%bb.1.less', '%bb.2.exit 2' ] + - id: 1 + name: less + - id: 2 + name: exit +... diff --git a/test/CodeGen/MIR/expected-mbb-reference-for-successor-mbb.mir b/test/CodeGen/MIR/expected-mbb-reference-for-successor-mbb.mir new file mode 100644 index 0000000000000..ce9192901d7dc --- /dev/null +++ b/test/CodeGen/MIR/expected-mbb-reference-for-successor-mbb.mir @@ -0,0 +1,29 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: + - id: 0 + name: entry + # CHECK: [[@LINE+1]]:35: expected a machine basic block reference + successors: [ '%bb.1.less', '2' ] + - id: 1 + name: less + - id: 2 + name: exit +... diff --git a/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir b/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir new file mode 100644 index 0000000000000..deac3b0b69bf1 --- /dev/null +++ b/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir @@ -0,0 +1,17 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: + # CHECK: redefinition of machine basic block with id #0 + - id: 0 + - id: 0 +... diff --git a/test/CodeGen/MIR/machine-basic-block-unknown-name.mir b/test/CodeGen/MIR/machine-basic-block-unknown-name.mir index 4c363c69edbb4..ed675c5edbc32 100644 --- a/test/CodeGen/MIR/machine-basic-block-unknown-name.mir +++ b/test/CodeGen/MIR/machine-basic-block-unknown-name.mir @@ -14,5 +14,6 @@ name: foo body: # CHECK: basic block 'entrie' is not defined in the function 'foo' - - name: entrie + - id: 0 + name: entrie ... diff --git a/test/CodeGen/MIR/machine-function.mir b/test/CodeGen/MIR/machine-function.mir index a3c1d1d739279..8f053adc22be0 100644 --- a/test/CodeGen/MIR/machine-function.mir +++ b/test/CodeGen/MIR/machine-function.mir @@ -25,7 +25,7 @@ # CHECK-NEXT: alignment: # CHECK-NEXT: exposesReturnsTwice: false # CHECK-NEXT: hasInlineAsm: false -# CHECK-NEXT: ... +# CHECK: ... name: foo ... --- @@ -33,7 +33,7 @@ name: foo # CHECK-NEXT: alignment: # CHECK-NEXT: exposesReturnsTwice: false # CHECK-NEXT: hasInlineAsm: false -# CHECK-NEXT: ... +# CHECK: ... name: bar ... --- @@ -41,7 +41,7 @@ name: bar # CHECK-NEXT: alignment: 8 # CHECK-NEXT: exposesReturnsTwice: false # CHECK-NEXT: hasInlineAsm: false -# CHECK-NEXT: ... +# CHECK: ... name: func alignment: 8 ... @@ -50,7 +50,7 @@ alignment: 8 # CHECK-NEXT: alignment: 16 # CHECK-NEXT: exposesReturnsTwice: true # CHECK-NEXT: hasInlineAsm: true -# CHECK-NEXT: ... +# CHECK: ... name: func2 alignment: 16 exposesReturnsTwice: true diff --git a/test/CodeGen/MIR/register-info.mir b/test/CodeGen/MIR/register-info.mir new file mode 100644 index 0000000000000..c01997b46859b --- /dev/null +++ b/test/CodeGen/MIR/register-info.mir @@ -0,0 +1,36 @@ +# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses machine register info properties +# correctly. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + + define i32 @bar() { + start: + ret i32 0 + } + +... +--- +# CHECK: name: foo +# CHECK: isSSA: false +# CHECK-NEXT: tracksRegLiveness: false +# CHECK-NEXT: tracksSubRegLiveness: false +# CHECK: ... +name: foo +... +--- +# CHECK: name: bar +# CHECK: isSSA: false +# CHECK-NEXT: tracksRegLiveness: true +# CHECK-NEXT: tracksSubRegLiveness: true +# CHECK: ... +name: bar +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +... diff --git a/test/CodeGen/MIR/successor-basic-blocks.mir b/test/CodeGen/MIR/successor-basic-blocks.mir new file mode 100644 index 0000000000000..3fe01e3ad4388 --- /dev/null +++ b/test/CodeGen/MIR/successor-basic-blocks.mir @@ -0,0 +1,58 @@ +# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses basic block successors correctly. + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + + define i32 @bar(i32 %a) { + entry: + %b = icmp sle i32 %a, 10 + br i1 %b, label %0, label %1 + + ; <label>:0 + ret i32 0 + + ; <label>:1 + ret i32 %a + } + +... +--- +name: foo +body: + # CHECK: name: entry + # CHECK: successors: [ '%bb.1.less', '%bb.2.exit' ] + # CHECK: name: less + - id: 0 + name: entry + successors: [ '%bb.1.less', '%bb.2.exit' ] + - id: 1 + name: less + - id: 2 + name: exit +... +--- +name: bar +body: + # CHECK: name: bar + # CHECK: name: entry + # CHECK: successors: [ '%bb.1', '%bb.2' ] + # CHECK: id: 1 + # CHECK: id: 2 + - id: 0 + name: entry + successors: [ '%bb.1', '%bb.2' ] + - id: 1 + - id: 2 +... diff --git a/test/CodeGen/NVPTX/call-with-alloca-buffer.ll b/test/CodeGen/NVPTX/call-with-alloca-buffer.ll index 8ff762aa7c480..7ca31bbbaf2d5 100644 --- a/test/CodeGen/NVPTX/call-with-alloca-buffer.ll +++ b/test/CodeGen/NVPTX/call-with-alloca-buffer.ll @@ -20,8 +20,7 @@ entry: %buf = alloca [16 x i8], align 4 ; CHECK: .local .align 4 .b8 __local_depot0[16] -; CHECK: mov.u64 %rd[[BUF_REG:[0-9]+]] -; CHECK: cvta.local.u64 %SP, %rd[[BUF_REG]] +; CHECK: mov.u64 %SPL ; CHECK: ld.param.u64 %rd[[A_REG:[0-9]+]], [kernel_func_param_0] ; CHECK: cvta.to.global.u64 %rd[[A1_REG:[0-9]+]], %rd[[A_REG]] diff --git a/test/CodeGen/NVPTX/extloadv.ll b/test/CodeGen/NVPTX/extloadv.ll new file mode 100644 index 0000000000000..8c264ae093316 --- /dev/null +++ b/test/CodeGen/NVPTX/extloadv.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s + +define void @foo(float* nocapture readonly %x_value, double* nocapture %output) #0 { + %1 = bitcast float* %x_value to <4 x float>* + %2 = load <4 x float>, <4 x float>* %1, align 16 + %3 = fpext <4 x float> %2 to <4 x double> +; CHECK-NOT: ld.v2.f32 {%fd{{[0-9]+}}, %fd{{[0-9]+}}}, [%rd{{[0-9]+}}]; +; CHECK: cvt.f64.f32 +; CHECK: cvt.f64.f32 +; CHECK: cvt.f64.f32 +; CHECK: cvt.f64.f32 + %4 = bitcast double* %output to <4 x double>* + store <4 x double> %3, <4 x double>* %4 + ret void +} diff --git a/test/CodeGen/NVPTX/globals_lowering.ll b/test/CodeGen/NVPTX/globals_lowering.ll new file mode 100644 index 0000000000000..84c61ef4033f7 --- /dev/null +++ b/test/CodeGen/NVPTX/globals_lowering.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -relocation-model=static | FileCheck %s --check-prefix CHK + +%MyStruct = type { i32, i32, float } +@Gbl = internal addrspace(3) global [1024 x %MyStruct] zeroinitializer + +; CHK-LABEL: foo +define void @foo(float %f) { +entry: + ; CHK: ld.shared.f32 %{{[a-zA-Z0-9]+}}, [Gbl+8]; + %0 = load float, float addrspace(3)* getelementptr inbounds ([1024 x %MyStruct], [1024 x %MyStruct] addrspace(3)* @Gbl, i32 0, i32 0, i32 2) + %add = fadd float %0, %f + ; CHK: st.shared.f32 [Gbl+8], %{{[a-zA-Z0-9]+}}; + store float %add, float addrspace(3)* getelementptr inbounds ([1024 x %MyStruct], [1024 x %MyStruct] addrspace(3)* @Gbl, i32 0, i32 0, i32 2) + ret void +} diff --git a/test/CodeGen/NVPTX/intrinsics.ll b/test/CodeGen/NVPTX/intrinsics.ll index 34b671d70e94f..06a8712c2102a 100644 --- a/test/CodeGen/NVPTX/intrinsics.ll +++ b/test/CodeGen/NVPTX/intrinsics.ll @@ -16,6 +16,8 @@ define ptx_device double @test_fabs(double %d) { } define float @test_nvvm_sqrt(float %a) { +; CHECK: sqrt.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}; +; CHECK: ret; %val = call float @llvm.nvvm.sqrt.f(float %a) ret float %val } diff --git a/test/CodeGen/NVPTX/local-stack-frame.ll b/test/CodeGen/NVPTX/local-stack-frame.ll index 377eee9170e63..ef1b7da6ad0f5 100644 --- a/test/CodeGen/NVPTX/local-stack-frame.ll +++ b/test/CodeGen/NVPTX/local-stack-frame.ll @@ -3,12 +3,12 @@ ; Ensure we access the local stack properly -; PTX32: mov.u32 %r{{[0-9]+}}, __local_depot{{[0-9]+}}; -; PTX32: cvta.local.u32 %SP, %r{{[0-9]+}}; +; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}}; +; PTX32: cvta.local.u32 %SP, %SPL; ; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo_param_0]; ; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}}; -; PTX64: mov.u64 %rd{{[0-9]+}}, __local_depot{{[0-9]+}}; -; PTX64: cvta.local.u64 %SP, %rd{{[0-9]+}}; +; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}}; +; PTX64: cvta.local.u64 %SP, %SPL; ; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo_param_0]; ; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}}; define void @foo(i32 %a) { @@ -16,3 +16,67 @@ define void @foo(i32 %a) { store volatile i32 %a, i32* %local ret void } + +; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}}; +; PTX32: cvta.local.u32 %SP, %SPL; +; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0]; +; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0; +; PTX32: st.local.u32 [%r[[SP_REG]]], %r{{[0-9]+}}; +; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}}; +; PTX64: cvta.local.u64 %SP, %SPL; +; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0]; +; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0; +; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}}; +define void @foo2(i32 %a) { + %local = alloca i32, align 4 + store i32 %a, i32* %local + call void @bar(i32* %local) + ret void +} + +declare void @bar(i32* %a) + +!nvvm.annotations = !{!0} +!0 = !{void (i32)* @foo2, !"kernel", i32 1} + +; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}}; +; PTX32-NOT: cvta.local.u32 %SP, %SPL; +; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0]; +; PTX32: add.u32 %r{{[0-9]+}}, %SPL, 0; +; PTX32: st.local.u32 [%r{{[0-9]+}}], %r{{[0-9]+}}; +; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}}; +; PTX64-NOT: cvta.local.u64 %SP, %SPL; +; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0]; +; PTX64: add.u64 %rd{{[0-9]+}}, %SPL, 0; +; PTX64: st.local.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}; +define void @foo3(i32 %a) { + %local = alloca [3 x i32], align 4 + %1 = bitcast [3 x i32]* %local to i32* + %2 = getelementptr inbounds i32, i32* %1, i32 %a + store i32 %a, i32* %2 + ret void +} + +; PTX32: cvta.local.u32 %SP, %SPL; +; PTX32: add.u32 {{%r[0-9]+}}, %SP, 0; +; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 0; +; PTX32: add.u32 {{%r[0-9]+}}, %SP, 4; +; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 4; +; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}} +; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}} +; PTX64: cvta.local.u64 %SP, %SPL; +; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 0; +; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 0; +; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 4; +; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 4; +; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}} +; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}} +define void @foo4() { + %A = alloca i32 + %B = alloca i32 + store i32 0, i32* %A + store i32 0, i32* %B + call void @bar(i32* %A) + call void @bar(i32* %B) + ret void +} diff --git a/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll b/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll index 53220bd905bda..0de72c4a1aed0 100644 --- a/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll +++ b/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll @@ -16,5 +16,16 @@ define void @kernel(float* %input, float* %output) { ret void } -!nvvm.annotations = !{!0} +define void @kernel2(float addrspace(1)* %input, float addrspace(1)* %output) { +; CHECK-LABEL: .visible .entry kernel2( +; CHECK-NOT: cvta.to.global.u64 + %1 = load float, float addrspace(1)* %input, align 4 +; CHECK: ld.global.f32 + store float %1, float addrspace(1)* %output, align 4 +; CHECK: st.global.f32 + ret void +} + +!nvvm.annotations = !{!0, !1} !0 = !{void (float*, float*)* @kernel, !"kernel", i32 1} +!1 = !{void (float addrspace(1)*, float addrspace(1)*)* @kernel2, !"kernel", i32 1} diff --git a/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll b/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll new file mode 100644 index 0000000000000..16dc2ccb111d9 --- /dev/null +++ b/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll @@ -0,0 +1,165 @@ +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +@vda = common global <2 x double> zeroinitializer, align 16 +@vdb = common global <2 x double> zeroinitializer, align 16 +@vdr = common global <2 x double> zeroinitializer, align 16 +@vfa = common global <4 x float> zeroinitializer, align 16 +@vfb = common global <4 x float> zeroinitializer, align 16 +@vfr = common global <4 x float> zeroinitializer, align 16 +@vbllr = common global <2 x i64> zeroinitializer, align 16 +@vbir = common global <4 x i32> zeroinitializer, align 16 +@vblla = common global <2 x i64> zeroinitializer, align 16 +@vbllb = common global <2 x i64> zeroinitializer, align 16 +@vbia = common global <4 x i32> zeroinitializer, align 16 +@vbib = common global <4 x i32> zeroinitializer, align 16 + +; Function Attrs: nounwind +define void @test1() { +entry: + %0 = load <2 x double>, <2 x double>* @vda, align 16 + %1 = load <2 x double>, <2 x double>* @vdb, align 16 + %2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1) + store <2 x double> %2, <2 x double>* @vdr, align 16 + ret void +; CHECK-LABEL: @test1 +; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test2() { +entry: + %0 = load <4 x float>, <4 x float>* @vfa, align 16 + %1 = load <4 x float>, <4 x float>* @vfb, align 16 + %2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1) + store <4 x float> %2, <4 x float>* @vfr, align 16 + ret void +; CHECK-LABEL: @test2 +; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test3() { +entry: + %0 = load <2 x double>, <2 x double>* @vda, align 16 + %1 = load <2 x double>, <2 x double>* @vda, align 16 + %2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1) + store <2 x double> %2, <2 x double>* @vdr, align 16 + ret void +; CHECK-LABEL: @test3 +; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test4() { +entry: + %0 = load <4 x float>, <4 x float>* @vfa, align 16 + %1 = load <4 x float>, <4 x float>* @vfa, align 16 + %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1) + store <4 x float> %2, <4 x float>* @vfr, align 16 + ret void +; CHECK-LABEL: @test4 +; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test5() { +entry: + %0 = load <2 x double>, <2 x double>* @vda, align 16 + %1 = load <2 x double>, <2 x double>* @vdb, align 16 + %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @vbllr, align 16 + ret void +; CHECK-LABEL: @test5 +; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test6() { +entry: + %0 = load <4 x float>, <4 x float>* @vfa, align 16 + %1 = load <4 x float>, <4 x float>* @vfb, align 16 + %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @vbir, align 16 + ret void +; CHECK-LABEL: @test6 +; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test7() { +entry: + %0 = load <2 x double>, <2 x double>* @vda, align 16 + %1 = load <2 x double>, <2 x double>* @vdb, align 16 + %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @vbllr, align 16 + ret void +; CHECK-LABEL: @test7 +; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test8() { +entry: + %0 = load <4 x float>, <4 x float>* @vfa, align 16 + %1 = load <4 x float>, <4 x float>* @vfb, align 16 + %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @vbir, align 16 + ret void +; CHECK-LABEL: @test8 +; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test9() { +entry: + %0 = load <2 x double>, <2 x double>* @vda, align 16 + %1 = load <2 x double>, <2 x double>* @vdb, align 16 + %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1) + store <2 x i64> %2, <2 x i64>* @vbllr, align 16 + ret void +; CHECK-LABEL: @test9 +; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind +define void @test10() { +entry: + %0 = load <4 x float>, <4 x float>* @vfa, align 16 + %1 = load <4 x float>, <4 x float>* @vfb, align 16 + %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1) + store <4 x i32> %2, <4 x i32>* @vbir, align 16 + ret void +; CHECK-LABEL: @test10 +; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +} + +; Function Attrs: nounwind readnone +declare <2 x double> @llvm.ceil.v2f64(<2 x double>) + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) + +; Function Attrs: nounwind readnone +declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>) + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>) + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>) + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>) + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>) + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>) + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>) + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>) diff --git a/test/CodeGen/PowerPC/lxvw4x-bug.ll b/test/CodeGen/PowerPC/lxvw4x-bug.ll new file mode 100644 index 0000000000000..1f521a5d533cf --- /dev/null +++ b/test/CodeGen/PowerPC/lxvw4x-bug.ll @@ -0,0 +1,25 @@ +; RUN: llc -O0 -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; Function Attrs: nounwind +define void @test() { +entry: + %__a.addr.i = alloca i32, align 4 + %__b.addr.i = alloca <4 x i32>*, align 8 + %i = alloca <4 x i32>, align 16 + %j = alloca <4 x i32>, align 16 + store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16 + store i32 0, i32* %__a.addr.i, align 4 + store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8 + %0 = load i32, i32* %__a.addr.i, align 4 + %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8 + %2 = bitcast <4 x i32>* %1 to i8* + %3 = getelementptr i8, i8* %2, i32 %0 + %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3) +; CHECK: lwa [[REG0:[0-9]+]], +; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]] +; CHECK: xxswapd [[REG1]], [[REG1]] + store <4 x i32> %4, <4 x i32>* %j, align 16 + ret void +} + +; Function Attrs: nounwind readonly +declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*) diff --git a/test/CodeGen/PowerPC/swaps-le-3.ll b/test/CodeGen/PowerPC/swaps-le-3.ll new file mode 100644 index 0000000000000..0c1748df9fcd7 --- /dev/null +++ b/test/CodeGen/PowerPC/swaps-le-3.ll @@ -0,0 +1,24 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s + +; This test verifies that VSX swap optimization works for the +; doubleword splat idiom. + +@a = external global <2 x double>, align 16 +@b = external global <2 x double>, align 16 + +define void @test(double %s) { +entry: + %0 = insertelement <2 x double> undef, double %s, i32 0 + %1 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer + %2 = load <2 x double>, <2 x double>* @a, align 16 + %3 = fadd <2 x double> %0, %2 + store <2 x double> %3, <2 x double>* @b, align 16 + ret void +} + +; CHECK-LABEL: @test +; CHECK: xxspltd +; CHECK: lxvd2x +; CHECK: xvadddp +; CHECK: stxvd2x +; CHECK-NOT: xxswapd diff --git a/test/CodeGen/PowerPC/swaps-le-4.ll b/test/CodeGen/PowerPC/swaps-le-4.ll new file mode 100644 index 0000000000000..7d8239bd25574 --- /dev/null +++ b/test/CodeGen/PowerPC/swaps-le-4.ll @@ -0,0 +1,27 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s + +; This test verifies that VSX swap optimization works when an implicit +; subregister is present (in this case, in the XXPERMDI associated with +; the store). + +define void @bar() { +entry: + %x = alloca <2 x i64>, align 16 + %0 = bitcast <2 x i64>* %x to i8* + call void @llvm.lifetime.start(i64 16, i8* %0) + %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %x, i64 0, i64 0 + store <2 x i64> <i64 0, i64 1>, <2 x i64>* %x, align 16 + call void @foo(i64* %arrayidx) + call void @llvm.lifetime.end(i64 16, i8* %0) + ret void +} + +; CHECK-LABEL: @bar +; CHECK: lxvd2x +; CHECK: stxvd2x +; CHECK-NOT: xxswapd + +declare void @llvm.lifetime.start(i64, i8* nocapture) +declare void @foo(i64*) +declare void @llvm.lifetime.end(i64, i8* nocapture) + diff --git a/test/CodeGen/PowerPC/vec_mergeow.ll b/test/CodeGen/PowerPC/vec_mergeow.ll new file mode 100644 index 0000000000000..c7c7448e3ae8b --- /dev/null +++ b/test/CodeGen/PowerPC/vec_mergeow.ll @@ -0,0 +1,101 @@ +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-LE +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-BE + +; Check for a vector merge instruction using two inputs +; The shufflevector specifies the even elements, using big endian element +; ordering. If run on a big endian machine, this should produce the vmrgew +; instruction. If run on a little endian machine, this should produce the +; vmrgow instruction. Note also that on little endian the input registers +; are swapped also. +define void @check_merge_even_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK-LE-LABEL: @check_merge_even_xy +; CHECK-BE-LABEL: @check_merge_even_xy + %tmp = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 16, i32 17, i32 18, i32 19, + i32 8, i32 9, i32 10, i32 11, + i32 24, i32 25, i32 26, i32 27> +; CHECK-LE: vmrgow 2, 3, 2 +; CHECK-BE: vmrgew 2, 2, 3 + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +; CHECK-LE: blr +; CHECK-BE: blr +} + +; Check for a vector merge instruction using a single input. +; The shufflevector specifies the even elements, using big endian element +; ordering. If run on a big endian machine, this should produce the vmrgew +; instruction. If run on a little endian machine, this should produce the +; vmrgow instruction. +define void @check_merge_even_xx(<16 x i8>* %A) { +entry: +; CHECK-LE-LABEL: @check_merge_even_xx +; CHECK-BE-LABEL: @check_merge_even_xx + %tmp = load <16 x i8>, <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 0, i32 1, i32 2, i32 3, + i32 8, i32 9, i32 10, i32 11, + i32 8, i32 9, i32 10, i32 11> +; CHECK-LE: vmrgow 2, 2, 2 +; CHECK-BE: vmrgew 2, 2, 2 + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +; CHECK-LE: blr +; CHECK-BE: blr +} + +; Check for a vector merge instruction using two inputs. +; The shufflevector specifies the odd elements, using big endian element +; ordering. If run on a big endian machine, this should produce the vmrgow +; instruction. If run on a little endian machine, this should produce the +; vmrgew instruction. Note also that on little endian the input registers +; are swapped also. +define void @check_merge_odd_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK-LE-LABEL: @check_merge_odd_xy +; CHECK-BE-LABEL: @check_merge_odd_xy + %tmp = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, + <16 x i32> <i32 4, i32 5, i32 6, i32 7, + i32 20, i32 21, i32 22, i32 23, + i32 12, i32 13, i32 14, i32 15, + i32 28, i32 29, i32 30, i32 31> +; CHECK-LE: vmrgew 2, 3, 2 +; CHECK-BE: vmrgow 2, 2, 3 + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +; CHECK-LE: blr +; CHECK-BE: blr +} + +; Check for a vector merge instruction using a single input. +; The shufflevector specifies the odd elements, using big endian element +; ordering. If run on a big endian machine, this should produce the vmrgow +; instruction. If run on a little endian machine, this should produce the +; vmrgew instruction. +define void @check_merge_odd_xx(<16 x i8>* %A) { +entry: +; CHECK-LE-LABEL: @check_merge_odd_xx +; CHECK-BE-LABEL: @check_merge_odd_xx + %tmp = load <16 x i8>, <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, + <16 x i32> <i32 4, i32 5, i32 6, i32 7, + i32 4, i32 5, i32 6, i32 7, + i32 12, i32 13, i32 14, i32 15, + i32 12, i32 13, i32 14, i32 15> +; CHECK-LE: vmrgew 2, 2, 2 +; CHECK-BE: vmrgow 2, 2, 2 + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +; CHECK-LE: blr +; CHECK-BE: blr +} + diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index b185fed4cd5b2..f85acebeea677 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -1,9 +1,8 @@ -; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s -; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s -; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s -; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s -target datalayout = "E-m:e-i64:64-n32:64" -target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s define double @test1(double %a, double %b) { entry: @@ -13,6 +12,10 @@ entry: ; CHECK-LABEL: @test1 ; CHECK: xsmuldp 1, 1, 2 ; CHECK: blr + +; CHECK-LE-LABEL: @test1 +; CHECK-LE: xsmuldp 1, 1, 2 +; CHECK-LE: blr } define double @test2(double %a, double %b) { @@ -23,6 +26,10 @@ entry: ; CHECK-LABEL: @test2 ; CHECK: xsdivdp 1, 1, 2 ; CHECK: blr + +; CHECK-LE-LABEL: @test2 +; CHECK-LE: xsdivdp 1, 1, 2 +; CHECK-LE: blr } define double @test3(double %a, double %b) { @@ -33,6 +40,10 @@ entry: ; CHECK-LABEL: @test3 ; CHECK: xsadddp 1, 1, 2 ; CHECK: blr + +; CHECK-LE-LABEL: @test3 +; CHECK-LE: xsadddp 1, 1, 2 +; CHECK-LE: blr } define <2 x double> @test4(<2 x double> %a, <2 x double> %b) { @@ -43,6 +54,10 @@ entry: ; CHECK-LABEL: @test4 ; CHECK: xvadddp 34, 34, 35 ; CHECK: blr + +; CHECK-LE-LABEL: @test4 +; CHECK-LE: xvadddp 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { @@ -60,6 +75,10 @@ entry: ; CHECK-FISL: xxlxor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test5 +; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: blr } define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) { @@ -77,6 +96,10 @@ entry: ; CHECK-FISL: xxlxor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test6 +; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: blr } define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) { @@ -94,6 +117,10 @@ entry: ; CHECK-FISL: xxlxor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test7 +; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) { @@ -111,6 +138,10 @@ entry: ; CHECK-FISL: xxlor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test8 +; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: blr } define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) { @@ -128,6 +159,10 @@ entry: ; CHECK-FISL: xxlor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test9 +; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: blr } define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) { @@ -145,6 +180,10 @@ entry: ; CHECK-FISL: xxlor 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test10 +; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { @@ -162,6 +201,10 @@ entry: ; CHECK-FISL: xxland 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test11 +; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: blr } define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) { @@ -179,6 +222,10 @@ entry: ; CHECK-FISL: xxland 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test12 +; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: blr } define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) { @@ -196,6 +243,10 @@ entry: ; CHECK-FISL: xxland 36, 36, 37 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test13 +; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) { @@ -221,6 +272,10 @@ entry: ; CHECK-FISL: ori 0, 0, 65520 ; CHECK-FISL: stvx 0, 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test14 +; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: blr } define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) { @@ -246,6 +301,10 @@ entry: ; CHECK-FISL: ori 0, 0, 65520 ; CHECK-FISL: stvx 0, 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test15 +; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: blr } define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) { @@ -271,6 +330,10 @@ entry: ; CHECK-FISL: ori 0, 0, 65520 ; CHECK-FISL: stvx 0, 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test16 +; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { @@ -294,6 +357,10 @@ entry: ; CHECK-FISL: xxland 37, 37, 32 ; CHECK-FISL: vor 2, 5, 5 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test17 +; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: blr } define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) { @@ -320,6 +387,10 @@ entry: ; CHECK-FISL: ori 0, 0, 65520 ; CHECK-FISL: stvx 4, 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test18 +; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: blr } define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) { @@ -346,6 +417,10 @@ entry: ; CHECK-FISL: ori 0, 0, 65520 ; CHECK-FISL: stvx 4, 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test19 +; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: blr } define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { @@ -367,6 +442,11 @@ entry: ; CHECK-FISL: xxsel 32, 32, 33, 38 ; CHECK-FISL: vor 2, 0, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test20 +; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5 +; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: blr } define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { @@ -389,6 +469,11 @@ entry: ; CHECK-FISL: xxsel 32, 38, 39, 32 ; CHECK-FISL: vor 2, 0, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test21 +; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37 +; CHECK-LE: xxsel 34, 35, 34, [[V1]] +; CHECK-LE: blr } define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { @@ -418,6 +503,17 @@ entry: ; CHECK-FISL-DAG: xxlor ; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}} ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test22 +; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 +; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 +; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 +; CHECK-LE-DAG: xxlnor +; CHECK-LE-DAG: xxlnor +; CHECK-LE-DAG: xxlor +; CHECK-LE-DAG: xxlor +; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: blr } define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { @@ -439,6 +535,11 @@ entry: ; CHECK-FISL: xxsel 32, 32, 33, 38 ; CHECK-FISL: vor 2, 0, ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test23 +; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5 +; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: blr } define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { @@ -460,6 +561,11 @@ entry: ; CHECK-FISL: xxsel 32, 32, 33, 38 ; CHECK-FISL: vor 2, 0, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test24 +; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5 +; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: blr } define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { @@ -472,6 +578,11 @@ entry: ; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37 ; CHECK: xxsel 34, 35, 34, [[V1]] ; CHECK: blr + +; CHECK-LE-LABEL: @test25 +; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37 +; CHECK-LE: xxsel 34, 35, 34, [[V1]] +; CHECK-LE: blr } define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) { @@ -489,6 +600,9 @@ define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) { ; CHECK: add ; CHECK: add ; CHECK: blr + +; CHECK-LE: vaddudm 2, 2, 3 +; CHECK-LE: blr } define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) { @@ -498,6 +612,10 @@ define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: @test27 ; CHECK: xxland 34, 34, 35 ; CHECK: blr + +; CHECK-LE-LABEL: @test27 +; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: blr } define <2 x double> @test28(<2 x double>* %a) { @@ -507,6 +625,11 @@ define <2 x double> @test28(<2 x double>* %a) { ; CHECK-LABEL: @test28 ; CHECK: lxvd2x 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test28 +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test29(<2 x double>* %a, <2 x double> %b) { @@ -516,6 +639,11 @@ define void @test29(<2 x double>* %a, <2 x double> %b) { ; CHECK-LABEL: @test29 ; CHECK: stxvd2x 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test29 +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <2 x double> @test28u(<2 x double>* %a) { @@ -525,6 +653,11 @@ define <2 x double> @test28u(<2 x double>* %a) { ; CHECK-LABEL: @test28u ; CHECK: lxvd2x 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test28u +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test29u(<2 x double>* %a, <2 x double> %b) { @@ -534,6 +667,11 @@ define void @test29u(<2 x double>* %a, <2 x double> %b) { ; CHECK-LABEL: @test29u ; CHECK: stxvd2x 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test29u +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <2 x i64> @test30(<2 x i64>* %a) { @@ -550,6 +688,11 @@ define <2 x i64> @test30(<2 x i64>* %a) { ; CHECK-FISL: vor 3, 2, 2 ; CHECK-FISL: vor 2, 3, 3 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test30 +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test31(<2 x i64>* %a, <2 x i64> %b) { @@ -559,6 +702,11 @@ define void @test31(<2 x i64>* %a, <2 x i64> %b) { ; CHECK-LABEL: @test31 ; CHECK: stxvd2x 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test31 +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <4 x float> @test32(<4 x float>* %a) { @@ -573,6 +721,11 @@ define <4 x float> @test32(<4 x float>* %a) { ; CHECK-FISL: lxvw4x 0, 0, 3 ; CHECK-FISL: xxlor 34, 0, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test32 +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test33(<4 x float>* %a, <4 x float> %b) { @@ -587,6 +740,11 @@ define void @test33(<4 x float>* %a, <4 x float> %b) { ; CHECK-FISL: vor 3, 2, 2 ; CHECK-FISL: stxvw4x 35, 0, 3 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test33 +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <4 x float> @test32u(<4 x float>* %a) { @@ -599,6 +757,11 @@ define <4 x float> @test32u(<4 x float>* %a) { ; CHECK-DAG: lvx ; CHECK: vperm 2, ; CHECK: blr + +; CHECK-LE-LABEL: @test32u +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test33u(<4 x float>* %a, <4 x float> %b) { @@ -613,6 +776,11 @@ define void @test33u(<4 x float>* %a, <4 x float> %b) { ; CHECK-FISL: vor 3, 2, 2 ; CHECK-FISL: stxvw4x 35, 0, 3 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test33u +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <4 x i32> @test34(<4 x i32>* %a) { @@ -629,6 +797,11 @@ define <4 x i32> @test34(<4 x i32>* %a) { ; CHECK-FISL: vor 3, 2, 2 ; CHECK-FISL: vor 2, 3, 3 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test34 +; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 +; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: blr } define void @test35(<4 x i32>* %a, <4 x i32> %b) { @@ -643,6 +816,11 @@ define void @test35(<4 x i32>* %a, <4 x i32> %b) { ; CHECK-FISL: vor 3, 2, 2 ; CHECK-FISL: stxvw4x 35, 0, 3 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test35 +; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 +; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: blr } define <2 x double> @test40(<2 x i64> %a) { @@ -652,6 +830,10 @@ define <2 x double> @test40(<2 x i64> %a) { ; CHECK-LABEL: @test40 ; CHECK: xvcvuxddp 34, 34 ; CHECK: blr + +; CHECK-LE-LABEL: @test40 +; CHECK-LE: xvcvuxddp 34, 34 +; CHECK-LE: blr } define <2 x double> @test41(<2 x i64> %a) { @@ -661,6 +843,10 @@ define <2 x double> @test41(<2 x i64> %a) { ; CHECK-LABEL: @test41 ; CHECK: xvcvsxddp 34, 34 ; CHECK: blr + +; CHECK-LE-LABEL: @test41 +; CHECK-LE: xvcvsxddp 34, 34 +; CHECK-LE: blr } define <2 x i64> @test42(<2 x double> %a) { @@ -670,6 +856,10 @@ define <2 x i64> @test42(<2 x double> %a) { ; CHECK-LABEL: @test42 ; CHECK: xvcvdpuxds 34, 34 ; CHECK: blr + +; CHECK-LE-LABEL: @test42 +; CHECK-LE: xvcvdpuxds 34, 34 +; CHECK-LE: blr } define <2 x i64> @test43(<2 x double> %a) { @@ -679,6 +869,10 @@ define <2 x i64> @test43(<2 x double> %a) { ; CHECK-LABEL: @test43 ; CHECK: xvcvdpsxds 34, 34 ; CHECK: blr + +; CHECK-LE-LABEL: @test43 +; CHECK-LE: xvcvdpsxds 34, 34 +; CHECK-LE: blr } define <2 x float> @test44(<2 x i64> %a) { @@ -726,6 +920,10 @@ define <2 x double> @test50(double* %a) { ; CHECK-LABEL: @test50 ; CHECK: lxvdsx 34, 0, 3 ; CHECK: blr + +; CHECK-LE-LABEL: @test50 +; CHECK-LE: lxvdsx 34, 0, 3 +; CHECK-LE: blr } define <2 x double> @test51(<2 x double> %a, <2 x double> %b) { @@ -735,6 +933,10 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) { ; CHECK-LABEL: @test51 ; CHECK: xxspltd 34, 34, 0 ; CHECK: blr + +; CHECK-LE-LABEL: @test51 +; CHECK-LE: xxspltd 34, 34, 1 +; CHECK-LE: blr } define <2 x double> @test52(<2 x double> %a, <2 x double> %b) { @@ -744,6 +946,10 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) { ; CHECK-LABEL: @test52 ; CHECK: xxmrghd 34, 34, 35 ; CHECK: blr + +; CHECK-LE-LABEL: @test52 +; CHECK-LE: xxmrgld 34, 35, 34 +; CHECK-LE: blr } define <2 x double> @test53(<2 x double> %a, <2 x double> %b) { @@ -753,6 +959,10 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) { ; CHECK-LABEL: @test53 ; CHECK: xxmrghd 34, 35, 34 ; CHECK: blr + +; CHECK-LE-LABEL: @test53 +; CHECK-LE: xxmrgld 34, 34, 35 +; CHECK-LE: blr } define <2 x double> @test54(<2 x double> %a, <2 x double> %b) { @@ -762,6 +972,10 @@ define <2 x double> @test54(<2 x double> %a, <2 x double> %b) { ; CHECK-LABEL: @test54 ; CHECK: xxpermdi 34, 34, 35, 2 ; CHECK: blr + +; CHECK-LE-LABEL: @test54 +; CHECK-LE: xxpermdi 34, 35, 34, 2 +; CHECK-LE: blr } define <2 x double> @test55(<2 x double> %a, <2 x double> %b) { @@ -771,6 +985,10 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) { ; CHECK-LABEL: @test55 ; CHECK: xxmrgld 34, 34, 35 ; CHECK: blr + +; CHECK-LE-LABEL: @test55 +; CHECK-LE: xxmrghd 34, 35, 34 +; CHECK-LE: blr } define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { @@ -780,6 +998,10 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: @test56 ; CHECK: xxmrgld 34, 34, 35 ; CHECK: blr + +; CHECK-LE-LABEL: @test56 +; CHECK-LE: xxmrghd 34, 35, 34 +; CHECK-LE: blr } define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) { @@ -836,6 +1058,10 @@ define double @test63(<2 x double> %a) { ; CHECK-FISL: xxlor 0, 34, 34 ; CHECK-FISL: fmr 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test63 +; CHECK-LE: xxswapd 1, 34 +; CHECK-LE: blr } define double @test64(<2 x double> %a) { @@ -851,6 +1077,9 @@ define double @test64(<2 x double> %a) { ; CHECK-FISL: xxlor 0, 34, 34 ; CHECK-FISL: fmr 1, 0 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test64 +; CHECK-LE: xxlor 1, 34, 34 } define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { @@ -867,6 +1096,10 @@ define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { ; CHECK-FISL: vcmpequw 4, 5, 4 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test65 +; CHECK-LE: vcmpequd 2, 2, 3 +; CHECK-LE: blr } define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) { @@ -882,6 +1115,11 @@ define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) { ; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4 ; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test66 +; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3 +; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} +; CHECK-LE: blr } define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) { @@ -896,6 +1134,10 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) { ; CHECK: cmpld ; CHECK: lxvd2x ; CHECK: blr + +; CHECK-LE-LABEL: @test67 +; CHECK-LE: vcmpgtud 2, 3, 2 +; CHECK-LE: blr } define <2 x double> @test68(<2 x i32> %a) { @@ -906,6 +1148,11 @@ define <2 x double> @test68(<2 x i32> %a) { ; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1 ; CHECK: xvcvsxwdp 34, [[V1]] ; CHECK: blr + +; CHECK-LE-LABEL: @test68 +; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1 +; CHECK-LE: xvcvsxwdp 34, [[V1]] +; CHECK-LE: blr } define <2 x double> @test69(<2 x i16> %a) { @@ -920,6 +1167,15 @@ define <2 x double> @test69(<2 x i16> %a) { ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 ; CHECK: xvcvsxwdp 34, [[V4]] ; CHECK: blr + +; CHECK-LE-LABEL: @test69 +; CHECK-LE: vspltisw [[V1:[0-9]+]], 8 +; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] +; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] +; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]] +; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 +; CHECK-LE: xvcvsxwdp 34, [[V4]] +; CHECK-LE: blr } define <2 x double> @test70(<2 x i8> %a) { @@ -934,6 +1190,15 @@ define <2 x double> @test70(<2 x i8> %a) { ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 ; CHECK: xvcvsxwdp 34, [[V4]] ; CHECK: blr + +; CHECK-LE-LABEL: @test70 +; CHECK-LE: vspltisw [[V1:[0-9]+]], 12 +; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] +; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] +; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]] +; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 +; CHECK-LE: xvcvsxwdp 34, [[V4]] +; CHECK-LE: blr } define <2 x i32> @test80(i32 %v) { @@ -960,6 +1225,16 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-FISL-DAG: std [[R3]], -16(1) ; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]] ; CHECK-FISL: blr + +; CHECK-LE-LABEL: @test80 +; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16 +; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI +; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]] +; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] +; CHECK-LE-DAG: xxswapd 34, [[V1]] +; CHECK-LE-DAG: xxswapd 35, [[V2]] +; CHECK-LE: vaddudm 2, 2, 3 +; CHECK-LE: blr } define <2 x double> @test81(<4 x float> %b) { @@ -968,6 +1243,9 @@ define <2 x double> @test81(<4 x float> %b) { ; CHECK-LABEL: @test81 ; CHECK: blr + +; CHECK-LE-LABEL: @test81 +; CHECK-LE: blr } define double @test82(double %a, double %b, double %c, double %d) { @@ -983,4 +1261,8 @@ entry: ; CHECK-FISL-LABEL: @test82 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4 ; CHECK-FISL: beq [[REG]], {{.*}} + +; CHECK-LE-LABEL: @test82 +; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4 +; CHECK-LE: beqlr [[REG]] } diff --git a/test/CodeGen/Thumb2/float-ops.ll b/test/CodeGen/Thumb2/float-ops.ll index 4c42908ce13b8..c9f93f2d61386 100644 --- a/test/CodeGen/Thumb2/float-ops.ll +++ b/test/CodeGen/Thumb2/float-ops.ll @@ -109,7 +109,7 @@ entry: define double @load_d(double* %a) { entry: ; CHECK-LABEL: load_d: -; NONE: ldrd r0, r1, [r0] +; NONE: ldm r0, {r0, r1} ; HARD: vldr d0, [r0] %0 = load double, double* %a, align 8 ret double %0 diff --git a/test/CodeGen/WinEH/cppeh-prepared-catch.ll b/test/CodeGen/WinEH/cppeh-prepared-catch.ll index c7a829ad7e425..02cc682cbe4be 100644 --- a/test/CodeGen/WinEH/cppeh-prepared-catch.ll +++ b/test/CodeGen/WinEH/cppeh-prepared-catch.ll @@ -61,7 +61,7 @@ entry: %.i8 = call i8* @llvm.framerecover(i8* bitcast (void ()* @"\01?f@@YAXXZ" to i8*), i8* %1, i32 1) %2 = bitcast i8* %.i8 to double* %3 = bitcast double* %2 to i8* - invoke void (...) @llvm.donothing() + invoke void () @llvm.donothing() to label %done unwind label %lpad done: @@ -201,7 +201,7 @@ declare void @llvm.frameescape(...) #3 ; Function Attrs: nounwind readnone declare i8* @llvm.framerecover(i8*, i8*, i32) #2 -declare void @llvm.donothing(...) +declare void @llvm.donothing() attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" "wineh-parent"="?f@@YAXXZ" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/X86/StackColoring.ll b/test/CodeGen/X86/StackColoring.ll index 414ccf469ebbd..634f66ad52dea 100644 --- a/test/CodeGen/X86/StackColoring.ll +++ b/test/CodeGen/X86/StackColoring.ll @@ -1,9 +1,10 @@ -; RUN: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR -; RUN: llc -mcpu=corei7 -no-stack-coloring=true < %s | FileCheck %s --check-prefix=NOCOLOR +; RUN: llc -mcpu=corei7 -no-stack-coloring=false < %s | FileCheck %s --check-prefix=YESCOLOR --check-prefix=CHECK +; RUN: llc -mcpu=corei7 -no-stack-coloring=true < %s | FileCheck %s --check-prefix=NOCOLOR --check-prefix=CHECK target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" +;CHECK-LABEL: myCall_w2: ;YESCOLOR: subq $144, %rsp ;NOCOLOR: subq $272, %rsp @@ -28,6 +29,7 @@ entry: } +;CHECK-LABEL: myCall2_no_merge ;YESCOLOR: subq $272, %rsp ;NOCOLOR: subq $272, %rsp @@ -56,6 +58,7 @@ bb3: ret i32 0 } +;CHECK-LABEL: myCall2_w2 ;YESCOLOR: subq $144, %rsp ;NOCOLOR: subq $272, %rsp @@ -82,12 +85,11 @@ bb2: bb3: ret i32 0 } + +;CHECK-LABEL: myCall_w4: ;YESCOLOR: subq $200, %rsp ;NOCOLOR: subq $408, %rsp - - - define i32 @myCall_w4(i32 %in) { entry: %a1 = alloca [14 x i8*], align 8 @@ -119,6 +121,7 @@ entry: ret i32 %t7 } +;CHECK-LABEL: myCall2_w4: ;YESCOLOR: subq $112, %rsp ;NOCOLOR: subq $400, %rsp @@ -158,6 +161,7 @@ bb3: } +;CHECK-LABEL: myCall2_noend: ;YESCOLOR: subq $144, %rsp ;NOCOLOR: subq $272, %rsp @@ -185,6 +189,7 @@ bb3: ret i32 0 } +;CHECK-LABEL: myCall2_noend2: ;YESCOLOR: subq $144, %rsp ;NOCOLOR: subq $272, %rsp define i32 @myCall2_noend2(i32 %in, i1 %d) { @@ -211,6 +216,7 @@ bb3: } +;CHECK-LABEL: myCall2_nostart: ;YESCOLOR: subq $144, %rsp ;NOCOLOR: subq $272, %rsp define i32 @myCall2_nostart(i32 %in, i1 %d) { @@ -236,6 +242,7 @@ bb3: } ; Adopt the test from Transforms/Inline/array_merge.ll' +;CHECK-LABEL: array_merge: ;YESCOLOR: subq $816, %rsp ;NOCOLOR: subq $1616, %rsp define void @array_merge() nounwind ssp { @@ -261,6 +268,7 @@ entry: ret void } +;CHECK-LABEL: func_phi_lifetime: ;YESCOLOR: subq $272, %rsp ;NOCOLOR: subq $272, %rsp define i32 @func_phi_lifetime(i32 %in, i1 %d) { @@ -297,8 +305,7 @@ bb3: } -;YESCOLOR-LABEL: multi_region_bb: -;NOCOLOR-LABEL: multi_region_bb: +;CHECK-LABEL: multi_region_bb: define void @multi_region_bb() nounwind ssp { entry: %A.i1 = alloca [100 x i32], align 4 @@ -323,10 +330,9 @@ entry: call void @llvm.lifetime.end(i64 -1, i8* %3) nounwind ret void } - - ;YESCOLOR: subq $272, %rsp ;NOCOLOR: subq $272, %rsp + define i32 @myCall_end_before_begin(i32 %in, i1 %d) { entry: %a = alloca [17 x i8*], align 8 @@ -353,9 +359,8 @@ bb3: ; Regression test for PR15707. %buf1 and %buf2 should not be merged ; in this test case. -;YESCOLOR-LABEL: myCall_pr15707: +;CHECK-LABEL: myCall_pr15707: ;YESCOLOR: subq $200008, %rsp -;NOCOLOR-LABEL: myCall_pr15707: ;NOCOLOR: subq $200008, %rsp define void @myCall_pr15707() { %buf1 = alloca i8, i32 100000, align 16 @@ -374,8 +379,7 @@ define void @myCall_pr15707() { ; Check that we don't assert and crash even when there are allocas ; outside the declared lifetime regions. -;YESCOLOR-LABEL: bad_range: -;NOCOLOR-LABEL: bad_range: +;CHECK-LABEL: bad_range: define void @bad_range() nounwind ssp { entry: %A.i1 = alloca [100 x i32], align 4 @@ -400,8 +404,7 @@ block2: ; Check that we don't assert and crash even when there are usages ; of allocas which do not read or write outside the declared lifetime regions. -;YESCOLOR-LABEL: shady_range: -;NOCOLOR-LABEL: shady_range: +;CHECK-LABEL: shady_range: %struct.Klass = type { i32, i32 } diff --git a/test/CodeGen/X86/asm-mismatched-types.ll b/test/CodeGen/X86/asm-mismatched-types.ll new file mode 100644 index 0000000000000..97f9c0872f8f5 --- /dev/null +++ b/test/CodeGen/X86/asm-mismatched-types.ll @@ -0,0 +1,135 @@ +; RUN: llc -o - %s -no-integrated-as | FileCheck %s +target triple = "x86_64--" + +; Allow to specify any of the 8/16/32/64 register names interchangeably in +; constraints + +; Produced by C-programs like this: +; void foo(int p) { register int reg __asm__("r8") = p; +; __asm__ __volatile__("# REG: %0" : : "r" (reg)); } + +; CHECK-LABEL: reg64_as_32: +; CHECK: # REG: %r8d +define void @reg64_as_32(i32 %p) { + call void asm sideeffect "# REG: $0", "{r8}"(i32 %p) + ret void +} + +; CHECK-LABEL: reg64_as_32_float: +; CHECK: # REG: %r8d +define void @reg64_as_32_float(float %p) { + call void asm sideeffect "# REG: $0", "{r8}"(float %p) + ret void +} + +; CHECK-LABEL: reg64_as_16: +; CHECK: # REG: %r9w +define void @reg64_as_16(i16 %p) { + call void asm sideeffect "# REG: $0", "{r9}"(i16 %p) + ret void +} + +; CHECK-LABEL: reg64_as_8: +; CHECK: # REG: %bpl +define void @reg64_as_8(i8 %p) { + call void asm sideeffect "# REG: $0", "{rbp}"(i8 %p) + ret void +} + +; CHECK-LABEL: reg32_as_16: +; CHECK: # REG: %r15w +define void @reg32_as_16(i16 %p) { + call void asm sideeffect "# REG: $0", "{r15d}"(i16 %p) + ret void +} + +; CHECK-LABEL: reg32_as_8: +; CHECK: # REG: %r12b +define void @reg32_as_8(i8 %p) { + call void asm sideeffect "# REG: $0", "{r12d}"(i8 %p) + ret void +} + +; CHECK-LABEL: reg16_as_8: +; CHECK: # REG: %cl +define void @reg16_as_8(i8 %p) { + call void asm sideeffect "# REG: $0", "{cx}"(i8 %p) + ret void +} + +; CHECK-LABEL: reg32_as_64: +; CHECK: # REG: %rbp +define void @reg32_as_64(i64 %p) { + call void asm sideeffect "# REG: $0", "{ebp}"(i64 %p) + ret void +} + +; CHECK-LABEL: reg32_as_64_float: +; CHECK: # REG: %rbp +define void @reg32_as_64_float(double %p) { + call void asm sideeffect "# REG: $0", "{ebp}"(double %p) + ret void +} + +; CHECK-LABEL: reg16_as_64: +; CHECK: # REG: %r13 +define void @reg16_as_64(i64 %p) { + call void asm sideeffect "# REG: $0", "{r13w}"(i64 %p) + ret void +} + +; CHECK-LABEL: reg16_as_64_float: +; CHECK: # REG: %r13 +define void @reg16_as_64_float(double %p) { + call void asm sideeffect "# REG: $0", "{r13w}"(double %p) + ret void +} + +; CHECK-LABEL: reg8_as_64: +; CHECK: # REG: %rax +define void @reg8_as_64(i64 %p) { + call void asm sideeffect "# REG: $0", "{al}"(i64 %p) + ret void +} + +; CHECK-LABEL: reg8_as_64_float: +; CHECK: # REG: %rax +define void @reg8_as_64_float(double %p) { + call void asm sideeffect "# REG: $0", "{al}"(double %p) + ret void +} + +; CHECK-LABEL: reg16_as_32: +; CHECK: # REG: %r11d +define void @reg16_as_32(i32 %p) { + call void asm sideeffect "# REG: $0", "{r11w}"(i32 %p) + ret void +} + +; CHECK-LABEL: reg16_as_32_float: +; CHECK: # REG: %r11d +define void @reg16_as_32_float(float %p) { + call void asm sideeffect "# REG: $0", "{r11w}"(float %p) + ret void +} + +; CHECK-LABEL: reg8_as_32: +; CHECK: # REG: %r9d +define void @reg8_as_32(i32 %p) { + call void asm sideeffect "# REG: $0", "{r9b}"(i32 %p) + ret void +} + +; CHECK-LABEL: reg8_as_32_float: +; CHECK: # REG: %r9d +define void @reg8_as_32_float(float %p) { + call void asm sideeffect "# REG: $0", "{r9b}"(float %p) + ret void +} + +; CHECK-LABEL: reg8_as_16: +; CHECK: # REG: %di +define void @reg8_as_16(i16 %p) { + call void asm sideeffect "# REG: $0", "{dil}"(i16 %p) + ret void +} diff --git a/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll b/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll index 016e2d261eef6..c7e86f565eefa 100644 --- a/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll +++ b/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll @@ -1,10 +1,8 @@ -; RUN: not llc -no-integrated-as %s -o - 2> %t1 -; RUN: FileCheck %s < %t1 -target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s target triple = "x86_64--" ; CHECK: error: couldn't allocate output register for constraint '{ax}' define i128 @blup() { - %v = tail call i128 asm "", "={ax},0,~{dirflag},~{fpsr},~{flags}"(i128 0) + %v = tail call i128 asm "", "={ax},0"(i128 0) ret i128 %v } diff --git a/test/CodeGen/X86/avx512-build-vector.ll b/test/CodeGen/X86/avx512-build-vector.ll index e70d9f3ad521c..e5373c575c1ad 100644 --- a/test/CodeGen/X86/avx512-build-vector.ll +++ b/test/CodeGen/X86/avx512-build-vector.ll @@ -1,15 +1,5 @@ ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s -define <16 x i32> @test1(i32* %x) { -; CHECK-LABEL: test1: -; CHECK: vmovd (%rdi), %xmm -; CHECK: vmovdqa32 -; CHECK: vpermt2d %zmm - %y = load i32, i32* %x, align 4 - %res = insertelement <16 x i32>zeroinitializer, i32 %y, i32 4 - ret <16 x i32>%res -} - define <16 x i32> @test2(<16 x i32> %x) { ; CHECK-LABEL: test2: ; CHECK: ## BB#0: diff --git a/test/CodeGen/X86/avx512-fma-intrinsics.ll b/test/CodeGen/X86/avx512-fma-intrinsics.ll index 9814a6108272a..c30fc909f09b5 100644 --- a/test/CodeGen/X86/avx512-fma-intrinsics.ll +++ b/test/CodeGen/X86/avx512-fma-intrinsics.ll @@ -1,422 +1,675 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f --show-mc-encoding | FileCheck %s -declare <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) -declare <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) -declare <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) - -define <8 x double> @test_x86_vfmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { - ; CHECK-LABEL: test_x86_vfmsubpd_z - ; CHECK: vfmsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind - ret <8 x double> %res -} -declare <8 x double> @llvm.x86.fma.mask.vfmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone - -define <8 x double> @test_mask_vfmsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsub_pd - ; CHECK: vfmsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind - ret <8 x double> %res -} +declare <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) +declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) define <16 x float> @test_x86_vfnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_x86_vfnmadd_ps_z ; CHECK: vfnmadd213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind ret <16 x float> %res } -declare <16 x float> @llvm.x86.fma.mask.vfnmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone +declare <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone define <16 x float> @test_mask_vfnmadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_vfnmadd_ps ; CHECK: vfnmadd213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind ret <16 x float> %res } define <8 x double> @test_x86_vfnmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_x86_vfnmadd_pd_z ; CHECK: vfnmadd213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind ret <8 x double> %res } -declare <8 x double> @llvm.x86.fma.mask.vfnmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone +declare <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone define <8 x double> @test_mask_vfnmadd_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmadd_pd ; CHECK: vfnmadd213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind ret <8 x double> %res } define <16 x float> @test_x86_vfnmsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_x86_vfnmsubps_z ; CHECK: vfnmsub213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind ret <16 x float> %res } -declare <16 x float> @llvm.x86.fma.mask.vfnmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone +declare <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone define <16 x float> @test_mask_vfnmsub_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_vfnmsub_ps ; CHECK: vfnmsub213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind ret <16 x float> %res } define <8 x double> @test_x86_vfnmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_x86_vfnmsubpd_z ; CHECK: vfnmsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind ret <8 x double> %res } -declare <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone +declare <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone define <8 x double> @test_mask_vfnmsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmsub_pd ; CHECK: vfnmsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind ret <8 x double> %res } define <16 x float> @test_x86_vfmaddsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_x86_vfmaddsubps_z ; CHECK: vfmaddsub213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfmaddsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind ret <16 x float> %res } define <16 x float> @test_mask_fmaddsub_ps(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) { ; CHECK-LABEL: test_mask_fmaddsub_ps: ; CHECK: vfmaddsub213ps %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xa6,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmaddsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask, i32 4) + %res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask, i32 4) ret <16 x float> %res } -declare <16 x float> @llvm.x86.fma.mask.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone +declare <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone define <8 x double> @test_x86_vfmaddsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_x86_vfmaddsubpd_z ; CHECK: vfmaddsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind ret <8 x double> %res } -declare <8 x double> @llvm.x86.fma.mask.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone +declare <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone define <8 x double> @test_mask_vfmaddsub_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmaddsub_pd ; CHECK: vfmaddsub213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind - ret <8 x double> %res -} - -define <16 x float> @test_x86_vfmsubaddps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_x86_vfmsubaddps_z - ; CHECK: vfmsubadd213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfmsubadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind - ret <16 x float> %res -} -declare <16 x float> @llvm.x86.fma.mask.vfmsubadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone - -define <16 x float> @test_mask_vfmsubadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd_ps - ; CHECK: vfmsubadd213ps %zmm - %res = call <16 x float> @llvm.x86.fma.mask.vfmsubadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind - ret <16 x float> %res -} - -define <8 x double> @test_x86_vfmsubaddpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { - ; CHECK-LABEL: test_x86_vfmsubaddpd_z - ; CHECK: vfmsubadd213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind ret <8 x double> %res } -declare <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone -define <8 x double> @test_mask_vfmsubadd_pd(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd_pd - ; CHECK: vfmsubadd213pd %zmm - %res = call <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind - ret <8 x double> %res +define <8 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231pd %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %zmm2, %zmm1, %zmm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +define <16 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231ps %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <16 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %zmm2, %zmm1, %zmm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231pd %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmsubadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231ps %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmsubadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 } define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rne ; CHECK: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtn ; CHECK: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x39,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtp ; CHECK: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x59,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_rtz ; CHECK: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x79,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrb_current ; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rne ; CHECK: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x18,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtn ; CHECK: vfmadd213ps {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x38,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtp ; CHECK: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x58,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_rtz ; CHECK: vfmadd213ps {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x78,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind ret <16 x float> %res } define <16 x float> @test_mask_round_vfmadd512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_ps_rrbz_current ; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xa8,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rne - ; CHECK: vfmsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x19,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 0) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtn - ; CHECK: vfmsub213ps {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x39,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 1) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtp - ; CHECK: vfmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x59,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 2) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrb_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_rtz - ; CHECK: vfmsub213ps {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x79,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 3) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrb_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrb_current - ; CHECK: vfmsub213ps %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x49,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rne(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rne - ; CHECK: vfmsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x18,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 0) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtn(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtn - ; CHECK: vfmsub213ps {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x38,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 1) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtp(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtp - ; CHECK: vfmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x58,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 2) nounwind - ret <16 x float> %res -} - -define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_rtz(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_rtz - ; CHECK: vfmsub213ps {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x78,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 3) nounwind + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind ret <16 x float> %res } -define <16 x float> @test_mask_round_vfmsub512_ps_rrbz_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) { - ; CHECK-LABEL: test_mask_round_vfmsub512_ps_rrbz_current - ; CHECK: vfmsub213ps %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0x75,0x48,0xaa,0xc2] - %res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind - ret <16 x float> %res +declare <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_mask3_vfmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231pd %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_mask3_vfmsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231ps %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 } define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rne ; CHECK: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtn ; CHECK: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtp ; CHECK: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_rtz ; CHECK: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrb_current ; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rne ; CHECK: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtn ; CHECK: vfmadd213pd {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtp ; CHECK: vfmadd213pd {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_rtz ; CHECK: vfmadd213pd {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfmadd512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfmadd512_pd_rrbz_current ; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xa8,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind ret <8 x double> %res } +define <8 x double>@test_int_x86_avx512_mask_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_mask3_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231pd %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_maskz_vfmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %zmm2, %zmm1, %zmm3 {%k1} {z} +; CHECK-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.maskz.vfmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +define <16 x float>@test_int_x86_avx512_mask_vfmadd_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask3.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_mask3_vfmadd_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231ps %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask3.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_maskz_vfmadd_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm3 {%k1} {z} +; CHECK-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.maskz.vfmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rne ; CHECK: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x19,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 0) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtn ; CHECK: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x39,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 1) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtp ; CHECK: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x59,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 2) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_rtz ; CHECK: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x79,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 3) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrb_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrb_current ; CHECK: vfnmsub213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rne(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rne ; CHECK: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x18,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 0) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtn(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtn ; CHECK: vfnmsub213pd {rd-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x38,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 1) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtp(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtp ; CHECK: vfnmsub213pd {ru-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x58,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 2) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_rtz(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_rtz ; CHECK: vfnmsub213pd {rz-sae}, %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x78,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 3) nounwind ret <8 x double> %res } define <8 x double> @test_mask_round_vfnmsub512_pd_rrbz_current(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) { ; CHECK-LABEL: test_mask_round_vfnmsub512_pd_rrbz_current ; CHECK: vfnmsub213pd %zmm2, %zmm1, %zmm0 ## encoding: [0x62,0xf2,0xf5,0x48,0xae,0xc2] - %res = call <8 x double> @llvm.x86.fma.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind ret <8 x double> %res } + +define <8 x double>@test_int_x86_avx512_mask_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) + +define <8 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231pd %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfnmsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +define <16 x float>@test_int_x86_avx512_mask_vfnmsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfnmsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) + +define <16 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231ps %zmm1, %zmm0, %zmm3 {%k1} +; CHECK-NEXT: vfnmsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +define <8 x double>@test_int_x86_avx512_mask_vfnmadd_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_512: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213pd %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfnmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddpd %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 4) + %res1 = call <8 x double> @llvm.x86.avx512.mask.vfnmadd.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +define <16 x float>@test_int_x86_avx512_mask_vfnmadd_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3){ +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_512: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213ps %zmm2, %zmm1, %zmm3 {%k1} +; CHECK-NEXT: vfnmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 +; CHECK-NEXT: vaddps %zmm0, %zmm3, %zmm0 +; CHECK-NEXT: retq + %res = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 4) + %res1 = call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} diff --git a/test/CodeGen/X86/avx512-fma.ll b/test/CodeGen/X86/avx512-fma.ll index d6926e2571abd..ed046de005cf6 100644 --- a/test/CodeGen/X86/avx512-fma.ll +++ b/test/CodeGen/X86/avx512-fma.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -fp-contract=fast | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f -fp-contract=fast | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx -fp-contract=fast | FileCheck %s --check-prefix=SKX ; CHECK-LABEL: test_x86_fmadd_ps_z ; CHECK: vfmadd213ps %zmm2, %zmm1, %zmm0 @@ -58,26 +59,129 @@ define <8 x double> @test_x86_fmsub_pd_z(<8 x double> %a0, <8 x double> %a1, <8 ret <8 x double> %res } -define double @test_x86_fmsub_sd_z(double %a0, double %a1, double %a2) { +define double @test_x86_fmsub_213(double %a0, double %a1, double %a2) { +; CHECK-LABEL: test_x86_fmsub_213: +; CHECK: ## BB#0: +; CHECK-NEXT: vfmsub213sd %xmm2, %xmm0, %xmm1 +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq %x = fmul double %a0, %a1 %res = fsub double %x, %a2 ret double %res } -;CHECK-LABEL: test132_br -;CHECK: vfmadd132ps LCP{{.*}}(%rip){1to16} -;CHECK: ret -define <16 x float> @test132_br(<16 x float> %a1, <16 x float> %a2) nounwind { +define double @test_x86_fmsub_213_m(double %a0, double %a1, double * %a2_ptr) { +; CHECK-LABEL: test_x86_fmsub_213_m: +; CHECK: ## BB#0: +; CHECK-NEXT: vfmsub213sd (%rdi), %xmm0, %xmm1 +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq + %a2 = load double , double *%a2_ptr + %x = fmul double %a0, %a1 + %res = fsub double %x, %a2 + ret double %res +} + +define double @test_x86_fmsub_231_m(double %a0, double %a1, double * %a2_ptr) { +; CHECK-LABEL: test_x86_fmsub_231_m: +; CHECK: ## BB#0: +; CHECK-NEXT: vfmsub231sd (%rdi), %xmm0, %xmm1 +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq + %a2 = load double , double *%a2_ptr + %x = fmul double %a0, %a2 + %res = fsub double %x, %a1 + ret double %res +} + +define <16 x float> @test231_br(<16 x float> %a1, <16 x float> %a2) nounwind { +; CHECK-LABEL: test231_br: +; CHECK: ## BB#0: +; CHECK-NEXT: vfmadd231ps {{.*}}(%rip){1to16}, %zmm0, %zmm1 +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq %b1 = fmul <16 x float> %a1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000> %b2 = fadd <16 x float> %b1, %a2 ret <16 x float> %b2 } -;CHECK-LABEL: test213_br -;CHECK: vfmadd213ps LCP{{.*}}(%rip){1to16} -;CHECK: ret define <16 x float> @test213_br(<16 x float> %a1, <16 x float> %a2) nounwind { +; CHECK-LABEL: test213_br: +; CHECK: ## BB#0: +; CHECK-NEXT: vfmadd213ps {{.*}}(%rip){1to16}, %zmm1, %zmm0 +; CHECK-NEXT: retq %b1 = fmul <16 x float> %a1, %a2 %b2 = fadd <16 x float> %b1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000> ret <16 x float> %b2 } + +;mask (a*c+b , a) +define <16 x float> @test_x86_fmadd132_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> *%a2_ptrt, <16 x i1> %mask) { +; CHECK-LABEL: test_x86_fmadd132_ps: +; CHECK: ## BB#0: +; CHECK-NEXT: vpmovsxbd %xmm2, %zmm2 +; CHECK-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm2, %zmm2 +; CHECK-NEXT: vptestmd %zmm2, %zmm2, %k1 +; CHECK-NEXT: vfmadd132ps (%rdi), %zmm1, %zmm0 {%k1} +; CHECK-NEXT: retq +; +; SKX-LABEL: test_x86_fmadd132_ps: +; SKX: ## BB#0: +; SKX-NEXT: vpmovb2m %xmm2, %k1 +; SKX-NEXT: vfmadd132ps (%rdi), %zmm1, %zmm0 {%k1} +; SKX-NEXT: retq + %a2 = load <16 x float>,<16 x float> *%a2_ptrt,align 1 + %x = fmul <16 x float> %a0, %a2 + %y = fadd <16 x float> %x, %a1 + %res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a0 + ret <16 x float> %res +} + +;mask (a*c+b , b) +define <16 x float> @test_x86_fmadd231_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> *%a2_ptrt, <16 x i1> %mask) { +; CHECK-LABEL: test_x86_fmadd231_ps: +; CHECK: ## BB#0: +; CHECK-NEXT: vpmovsxbd %xmm2, %zmm2 +; CHECK-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm2, %zmm2 +; CHECK-NEXT: vptestmd %zmm2, %zmm2, %k1 +; CHECK-NEXT: vfmadd231ps (%rdi), %zmm0, %zmm1 {%k1} +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq +; +; SKX-LABEL: test_x86_fmadd231_ps: +; SKX: ## BB#0: +; SKX-NEXT: vpmovb2m %xmm2, %k1 +; SKX-NEXT: vfmadd231ps (%rdi), %zmm0, %zmm1 {%k1} +; SKX-NEXT: vmovaps %zmm1, %zmm0 +; SKX-NEXT: retq + %a2 = load <16 x float>,<16 x float> *%a2_ptrt,align 1 + %x = fmul <16 x float> %a0, %a2 + %y = fadd <16 x float> %x, %a1 + %res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a1 + ret <16 x float> %res +} + +;mask (b*a+c , b) +define <16 x float> @test_x86_fmadd213_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> *%a2_ptrt, <16 x i1> %mask) { +; CHECK-LABEL: test_x86_fmadd213_ps: +; CHECK: ## BB#0: +; CHECK-NEXT: vpmovsxbd %xmm2, %zmm2 +; CHECK-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm2, %zmm2 +; CHECK-NEXT: vptestmd %zmm2, %zmm2, %k1 +; CHECK-NEXT: vfmadd213ps (%rdi), %zmm0, %zmm1 {%k1} +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq +; +; SKX-LABEL: test_x86_fmadd213_ps: +; SKX: ## BB#0: +; SKX-NEXT: vpmovb2m %xmm2, %k1 +; SKX-NEXT: vfmadd213ps (%rdi), %zmm0, %zmm1 {%k1} +; SKX-NEXT: vmovaps %zmm1, %zmm0 +; SKX-NEXT: retq + %a2 = load <16 x float>,<16 x float> *%a2_ptrt,align 1 + %x = fmul <16 x float> %a1, %a0 + %y = fadd <16 x float> %x, %a2 + %res = select <16 x i1> %mask, <16 x float> %y, <16 x float> %a1 + ret <16 x float> %res +} + diff --git a/test/CodeGen/X86/avx512-gather-scatter-intrin.ll b/test/CodeGen/X86/avx512-gather-scatter-intrin.ll index 0e32a1c280676..3fca5a89a6a48 100644 --- a/test/CodeGen/X86/avx512-gather-scatter-intrin.ll +++ b/test/CodeGen/X86/avx512-gather-scatter-intrin.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s declare <16 x float> @llvm.x86.avx512.gather.dps.512 (<16 x float>, i8*, <16 x i32>, i16, i32) declare void @llvm.x86.avx512.scatter.dps.512 (i8*, i16, <16 x i32>, <16 x float>, i32) @@ -10,52 +10,60 @@ declare void @llvm.x86.avx512.scatter.qps.512 (i8*, i8, <8 x i64>, <8 x float>, declare <8 x double> @llvm.x86.avx512.gather.qpd.512 (<8 x double>, i8*, <8 x i64>, i8, i32) declare void @llvm.x86.avx512.scatter.qpd.512 (i8*, i8, <8 x i64>, <8 x double>, i32) -;CHECK-LABEL: gather_mask_dps -;CHECK: kmovw -;CHECK: vgatherdps -;CHECK: vpadd -;CHECK: vscatterdps -;CHECK: ret define void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_dps: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vgatherdps (%rsi,%zmm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <16 x float> @llvm.x86.avx512.gather.dps.512 (<16 x float> %src, i8* %base, <16 x i32>%ind, i16 %mask, i32 4) %ind2 = add <16 x i32> %ind, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> call void @llvm.x86.avx512.scatter.dps.512 (i8* %stbuf, i16 %mask, <16 x i32>%ind2, <16 x float> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_dpd -;CHECK: kmovw -;CHECK: vgatherdpd -;CHECK: vpadd -;CHECK: vscatterdpd -;CHECK: ret define void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_dpd: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x double> @llvm.x86.avx512.gather.dpd.512 (<8 x double> %src, i8* %base, <8 x i32>%ind, i8 %mask, i32 4) %ind2 = add <8 x i32> %ind, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> call void @llvm.x86.avx512.scatter.dpd.512 (i8* %stbuf, i8 %mask, <8 x i32>%ind2, <8 x double> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_qps -;CHECK: kmovw -;CHECK: vgatherqps -;CHECK: vpadd -;CHECK: vscatterqps -;CHECK: ret define void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_qps: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vgatherqps (%rsi,%zmm0,4), %ymm1 {%k2} +; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x float> @llvm.x86.avx512.gather.qps.512 (<8 x float> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) %ind2 = add <8 x i64> %ind, <i64 0, i64 1, i64 2, i64 3, i64 0, i64 1, i64 2, i64 3> call void @llvm.x86.avx512.scatter.qps.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind2, <8 x float> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_qpd -;CHECK: kmovw -;CHECK: vgatherqpd -;CHECK: vpadd -;CHECK: vscatterqpd -;CHECK: ret define void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_qpd: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vgatherqpd (%rsi,%zmm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x double> @llvm.x86.avx512.gather.qpd.512 (<8 x double> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) %ind2 = add <8 x i64> %ind, <i64 0, i64 1, i64 2, i64 3, i64 0, i64 1, i64 2, i64 3> call void @llvm.x86.avx512.scatter.qpd.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind2, <8 x double> %x, i32 4) @@ -74,162 +82,710 @@ declare void @llvm.x86.avx512.scatter.qpi.512 (i8*, i8, <8 x i64>, <8 x i32>, i3 declare <8 x i64> @llvm.x86.avx512.gather.qpq.512 (<8 x i64>, i8*, <8 x i64>, i8, i32) declare void @llvm.x86.avx512.scatter.qpq.512 (i8*, i8, <8 x i64>, <8 x i64>, i32) -;CHECK-LABEL: gather_mask_dd -;CHECK: kmovw -;CHECK: vpgatherdd -;CHECK: vpadd -;CHECK: vpscatterdd -;CHECK: ret define void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_dd: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherdd (%rsi,%zmm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddd {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <16 x i32> @llvm.x86.avx512.gather.dpi.512 (<16 x i32> %src, i8* %base, <16 x i32>%ind, i16 %mask, i32 4) %ind2 = add <16 x i32> %ind, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> call void @llvm.x86.avx512.scatter.dpi.512 (i8* %stbuf, i16 %mask, <16 x i32>%ind2, <16 x i32> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_qd -;CHECK: kmovw -;CHECK: vpgatherqd -;CHECK: vpadd -;CHECK: vpscatterqd -;CHECK: ret define void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_qd: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherqd (%rsi,%zmm0,4), %ymm1 {%k2} +; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x i32> @llvm.x86.avx512.gather.qpi.512 (<8 x i32> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) %ind2 = add <8 x i64> %ind, <i64 0, i64 1, i64 2, i64 3, i64 0, i64 1, i64 2, i64 3> call void @llvm.x86.avx512.scatter.qpi.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind2, <8 x i32> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_qq -;CHECK: kmovw -;CHECK: vpgatherqq -;CHECK: vpadd -;CHECK: vpscatterqq -;CHECK: ret define void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_qq: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherqq (%rsi,%zmm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x i64> @llvm.x86.avx512.gather.qpq.512 (<8 x i64> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) %ind2 = add <8 x i64> %ind, <i64 0, i64 1, i64 2, i64 3, i64 0, i64 1, i64 2, i64 3> call void @llvm.x86.avx512.scatter.qpq.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind2, <8 x i64> %x, i32 4) ret void } -;CHECK-LABEL: gather_mask_dq -;CHECK: kmovw -;CHECK: vpgatherdq -;CHECK: vpadd -;CHECK: vpscatterdq -;CHECK: ret define void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_mask_dq: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherdq (%rsi,%ymm0,4), %zmm1 {%k2} +; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x i64> @llvm.x86.avx512.gather.dpq.512 (<8 x i64> %src, i8* %base, <8 x i32>%ind, i8 %mask, i32 4) %ind2 = add <8 x i32> %ind, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> call void @llvm.x86.avx512.scatter.dpq.512 (i8* %stbuf, i8 %mask, <8 x i32>%ind2, <8 x i64> %x, i32 4) ret void } - -;CHECK-LABEL: gather_mask_dpd_execdomain -;CHECK: vgatherdpd -;CHECK: vmovapd -;CHECK: ret define void @gather_mask_dpd_execdomain(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) { +; CHECK-LABEL: gather_mask_dpd_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k1} +; CHECK-NEXT: vmovapd %zmm1, (%rdx) +; CHECK-NEXT: retq %x = call <8 x double> @llvm.x86.avx512.gather.dpd.512 (<8 x double> %src, i8* %base, <8 x i32>%ind, i8 %mask, i32 4) store <8 x double> %x, <8 x double>* %stbuf ret void } -;CHECK-LABEL: gather_mask_qpd_execdomain -;CHECK: vgatherqpd -;CHECK: vmovapd -;CHECK: ret define void @gather_mask_qpd_execdomain(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) { +; CHECK-LABEL: gather_mask_qpd_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: vgatherqpd (%rsi,%zmm0,4), %zmm1 {%k1} +; CHECK-NEXT: vmovapd %zmm1, (%rdx) +; CHECK-NEXT: retq %x = call <8 x double> @llvm.x86.avx512.gather.qpd.512 (<8 x double> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) store <8 x double> %x, <8 x double>* %stbuf ret void } -;CHECK-LABEL: gather_mask_dps_execdomain -;CHECK: vgatherdps -;CHECK: vmovaps -;CHECK: ret define <16 x float> @gather_mask_dps_execdomain(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8* %base) { +; CHECK-LABEL: gather_mask_dps_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %edi, %k1 +; CHECK-NEXT: vgatherdps (%rsi,%zmm0,4), %zmm1 {%k1} +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq %res = call <16 x float> @llvm.x86.avx512.gather.dps.512 (<16 x float> %src, i8* %base, <16 x i32>%ind, i16 %mask, i32 4) ret <16 x float> %res; } -;CHECK-LABEL: gather_mask_qps_execdomain -;CHECK: vgatherqps -;CHECK: vmovaps -;CHECK: ret define <8 x float> @gather_mask_qps_execdomain(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %base) { +; CHECK-LABEL: gather_mask_qps_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %edi, %k1 +; CHECK-NEXT: vgatherqps (%rsi,%zmm0,4), %ymm1 {%k1} +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq %res = call <8 x float> @llvm.x86.avx512.gather.qps.512 (<8 x float> %src, i8* %base, <8 x i64>%ind, i8 %mask, i32 4) ret <8 x float> %res; } -;CHECK-LABEL: scatter_mask_dpd_execdomain -;CHECK: vmovapd -;CHECK: vscatterdpd -;CHECK: ret define void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) { - %x = load <8 x double>, <8 x double>* %src, align 64 +; CHECK-LABEL: scatter_mask_dpd_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovapd (%rdi), %zmm1 +; CHECK-NEXT: vscatterdpd %zmm1, (%rcx,%ymm0,4) {%k1} +; CHECK-NEXT: retq + %x = load <8 x double>, <8 x double>* %src, align 64 call void @llvm.x86.avx512.scatter.dpd.512 (i8* %stbuf, i8 %mask, <8 x i32>%ind, <8 x double> %x, i32 4) ret void } -;CHECK-LABEL: scatter_mask_qpd_execdomain -;CHECK: vmovapd -;CHECK: vscatterqpd -;CHECK: ret define void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: scatter_mask_qpd_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovapd (%rdi), %zmm1 +; CHECK-NEXT: vscatterqpd %zmm1, (%rcx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = load <8 x double>, <8 x double>* %src, align 64 call void @llvm.x86.avx512.scatter.qpd.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind, <8 x double> %x, i32 4) ret void } -;CHECK-LABEL: scatter_mask_dps_execdomain -;CHECK: vmovaps -;CHECK: vscatterdps -;CHECK: ret define void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i16 %mask, i8* %base, i8* %stbuf) { +; CHECK-LABEL: scatter_mask_dps_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovw %esi, %k1 +; CHECK-NEXT: vmovaps (%rdi), %zmm1 +; CHECK-NEXT: vscatterdps %zmm1, (%rcx,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = load <16 x float>, <16 x float>* %src, align 64 call void @llvm.x86.avx512.scatter.dps.512 (i8* %stbuf, i16 %mask, <16 x i32>%ind, <16 x float> %x, i32 4) ret void } -;CHECK-LABEL: scatter_mask_qps_execdomain -;CHECK: vmovaps -;CHECK: vscatterqps -;CHECK: ret define void @scatter_mask_qps_execdomain(<8 x i64> %ind, <8 x float>* %src, i8 %mask, i8* %base, i8* %stbuf) { - %x = load <8 x float>, <8 x float>* %src, align 32 +; CHECK-LABEL: scatter_mask_qps_execdomain: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps (%rdi), %ymm1 +; CHECK-NEXT: vscatterqps %ymm1, (%rcx,%zmm0,4) {%k1} +; CHECK-NEXT: retq + %x = load <8 x float>, <8 x float>* %src, align 32 call void @llvm.x86.avx512.scatter.qps.512 (i8* %stbuf, i8 %mask, <8 x i64>%ind, <8 x float> %x, i32 4) ret void } -;CHECK-LABEL: gather_qps -;CHECK: kxnorw -;CHECK: vgatherqps -;CHECK: vpadd -;CHECK: vscatterqps -;CHECK: ret define void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i8* %stbuf) { +; CHECK-LABEL: gather_qps: +; CHECK: ## BB#0: +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vgatherqps (%rdi,%zmm0,4), %ymm1 {%k2} +; CHECK-NEXT: vpaddq {{.*}}(%rip), %zmm0, %zmm0 +; CHECK-NEXT: vscatterqps %ymm1, (%rsi,%zmm0,4) {%k1} +; CHECK-NEXT: retq %x = call <8 x float> @llvm.x86.avx512.gather.qps.512 (<8 x float> %src, i8* %base, <8 x i64>%ind, i8 -1, i32 4) %ind2 = add <8 x i64> %ind, <i64 0, i64 1, i64 2, i64 3, i64 0, i64 1, i64 2, i64 3> call void @llvm.x86.avx512.scatter.qps.512 (i8* %stbuf, i8 -1, <8 x i64>%ind2, <8 x float> %x, i32 4) ret void } -;CHECK-LABEL: prefetch -;CHECK: gatherpf0 -;CHECK: gatherpf1 -;CHECK: scatterpf0 -;CHECK: scatterpf1 -;CHECK: ret declare void @llvm.x86.avx512.gatherpf.qps.512(i8, <8 x i64>, i8* , i32, i32); declare void @llvm.x86.avx512.scatterpf.qps.512(i8, <8 x i64>, i8* , i32, i32); define void @prefetch(<8 x i64> %ind, i8* %base) { +; CHECK-LABEL: prefetch: +; CHECK: ## BB#0: +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherpf0qps (%rdi,%zmm0,4) {%k1} +; CHECK-NEXT: vgatherpf1qps (%rdi,%zmm0,4) {%k1} +; CHECK-NEXT: vscatterpf0qps (%rdi,%zmm0,2) {%k1} +; CHECK-NEXT: vscatterpf1qps (%rdi,%zmm0,2) {%k1} +; CHECK-NEXT: retq call void @llvm.x86.avx512.gatherpf.qps.512(i8 -1, <8 x i64> %ind, i8* %base, i32 4, i32 0) call void @llvm.x86.avx512.gatherpf.qps.512(i8 -1, <8 x i64> %ind, i8* %base, i32 4, i32 1) call void @llvm.x86.avx512.scatterpf.qps.512(i8 -1, <8 x i64> %ind, i8* %base, i32 2, i32 0) call void @llvm.x86.avx512.scatterpf.qps.512(i8 -1, <8 x i64> %ind, i8* %base, i32 2, i32 1) ret void } + + +declare <2 x double> @llvm.x86.avx512.gather3div2.df(<2 x double>, i8*, <2 x i64>, i8, i32) + +define <2 x double>@test_int_x86_avx512_gather3div2_df(<2 x double> %x0, i8* %x1, <2 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div2_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherqpd (%rdi,%xmm1,4), %xmm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherqpd (%rdi,%xmm1,0), %xmm0 {%k1} +; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.gather3div2.df(<2 x double> %x0, i8* %x1, <2 x i64> %x2, i8 %x3, i32 4) + %res1 = call <2 x double> @llvm.x86.avx512.gather3div2.df(<2 x double> %x0, i8* %x1, <2 x i64> %x2, i8 -1, i32 0) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.gather3div2.di(<2 x i64>, i8*, <2 x i64>, i8, i32) + +define <4 x i32>@test_int_x86_avx512_gather3div2_di(<2 x i64> %x0, i8* %x1, <2 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div2_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpgatherqq (%rdi,%xmm1,8), %xmm0 {%k1} +; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x i32> @llvm.x86.avx512.gather3div2.di(<2 x i64> %x0, i8* %x1, <2 x i64> %x2, i8 %x3, i32 8) + %res1 = call <4 x i32> @llvm.x86.avx512.gather3div2.di(<2 x i64> %x0, i8* %x1, <2 x i64> %x2, i8 %x3, i32 8) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <4 x double> @llvm.x86.avx512.gather3div4.df(<4 x double>, i8*, <4 x i64>, i8, i32) + +define <4 x double>@test_int_x86_avx512_gather3div4_df(<4 x double> %x0, i8* %x1, <4 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div4_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherqpd (%rdi,%ymm1,4), %ymm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherqpd (%rdi,%ymm1,0), %ymm0 {%k1} +; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.gather3div4.df(<4 x double> %x0, i8* %x1, <4 x i64> %x2, i8 %x3, i32 4) + %res1 = call <4 x double> @llvm.x86.avx512.gather3div4.df(<4 x double> %x0, i8* %x1, <4 x i64> %x2, i8 -1, i32 0) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.gather3div4.di(<4 x i64>, i8*, <4 x i64>, i8, i32) + +define <8 x i32>@test_int_x86_avx512_gather3div4_di(<4 x i64> %x0, i8* %x1, <4 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div4_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vpgatherqq (%rdi,%ymm1,8), %ymm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpgatherqq (%rdi,%ymm1,8), %ymm0 {%k1} +; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x i32> @llvm.x86.avx512.gather3div4.di(<4 x i64> %x0, i8* %x1, <4 x i64> %x2, i8 %x3, i32 8) + %res1 = call <8 x i32> @llvm.x86.avx512.gather3div4.di(<4 x i64> %x0, i8* %x1, <4 x i64> %x2, i8 -1, i32 8) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + +declare <4 x float> @llvm.x86.avx512.gather3div4.sf(<4 x float>, i8*, <2 x i64>, i8, i32) + +define <4 x float>@test_int_x86_avx512_gather3div4_sf(<4 x float> %x0, i8* %x1, <2 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div4_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherqps (%rdi,%xmm1,4), %xmm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherqps (%rdi,%xmm1,0), %xmm0 {%k1} +; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.gather3div4.sf(<4 x float> %x0, i8* %x1, <2 x i64> %x2, i8 %x3, i32 4) + %res1 = call <4 x float> @llvm.x86.avx512.gather3div4.sf(<4 x float> %x0, i8* %x1, <2 x i64> %x2, i8 -1, i32 0) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.gather3div4.si(<4 x i32>, i8*, <2 x i64>, i8, i32) + +define <4 x i32>@test_int_x86_avx512_gather3div4_si(<4 x i32> %x0, i8* %x1, <2 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div4_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vpgatherqd (%rdi,%xmm1,4), %xmm2 {%k2} +; CHECK-NEXT: vpgatherqd (%rdi,%xmm1,4), %xmm0 {%k1} +; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x i32> @llvm.x86.avx512.gather3div4.si(<4 x i32> %x0, i8* %x1, <2 x i64> %x2, i8 -1, i32 4) + %res1 = call <4 x i32> @llvm.x86.avx512.gather3div4.si(<4 x i32> %x0, i8* %x1, <2 x i64> %x2, i8 %x3, i32 4) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <4 x float> @llvm.x86.avx512.gather3div8.sf(<4 x float>, i8*, <4 x i64>, i8, i32) + +define <4 x float>@test_int_x86_avx512_gather3div8_sf(<4 x float> %x0, i8* %x1, <4 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div8_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherqps (%rdi,%ymm1,4), %xmm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherqps (%rdi,%ymm1,0), %xmm0 {%k1} +; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.gather3div8.sf(<4 x float> %x0, i8* %x1, <4 x i64> %x2, i8 %x3, i32 4) + %res1 = call <4 x float> @llvm.x86.avx512.gather3div8.sf(<4 x float> %x0, i8* %x1, <4 x i64> %x2, i8 -1, i32 0) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.gather3div8.si(<4 x i32>, i8*, <4 x i64>, i8, i32) + +define <4 x i32>@test_int_x86_avx512_gather3div8_si(<4 x i32> %x0, i8* %x1, <4 x i64> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3div8_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherqd (%rdi,%ymm1,4), %xmm2 {%k2} +; CHECK-NEXT: vpgatherqd (%rdi,%ymm1,2), %xmm0 {%k1} +; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x i32> @llvm.x86.avx512.gather3div8.si(<4 x i32> %x0, i8* %x1, <4 x i64> %x2, i8 %x3, i32 4) + %res1 = call <4 x i32> @llvm.x86.avx512.gather3div8.si(<4 x i32> %x0, i8* %x1, <4 x i64> %x2, i8 %x3, i32 2) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <2 x double> @llvm.x86.avx512.gather3siv2.df(<2 x double>, i8*, <4 x i32>, i8, i32) + +define <2 x double>@test_int_x86_avx512_gather3siv2_df(<2 x double> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv2_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherdpd (%rdi,%xmm1,4), %xmm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherdpd (%rdi,%xmm1,0), %xmm0 {%k1} +; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.gather3siv2.df(<2 x double> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 4) + %res1 = call <2 x double> @llvm.x86.avx512.gather3siv2.df(<2 x double> %x0, i8* %x1, <4 x i32> %x2, i8 -1, i32 0) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.gather3siv2.di(<2 x i64>, i8*, <4 x i32>, i8, i32) + +define <4 x i32>@test_int_x86_avx512_gather3siv2_di(<2 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv2_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1} +; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x i32> @llvm.x86.avx512.gather3siv2.di(<2 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 8) + %res1 = call <4 x i32> @llvm.x86.avx512.gather3siv2.di(<2 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 8) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <4 x double> @llvm.x86.avx512.gather3siv4.df(<4 x double>, i8*, <4 x i32>, i8, i32) + +define <4 x double>@test_int_x86_avx512_gather3siv4_df(<4 x double> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv4_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherdpd (%rdi,%xmm1,4), %ymm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherdpd (%rdi,%xmm1,0), %ymm0 {%k1} +; CHECK-NEXT: vaddpd %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.gather3siv4.df(<4 x double> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 4) + %res1 = call <4 x double> @llvm.x86.avx512.gather3siv4.df(<4 x double> %x0, i8* %x1, <4 x i32> %x2, i8 -1, i32 0) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.gather3siv4.di(<4 x i64>, i8*, <4 x i32>, i8, i32) + +define <8 x i32>@test_int_x86_avx512_gather3siv4_di(<4 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv4_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpgatherdq (%rdi,%xmm1,8), %ymm0 {%k1} +; CHECK-NEXT: vpaddd %ymm0, %ymm0, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x i32> @llvm.x86.avx512.gather3siv4.di(<4 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 8) + %res1 = call <8 x i32> @llvm.x86.avx512.gather3siv4.di(<4 x i64> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 8) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + +declare <4 x float> @llvm.x86.avx512.gather3siv4.sf(<4 x float>, i8*, <4 x i32>, i8, i32) + +define <4 x float>@test_int_x86_avx512_gather3siv4_sf(<4 x float> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv4_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherdps (%rdi,%xmm1,4), %xmm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherdps (%rdi,%xmm1,0), %xmm0 {%k1} +; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.gather3siv4.sf(<4 x float> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 4) + %res1 = call <4 x float> @llvm.x86.avx512.gather3siv4.sf(<4 x float> %x0, i8* %x1, <4 x i32> %x2, i8 -1, i32 0) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.gather3siv4.si(<4 x i32>, i8*, <4 x i32>, i8, i32) + +define <4 x i32>@test_int_x86_avx512_gather3siv4_si(<4 x i32> %x0, i8* %x1, <4 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv4_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vpgatherdd (%rdi,%xmm1,4), %xmm2 {%k2} +; CHECK-NEXT: vpgatherdd (%rdi,%xmm1,0), %xmm0 {%k1} +; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x i32> @llvm.x86.avx512.gather3siv4.si(<4 x i32> %x0, i8* %x1, <4 x i32> %x2, i8 -1, i32 4) + %res1 = call <4 x i32> @llvm.x86.avx512.gather3siv4.si(<4 x i32> %x0, i8* %x1, <4 x i32> %x2, i8 %x3, i32 0) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <8 x float> @llvm.x86.avx512.gather3siv8.sf(<8 x float>, i8*, <8 x i32>, i8, i32) + +define <8 x float>@test_int_x86_avx512_gather3siv8_sf(<8 x float> %x0, i8* %x1, <8 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv8_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: vgatherdps (%rdi,%ymm1,4), %ymm2 {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vgatherdps (%rdi,%ymm1,0), %ymm0 {%k1} +; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.gather3siv8.sf(<8 x float> %x0, i8* %x1, <8 x i32> %x2, i8 %x3, i32 4) + %res1 = call <8 x float> @llvm.x86.avx512.gather3siv8.sf(<8 x float> %x0, i8* %x1, <8 x i32> %x2, i8 -1, i32 0) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.gather3siv8.si(<8 x i32>, i8*, <8 x i32>, i8, i32) + +define <8 x i32>@test_int_x86_avx512_gather3siv8_si(<8 x i32> %x0, i8* %x1, <8 x i32> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_gather3siv8_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm2 +; CHECK-NEXT: kmovw %k1, %k2 +; CHECK-NEXT: vpgatherdd (%rdi,%ymm1,4), %ymm2 {%k2} +; CHECK-NEXT: vpgatherdd (%rdi,%ymm1,0), %ymm0 {%k1} +; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x i32> @llvm.x86.avx512.gather3siv8.si(<8 x i32> %x0, i8* %x1, <8 x i32> %x2, i8 %x3, i32 4) + %res1 = call <8 x i32> @llvm.x86.avx512.gather3siv8.si(<8 x i32> %x0, i8* %x1, <8 x i32> %x2, i8 %x3, i32 0) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + +declare void @llvm.x86.avx512.scatterdiv2.df(i8*, i8, <2 x i64>, <2 x double>, i32) + +define void@test_int_x86_avx512_scatterdiv2_df(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x double> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv2_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vscatterqpd %xmm1, (%rdi,%xmm0,0) {%k2} +; CHECK-NEXT: vscatterqpd %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv2.df(i8* %x0, i8 -1, <2 x i64> %x2, <2 x double> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv2.df(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x double> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv2.di(i8*, i8, <2 x i64>, <2 x i64>, i32) + +define void@test_int_x86_avx512_scatterdiv2_di(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x i64> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv2_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpscatterqq %xmm1, (%rdi,%xmm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpscatterqq %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv2.di(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x i64> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv2.di(i8* %x0, i8 -1, <2 x i64> %x2, <2 x i64> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv4.df(i8*, i8, <4 x i64>, <4 x double>, i32) + +define void@test_int_x86_avx512_scatterdiv4_df(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x double> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterqpd %ymm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterqpd %ymm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv4.df(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x double> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv4.df(i8* %x0, i8 -1, <4 x i64> %x2, <4 x double> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv4.di(i8*, i8, <4 x i64>, <4 x i64>, i32) + +define void@test_int_x86_avx512_scatterdiv4_di(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i64> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpscatterqq %ymm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpscatterqq %ymm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv4.di(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i64> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv4.di(i8* %x0, i8 -1, <4 x i64> %x2, <4 x i64> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv4.sf(i8*, i8, <2 x i64>, <4 x float>, i32) + +define void@test_int_x86_avx512_scatterdiv4_sf(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x float> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterqps %xmm1, (%rdi,%xmm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterqps %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv4.sf(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x float> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv4.sf(i8* %x0, i8 -1, <2 x i64> %x2, <4 x float> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv4.si(i8*, i8, <2 x i64>, <4 x i32>, i32) + +define void@test_int_x86_avx512_scatterdiv4_si(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x i32> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vpscatterqd %xmm1, (%rdi,%xmm0,0) {%k2} +; CHECK-NEXT: vpscatterqd %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv4.si(i8* %x0, i8 -1, <2 x i64> %x2, <4 x i32> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv4.si(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x i32> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv8.sf(i8*, i8, <4 x i64>, <4 x float>, i32) + +define void@test_int_x86_avx512_scatterdiv8_sf(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x float> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv8_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterqps %xmm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterqps %xmm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv8.sf(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x float> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv8.sf(i8* %x0, i8 -1, <4 x i64> %x2, <4 x float> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scatterdiv8.si(i8*, i8, <4 x i64>, <4 x i32>, i32) + +define void@test_int_x86_avx512_scatterdiv8_si(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i32> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scatterdiv8_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpscatterqd %xmm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpscatterqd %xmm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scatterdiv8.si(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i32> %x3, i32 0) + call void @llvm.x86.avx512.scatterdiv8.si(i8* %x0, i8 -1, <4 x i64> %x2, <4 x i32> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv2.df(i8*, i8, <4 x i32>, <2 x double>, i32) + +define void@test_int_x86_avx512_scattersiv2_df(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x double> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv2_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vscatterdpd %xmm1, (%rdi,%xmm0,0) {%k2} +; CHECK-NEXT: vscatterdpd %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv2.df(i8* %x0, i8 -1, <4 x i32> %x2, <2 x double> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv2.df(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x double> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv2.di(i8*, i8, <4 x i32>, <2 x i64>, i32) + +define void@test_int_x86_avx512_scattersiv2_di(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x i64> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv2_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vpscatterdq %xmm1, (%rdi,%xmm0,0) {%k2} +; CHECK-NEXT: vpscatterdq %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv2.di(i8* %x0, i8 -1, <4 x i32> %x2, <2 x i64> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv2.di(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x i64> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv4.df(i8*, i8, <4 x i32>, <4 x double>, i32) + +define void@test_int_x86_avx512_scattersiv4_df(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x double> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv4_df: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterdpd %ymm1, (%rdi,%xmm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterdpd %ymm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv4.df(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x double> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv4.df(i8* %x0, i8 -1, <4 x i32> %x2, <4 x double> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv4.di(i8*, i8, <4 x i32>, <4 x i64>, i32) + +define void@test_int_x86_avx512_scattersiv4_di(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i64> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv4_di: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: kxnorw %k2, %k2, %k2 +; CHECK-NEXT: vpscatterdq %ymm1, (%rdi,%xmm0,0) {%k2} +; CHECK-NEXT: vpscatterdq %ymm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv4.di(i8* %x0, i8 -1, <4 x i32> %x2, <4 x i64> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv4.di(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i64> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv4.sf(i8*, i8, <4 x i32>, <4 x float>, i32) + +define void@test_int_x86_avx512_scattersiv4_sf(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x float> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv4_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterdps %xmm1, (%rdi,%xmm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterdps %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv4.sf(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x float> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv4.sf(i8* %x0, i8 -1, <4 x i32> %x2, <4 x float> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv4.si(i8*, i8, <4 x i32>, <4 x i32>, i32) + +define void@test_int_x86_avx512_scattersiv4_si(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i32> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv4_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv4.si(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i32> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv4.si(i8* %x0, i8 -1, <4 x i32> %x2, <4 x i32> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv8.sf(i8*, i8, <8 x i32>, <8 x float>, i32) + +define void@test_int_x86_avx512_scattersiv8_sf(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x float> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv8_sf: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vscatterdps %ymm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vscatterdps %ymm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv8.sf(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x float> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv8.sf(i8* %x0, i8 -1, <8 x i32> %x2, <8 x float> %x3, i32 4) + ret void +} + +declare void @llvm.x86.avx512.scattersiv8.si(i8*, i8, <8 x i32>, <8 x i32>, i32) + +define void@test_int_x86_avx512_scattersiv8_si(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x i32> %x3) { +; CHECK-LABEL: test_int_x86_avx512_scattersiv8_si: +; CHECK: ## BB#0: +; CHECK-NEXT: kmovb %esi, %k1 +; CHECK-NEXT: vpscatterdd %ymm1, (%rdi,%ymm0,0) {%k1} +; CHECK-NEXT: kxnorw %k1, %k1, %k1 +; CHECK-NEXT: vpscatterdd %ymm1, (%rdi,%ymm0,4) {%k1} +; CHECK-NEXT: retq + call void @llvm.x86.avx512.scattersiv8.si(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x i32> %x3, i32 0) + call void @llvm.x86.avx512.scattersiv8.si(i8* %x0, i8 -1, <8 x i32> %x2, <8 x i32> %x3, i32 4) + ret void +} + diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll index a06cadaa3f5ab..b9f490b8a39af 100644 --- a/test/CodeGen/X86/avx512-intrinsics.ll +++ b/test/CodeGen/X86/avx512-intrinsics.ll @@ -489,19 +489,31 @@ declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double> } declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32) - define <16 x i32> @test_pabsd(<16 x i32> %a) { - ;CHECK: vpabsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x1e,0xc0] - %res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %a, <16 x i32>zeroinitializer, i16 -1) - ret < 16 x i32> %res - } declare <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32>, <16 x i32>, i16) - define <8 x i64> @test_pabsq(<8 x i64> %a) { - ;CHECK: vpabsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xc0] - %res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %a, <8 x i64>zeroinitializer, i8 -1) - ret <8 x i64> %res - } - declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8) +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_d_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsd{{.*}}{%k1} +define <16 x i32>@test_int_x86_avx512_mask_pabs_d_512(<16 x i32> %x0, <16 x i32> %x1, i16 %x2) { + %res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %x0, <16 x i32> %x1, i16 %x2) + %res1 = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %x0, <16 x i32> %x1, i16 -1) + %res2 = add <16 x i32> %res, %res1 + ret <16 x i32> %res2 +} + +declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_q_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsq{{.*}}{%k1} +define <8 x i64>@test_int_x86_avx512_mask_pabs_q_512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) { + %res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) + %res1 = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 -1) + %res2 = add <8 x i64> %res, %res1 + ret <8 x i64> %res2 +} define i8 @test_vptestmq(<8 x i64> %a0, <8 x i64> %a1) { ; CHECK: vptestmq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc1] @@ -3013,3 +3025,146 @@ define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> % %res2 = add <8 x i64> %res, %res1 ret <8 x i64> %res2 } + +declare <16 x i32> @llvm.x86.avx512.mask.vpermi2var.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_d_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2d {{.*}}{%k1} +define <16 x i32>@test_int_x86_avx512_mask_vpermi2var_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) { + %res = call <16 x i32> @llvm.x86.avx512.mask.vpermi2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) + %res1 = call <16 x i32> @llvm.x86.avx512.mask.vpermi2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1) + %res2 = add <16 x i32> %res, %res1 + ret <16 x i32> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double>, <8 x i64>, <8 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_pd_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2pd {{.*}}{%k1} +define <8 x double>@test_int_x86_avx512_mask_vpermi2var_pd_512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) { + %res = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 %x3) + %res1 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> %x1, <8 x double> %x2, i8 -1) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask.vpermi2var.ps.512(<16 x float>, <16 x i32>, <16 x float>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_ps_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2ps {{.*}}{%k1} +define <16 x float>@test_int_x86_avx512_mask_vpermi2var_ps_512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) { + %res = call <16 x float> @llvm.x86.avx512.mask.vpermi2var.ps.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 %x3) + %res1 = call <16 x float> @llvm.x86.avx512.mask.vpermi2var.ps.512(<16 x float> %x0, <16 x i32> %x1, <16 x float> %x2, i16 -1) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + +declare <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_q_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2q {{.*}}{%k1} +define <8 x i64>@test_int_x86_avx512_mask_vpermi2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { + %res = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) + %res1 = call <8 x i64> @llvm.x86.avx512.mask.vpermi2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) + %res2 = add <8 x i64> %res, %res1 + ret <8 x i64> %res2 +} + +declare <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_d_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d {{.*}}{%k1} {z} +define <16 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) { + %res = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) + %res1 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1) + %res2 = add <16 x i32> %res, %res1 + ret <16 x i32> %res2 +} + +declare <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64>, <8 x double>, <8 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_pd_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2pd {{.*}}{%k1} {z} +define <8 x double>@test_int_x86_avx512_maskz_vpermt2var_pd_512(<8 x i64> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) { + %res = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) + %res1 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32>, <16 x float>, <16 x float>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_ps_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2ps {{.*}}{%k1} {z} +define <16 x float>@test_int_x86_avx512_maskz_vpermt2var_ps_512(<16 x i32> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3) { + %res = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3) + %res1 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} + + +declare <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_q_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2q {{.*}}{%k1} {z} +define <8 x i64>@test_int_x86_avx512_maskz_vpermt2var_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) { + %res = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) + %res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1) + %res2 = add <8 x i64> %res, %res1 + ret <8 x i64> %res2 +} + +declare <16 x i32> @llvm.x86.avx512.mask.vpermt2var.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_d_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d {{.*}}{%k1} +; CHECK-NOT: {z} +define <16 x i32>@test_int_x86_avx512_mask_vpermt2var_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) { + %res = call <16 x i32> @llvm.x86.avx512.mask.vpermt2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) + %res1 = call <16 x i32> @llvm.x86.avx512.mask.vpermt2var.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1) + %res2 = add <16 x i32> %res, %res1 + ret <16 x i32> %res2 +} + +declare <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_pd_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefpd{{.*}}{%k1} +define <8 x double>@test_int_x86_avx512_mask_scalef_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3) { + %res = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 %x3, i32 3) + %res1 = call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, i8 -1, i32 0) + %res2 = fadd <8 x double> %res, %res1 + ret <8 x double> %res2 +} + +declare <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_ps_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefps{{.*}}{%k1} +define <16 x float>@test_int_x86_avx512_mask_scalef_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3) { + %res = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 %x3, i32 2) + %res1 = call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, i16 -1, i32 0) + %res2 = fadd <16 x float> %res, %res1 + ret <16 x float> %res2 +} diff --git a/test/CodeGen/X86/avx512-shuffle.ll b/test/CodeGen/X86/avx512-shuffle.ll deleted file mode 100644 index 7e9eda58737d1..0000000000000 --- a/test/CodeGen/X86/avx512-shuffle.ll +++ /dev/null @@ -1,392 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=CHECK-SKX - -; CHECK-LABEL: test1: -; CHECK: vpermps -; CHECK: ret -define <16 x float> @test1(<16 x float> %a) nounwind { - %c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1> - ret <16 x float> %c -} - -; CHECK-LABEL: test2: -; CHECK: vpermd -; CHECK: ret -define <16 x i32> @test2(<16 x i32> %a) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1> - ret <16 x i32> %c -} - -; CHECK-LABEL: test3: -; CHECK: vpermq -; CHECK: ret -define <8 x i64> @test3(<8 x i64> %a) nounwind { - %c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1> - ret <8 x i64> %c -} - -; CHECK-LABEL: test4: -; CHECK: vpermpd -; CHECK: ret -define <8 x double> @test4(<8 x double> %a) nounwind { - %c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - ret <8 x double> %c -} - -; CHECK-LABEL: test5: -; CHECK: vpermt2pd -; CHECK: ret -define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind { - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5> - ret <8 x double> %c -} - -; CHECK-LABEL: test6: -; CHECK: vpermq $30 -; CHECK: ret -define <8 x i64> @test6(<8 x i64> %a) nounwind { - %c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4> - ret <8 x i64> %c -} - -; CHECK-LABEL: test7: -; CHECK: vpermt2q -; CHECK: ret -define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind { - %c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5> - ret <8 x i64> %c -} - -; CHECK-LABEL: test8: -; CHECK: vpermt2d -; CHECK: ret -define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24> - ret <16 x i32> %c -} - -; CHECK-LABEL: test9: -; CHECK: vpermt2ps -; CHECK: ret -define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind { - %c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24> - ret <16 x float> %c -} - -; CHECK-LABEL: test10: -; CHECK: vpermt2ps ( -; CHECK: ret -define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind { - %c = load <16 x float>, <16 x float>* %b - %d = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24> - ret <16 x float> %d -} - -; CHECK-LABEL: test11: -; CHECK: vpermt2d -; CHECK: ret -define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind { - %c = load <16 x i32>, <16 x i32>* %b - %d = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24> - ret <16 x i32> %d -} - -; CHECK-LABEL: test13 -; CHECK: vpermilps $177, %zmm -; CHECK: ret -define <16 x float> @test13(<16 x float> %a) { - %b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> - ret <16 x float> %b -} - -; CHECK-LABEL: test14 -; CHECK: vpermilpd $203, %zmm -; CHECK: ret -define <8 x double> @test14(<8 x double> %a) { - %b = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32><i32 1, i32 1, i32 2, i32 3, i32 4, i32 4, i32 7, i32 7> - ret <8 x double> %b -} - -; CHECK-LABEL: test15 -; CHECK: vpshufd $177, %zmm -; CHECK: ret -define <16 x i32> @test15(<16 x i32> %a) { -; mask 1-0-3-2 = 10110001 = 0xb1 = 177 - %b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32><i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> - ret <16 x i32> %b -} -; CHECK-LABEL: test16 -; CHECK: valignq $3, %zmm0, %zmm1 -; CHECK: ret -define <8 x double> @test16(<8 x double> %a, <8 x double> %b) nounwind { - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> - ret <8 x double> %c -} - -; CHECK-LABEL: test17 -; CHECK: vshufpd $19, %zmm1, %zmm0 -; CHECK: ret -define <8 x double> @test17(<8 x double> %a, <8 x double> %b) nounwind { - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 9, i32 2, i32 10, i32 5, i32 undef, i32 undef, i32 undef> - ret <8 x double> %c -} - -; CHECK-LABEL: test18 -; CHECK: vpunpckhdq %zmm -; CHECK: ret -define <16 x i32> @test18(<16 x i32> %a, <16 x i32> %c) { - %b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> - ret <16 x i32> %b -} - -; CHECK-LABEL: test19 -; CHECK: vpunpckldq %zmm -; CHECK: ret -define <16 x i32> @test19(<16 x i32> %a, <16 x i32> %c) { - %b = shufflevector <16 x i32> %a, <16 x i32> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> - ret <16 x i32> %b -} - -; CHECK-LABEL: test20 -; CHECK: vpunpckhqdq %zmm -; CHECK: ret -define <8 x i64> @test20(<8 x i64> %a, <8 x i64> %c) { - %b = shufflevector <8 x i64> %a, <8 x i64> %c, <8 x i32><i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> - ret <8 x i64> %b -} - -; CHECK-LABEL: test21 -; CHECK: vbroadcastsd %xmm0, %zmm -; CHECK: ret -define <8 x double> @test21(<8 x double> %a, <8 x double> %b) { - %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> - ret <8 x double> %shuffle -} - -; CHECK-LABEL: test22 -; CHECK: vpbroadcastq %xmm0, %zmm -; CHECK: ret -define <8 x i64> @test22(<8 x i64> %a, <8 x i64> %b) { - %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> - ret <8 x i64> %shuffle -} - -; CHECK-LABEL: @test23 -; CHECK: vshufps -; CHECK: vshufps -; CHECK: ret -define <16 x i32> @test23(<16 x i32> %a, <16 x i32> %b) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - ret <16 x i32> %c -} - -; CHECK-LABEL: @test24 -; CHECK: vpermt2d -; CHECK: ret -define <16 x i32> @test24(<16 x i32> %a, <16 x i32> %b) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 25, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - ret <16 x i32> %c -} - -; CHECK-LABEL: @test25 -; CHECK: vshufps $52 -; CHECK: ret -define <16 x i32> @test25(<16 x i32> %a, <16 x i32> %b) nounwind { -; mask - 0-1-3-0 00110100 = 0x34 = 52 - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 19, i32 16, i32 4, i32 5, i32 23, i32 undef, i32 8, i32 9, i32 27, i32 undef, i32 12, i32 13, i32 undef, i32 undef> - ret <16 x i32> %c -} - -; CHECK-LABEL: @test26 -; CHECK: vmovshdup -; CHECK: ret -define <16 x i32> @test26(<16 x i32> %a) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 undef, i32 9, i32 9, i32 undef, i32 11, i32 13, i32 undef, i32 undef, i32 undef> - ret <16 x i32> %c -} - -; CHECK-LABEL: @test27 -; CHECK: ret -define <16 x i32> @test27(<4 x i32>%a) { - %res = shufflevector <4 x i32> %a, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - ret <16 x i32> %res -} - -; CHECK-LABEL: test28 -; CHECK: vpshufhw $177, %ymm -; CHECK: ret -define <16 x i16> @test28(<16 x i16> %a) { - %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32><i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 10, i32 11, i32 13, i32 12, i32 15, i32 14> - ret <16 x i16> %b -} - -; CHECK-LABEL: test29 -; CHECK: vunpcklps %zmm -; CHECK: ret -define <16 x float> @test29(<16 x float> %a, <16 x float> %c) { - %b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> - ret <16 x float> %b -} - -; CHECK-LABEL: @test30 -; CHECK: vshufps $144, %zmm -; CHECK: ret -define <16 x float> @test30(<16 x float> %a, <16 x float> %c) { - %b = shufflevector <16 x float> %a, <16 x float> %c, <16 x i32><i32 0, i32 0, i32 17, i32 18, i32 4, i32 4, i32 21, i32 22, i32 8, i32 8, i32 25, i32 26, i32 12, i32 12, i32 29, i32 30> - ret <16 x float> %b -} - -; CHECK-LABEL: test31 -; CHECK: valignd $3, %zmm0, %zmm1 -; CHECK: ret -define <16 x i32> @test31(<16 x i32> %a, <16 x i32> %b) nounwind { - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> - ret <16 x i32> %c -} - -; CHECK-LABEL: test32 -; CHECK: vshufpd $99, %zmm0, %zmm1 -; CHECK: ret -define <8 x double> @test32(<8 x double> %a, <8 x double> %b) nounwind { - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 1, i32 10, i32 2, i32 undef, i32 5, i32 15, i32 undef> - ret <8 x double> %c -} - -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s -define <8 x double> @test_vshuff64x2_512(<8 x double> %x, <8 x double> %x1) nounwind { -; CHECK-LABEL: test_vshuff64x2_512: -; CHECK: ## BB#0: -; CHECK-NEXT: vshuff64x2 $136, %zmm0, %zmm0, %zmm0 -; CHECK-NEXT: retq - %res = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 0, i32 1, i32 4, i32 5> - ret <8 x double> %res -} - -define <8 x double> @test_vshuff64x2_512_mask(<8 x double> %x, <8 x double> %x1, <8 x i1> %mask) nounwind { -; CHECK-LABEL: test_vshuff64x2_512_mask: -; CHECK: ## BB#0: -; CHECK-NEXT: vpmovsxwq %xmm2, %zmm1 -; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1 -; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 -; CHECK-NEXT: vshuff64x2 $136, %zmm0, %zmm0, %zmm0 {%k1} {z} -; CHECK-NEXT: retq - %y = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 0, i32 1, i32 4, i32 5> - %res = select <8 x i1> %mask, <8 x double> %y, <8 x double> zeroinitializer - ret <8 x double> %res -} - -define <8 x i64> @test_vshufi64x2_512_mask(<8 x i64> %x, <8 x i64> %x1, <8 x i1> %mask) nounwind { -; CHECK-LABEL: test_vshufi64x2_512_mask: -; CHECK: ## BB#0: -; CHECK-NEXT: vpmovsxwq %xmm2, %zmm1 -; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1 -; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 -; CHECK-NEXT: vshufi64x2 $168, %zmm0, %zmm0, %zmm0 {%k1} -; CHECK-NEXT: retq - %y = shufflevector <8 x i64> %x, <8 x i64> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 4, i32 5> - %res = select <8 x i1> %mask, <8 x i64> %y, <8 x i64> %x - ret <8 x i64> %res -} - -define <8 x double> @test_vshuff64x2_512_mem(<8 x double> %x, <8 x double> *%ptr) nounwind { -; CHECK-LABEL: test_vshuff64x2_512_mem: -; CHECK: ## BB#0: -; CHECK-NEXT: vshuff64x2 $40, %zmm0, %zmm0, %zmm0 -; CHECK-NEXT: retq - %x1 = load <8 x double>,<8 x double> *%ptr,align 1 - %res = shufflevector <8 x double> %x, <8 x double> %x1, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 0, i32 1> - ret <8 x double> %res -} - -define <16 x float> @test_vshuff32x4_512_mem(<16 x float> %x, <16 x float> *%ptr) nounwind { -; CHECK-LABEL: test_vshuff32x4_512_mem: -; CHECK: ## BB#0: -; CHECK-NEXT: vshuff64x2 $20, %zmm0, %zmm0, %zmm0 -; CHECK-NEXT: retq - %x1 = load <16 x float>,<16 x float> *%ptr,align 1 - %res = shufflevector <16 x float> %x, <16 x float> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> - ret <16 x float> %res -} - -define <16 x i32> @test_align_v16i32_rr(<16 x i32> %a, <16 x i32> %b) nounwind { -; CHECK-LABEL: test_align_v16i32_rr: -; CHECK: ## BB#0: -; CHECK-NEXT: valignd $3, %zmm0, %zmm1, %zmm0 -; CHECK-NEXT: retq - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> - ret <16 x i32> %c -} - -define <16 x i32> @test_align_v16i32_rm(<16 x i32>* %a.ptr, <16 x i32> %b) nounwind { -; CHECK-LABEL: test_align_v16i32_rm: -; CHECK: ## BB#0: -; CHECK-NEXT: valignd $3, (%rdi), %zmm0, %zmm0 -; CHECK-NEXT: retq - %a = load <16 x i32>, <16 x i32>* %a.ptr - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> - ret <16 x i32> %c -} - -define <16 x i32> @test_align_v16i32_rm_mask(<16 x i32>* %a.ptr, <16 x i32> %b, <16 x i1> %mask) nounwind { -; CHECK-LABEL: test_align_v16i32_rm_mask: -; CHECK: ## BB#0: -; CHECK-NEXT: vpmovsxbd %xmm1, %zmm1 -; CHECK-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm1, %zmm1 -; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1 -; CHECK-NEXT: vmovdqa32 (%rdi), %zmm1 -; CHECK-NEXT: valignd $3, %zmm1, %zmm0, %zmm1 {%k1} -; CHECK-NEXT: vmovaps %zmm1, %zmm0 -; CHECK-NEXT: retq -; -; CHECK-SKX-LABEL: test_align_v16i32_rm_mask: -; CHECK-SKX: ## BB#0: -; CHECK-SKX-NEXT: vpmovb2m %xmm1, %k1 -; CHECK-SKX-NEXT: vmovdqa32 (%rdi), %zmm1 -; CHECK-SKX-NEXT: valignd $3, %zmm1, %zmm0, %zmm1 {%k1} -; CHECK-SKX-NEXT: vmovaps %zmm1, %zmm0 -; CHECK-SKX-NEXT: retq - %a = load <16 x i32>, <16 x i32>* %a.ptr - %c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> - %res = select <16 x i1> %mask,<16 x i32> %c, <16 x i32> %a - ret <16 x i32> %res -} - -define <8 x double> @test_align_v8f64_rr(<8 x double> %a, <8 x double> %b) nounwind { -; CHECK-LABEL: test_align_v8f64_rr: -; CHECK: ## BB#0: -; CHECK-NEXT: valignq $3, %zmm0, %zmm1, %zmm0 -; CHECK-NEXT: retq - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> - ret <8 x double> %c -} - -define <8 x double> @test_align_v18f64_rm(<8 x double>* %a.ptr, <8 x double> %b) nounwind { -; CHECK-LABEL: test_align_v18f64_rm: -; CHECK: ## BB#0: -; CHECK-NEXT: valignq $3, (%rdi), %zmm0, %zmm0 -; CHECK-NEXT: retq - %a = load <8 x double>, <8 x double>* %a.ptr - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> - ret <8 x double> %c -} - -define <8 x double> @test_align_v18f64_rm_mask(<8 x double>* %a.ptr, <8 x double> %b, <8 x i1> %mask) nounwind { -; CHECK-LABEL: test_align_v18f64_rm_mask: -; CHECK: ## BB#0: -; CHECK-NEXT: vpmovsxwq %xmm1, %zmm1 -; CHECK-NEXT: vpandq {{.*}}(%rip){1to8}, %zmm1, %zmm1 -; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 -; CHECK-NEXT: valignq $3, (%rdi), %zmm0, %zmm0 {%k1} {z} -; CHECK-NEXT: retq -; -; CHECK-SKX-LABEL: test_align_v18f64_rm_mask: -; CHECK-SKX: ## BB#0: -; CHECK-SKX-NEXT: vpmovw2m %xmm1, %k1 -; CHECK-SKX-NEXT: valignq $3, (%rdi), %zmm0, %zmm0 {%k1} {z} -; CHECK-SKX-NEXT: retq - %a = load <8 x double>, <8 x double>* %a.ptr - %c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> - %res = select <8 x i1> %mask,<8 x double> %c, <8 x double> zeroinitializer - ret <8 x double> %res -} - diff --git a/test/CodeGen/X86/avx512bw-intrinsics.ll b/test/CodeGen/X86/avx512bw-intrinsics.ll index 9ee0e09d1b7a2..9574c016ad509 100644 --- a/test/CodeGen/X86/avx512bw-intrinsics.ll +++ b/test/CodeGen/X86/avx512bw-intrinsics.ll @@ -893,6 +893,45 @@ define <32 x i16>@test_int_x86_avx512_mask_pminu_w_512(<32 x i16> %x0, <32 x i16 ret <32 x i16> %res2 } +declare <32 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.512(<32 x i16>, <32 x i16>, <32 x i16>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_hi_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %zmm{{.*}}{%k1} +define <32 x i16>@test_int_x86_avx512_mask_vpermt2var_hi_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) { + %res = call <32 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) + %res1 = call <32 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1) + %res2 = add <32 x i16> %res, %res1 + ret <32 x i16> %res2 +} + +declare <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16>, <32 x i16>, <32 x i16>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_hi_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %zmm{{.*}}{%k1} {z} +define <32 x i16>@test_int_x86_avx512_maskz_vpermt2var_hi_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) { + %res = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) + %res1 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1) + %res2 = add <32 x i16> %res, %res1 + ret <32 x i16> %res2 +} + +declare <32 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.512(<32 x i16>, <32 x i16>, <32 x i16>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_hi_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2w %zmm{{.*}}{%k1} +define <32 x i16>@test_int_x86_avx512_mask_vpermi2var_hi_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) { + %res = call <32 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) + %res1 = call <32 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1) + %res2 = add <32 x i16> %res, %res1 + ret <32 x i16> %res2 +} + declare <64 x i8> @llvm.x86.avx512.mask.pavg.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64) ; CHECK-LABEL: @test_int_x86_avx512_mask_pavg_b_512 @@ -918,3 +957,43 @@ define <32 x i16>@test_int_x86_avx512_mask_pavg_w_512(<32 x i16> %x0, <32 x i16> %res2 = add <32 x i16> %res, %res1 ret <32 x i16> %res2 } + +declare <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pshuf_b_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpshufb %zmm{{.*}}{%k1} +define <64 x i8>@test_int_x86_avx512_mask_pshuf_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) { + %res = call <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1) + %res2 = add <64 x i8> %res, %res1 + ret <64 x i8> %res2 +} + +declare <32 x i16> @llvm.x86.avx512.mask.pabs.w.512(<32 x i16>, <32 x i16>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_w_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsw{{.*}}{%k1} +define <32 x i16>@test_int_x86_avx512_mask_pabs_w_512(<32 x i16> %x0, <32 x i16> %x1, i32 %x2) { + %res = call <32 x i16> @llvm.x86.avx512.mask.pabs.w.512(<32 x i16> %x0, <32 x i16> %x1, i32 %x2) + %res1 = call <32 x i16> @llvm.x86.avx512.mask.pabs.w.512(<32 x i16> %x0, <32 x i16> %x1, i32 -1) + %res2 = add <32 x i16> %res, %res1 + ret <32 x i16> %res2 +} + +declare <64 x i8> @llvm.x86.avx512.mask.pabs.b.512(<64 x i8>, <64 x i8>, i64) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_b_512 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsb{{.*}}{%k1} +define <64 x i8>@test_int_x86_avx512_mask_pabs_b_512(<64 x i8> %x0, <64 x i8> %x1, i64 %x2) { + %res = call <64 x i8> @llvm.x86.avx512.mask.pabs.b.512(<64 x i8> %x0, <64 x i8> %x1, i64 %x2) + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pabs.b.512(<64 x i8> %x0, <64 x i8> %x1, i64 -1) + %res2 = add <64 x i8> %res, %res1 + ret <64 x i8> %res2 +} + diff --git a/test/CodeGen/X86/avx512bwvl-intrinsics.ll b/test/CodeGen/X86/avx512bwvl-intrinsics.ll index cf8c32a48b6b0..0119d3945f4e8 100644 --- a/test/CodeGen/X86/avx512bwvl-intrinsics.ll +++ b/test/CodeGen/X86/avx512bwvl-intrinsics.ll @@ -612,248 +612,925 @@ define <8 x i8> @test_mask_ucmp_w_128(<8 x i16> %a0, <8 x i16> %a1, i8 %mask) { declare i8 @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16>, <8 x i16>, i32, i8) nounwind readnone -declare <8 x float> @llvm.x86.fma.mask.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone +declare <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone define <8 x float> @test_mask_vfmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmadd256_ps ; CHECK: vfmadd213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xa8,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind + %res = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind ret <8 x float> %res } -declare <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone +declare <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone define <4 x float> @test_mask_vfmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmadd128_ps ; CHECK: vfmadd213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } -declare <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) +declare <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) define <4 x double> @test_mask_fmadd256_pd(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8 %mask) { ; CHECK-LABEL: test_mask_fmadd256_pd: ; CHECK: vfmadd213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa8,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8 %mask) + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8 %mask) ret <4 x double> %res } -declare <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) +declare <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) define <2 x double> @test_mask_fmadd128_pd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { ; CHECK-LABEL: test_mask_fmadd128_pd: ; CHECK: vfmadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) ret <2 x double> %res } -declare <8 x float> @llvm.x86.fma.mask.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone - -define <8 x float> @test_mask_vfmsub256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsub256_ps - ; CHECK: vfmsub213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xaa,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfmsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind - ret <8 x float> %res -} - -declare <4 x float> @llvm.x86.fma.mask.vfmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone - -define <4 x float> @test_mask_vfmsub128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsub128_ps - ; CHECK: vfmsub213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xaa,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmsub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind - ret <4 x float> %res -} - -declare <4 x double> @llvm.x86.fma.mask.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone - -define <4 x double> @test_mask_vfmsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsub256_pd - ; CHECK: vfmsub213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xaa,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind - ret <4 x double> %res -} - -declare <2 x double> @llvm.x86.fma.mask.vfmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone - -define <2 x double> @test_mask_vfmsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsub128_pd - ; CHECK: vfmsub213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xaa,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind - ret <2 x double> %res -} - -declare <8 x float> @llvm.x86.fma.mask.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone +define <2 x double>@test_int_x86_avx512_mask_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_mask3_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231pd %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_maskz_vfmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm3 {%k1} {z} +; CHECK-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +define <4 x double>@test_int_x86_avx512_mask_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask3_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231pd %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_maskz_vfmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm3 {%k1} {z} +; CHECK-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +define <4 x float>@test_int_x86_avx512_mask_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_mask3_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231ps %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_maskz_vfmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm3 {%k1} {z} +; CHECK-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +define <8 x float>@test_int_x86_avx512_mask_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask3_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmadd_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmadd231ps %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_maskz_vfmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmadd_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm3 {%k1} {z} +; CHECK-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + + +declare <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_mask3_vfmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231pd %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + + +declare <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask3_vfmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231pd %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_mask3_vfmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231ps %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask3_vfmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsub231ps %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone define <8 x float> @test_mask_vfnmadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmadd256_ps ; CHECK: vfnmadd213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xac,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfnmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind + %res = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind ret <8 x float> %res } -declare <4 x float> @llvm.x86.fma.mask.vfnmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone +declare <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone define <4 x float> @test_mask_vfnmadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmadd128_ps ; CHECK: vfnmadd213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xac,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfnmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } -declare <4 x double> @llvm.x86.fma.mask.vfnmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone +declare <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone define <4 x double> @test_mask_vfnmadd256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmadd256_pd ; CHECK: vfnmadd213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xac,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfnmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind ret <4 x double> %res } -declare <2 x double> @llvm.x86.fma.mask.vfnmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone +declare <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone define <2 x double> @test_mask_vfnmadd128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmadd128_pd ; CHECK: vfnmadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xac,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfnmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind ret <2 x double> %res } -declare <8 x float> @llvm.x86.fma.mask.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone +declare <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone define <8 x float> @test_mask_vfnmsub256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmsub256_ps ; CHECK: vfnmsub213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xae,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfnmsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind + %res = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind ret <8 x float> %res } -declare <4 x float> @llvm.x86.fma.mask.vfnmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone +declare <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone define <4 x float> @test_mask_vfnmsub128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmsub128_ps ; CHECK: vfnmsub213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xae,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfnmsub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } -declare <4 x double> @llvm.x86.fma.mask.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone +declare <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone define <4 x double> @test_mask_vfnmsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmsub256_pd ; CHECK: vfnmsub213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xae,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfnmsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind ret <4 x double> %res } -declare <2 x double> @llvm.x86.fma.mask.vfnmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone +declare <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone define <2 x double> @test_mask_vfnmsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfnmsub128_pd ; CHECK: vfnmsub213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xae,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfnmsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind ret <2 x double> %res } -declare <8 x float> @llvm.x86.fma.mask.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone + +define <2 x double>@test_int_x86_avx512_mask_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231pd %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +define <4 x double>@test_int_x86_avx512_mask_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask3_vfnmsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231pd %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfnmsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +define <4 x float>@test_int_x86_avx512_mask_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231ps %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +define <8 x float>@test_int_x86_avx512_mask_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask3_vfnmsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfnmsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfnmsub231ps %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfnmsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +define <2 x double>@test_int_x86_avx512_mask_vfnmadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.vfnmadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +define <4 x double>@test_int_x86_avx512_mask_vfnmadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.vfnmadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +define <4 x float>@test_int_x86_avx512_mask_vfnmadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.vfnmadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +define <8 x float>@test_int_x86_avx512_mask_vfnmadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfnmadd_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.vfnmadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone define <8 x float> @test_mask_fmaddsub256_ps(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask) { ; CHECK-LABEL: test_mask_fmaddsub256_ps: ; CHECK: vfmaddsub213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xa6,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfmaddsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask) + %res = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask) ret <8 x float> %res } -declare <4 x float> @llvm.x86.fma.mask.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone +declare <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone define <4 x float> @test_mask_fmaddsub128_ps(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) { ; CHECK-LABEL: test_mask_fmaddsub128_ps: ; CHECK: vfmaddsub213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa6,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmaddsub.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) + %res = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) ret <4 x float> %res } -declare <4 x double> @llvm.x86.fma.mask.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone +declare <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone define <4 x double> @test_mask_vfmaddsub256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmaddsub256_pd ; CHECK: vfmaddsub213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa6,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmaddsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind ret <4 x double> %res } -declare <2 x double> @llvm.x86.fma.mask.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone +declare <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone define <2 x double> @test_mask_vfmaddsub128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmaddsub128_pd ; CHECK: vfmaddsub213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa6,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmaddsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind ret <2 x double> %res } -declare <8 x float> @llvm.x86.fma.mask.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) nounwind readnone - -define <8 x float> @test_mask_vfmsubadd256_ps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd256_ps - ; CHECK: vfmsubadd213ps %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x29,0xa7,0xc2] - %res = call <8 x float> @llvm.x86.fma.mask.vfmsubadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, i8 %mask) nounwind - ret <8 x float> %res -} - -declare <4 x float> @llvm.x86.fma.mask.vfmsubadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone - -define <4 x float> @test_mask_vfmsubadd128_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd128_ps - ; CHECK: vfmsubadd213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa7,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmsubadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind - ret <4 x float> %res -} - -declare <4 x double> @llvm.x86.fma.mask.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nounwind readnone - -define <4 x double> @test_mask_vfmsubadd256_pd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd256_pd - ; CHECK: vfmsubadd213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa7,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmsubadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind - ret <4 x double> %res -} -declare <2 x double> @llvm.x86.fma.mask.vfmsubadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) nounwind readnone - -define <2 x double> @test_mask_vfmsubadd128_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd128_pd - ; CHECK: vfmsubadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa7,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmsubadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind - ret <2 x double> %res +define <2 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231pd %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +define <4 x double>@test_int_x86_avx512_mask_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask3_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231pd %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_maskz_vfmaddsub_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.maskz.vfmaddsub.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +define <4 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231ps %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +define <8 x float>@test_int_x86_avx512_mask_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask_vfmaddsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask3_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmaddsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmaddsub231ps %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_maskz_vfmaddsub_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_maskz_vfmaddsub_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm0, %zmm3 +; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm3 {%k1} {z} +; CHECK-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.maskz.vfmaddsub.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +define <2 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231pd %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddpd %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2=fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask3_vfmsubadd_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_pd_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231pd %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddpd %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask3.vfmsubadd.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2=fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) + +define <4 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_128: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231ps %xmm1, %xmm0, %xmm3 {%k1} +; CHECK-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0 +; CHECK-NEXT: retq + %res = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2=fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask3_vfmsubadd_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { +; CHECK-LABEL: test_int_x86_avx512_mask3_vfmsubadd_ps_256: +; CHECK: ## BB#0: +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: kmovw %eax, %k1 +; CHECK-NEXT: vmovaps %zmm2, %zmm3 +; CHECK-NEXT: vfmsubadd231ps %ymm1, %ymm0, %ymm3 {%k1} +; CHECK-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; CHECK-NEXT: retq + %res = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask3.vfmsubadd.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2=fadd <8 x float> %res, %res1 + ret <8 x float> %res2 } -define <2 x double> @test_mask_vfmsubadd128rm_pd(<2 x double> %a0, <2 x double> %a1, <2 x double>* %ptr_a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubadd128rm_pd - ; CHECK: vfmsubadd213pd (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa7,0x07] - %a2 = load <2 x double>, <2 x double>* %ptr_a2 - %res = call <2 x double> @llvm.x86.fma.mask.vfmsubadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind - ret <2 x double> %res -} -declare <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32) nounwind readnone -define <8 x double> @test_mask_vfmsubaddrm_pd(<8 x double> %a0, <8 x double> %a1, <8 x double>* %ptr_a2, i8 %mask) { - ; CHECK-LABEL: test_mask_vfmsubaddrm_pd - ; CHECK: vfmsubadd213pd (%rdi), %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa7,0x07] - %a2 = load <8 x double>, <8 x double>* %ptr_a2, align 8 - %res = call <8 x double> @llvm.x86.fma.mask.vfmsubadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 %mask, i32 4) nounwind - ret <8 x double> %res -} define <4 x float> @test_mask_vfmadd128_ps_r(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmadd128_ps_r ; CHECK: vfmadd213ps %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } define <4 x float> @test_mask_vfmadd128_ps_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { ; CHECK-LABEL: test_mask_vfmadd128_ps_rz ; CHECK: vfmadd213ps %xmm2, %xmm1, %xmm0 ## encoding: [0x62,0xf2,0x75,0x08,0xa8,0xc2] - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind ret <4 x float> %res } @@ -861,7 +1538,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmk(<4 x float> %a0, <4 x float> %a1, ; CHECK-LABEL: test_mask_vfmadd128_ps_rmk ; CHECK: vfmadd213ps (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0x07] %a2 = load <4 x float>, <4 x float>* %ptr_a2 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } @@ -869,7 +1546,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmka(<4 x float> %a0, <4 x float> %a1 ; CHECK-LABEL: test_mask_vfmadd128_ps_rmka ; CHECK: vfmadd213ps (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0x75,0x09,0xa8,0x07] %a2 = load <4 x float>, <4 x float>* %ptr_a2, align 8 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) nounwind ret <4 x float> %res } @@ -877,7 +1554,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmkz(<4 x float> %a0, <4 x float> %a1 ; CHECK-LABEL: test_mask_vfmadd128_ps_rmkz ; CHECK: vfmadd213ps (%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0x07] %a2 = load <4 x float>, <4 x float>* %ptr_a2 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind ret <4 x float> %res } @@ -885,7 +1562,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmkza(<4 x float> %a0, <4 x float> %a ; CHECK-LABEL: test_mask_vfmadd128_ps_rmkza ; CHECK: vfmadd213ps (%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0xa8,0x07] %a2 = load <4 x float>, <4 x float>* %ptr_a2, align 4 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 -1) nounwind ret <4 x float> %res } @@ -897,7 +1574,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmb(<4 x float> %a0, <4 x float> %a1, %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 %mask) nounwind ret <4 x float> %res } @@ -909,7 +1586,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmba(<4 x float> %a0, <4 x float> %a1 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 %mask) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 %mask) nounwind ret <4 x float> %res } @@ -921,7 +1598,7 @@ define <4 x float> @test_mask_vfmadd128_ps_rmbz(<4 x float> %a0, <4 x float> %a1 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 -1) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 -1) nounwind ret <4 x float> %res } @@ -933,21 +1610,21 @@ define <4 x float> @test_mask_vfmadd128_ps_rmbza(<4 x float> %a0, <4 x float> %a %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3 - %res = call <4 x float> @llvm.x86.fma.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 -1) nounwind + %res = call <4 x float> @llvm.x86.avx512.mask.vfmadd.ps.128(<4 x float> %a0, <4 x float> %a1, <4 x float> %vecinit6.i, i8 -1) nounwind ret <4 x float> %res } define <2 x double> @test_mask_vfmadd128_pd_r(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmadd128_pd_r ; CHECK: vfmadd213pd %xmm2, %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind ret <2 x double> %res } define <2 x double> @test_mask_vfmadd128_pd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { ; CHECK-LABEL: test_mask_vfmadd128_pd_rz ; CHECK: vfmadd213pd %xmm2, %xmm1, %xmm0 ## encoding: [0x62,0xf2,0xf5,0x08,0xa8,0xc2] - %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 -1) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 -1) nounwind ret <2 x double> %res } @@ -955,7 +1632,7 @@ define <2 x double> @test_mask_vfmadd128_pd_rmk(<2 x double> %a0, <2 x double> % ; CHECK-LABEL: test_mask_vfmadd128_pd_rmk ; CHECK: vfmadd213pd (%rdi), %xmm1, %xmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x09,0xa8,0x07] %a2 = load <2 x double>, <2 x double>* %ptr_a2 - %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) nounwind ret <2 x double> %res } @@ -963,21 +1640,21 @@ define <2 x double> @test_mask_vfmadd128_pd_rmkz(<2 x double> %a0, <2 x double> ; CHECK-LABEL: test_mask_vfmadd128_pd_rmkz ; CHECK: vfmadd213pd (%rdi), %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0xf1,0xa8,0x07] %a2 = load <2 x double>, <2 x double>* %ptr_a2 - %res = call <2 x double> @llvm.x86.fma.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 -1) nounwind + %res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.pd.128(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 -1) nounwind ret <2 x double> %res } define <4 x double> @test_mask_vfmadd256_pd_r(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) { ; CHECK-LABEL: test_mask_vfmadd256_pd_r ; CHECK: vfmadd213pd %ymm2, %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa8,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind ret <4 x double> %res } define <4 x double> @test_mask_vfmadd256_pd_rz(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) { ; CHECK-LABEL: test_mask_vfmadd256_pd_rz ; CHECK: vfmadd213pd %ymm2, %ymm1, %ymm0 ## encoding: [0x62,0xf2,0xf5,0x28,0xa8,0xc2] - %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 -1) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 -1) nounwind ret <4 x double> %res } @@ -985,7 +1662,7 @@ define <4 x double> @test_mask_vfmadd256_pd_rmk(<4 x double> %a0, <4 x double> % ; CHECK-LABEL: test_mask_vfmadd256_pd_rmk ; CHECK: vfmadd213pd (%rdi), %ymm1, %ymm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x29,0xa8,0x07] %a2 = load <4 x double>, <4 x double>* %ptr_a2 - %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 %mask) nounwind ret <4 x double> %res } @@ -993,7 +1670,7 @@ define <4 x double> @test_mask_vfmadd256_pd_rmkz(<4 x double> %a0, <4 x double> ; CHECK-LABEL: test_mask_vfmadd256_pd_rmkz ; CHECK: vfmadd213pd (%rdi), %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0xf5,0xa8,0x07] %a2 = load <4 x double>, <4 x double>* %ptr_a2 - %res = call <4 x double> @llvm.x86.fma.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 -1) nounwind + %res = call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, i8 -1) nounwind ret <4 x double> %res } define <8 x i16> @test_mask_add_epi16_rr_128(<8 x i16> %a, <8 x i16> %b) { @@ -2877,6 +3554,85 @@ define <16 x i16>@test_int_x86_avx512_mask_pminu_w_256(<16 x i16> %x0, <16 x i16 ret <16 x i16> %res2 } +declare <8 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_hi_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %xmm{{.*}}{%k1} +; CHECK-NOT: {z} +define <8 x i16>@test_int_x86_avx512_mask_vpermt2var_hi_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { + %res = call <8 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) + %res1 = call <8 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) + %res2 = add <8 x i16> %res, %res1 + ret <8 x i16> %res2 +} + +declare <8 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_hi_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %xmm{{.*}}{%k1} {z} +define <8 x i16>@test_int_x86_avx512_maskz_vpermt2var_hi_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { + %res = call <8 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) + %res1 = call <8 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) + %res2 = add <8 x i16> %res, %res1 + ret <8 x i16> %res2 +} + +declare <16 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_hi_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %ymm{{.*}}{%k1} +define <16 x i16>@test_int_x86_avx512_mask_vpermt2var_hi_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) { + %res = call <16 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) + %res1 = call <16 x i16> @llvm.x86.avx512.mask.vpermt2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 -1) + %res2 = add <16 x i16> %res, %res1 + ret <16 x i16> %res2 +} + +declare <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_hi_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2w %ymm{{.*}}{%k1} {z} +define <16 x i16>@test_int_x86_avx512_maskz_vpermt2var_hi_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) { + %res = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) + %res1 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 -1) + %res2 = add <16 x i16> %res, %res1 + ret <16 x i16> %res2 +} + +declare <8 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.128(<8 x i16>, <8 x i16>, <8 x i16>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_hi_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2w %xmm{{.*}}{%k1} +define <8 x i16>@test_int_x86_avx512_mask_vpermi2var_hi_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) { + %res = call <8 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) + %res1 = call <8 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1) + %res2 = add <8 x i16> %res, %res1 + ret <8 x i16> %res2 +} + +declare <16 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_hi_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2w %ymm{{.*}}{%k1} +define <16 x i16>@test_int_x86_avx512_mask_vpermi2var_hi_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) { + %res = call <16 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %x3) + %res1 = call <16 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 -1) + %res2 = add <16 x i16> %res, %res1 + ret <16 x i16> %res2 +} + declare <16 x i8> @llvm.x86.avx512.mask.pavg.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16) ; CHECK-LABEL: @test_int_x86_avx512_mask_pavg_b_128 @@ -2928,3 +3684,82 @@ define <16 x i16>@test_int_x86_avx512_mask_pavg_w_256(<16 x i16> %x0, <16 x i16> %res2 = add <16 x i16> %res, %res1 ret <16 x i16> %res2 } + +declare <16 x i8> @llvm.x86.avx512.mask.pshuf.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pshuf_b_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpshufb %xmm{{.*}}{%k1} +define <16 x i8>@test_int_x86_avx512_mask_pshuf_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) { + %res = call <16 x i8> @llvm.x86.avx512.mask.pshuf.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pshuf.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1) + %res2 = add <16 x i8> %res, %res1 + ret <16 x i8> %res2 +} + +declare <32 x i8> @llvm.x86.avx512.mask.pshuf.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pshuf_b_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpshufb %ymm{{.*}}{%k1} +define <32 x i8>@test_int_x86_avx512_mask_pshuf_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) { + %res = call <32 x i8> @llvm.x86.avx512.mask.pshuf.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pshuf.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1) + %res2 = add <32 x i8> %res, %res1 + ret <32 x i8> %res2 +} + +declare <16 x i8> @llvm.x86.avx512.mask.pabs.b.128(<16 x i8>, <16 x i8>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_b_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsb{{.*}}{%k1} +define <16 x i8>@test_int_x86_avx512_mask_pabs_b_128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2) { + %res = call <16 x i8> @llvm.x86.avx512.mask.pabs.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2) + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pabs.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 -1) + %res2 = add <16 x i8> %res, %res1 + ret <16 x i8> %res2 +} + +declare <32 x i8> @llvm.x86.avx512.mask.pabs.b.256(<32 x i8>, <32 x i8>, i32) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_b_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsb{{.*}}{%k1} +define <32 x i8>@test_int_x86_avx512_mask_pabs_b_256(<32 x i8> %x0, <32 x i8> %x1, i32 %x2) { + %res = call <32 x i8> @llvm.x86.avx512.mask.pabs.b.256(<32 x i8> %x0, <32 x i8> %x1, i32 %x2) + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pabs.b.256(<32 x i8> %x0, <32 x i8> %x1, i32 -1) + %res2 = add <32 x i8> %res, %res1 + ret <32 x i8> %res2 +} + +declare <8 x i16> @llvm.x86.avx512.mask.pabs.w.128(<8 x i16>, <8 x i16>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_w_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsw{{.*}}{%k1} +define <8 x i16>@test_int_x86_avx512_mask_pabs_w_128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2) { + %res = call <8 x i16> @llvm.x86.avx512.mask.pabs.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2) + %res1 = call <8 x i16> @llvm.x86.avx512.mask.pabs.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 -1) + %res2 = add <8 x i16> %res, %res1 + ret <8 x i16> %res2 +} + +declare <16 x i16> @llvm.x86.avx512.mask.pabs.w.256(<16 x i16>, <16 x i16>, i16) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_w_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsw{{.*}}{%k1} +define <16 x i16>@test_int_x86_avx512_mask_pabs_w_256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2) { + %res = call <16 x i16> @llvm.x86.avx512.mask.pabs.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2) + %res1 = call <16 x i16> @llvm.x86.avx512.mask.pabs.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 -1) + %res2 = add <16 x i16> %res, %res1 + ret <16 x i16> %res2 +} + diff --git a/test/CodeGen/X86/avx512vl-intrinsics.ll b/test/CodeGen/X86/avx512vl-intrinsics.ll index dfd4986b85c1e..fb7c93dc53b3a 100644 --- a/test/CodeGen/X86/avx512vl-intrinsics.ll +++ b/test/CodeGen/X86/avx512vl-intrinsics.ll @@ -2794,4 +2794,213 @@ define <4 x i64>@test_int_x86_avx512_mask_pminu_q_256(<4 x i64> %x0, <4 x i64> % %res1 = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask) %res2 = add <4 x i64> %res, %res1 ret <4 x i64> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.mask.vpermt2var.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_d_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d %xmm{{.*}}{%k1} +; CHECK-NOT: {z} +define <4 x i32>@test_int_x86_avx512_mask_vpermt2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { + %res = call <4 x i32> @llvm.x86.avx512.mask.vpermt2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) + %res1 = call <4 x i32> @llvm.x86.avx512.mask.vpermt2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_d_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d %xmm{{.*}}{%k1} {z} +define <4 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) { + %res = call <4 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %x3) + %res1 = call <4 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 -1) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.mask.vpermt2var.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermt2var_d_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d %ymm{{.*}}{%k1} +; CHECK-NOT: {z} +define <8 x i32>@test_int_x86_avx512_mask_vpermt2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { + %res = call <8 x i32> @llvm.x86.avx512.mask.vpermt2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) + %res1 = call <8 x i32> @llvm.x86.avx512.mask.vpermt2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_maskz_vpermt2var_d_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermt2d {{.*}}{%k1} {z} +define <8 x i32>@test_int_x86_avx512_maskz_vpermt2var_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) { + %res = call <8 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) + %res1 = call <8 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + +declare <2 x double> @llvm.x86.avx512.mask.vpermi2var.pd.128(<2 x double>, <2 x i64>, <2 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_pd_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2pd %xmm{{.*}}{%k1} +define <2 x double>@test_int_x86_avx512_mask_vpermi2var_pd_128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) { + %res = call <2 x double> @llvm.x86.avx512.mask.vpermi2var.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.vpermi2var.pd.128(<2 x double> %x0, <2 x i64> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask.vpermi2var.pd.256(<4 x double>, <4 x i64>, <4 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_pd_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2pd %ymm{{.*}}{%k1} +define <4 x double>@test_int_x86_avx512_mask_vpermi2var_pd_256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) { + %res = call <4 x double> @llvm.x86.avx512.mask.vpermi2var.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.vpermi2var.pd.256(<4 x double> %x0, <4 x i64> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask.vpermi2var.ps.128(<4 x float>, <4 x i32>, <4 x float>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_ps_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2ps %xmm{{.*}}{%k1} +define <4 x float>@test_int_x86_avx512_mask_vpermi2var_ps_128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) { + %res = call <4 x float> @llvm.x86.avx512.mask.vpermi2var.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.vpermi2var.ps.128(<4 x float> %x0, <4 x i32> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask.vpermi2var.ps.256(<8 x float>, <8 x i32>, <8 x float>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_vpermi2var_ps_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpermi2ps %ymm{{.*}}{%k1} +define <8 x float>@test_int_x86_avx512_mask_vpermi2var_ps_256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) { + %res = call <8 x float> @llvm.x86.avx512.mask.vpermi2var.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.vpermi2var.ps.256(<8 x float> %x0, <8 x i32> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 +} + +declare <2 x i64> @llvm.x86.avx512.mask.pabs.q.128(<2 x i64>, <2 x i64>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_q_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsq{{.*}}{%k1} +define <2 x i64>@test_int_x86_avx512_mask_pabs_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) { + %res = call <2 x i64> @llvm.x86.avx512.mask.pabs.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) + %res1 = call <2 x i64> @llvm.x86.avx512.mask.pabs.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1) + %res2 = add <2 x i64> %res, %res1 + ret <2 x i64> %res2 +} + +declare <4 x i64> @llvm.x86.avx512.mask.pabs.q.256(<4 x i64>, <4 x i64>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_q_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsq{{.*}}{%k1} +define <4 x i64>@test_int_x86_avx512_mask_pabs_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) { + %res = call <4 x i64> @llvm.x86.avx512.mask.pabs.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) + %res1 = call <4 x i64> @llvm.x86.avx512.mask.pabs.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 -1) + %res2 = add <4 x i64> %res, %res1 + ret <4 x i64> %res2 +} + +declare <4 x i32> @llvm.x86.avx512.mask.pabs.d.128(<4 x i32>, <4 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_d_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsd{{.*}}{%k1} +define <4 x i32>@test_int_x86_avx512_mask_pabs_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) { + %res = call <4 x i32> @llvm.x86.avx512.mask.pabs.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) + %res1 = call <4 x i32> @llvm.x86.avx512.mask.pabs.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1) + %res2 = add <4 x i32> %res, %res1 + ret <4 x i32> %res2 +} + +declare <8 x i32> @llvm.x86.avx512.mask.pabs.d.256(<8 x i32>, <8 x i32>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_d_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vpabsd{{.*}}{%k1} +define <8 x i32>@test_int_x86_avx512_mask_pabs_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) { + %res = call <8 x i32> @llvm.x86.avx512.mask.pabs.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) + %res1 = call <8 x i32> @llvm.x86.avx512.mask.pabs.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1) + %res2 = add <8 x i32> %res, %res1 + ret <8 x i32> %res2 +} + + +declare <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double>, <2 x double>, <2 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_pd_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefpd{{.*}}{%k1} +define <2 x double>@test_int_x86_avx512_mask_scalef_pd_128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) { + %res = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 %x3) + %res1 = call <2 x double> @llvm.x86.avx512.mask.scalef.pd.128(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, i8 -1) + %res2 = fadd <2 x double> %res, %res1 + ret <2 x double> %res2 +} + +declare <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double>, <4 x double>, <4 x double>, i8) + +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_pd_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefpd{{.*}}{%k1} +define <4 x double>@test_int_x86_avx512_mask_scalef_pd_256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) { + %res = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 %x3) + %res1 = call <4 x double> @llvm.x86.avx512.mask.scalef.pd.256(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, i8 -1) + %res2 = fadd <4 x double> %res, %res1 + ret <4 x double> %res2 +} + +declare <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_ps_128 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefps{{.*}}{%k1} +define <4 x float>@test_int_x86_avx512_mask_scalef_ps_128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) { + %res = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) + %res1 = call <4 x float> @llvm.x86.avx512.mask.scalef.ps.128(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1) + %res2 = fadd <4 x float> %res, %res1 + ret <4 x float> %res2 +} + +declare <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float>, <8 x float>, <8 x float>, i8) +; CHECK-LABEL: @test_int_x86_avx512_mask_scalef_ps_256 +; CHECK-NOT: call +; CHECK: kmov +; CHECK: vscalefps{{.*}}{%k1} +define <8 x float>@test_int_x86_avx512_mask_scalef_ps_256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) { + %res = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 %x3) + %res1 = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1) + %res2 = fadd <8 x float> %res, %res1 + ret <8 x float> %res2 }
\ No newline at end of file diff --git a/test/CodeGen/X86/coff-weak.ll b/test/CodeGen/X86/coff-weak.ll new file mode 100644 index 0000000000000..369750147f292 --- /dev/null +++ b/test/CodeGen/X86/coff-weak.ll @@ -0,0 +1,9 @@ +; RUN: llc -function-sections -o - %s | FileCheck %s + +target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-pc-windows-msvc" + +; CHECK: .section{{.*}}one_only +define linkonce_odr void @foo() { + ret void +} diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll index 656c385e2bc7d..5b01e2f4e90d5 100644 --- a/test/CodeGen/X86/commute-two-addr.ll +++ b/test/CodeGen/X86/commute-two-addr.ll @@ -39,7 +39,7 @@ define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 entry: ; DARWIN-LABEL: t3: ; DARWIN: shlq $32, %rcx -; DARWIN-NEXT: orq %rcx, %rax +; DARWIN-NEXT: leaq (%rax,%rcx), %rax ; DARWIN-NEXT: shll $8 ; DARWIN-NOT: leaq %tmp21 = zext i32 %lb to i64 diff --git a/test/CodeGen/X86/dllexport-x86_64.ll b/test/CodeGen/X86/dllexport-x86_64.ll index 629a5572977f8..bb5e92f98c7d7 100644 --- a/test/CodeGen/X86/dllexport-x86_64.ll +++ b/test/CodeGen/X86/dllexport-x86_64.ll @@ -71,33 +71,33 @@ define weak_odr dllexport void @weak1() { @blob_alias = dllexport alias bitcast ([6 x i8]* @blob to i32 ()*) ; CHECK: .section .drectve -; WIN32: " /EXPORT:Var1,DATA" -; WIN32: " /EXPORT:Var2,DATA" -; WIN32: " /EXPORT:Var3,DATA" -; WIN32: " /EXPORT:WeakVar1,DATA" -; WIN32: " /EXPORT:WeakVar2,DATA" -; WIN32: " /EXPORT:f1" -; WIN32: " /EXPORT:f2" -; WIN32: " /EXPORT:lnk1" -; WIN32: " /EXPORT:lnk2" -; WIN32: " /EXPORT:weak1" -; WIN32: " /EXPORT:alias" -; WIN32: " /EXPORT:alias2" -; WIN32: " /EXPORT:alias3" -; WIN32: " /EXPORT:weak_alias" -; WIN32: " /EXPORT:blob_alias" -; MINGW: " -export:Var1,data" -; MINGW: " -export:Var2,data" -; MINGW: " -export:Var3,data" -; MINGW: " -export:WeakVar1,data" -; MINGW: " -export:WeakVar2,data" -; MINGW: " -export:f1" -; MINGW: " -export:f2" -; MINGW: " -export:lnk1" -; MINGW: " -export:lnk2" -; MINGW: " -export:weak1" -; MINGW: " -export:alias" -; MINGW: " -export:alias2" -; MINGW: " -export:alias3" -; MINGW: " -export:weak_alias" -; MINGW: " -export:blob_alias" +; WIN32: /EXPORT:f1 +; WIN32-SAME: /EXPORT:f2 +; WIN32-SAME: /EXPORT:lnk1 +; WIN32-SAME: /EXPORT:lnk2 +; WIN32-SAME: /EXPORT:weak1 +; WIN32-SAME: /EXPORT:Var1,DATA +; WIN32-SAME: /EXPORT:Var2,DATA +; WIN32-SAME: /EXPORT:Var3,DATA +; WIN32-SAME: /EXPORT:WeakVar1,DATA +; WIN32-SAME: /EXPORT:WeakVar2,DATA +; WIN32-SAME: /EXPORT:alias +; WIN32-SAME: /EXPORT:alias2 +; WIN32-SAME: /EXPORT:alias3 +; WIN32-SAME: /EXPORT:weak_alias +; WIN32-SAME: /EXPORT:blob_alias +; MINGW: -export:f1 +; MINGW-SAME: -export:f2 +; MINGW-SAME: -export:lnk1 +; MINGW-SAME: -export:lnk2 +; MINGW-SAME: -export:weak1 +; MINGW-SAME: -export:Var1,data +; MINGW-SAME: -export:Var2,data +; MINGW-SAME: -export:Var3,data +; MINGW-SAME: -export:WeakVar1,data +; MINGW-SAME: -export:WeakVar2,data +; MINGW-SAME: -export:alias +; MINGW-SAME: -export:alias2 +; MINGW-SAME: -export:alias3 +; MINGW-SAME: -export:weak_alias +; MINGW-SAME: -export:blob_alias" diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll index 02a83ae7b191d..915567de5bf77 100644 --- a/test/CodeGen/X86/dllexport.ll +++ b/test/CodeGen/X86/dllexport.ll @@ -89,40 +89,41 @@ define weak_odr dllexport void @weak1() { @weak_alias = weak_odr dllexport alias void()* @f1 ; CHECK: .section .drectve -; CHECK-CL: " /EXPORT:_Var1,DATA" -; CHECK-CL: " /EXPORT:_Var2,DATA" -; CHECK-CL: " /EXPORT:_Var3,DATA" -; CHECK-CL: " /EXPORT:_WeakVar1,DATA" -; CHECK-CL: " /EXPORT:_WeakVar2,DATA" -; CHECK-CL: " /EXPORT:_f1" -; CHECK-CL: " /EXPORT:_f2" ; CHECK-CL-NOT: not_exported -; CHECK-CL: " /EXPORT:_stdfun@0" -; CHECK-CL: " /EXPORT:@fastfun@0" -; CHECK-CL: " /EXPORT:_thisfun" -; CHECK-CL: " /EXPORT:_lnk1" -; CHECK-CL: " /EXPORT:_lnk2" -; CHECK-CL: " /EXPORT:_weak1" -; CHECK-CL: " /EXPORT:_alias" -; CHECK-CL: " /EXPORT:_alias2" -; CHECK-CL: " /EXPORT:_alias3" -; CHECK-CL: " /EXPORT:_weak_alias" -; CHECK-GCC: " -export:Var1,data" -; CHECK-GCC: " -export:Var2,data" -; CHECK-GCC: " -export:Var3,data" -; CHECK-GCC: " -export:WeakVar1,data" -; CHECK-GCC: " -export:WeakVar2,data" -; CHECK-GCC: " -export:f1" -; CHECK-GCC: " -export:f2" +; CHECK-CL: /EXPORT:_f1 +; CHECK-CL-SAME: /EXPORT:_f2 +; CHECK-CL-SAME: /EXPORT:_stdfun@0 +; CHECK-CL-SAME: /EXPORT:@fastfun@0 +; CHECK-CL-SAME: /EXPORT:_thisfun +; CHECK-CL-SAME: /EXPORT:_lnk1 +; CHECK-CL-SAME: /EXPORT:_lnk2 +; CHECK-CL-SAME: /EXPORT:_weak1 +; CHECK-CL-SAME: /EXPORT:_Var1,DATA +; CHECK-CL-SAME: /EXPORT:_Var2,DATA +; CHECK-CL-SAME: /EXPORT:_Var3,DATA +; CHECK-CL-SAME: /EXPORT:_WeakVar1,DATA +; CHECK-CL-SAME: /EXPORT:_WeakVar2,DATA +; CHECK-CL-SAME: /EXPORT:_alias +; CHECK-CL-SAME: /EXPORT:_alias2 +; CHECK-CL-SAME: /EXPORT:_alias3 +; CHECK-CL-SAME: /EXPORT:_weak_alias" ; CHECK-CL-NOT: not_exported -; CHECK-GCC: " -export:stdfun@0" -; CHECK-GCC: " -export:@fastfun@0" -; CHECK-GCC: " -export:thisfun" -; CHECK-GCC: " -export:lnk1" -; CHECK-GCC: " -export:lnk2" -; CHECK-GCC: " -export:weak1" -; CHECK-GCC: " -export:alias" -; CHECK-GCC: " -export:alias2" -; CHECK-GCC: " -export:alias3" -; CHECK-GCC: " -export:weak_alias" - +; CHECK-GCC-NOT: not_exported +; CHECK-GCC: -export:f1 +; CHECK-GCC-SAME: -export:f2 +; CHECK-GCC-SAME: -export:stdfun@0 +; CHECK-GCC-SAME: -export:@fastfun@0 +; CHECK-GCC-SAME: -export:thisfun +; CHECK-GCC-SAME: -export:lnk1 +; CHECK-GCC-SAME: -export:lnk2 +; CHECK-GCC-SAME: -export:weak1 +; CHECK-GCC-SAME: -export:Var1,data +; CHECK-GCC-SAME: -export:Var2,data +; CHECK-GCC-SAME: -export:Var3,data +; CHECK-GCC-SAME: -export:WeakVar1,data +; CHECK-GCC-SAME: -export:WeakVar2,data +; CHECK-GCC-SAME: -export:alias +; CHECK-GCC-SAME: -export:alias2 +; CHECK-GCC-SAME: -export:alias3 +; CHECK-GCC-SAME: -export:weak_alias" +; CHECK-GCC-NOT: not_exported diff --git a/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll b/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll new file mode 100644 index 0000000000000..f7d0cdf3c65a1 --- /dev/null +++ b/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll @@ -0,0 +1,204 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fma | FileCheck %s + +; CHECK-LABEL: fmaddsubpd_loop: +; CHECK: vfmaddsub231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <4 x double> @fmaddsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <4 x double> %c.addr.0 +} + +; CHECK-LABEL: fmsubaddpd_loop: +; CHECK: vfmsubadd231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <4 x double> @fmsubaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <4 x double> %c.addr.0 +} + +; CHECK-LABEL: fmaddpd_loop: +; CHECK: vfmadd231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <4 x double> @fmaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <4 x double> %c.addr.0 +} + +; CHECK-LABEL: fmsubpd_loop: +; CHECK: vfmsub231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <4 x double> @fmsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <4 x double> %c.addr.0 +} + +declare <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>) +declare <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>) +declare <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>) +declare <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>) + + +; CHECK-LABEL: fmaddsubps_loop: +; CHECK: vfmaddsub231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <8 x float> @fmaddsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <8 x float> %c.addr.0 +} + +; CHECK-LABEL: fmsubaddps_loop: +; CHECK: vfmsubadd231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <8 x float> @fmsubaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <8 x float> %c.addr.0 +} + +; CHECK-LABEL: fmaddps_loop: +; CHECK: vfmadd231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <8 x float> @fmaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <8 x float> %c.addr.0 +} + +; CHECK-LABEL: fmsubps_loop: +; CHECK: vfmsub231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} +define <8 x float> @fmsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { +entry: + br label %for.cond + +for.cond: + %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp slt i32 %i.0, %iter + br i1 %cmp, label %for.body, label %for.end + +for.body: + br label %for.inc + +for.inc: + %0 = call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: + ret <8 x float> %c.addr.0 +} + +declare <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>) +declare <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>) +declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) +declare <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>) diff --git a/test/CodeGen/X86/fma-intrinsics-x86.ll b/test/CodeGen/X86/fma-intrinsics-x86.ll new file mode 100644 index 0000000000000..881436386bac8 --- /dev/null +++ b/test/CodeGen/X86/fma-intrinsics-x86.ll @@ -0,0 +1,493 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=corei7-avx -mattr=+fma | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=corei7-avx -mattr=+fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=+avx,-fma | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA + +; VFMADD +define <4 x float> @test_x86_fma_vfmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_ss: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_ss: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_sd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_sd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>) + +define <4 x float> @test_x86_fma_vfmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfmadd_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfmadd_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmadd_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmadd_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>) + +; VFMSUB +define <4 x float> @test_x86_fma_vfmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_ss: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213ss %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_ss: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubss %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_sd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213sd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_sd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmsub.sd(<2 x double>, <2 x double>, <2 x double>) + +define <4 x float> @test_x86_fma_vfmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmsub.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmsub.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfmsub_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfmsub_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsub_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsub_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>) + +; VFNMADD +define <4 x float> @test_x86_fma_vfnmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_ss: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213ss %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_ss: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfnmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_sd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213sd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_sd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfnmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfnmadd.sd(<2 x double>, <2 x double>, <2 x double>) + +define <4 x float> @test_x86_fma_vfnmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfnmadd.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfnmadd.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfnmadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfnmadd.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfnmadd.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfnmadd_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfnmadd_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmadd_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmadd_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfnmadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfnmadd.pd.256(<4 x double>, <4 x double>, <4 x double>) + +; VFNMSUB +define <4 x float> @test_x86_fma_vfnmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_ss: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213ss %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_ss: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfnmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_sd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213sd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_sd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfnmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfnmsub.sd(<2 x double>, <2 x double>, <2 x double>) + +define <4 x float> @test_x86_fma_vfnmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfnmsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfnmsub.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfnmsub.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfnmsub_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfnmsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfnmsub.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfnmsub_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfnmsub_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfnmsub_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfnmsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfnmsub.pd.256(<4 x double>, <4 x double>, <4 x double>) + +; VFMADDSUB +define <4 x float> @test_x86_fma_vfmaddsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmaddsub_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmaddsub_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmaddsub.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmaddsub.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmaddsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmaddsub_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmaddsub_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmaddsub.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmaddsub.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfmaddsub_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmaddsub_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmaddsub_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfmaddsub_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmaddsub_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmaddsub_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>) + +; VFMSUBADD +define <4 x float> @test_x86_fma_vfmsubadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsubadd_ps: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsubadd_ps: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x float> @llvm.x86.fma.vfmsubadd.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.fma.vfmsubadd.ps(<4 x float>, <4 x float>, <4 x float>) + +define <2 x double> @test_x86_fma_vfmsubadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsubadd_pd: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsubadd_pd: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0 +; CHECK-FMA4-NEXT: retq + %res = call <2 x double> @llvm.x86.fma.vfmsubadd.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.fma.vfmsubadd.pd(<2 x double>, <2 x double>, <2 x double>) + +define <8 x float> @test_x86_fma_vfmsubadd_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsubadd_ps_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsubadd_ps_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>) + +define <4 x double> @test_x86_fma_vfmsubadd_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { +; CHECK-FMA-LABEL: test_x86_fma_vfmsubadd_pd_256: +; CHECK-FMA: # BB#0: +; CHECK-FMA-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 +; CHECK-FMA-NEXT: retq +; +; CHECK-FMA4-LABEL: test_x86_fma_vfmsubadd_pd_256: +; CHECK-FMA4: # BB#0: +; CHECK-FMA4-NEXT: vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0 +; CHECK-FMA4-NEXT: retq + %res = call <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>) + +attributes #0 = { nounwind } diff --git a/test/CodeGen/X86/fma-intrinsics-x86_64.ll b/test/CodeGen/X86/fma-intrinsics-x86_64.ll deleted file mode 100644 index aadd7311bb89e..0000000000000 --- a/test/CodeGen/X86/fma-intrinsics-x86_64.ll +++ /dev/null @@ -1,278 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=corei7-avx -mattr=+fma | FileCheck %s --check-prefix=CHECK-FMA --check-prefix=CHECK -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=core-avx2 -mattr=+fma,+avx2 | FileCheck %s --check-prefix=CHECK-FMA --check-prefix=CHECK -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=corei7-avx -mattr=+fma4 | FileCheck %s --check-prefix=CHECK-FMA4 --check-prefix=CHECK -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=+avx,-fma | FileCheck %s --check-prefix=CHECK-FMA4 --check-prefix=CHECK - -; VFMADD -define < 4 x float > @test_x86_fma_vfmadd_ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmaddss - ; CHECK-FMA: vfmadd213ss - %res = call < 4 x float > @llvm.x86.fma.vfmadd.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmadd.ss(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmadd_sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmaddsd - ; CHECK-FMA: vfmadd213sd - %res = call < 2 x double > @llvm.x86.fma.vfmadd.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmadd.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 4 x float > @test_x86_fma_vfmadd_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmaddps - ; CHECK-FMA: vfmadd213ps - %res = call < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmadd_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmaddpd - ; CHECK-FMA: vfmadd213pd - %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfmadd_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfmaddps - ; CHECK-FMA: vfmadd213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfmadd.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfmadd.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfmadd_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfmaddpd - ; CHECK-FMA: vfmadd213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfmadd.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfmadd.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone - -; VFMSUB -define < 4 x float > @test_x86_fma_vfmsub_ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmsubss - ; CHECK-FMA: vfmsub213ss - %res = call < 4 x float > @llvm.x86.fma.vfmsub.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmsub.ss(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmsub_sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmsubsd - ; CHECK-FMA: vfmsub213sd - %res = call < 2 x double > @llvm.x86.fma.vfmsub.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmsub.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 4 x float > @test_x86_fma_vfmsub_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmsubps - ; CHECK-FMA: vfmsub213ps - %res = call < 4 x float > @llvm.x86.fma.vfmsub.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmsub.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmsub_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmsubpd - ; CHECK-FMA: vfmsub213pd - %res = call < 2 x double > @llvm.x86.fma.vfmsub.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmsub.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfmsub_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfmsubps - ; CHECK-FMA: vfmsub213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfmsub.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfmsub.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfmsub_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfmsubpd - ; CHECK-FMA: vfmsub213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfmsub.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfmsub.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone - -; VFNMADD -define < 4 x float > @test_x86_fma_vfnmadd_ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfnmaddss - ; CHECK-FMA: vfnmadd213ss - %res = call < 4 x float > @llvm.x86.fma.vfnmadd.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfnmadd.ss(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfnmadd_sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfnmaddsd - ; CHECK-FMA: vfnmadd213sd - %res = call < 2 x double > @llvm.x86.fma.vfnmadd.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfnmadd.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 4 x float > @test_x86_fma_vfnmadd_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfnmaddps - ; CHECK-FMA: vfnmadd213ps - %res = call < 4 x float > @llvm.x86.fma.vfnmadd.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfnmadd.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfnmadd_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfnmaddpd - ; CHECK-FMA: vfnmadd213pd - %res = call < 2 x double > @llvm.x86.fma.vfnmadd.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfnmadd.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfnmadd_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfnmaddps - ; CHECK-FMA: vfnmadd213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfnmadd.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfnmadd.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfnmadd_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfnmaddpd - ; CHECK-FMA: vfnmadd213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfnmadd.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfnmadd.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone - -; VFNMSUB -define < 4 x float > @test_x86_fma_vfnmsub_ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfnmsubss - ; CHECK-FMA: vfnmsub213ss - %res = call < 4 x float > @llvm.x86.fma.vfnmsub.ss(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfnmsub.ss(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfnmsub_sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfnmsubsd - ; CHECK-FMA: vfnmsub213sd - %res = call < 2 x double > @llvm.x86.fma.vfnmsub.sd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfnmsub.sd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 4 x float > @test_x86_fma_vfnmsub_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfnmsubps - ; CHECK-FMA: vfnmsub213ps - %res = call < 4 x float > @llvm.x86.fma.vfnmsub.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfnmsub.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfnmsub_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfnmsubpd - ; CHECK-FMA: vfnmsub213pd - %res = call < 2 x double > @llvm.x86.fma.vfnmsub.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfnmsub.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfnmsub_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfnmsubps - ; CHECK-FMA: vfnmsub213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfnmsub.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfnmsub.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfnmsub_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfnmsubpd - ; CHECK-FMA: vfnmsub213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfnmsub.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfnmsub.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone - -; VFMADDSUB -define < 4 x float > @test_x86_fma_vfmaddsub_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmaddsubps - ; CHECK-FMA: vfmaddsub213ps - %res = call < 4 x float > @llvm.x86.fma.vfmaddsub.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmaddsub.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmaddsub_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmaddsubpd - ; CHECK-FMA: vfmaddsub213pd - %res = call < 2 x double > @llvm.x86.fma.vfmaddsub.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmaddsub.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfmaddsub_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfmaddsubps - ; CHECK-FMA: vfmaddsub213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfmaddsub.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfmaddsub.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfmaddsub_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfmaddsubpd - ; CHECK-FMA: vfmaddsub213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfmaddsub.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfmaddsub.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone - -; VFMSUBADD -define < 4 x float > @test_x86_fma_vfmsubadd_ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) { - ; CHECK-FMA4: vfmsubaddps - ; CHECK-FMA: vfmsubadd213ps - %res = call < 4 x float > @llvm.x86.fma.vfmsubadd.ps(< 4 x float > %a0, < 4 x float > %a1, < 4 x float > %a2) - ret < 4 x float > %res -} -declare < 4 x float > @llvm.x86.fma.vfmsubadd.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone - -define < 2 x double > @test_x86_fma_vfmsubadd_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { - ; CHECK-FMA4: vfmsubaddpd - ; CHECK-FMA: vfmsubadd213pd - %res = call < 2 x double > @llvm.x86.fma.vfmsubadd.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) - ret < 2 x double > %res -} -declare < 2 x double > @llvm.x86.fma.vfmsubadd.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone - -define < 8 x float > @test_x86_fma_vfmsubadd_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { - ; CHECK-FMA4: vfmsubaddps - ; CHECK-FMA: vfmsubadd213ps - ; CHECK: ymm - %res = call < 8 x float > @llvm.x86.fma.vfmsubadd.ps.256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) - ret < 8 x float > %res -} -declare < 8 x float > @llvm.x86.fma.vfmsubadd.ps.256(< 8 x float >, < 8 x float >, < 8 x float >) nounwind readnone - -define < 4 x double > @test_x86_fma_vfmsubadd_pd_256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) { - ; CHECK-FMA4: vfmsubaddpd - ; CHECK-FMA: vfmsubadd213pd - ; CHECK: ymm - %res = call < 4 x double > @llvm.x86.fma.vfmsubadd.pd.256(< 4 x double > %a0, < 4 x double > %a1, < 4 x double > %a2) - ret < 4 x double > %res -} -declare < 4 x double > @llvm.x86.fma.vfmsubadd.pd.256(< 4 x double >, < 4 x double >, < 4 x double >) nounwind readnone diff --git a/test/CodeGen/X86/fma-phi-213-to-231.ll b/test/CodeGen/X86/fma-phi-213-to-231.ll index 9715bc7b328b7..34acdfe830f0e 100644 --- a/test/CodeGen/X86/fma-phi-213-to-231.ll +++ b/test/CodeGen/X86/fma-phi-213-to-231.ll @@ -1,246 +1,37 @@ -; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s -target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-apple-macosx10.10.0" - -; CHECK-LABEL: fmaddsubpd_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmaddsub231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <4 x double> @fmaddsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <4 x double> %c.addr.0 -} - -; CHECK-LABEL: fmsubaddpd_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmsubadd231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <4 x double> @fmsubaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <4 x double> %c.addr.0 -} - -; CHECK-LABEL: fmaddpd_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmadd231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <4 x double> @fmaddpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <4 x double> %c.addr.0 -} - -; CHECK-LABEL: fmsubpd_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmsub231pd %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <4 x double> @fmsubpd_loop(i32 %iter, <4 x double> %a, <4 x double> %b, <4 x double> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <4 x double> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <4 x double> %c.addr.0 -} - -declare <4 x double> @llvm.x86.fma.vfmaddsub.pd.256(<4 x double>, <4 x double>, <4 x double>) -declare <4 x double> @llvm.x86.fma.vfmsubadd.pd.256(<4 x double>, <4 x double>, <4 x double>) -declare <4 x double> @llvm.x86.fma.vfmadd.pd.256(<4 x double>, <4 x double>, <4 x double>) -declare <4 x double> @llvm.x86.fma.vfmsub.pd.256(<4 x double>, <4 x double>, <4 x double>) - - -; CHECK-LABEL: fmaddsubps_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmaddsub231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <8 x float> @fmaddsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <8 x float> %c.addr.0 -} - -; CHECK-LABEL: fmsubaddps_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmsubadd231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <8 x float> @fmsubaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <8 x float> %c.addr.0 -} - -; CHECK-LABEL: fmaddps_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmadd231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <8 x float> @fmaddps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <8 x float> %c.addr.0 -} - -; CHECK-LABEL: fmsubps_loop -; CHECK: [[BODYLBL:LBB.+]]: -; CHECK: vfmsub231ps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, %ymm{{[0-9]+}} -; CHECK: [[INCLBL:LBB.+]]: -; CHECK: addl $1, [[INDREG:%[a-z0-9]+]] -; CHECK: cmpl {{%.+}}, [[INDREG]] -; CHECK: jl [[BODYLBL]] -define <8 x float> @fmsubps_loop(i32 %iter, <8 x float> %a, <8 x float> %b, <8 x float> %c) { -entry: - br label %for.cond - -for.cond: - %c.addr.0 = phi <8 x float> [ %c, %entry ], [ %0, %for.inc ] - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] - %cmp = icmp slt i32 %i.0, %iter - br i1 %cmp, label %for.body, label %for.end - -for.body: - br label %for.inc - -for.inc: - %0 = call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c.addr.0) - %inc = add nsw i32 %i.0, 1 - br label %for.cond - -for.end: - ret <8 x float> %c.addr.0 -} - -declare <8 x float> @llvm.x86.fma.vfmaddsub.ps.256(<8 x float>, <8 x float>, <8 x float>) -declare <8 x float> @llvm.x86.fma.vfmsubadd.ps.256(<8 x float>, <8 x float>, <8 x float>) -declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) -declare <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>) +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s + +; Test FMA3 variant selection + +; CHECK-LABEL: fma3_select231ssX: +; CHECK: vfmadd231ss %xmm +define float @fma3_select231ssX(float %x, float %y) { +entry: + br label %while.body +while.body: + %acc.01 = phi float [ 0.000000e+00, %entry ], [ %acc, %while.body ] + %acc = call float @llvm.fma.f32(float %x, float %y, float %acc.01) + %b = fcmp ueq float %acc, 0.0 + br i1 %b, label %while.body, label %while.end +while.end: + ret float %acc +} + +; CHECK-LABEL: fma3_select231pdY: +; CHECK: vfmadd231pd %ymm +define <4 x double> @fma3_select231pdY(<4 x double> %x, <4 x double> %y) { +entry: + br label %while.body +while.body: + %acc.04 = phi <4 x double> [ zeroinitializer, %entry ], [ %add, %while.body ] + %add = call <4 x double> @llvm.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %acc.04) + %vecext = extractelement <4 x double> %add, i32 0 + %cmp = fcmp oeq double %vecext, 0.000000e+00 + br i1 %cmp, label %while.body, label %while.end +while.end: + ret <4 x double> %add +} + +declare float @llvm.fma.f32(float, float, float) +declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) diff --git a/test/CodeGen/X86/fma.ll b/test/CodeGen/X86/fma.ll index 2eb152b078eff..b91479cda8715 100644 --- a/test/CodeGen/X86/fma.ll +++ b/test/CodeGen/X86/fma.ll @@ -1,80 +1,47 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST -; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-CALL -; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST -; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-CALL -; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST -; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-CALL - -; CHECK: test_f32 +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+avx512f,-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST +; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST +; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-CALL + +; CHECK-LABEL: test_f32: ; CHECK-FMA-INST: vfmadd213ss ; CHECK-FMA-CALL: fmaf - -define float @test_f32(float %a, float %b, float %c) nounwind readnone ssp { +define float @test_f32(float %a, float %b, float %c) #0 { entry: - %call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone + %call = call float @llvm.fma.f32(float %a, float %b, float %c) ret float %call } -; CHECK: test_f64 +; CHECK-LABEL: test_f64: ; CHECK-FMA-INST: vfmadd213sd ; CHECK-FMA-CALL: fma - -define double @test_f64(double %a, double %b, double %c) nounwind readnone ssp { +define double @test_f64(double %a, double %b, double %c) #0 { entry: - %call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone + %call = call double @llvm.fma.f64(double %a, double %b, double %c) ret double %call } -; CHECK: test_f80 +; CHECK-LABEL: test_f80: ; CHECK: fmal - -define x86_fp80 @test_f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone ssp { +define x86_fp80 @test_f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) #0 { entry: - %call = tail call x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone + %call = call x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) ret x86_fp80 %call } -; CHECK: test_f32_cst -; CHECK-NOT: fma -define float @test_f32_cst() nounwind readnone ssp { +; CHECK-LABEL: test_f32_cst: +; CHECK-NOT: vfmadd +define float @test_f32_cst() #0 { entry: - %call = tail call float @llvm.fma.f32(float 3.0, float 3.0, float 3.0) nounwind readnone + %call = call float @llvm.fma.f32(float 3.0, float 3.0, float 3.0) ret float %call } -; Test FMA3 variant selection -; CHECK-FMA-INST: fma3_select231ssX: -; CHECK-FMA-INST: vfmadd231ss %xmm -define float @fma3_select231ssX(float %x, float %y) #0 { -entry: - br label %while.body -while.body: ; preds = %while.body, %while.body - %acc.01 = phi float [ 0.000000e+00, %entry ], [ %acc, %while.body ] - %acc = tail call float @llvm.fma.f32(float %x, float %y, float %acc.01) nounwind readnone - %b = fcmp ueq float %acc, 0.0 - br i1 %b, label %while.body, label %while.end -while.end: ; preds = %while.body, %entry - ret float %acc -} - -; Test FMA3 variant selection -; CHECK-FMA-INST: fma3_select231pdY: -; CHECK-FMA-INST: vfmadd231pd %ymm -define <4 x double> @fma3_select231pdY(<4 x double> %x, <4 x double> %y) #0 { -entry: - br label %while.body -while.body: ; preds = %entry, %while.body - %acc.04 = phi <4 x double> [ zeroinitializer, %entry ], [ %add, %while.body ] - %add = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %acc.04) - %vecext = extractelement <4 x double> %add, i32 0 - %cmp = fcmp oeq double %vecext, 0.000000e+00 - br i1 %cmp, label %while.body, label %while.end - -while.end: ; preds = %while.body - ret <4 x double> %add -} +declare float @llvm.fma.f32(float, float, float) +declare double @llvm.fma.f64(double, double, double) +declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) -declare float @llvm.fma.f32(float, float, float) nounwind readnone -declare double @llvm.fma.f64(double, double, double) nounwind readnone -declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone -declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone +attributes #0 = { nounwind } diff --git a/test/CodeGen/X86/fma3-intrinsics.ll b/test/CodeGen/X86/fma3-intrinsics.ll deleted file mode 100755 index fa9c252f30b46..0000000000000 --- a/test/CodeGen/X86/fma3-intrinsics.ll +++ /dev/null @@ -1,150 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=core-avx2 | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-pc-win32 -mattr=+fma,+fma4 | FileCheck %s -; RUN: llc < %s -mcpu=bdver2 -mtriple=x86_64-pc-win32 -mattr=-fma4 | FileCheck %s - -define <4 x float> @test_x86_fmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fmadd213ss (%r8), [[XMM1]], [[XMM0]] - %res = call <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <4 x float> @test_x86_fmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK: fmadd213ps - %res = call <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <8 x float> @test_x86_fmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) { - ; CHECK: fmadd213ps {{.*\(%r.*}}, %ymm - %res = call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) nounwind - ret <8 x float> %res -} -declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone - -define <4 x float> @test_x86_fnmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fnmadd213ss (%r8), [[XMM1]], [[XMM0]] - %res = call <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <4 x float> @test_x86_fnmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK: fnmadd213ps - %res = call <4 x float> @llvm.x86.fma.vfnmadd.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfnmadd.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <8 x float> @test_x86_fnmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) { - ; CHECK: fnmadd213ps {{.*\(%r.*}}, %ymm - %res = call <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) nounwind - ret <8 x float> %res -} -declare <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone - - -define <4 x float> @test_x86_fmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fmsub213ss (%r8), [[XMM1]], [[XMM0]] - %res = call <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <4 x float> @test_x86_fmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK: fmsub213ps - %res = call <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <4 x float> @test_x86_fnmsub_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fnmsub213ss (%r8), [[XMM1]], [[XMM0]] - %res = call <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -define <4 x float> @test_x86_fnmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) { - ; CHECK: fnmsub213ps - %res = call <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) nounwind - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone - -;;;; - -define <2 x double> @test_x86_fmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fmadd213sd (%r8), [[XMM1]], [[XMM0]] - %res = call <2 x double> @llvm.x86.fma.vfmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fmadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK: fmadd213pd - %res = call <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fnmadd_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fnmadd213sd (%r8), [[XMM1]], [[XMM0]] - %res = call <2 x double> @llvm.x86.fma.vfnmadd.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfnmadd.sd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fnmadd_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK: fnmadd213pd - %res = call <2 x double> @llvm.x86.fma.vfnmadd.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfnmadd.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - - - -define <2 x double> @test_x86_fmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fmsub213sd (%r8), [[XMM1]], [[XMM0]] - %res = call <2 x double> @llvm.x86.fma.vfmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfmsub.sd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fmsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK: fmsub213pd - %res = call <2 x double> @llvm.x86.fma.vfmsub.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfmsub.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fnmsub_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK-DAG: vmovaps (%rcx), [[XMM1:%xmm[0-9]+]] - ; CHECK-DAG: vmovaps (%rdx), [[XMM0:%xmm[0-9]+]] - ; CHECK: fnmsub213sd (%r8), [[XMM1]], [[XMM0]] - %res = call <2 x double> @llvm.x86.fma.vfnmsub.sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfnmsub.sd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone - -define <2 x double> @test_x86_fnmsub_pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { - ; CHECK: fnmsub213pd - %res = call <2 x double> @llvm.x86.fma.vfnmsub.pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) nounwind - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.fma.vfnmsub.pd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone diff --git a/test/CodeGen/X86/fold-load-binops.ll b/test/CodeGen/X86/fold-load-binops.ll new file mode 100644 index 0000000000000..6d501c74fe57b --- /dev/null +++ b/test/CodeGen/X86/fold-load-binops.ll @@ -0,0 +1,142 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX + +; Verify that we're folding the load into the math instruction. +; This pattern is generated out of the simplest intrinsics usage: +; _mm_add_ss(a, _mm_load_ss(b)); + +define <4 x float> @addss(<4 x float> %va, float* %pb) { +; SSE-LABEL: addss: +; SSE: # BB#0: +; SSE-NEXT: addss (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: addss: +; AVX: # BB#0: +; AVX-NEXT: vaddss (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <4 x float> %va, i32 0 + %b = load float, float* %pb + %r = fadd float %a, %b + %vr = insertelement <4 x float> %va, float %r, i32 0 + ret <4 x float> %vr +} + +define <2 x double> @addsd(<2 x double> %va, double* %pb) { +; SSE-LABEL: addsd: +; SSE: # BB#0: +; SSE-NEXT: addsd (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: addsd: +; AVX: # BB#0: +; AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <2 x double> %va, i32 0 + %b = load double, double* %pb + %r = fadd double %a, %b + %vr = insertelement <2 x double> %va, double %r, i32 0 + ret <2 x double> %vr +} + +define <4 x float> @subss(<4 x float> %va, float* %pb) { +; SSE-LABEL: subss: +; SSE: # BB#0: +; SSE-NEXT: subss (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: subss: +; AVX: # BB#0: +; AVX-NEXT: vsubss (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <4 x float> %va, i32 0 + %b = load float, float* %pb + %r = fsub float %a, %b + %vr = insertelement <4 x float> %va, float %r, i32 0 + ret <4 x float> %vr +} + +define <2 x double> @subsd(<2 x double> %va, double* %pb) { +; SSE-LABEL: subsd: +; SSE: # BB#0: +; SSE-NEXT: subsd (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: subsd: +; AVX: # BB#0: +; AVX-NEXT: vsubsd (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <2 x double> %va, i32 0 + %b = load double, double* %pb + %r = fsub double %a, %b + %vr = insertelement <2 x double> %va, double %r, i32 0 + ret <2 x double> %vr +} + +define <4 x float> @mulss(<4 x float> %va, float* %pb) { +; SSE-LABEL: mulss: +; SSE: # BB#0: +; SSE-NEXT: mulss (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: mulss: +; AVX: # BB#0: +; AVX-NEXT: vmulss (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <4 x float> %va, i32 0 + %b = load float, float* %pb + %r = fmul float %a, %b + %vr = insertelement <4 x float> %va, float %r, i32 0 + ret <4 x float> %vr +} + +define <2 x double> @mulsd(<2 x double> %va, double* %pb) { +; SSE-LABEL: mulsd: +; SSE: # BB#0: +; SSE-NEXT: mulsd (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: mulsd: +; AVX: # BB#0: +; AVX-NEXT: vmulsd (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <2 x double> %va, i32 0 + %b = load double, double* %pb + %r = fmul double %a, %b + %vr = insertelement <2 x double> %va, double %r, i32 0 + ret <2 x double> %vr +} + +define <4 x float> @divss(<4 x float> %va, float* %pb) { +; SSE-LABEL: divss: +; SSE: # BB#0: +; SSE-NEXT: divss (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: divss: +; AVX: # BB#0: +; AVX-NEXT: vdivss (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <4 x float> %va, i32 0 + %b = load float, float* %pb + %r = fdiv float %a, %b + %vr = insertelement <4 x float> %va, float %r, i32 0 + ret <4 x float> %vr +} + +define <2 x double> @divsd(<2 x double> %va, double* %pb) { +; SSE-LABEL: divsd: +; SSE: # BB#0: +; SSE-NEXT: divsd (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: divsd: +; AVX: # BB#0: +; AVX-NEXT: vdivsd (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %a = extractelement <2 x double> %va, i32 0 + %b = load double, double* %pb + %r = fdiv double %a, %b + %vr = insertelement <2 x double> %va, double %r, i32 0 + ret <2 x double> %vr +} diff --git a/test/CodeGen/X86/fold-vector-sext-crash2.ll b/test/CodeGen/X86/fold-vector-sext-crash2.ll new file mode 100644 index 0000000000000..44c836195abc2 --- /dev/null +++ b/test/CodeGen/X86/fold-vector-sext-crash2.ll @@ -0,0 +1,92 @@ +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64 + +; DAGCombiner crashes during sext folding + +define <2 x i256> @test_sext1() { + %Se = sext <2 x i8> <i8 -100, i8 -99> to <2 x i256> + %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3> + ret <2 x i256> %Shuff + + ; X64-LABEL: test_sext1 + ; X64: movq $-1 + ; X64-NEXT: movq $-1 + ; X64-NEXT: movq $-1 + ; X64-NEXT: movq $-99 + + ; X32-LABEL: test_sext1 + ; X32: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-99 +} + +define <2 x i256> @test_sext2() { + %Se = sext <2 x i128> <i128 -2000, i128 -1999> to <2 x i256> + %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3> + ret <2 x i256> %Shuff + + ; X64-LABEL: test_sext2 + ; X64: movq $-1 + ; X64-NEXT: movq $-1 + ; X64-NEXT: movq $-1 + ; X64-NEXT: movq $-1999 + + ; X32-LABEL: test_sext2 + ; X32: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1999 +} + +define <2 x i256> @test_zext1() { + %Se = zext <2 x i8> <i8 -1, i8 -2> to <2 x i256> + %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3> + ret <2 x i256> %Shuff + + ; X64-LABEL: test_zext1 + ; X64: movq $0 + ; X64-NEXT: movq $0 + ; X64-NEXT: movq $0 + ; X64-NEXT: movq $254 + + ; X32-LABEL: test_zext1 + ; X32: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $254 +} + +define <2 x i256> @test_zext2() { + %Se = zext <2 x i128> <i128 -1, i128 -2> to <2 x i256> + %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3> + ret <2 x i256> %Shuff + + ; X64-LABEL: test_zext2 + ; X64: movq $0 + ; X64-NEXT: movq $0 + ; X64-NEXT: movq $-1 + ; X64-NEXT: movq $-2 + + ; X32-LABEL: test_zext2 + ; X32: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $0 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-1 + ; X32-NEXT: movl $-2 +} diff --git a/test/CodeGen/X86/fold-vector-shl-crash.ll b/test/CodeGen/X86/fold-vector-shl-crash.ll new file mode 100644 index 0000000000000..9f81e44074f1d --- /dev/null +++ b/test/CodeGen/X86/fold-vector-shl-crash.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -march=x86 | FileCheck %s + +;CHECK-LABEL: test +define <2 x i256> @test() { + %S = shufflevector <2 x i256> zeroinitializer, <2 x i256> <i256 -1, i256 -1>, <2 x i32> <i32 0, i32 2> + %B = shl <2 x i256> %S, <i256 -1, i256 -1> ; DAG Combiner crashes here + ret <2 x i256> %B +} diff --git a/test/CodeGen/X86/fp-fast.ll b/test/CodeGen/X86/fp-fast.ll index 4f503af716a80..27af5738ca3e8 100644 --- a/test/CodeGen/X86/fp-fast.ll +++ b/test/CodeGen/X86/fp-fast.ll @@ -114,81 +114,3 @@ define float @test11(float %a) { ret float %t2 } -; Verify that the first two adds are independent regardless of how the inputs are -; commuted. The destination registers are used as source registers for the third add. - -define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { -; CHECK-LABEL: reassociate_adds1: -; CHECK: # BB#0: -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: retq - %t0 = fadd float %x0, %x1 - %t1 = fadd float %t0, %x2 - %t2 = fadd float %t1, %x3 - ret float %t2 -} - -define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { -; CHECK-LABEL: reassociate_adds2: -; CHECK: # BB#0: -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: retq - %t0 = fadd float %x0, %x1 - %t1 = fadd float %x2, %t0 - %t2 = fadd float %t1, %x3 - ret float %t2 -} - -define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { -; CHECK-LABEL: reassociate_adds3: -; CHECK: # BB#0: -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: retq - %t0 = fadd float %x0, %x1 - %t1 = fadd float %t0, %x2 - %t2 = fadd float %x3, %t1 - ret float %t2 -} - -define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { -; CHECK-LABEL: reassociate_adds4: -; CHECK: # BB#0: -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: retq - %t0 = fadd float %x0, %x1 - %t1 = fadd float %x2, %t0 - %t2 = fadd float %x3, %t1 - ret float %t2 -} - -; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not -; produced because that would cost more compile time. - -define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { -; CHECK-LABEL: reassociate_adds5: -; CHECK: # BB#0: -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm5, %xmm4, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vaddss %xmm7, %xmm6, %xmm1 -; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: retq - %t0 = fadd float %x0, %x1 - %t1 = fadd float %t0, %x2 - %t2 = fadd float %t1, %x3 - %t3 = fadd float %t2, %x4 - %t4 = fadd float %t3, %x5 - %t5 = fadd float %t4, %x6 - %t6 = fadd float %t5, %x7 - ret float %t6 -} diff --git a/test/CodeGen/X86/implicit-null-check-negative.ll b/test/CodeGen/X86/implicit-null-check-negative.ll index e0210d9315f14..8fbed9f7bee85 100644 --- a/test/CodeGen/X86/implicit-null-check-negative.ll +++ b/test/CodeGen/X86/implicit-null-check-negative.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-apple-macosx -O3 -debug-only=faultmaps -enable-implicit-null-checks < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-macosx -O3 -debug-only=faultmaps -enable-implicit-null-checks < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; List cases where we should *not* be emitting implicit null checks. @@ -10,7 +10,7 @@ define i32 @imp_null_check_load(i32* %x, i32* %y) { %c = icmp eq i32* %x, null ; It isn't legal to move the load from %x from "not_null" to here -- ; the store to %y could be aliasing it. - br i1 %c, label %is_null, label %not_null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 @@ -24,7 +24,7 @@ define i32 @imp_null_check_load(i32* %x, i32* %y) { define i32 @imp_null_check_gep_load(i32* %x) { entry: %c = icmp eq i32* %x, null - br i1 %c, label %is_null, label %not_null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 @@ -38,8 +38,7 @@ define i32 @imp_null_check_gep_load(i32* %x) { } define i32 @imp_null_check_load_no_md(i32* %x) { -; Everything is okay except that the !never.executed metadata is -; missing. +; This is fine, except it is missing the !make.implicit metadata. entry: %c = icmp eq i32* %x, null br i1 %c, label %is_null, label %not_null @@ -51,3 +50,5 @@ define i32 @imp_null_check_load_no_md(i32* %x) { %t = load i32, i32* %x ret i32 %t } + +!0 = !{} diff --git a/test/CodeGen/X86/implicit-null-check.ll b/test/CodeGen/X86/implicit-null-check.ll index f4c539800fbbf..1d1b36bbd5d06 100644 --- a/test/CodeGen/X86/implicit-null-check.ll +++ b/test/CodeGen/X86/implicit-null-check.ll @@ -1,5 +1,15 @@ ; RUN: llc -O3 -mtriple=x86_64-apple-macosx -enable-implicit-null-checks < %s | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-implicit-null-checks \ +; RUN: | llvm-mc -triple x86_64-apple-macosx -filetype=obj -o - \ +; RUN: | llvm-objdump -triple x86_64-apple-macosx -fault-map-section - \ +; RUN: | FileCheck %s -check-prefix OBJDUMP + +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -enable-implicit-null-checks \ +; RUN: | llvm-mc -triple x86_64-unknown-linux-gnu -filetype=obj -o - \ +; RUN: | llvm-objdump -triple x86_64-unknown-linux-gnu -fault-map-section - \ +; RUN: | FileCheck %s -check-prefix OBJDUMP + define i32 @imp_null_check_load(i32* %x) { ; CHECK-LABEL: _imp_null_check_load: ; CHECK: Ltmp1: @@ -11,7 +21,7 @@ define i32 @imp_null_check_load(i32* %x) { entry: %c = icmp eq i32* %x, null - br i1 %c, label %is_null, label %not_null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 @@ -32,7 +42,7 @@ define i32 @imp_null_check_gep_load(i32* %x) { entry: %c = icmp eq i32* %x, null - br i1 %c, label %is_null, label %not_null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 @@ -55,7 +65,7 @@ define i32 @imp_null_check_add_result(i32* %x, i32 %p) { entry: %c = icmp eq i32* %x, null - br i1 %c, label %is_null, label %not_null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 @@ -66,6 +76,8 @@ define i32 @imp_null_check_add_result(i32* %x, i32 %p) { ret i32 %p1 } +!0 = !{} + ; CHECK-LABEL: __LLVM_FaultMaps: ; Version: @@ -116,3 +128,13 @@ define i32 @imp_null_check_add_result(i32* %x, i32 %p) { ; CHECK-NEXT: .long Ltmp1-_imp_null_check_load ; Fault[0].HandlerOffset: ; CHECK-NEXT: .long Ltmp0-_imp_null_check_load + +; OBJDUMP: FaultMap table: +; OBJDUMP-NEXT: Version: 0x1 +; OBJDUMP-NEXT: NumFunctions: 3 +; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1 +; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 5 +; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1 +; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 7 +; OBJDUMP-NEXT: FunctionAddress: 0x000000, NumFaultingPCs: 1 +; OBJDUMP-NEXT: Fault kind: FaultingLoad, faulting PC offset: 0, handling PC offset: 3 diff --git a/test/CodeGen/X86/machine-combiner.ll b/test/CodeGen/X86/machine-combiner.ll new file mode 100644 index 0000000000000..d4cd59ffac3ac --- /dev/null +++ b/test/CodeGen/X86/machine-combiner.ll @@ -0,0 +1,99 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s + +; Verify that the first two adds are independent regardless of how the inputs are +; commuted. The destination registers are used as source registers for the third add. + +define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds1: +; CHECK: # BB#0: +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %t1, %x3 + ret float %t2 +} + +define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds2: +; CHECK: # BB#0: +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fadd float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %t1, %x3 + ret float %t2 +} + +define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds3: +; CHECK: # BB#0: +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + +define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds4: +; CHECK: # BB#0: +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fadd float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + +; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not +; produced because that would cost more compile time. + +define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { +; CHECK-LABEL: reassociate_adds5: +; CHECK: # BB#0: +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm5, %xmm4, %xmm1 +; CHECK-NEXT: vaddss %xmm6, %xmm1, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm7, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %t1, %x3 + %t3 = fadd float %t2, %x4 + %t4 = fadd float %t3, %x5 + %t5 = fadd float %t4, %x6 + %t6 = fadd float %t5, %x7 + ret float %t6 +} + +; Verify that we only need two associative operations to reassociate the operands. +; Also, we should reassociate such that the result of the high latency division +; is used by the final 'add' rather than reassociating the %x3 operand with the +; division. The latter reassociation would not improve anything. + +define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds6: +; CHECK: # BB#0: +; CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vaddss %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: retq + %t0 = fdiv float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + diff --git a/test/CodeGen/X86/movtopush.ll b/test/CodeGen/X86/movtopush.ll index f89e52457f355..b02f9ec45e7fb 100644 --- a/test/CodeGen/X86/movtopush.ll +++ b/test/CodeGen/X86/movtopush.ll @@ -2,11 +2,15 @@ ; RUN: llc < %s -mtriple=x86_64-windows | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -mtriple=i686-windows -force-align-stack -stack-alignment=32 | FileCheck %s -check-prefix=ALIGNED +%class.Class = type { i32 } +%struct.s = type { i64 } + declare void @good(i32 %a, i32 %b, i32 %c, i32 %d) declare void @inreg(i32 %a, i32 inreg %b, i32 %c, i32 %d) +declare x86_thiscallcc void @thiscall(%class.Class* %class, i32 %a, i32 %b, i32 %c, i32 %d) declare void @oneparam(i32 %a) declare void @eightparams(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) - +declare void @struct(%struct.s* byval %a, i32 %b, i32 %c, i32 %d) ; Here, we should have a reserved frame, so we don't expect pushes ; NORMAL-LABEL: test1: @@ -108,13 +112,12 @@ entry: ret void } -; We don't support weird calling conventions +; We support weird calling conventions ; NORMAL-LABEL: test4: -; NORMAL: subl $12, %esp -; NORMAL-NEXT: movl $4, 8(%esp) -; NORMAL-NEXT: movl $3, 4(%esp) -; NORMAL-NEXT: movl $1, (%esp) -; NORMAL-NEXT: movl $2, %eax +; NORMAL: movl $2, %eax +; NORMAL-NEXT: pushl $4 +; NORMAL-NEXT: pushl $3 +; NORMAL-NEXT: pushl $1 ; NORMAL-NEXT: call ; NORMAL-NEXT: addl $12, %esp define void @test4() optsize { @@ -123,6 +126,20 @@ entry: ret void } +; NORMAL-LABEL: test4b: +; NORMAL: movl 4(%esp), %ecx +; NORMAL-NEXT: pushl $4 +; NORMAL-NEXT: pushl $3 +; NORMAL-NEXT: pushl $2 +; NORMAL-NEXT: pushl $1 +; NORMAL-NEXT: call +; NORMAL-NEXT: ret +define void @test4b(%class.Class* %f) optsize { +entry: + call x86_thiscallcc void @thiscall(%class.Class* %f, i32 1, i32 2, i32 3, i32 4) + ret void +} + ; When there is no reserved call frame, check that additional alignment ; is added when the pushes don't add up to the required alignment. ; ALIGNED-LABEL: test5: @@ -229,20 +246,27 @@ entry: ; NORMAL-NEXT: pushl $1 ; NORMAL-NEXT: call ; NORMAL-NEXT: addl $16, %esp -; NORMAL-NEXT: subl $16, %esp -; NORMAL-NEXT: leal 16(%esp), [[EAX:%e..]] -; NORMAL-NEXT: movl [[EAX]], 12(%esp) -; NORMAL-NEXT: movl $7, 8(%esp) -; NORMAL-NEXT: movl $6, 4(%esp) -; NORMAL-NEXT: movl $5, (%esp) +; NORMAL-NEXT: subl $20, %esp +; NORMAL-NEXT: movl 20(%esp), [[E1:%e..]] +; NORMAL-NEXT: movl 24(%esp), [[E2:%e..]] +; NORMAL-NEXT: movl [[E2]], 4(%esp) +; NORMAL-NEXT: movl [[E1]], (%esp) +; NORMAL-NEXT: leal 32(%esp), [[E3:%e..]] +; NORMAL-NEXT: movl [[E3]], 16(%esp) +; NORMAL-NEXT: leal 28(%esp), [[E4:%e..]] +; NORMAL-NEXT: movl [[E4]], 12(%esp) +; NORMAL-NEXT: movl $6, 8(%esp) ; NORMAL-NEXT: call -; NORMAL-NEXT: addl $16, %esp +; NORMAL-NEXT: addl $20, %esp define void @test9() optsize { entry: %p = alloca i32, align 4 + %q = alloca i32, align 4 + %s = alloca %struct.s, align 4 call void @good(i32 1, i32 2, i32 3, i32 4) - %0 = ptrtoint i32* %p to i32 - call void @good(i32 5, i32 6, i32 7, i32 %0) + %pv = ptrtoint i32* %p to i32 + %qv = ptrtoint i32* %q to i32 + call void @struct(%struct.s* byval %s, i32 6, i32 %qv, i32 %pv) ret void } @@ -291,28 +315,17 @@ define void @test11() optsize { ; Converting one mov into a push isn't worth it when ; doing so forces too much overhead for other calls. ; NORMAL-LABEL: test12: -; NORMAL: subl $16, %esp -; NORMAL-NEXT: movl $4, 8(%esp) -; NORMAL-NEXT: movl $3, 4(%esp) -; NORMAL-NEXT: movl $1, (%esp) -; NORMAL-NEXT: movl $2, %eax -; NORMAL-NEXT: calll _inreg -; NORMAL-NEXT: movl $8, 12(%esp) +; NORMAL: movl $8, 12(%esp) ; NORMAL-NEXT: movl $7, 8(%esp) ; NORMAL-NEXT: movl $6, 4(%esp) ; NORMAL-NEXT: movl $5, (%esp) ; NORMAL-NEXT: calll _good -; NORMAL-NEXT: movl $12, 8(%esp) -; NORMAL-NEXT: movl $11, 4(%esp) -; NORMAL-NEXT: movl $9, (%esp) -; NORMAL-NEXT: movl $10, %eax -; NORMAL-NEXT: calll _inreg -; NORMAL-NEXT: addl $16, %esp define void @test12() optsize { entry: - call void @inreg(i32 1, i32 2, i32 3, i32 4) + %s = alloca %struct.s, align 4 + call void @struct(%struct.s* %s, i32 2, i32 3, i32 4) call void @good(i32 5, i32 6, i32 7, i32 8) - call void @inreg(i32 9, i32 10, i32 11, i32 12) + call void @struct(%struct.s* %s, i32 10, i32 11, i32 12) ret void } @@ -324,13 +337,12 @@ entry: ; NORMAL-NEXT: pushl $1 ; NORMAL-NEXT: calll _good ; NORMAL-NEXT: addl $16, %esp -; NORMAL-NEXT: subl $12, %esp -; NORMAL-NEXT: movl $8, 8(%esp) -; NORMAL-NEXT: movl $7, 4(%esp) -; NORMAL-NEXT: movl $5, (%esp) -; NORMAL-NEXT: movl $6, %eax -; NORMAL-NEXT: calll _inreg -; NORMAL-NEXT: addl $12, %esp +; NORMAL-NEXT: subl $20, %esp +; NORMAL: movl $8, 16(%esp) +; NORMAL-NEXT: movl $7, 12(%esp) +; NORMAL-NEXT: movl $6, 8(%esp) +; NORMAL-NEXT: calll _struct +; NORMAL-NEXT: addl $20, %esp ; NORMAL-NEXT: pushl $12 ; NORMAL-NEXT: pushl $11 ; NORMAL-NEXT: pushl $10 @@ -339,8 +351,9 @@ entry: ; NORMAL-NEXT: addl $16, %esp define void @test12b() optsize { entry: - call void @good(i32 1, i32 2, i32 3, i32 4) - call void @inreg(i32 5, i32 6, i32 7, i32 8) + %s = alloca %struct.s, align 4 + call void @good(i32 1, i32 2, i32 3, i32 4) + call void @struct(%struct.s* %s, i32 6, i32 7, i32 8) call void @good(i32 9, i32 10, i32 11, i32 12) ret void } diff --git a/test/CodeGen/X86/or-branch.ll b/test/CodeGen/X86/or-branch.ll index ae3ed3f8344a6..9db948adb4652 100644 --- a/test/CodeGen/X86/or-branch.ll +++ b/test/CodeGen/X86/or-branch.ll @@ -1,19 +1,28 @@ -; RUN: llc < %s -march=x86 | not grep set +; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=0 | FileCheck %s --check-prefix=JUMP2 +; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=1 | FileCheck %s --check-prefix=JUMP1 define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind { +; JUMP2-LABEL: foo: +; JUMP2-DAG: jl +; JUMP2-DAG: je +; +; JUMP1-LABEL: foo: +; JUMP1-DAG: sete +; JUMP1-DAG: setl +; JUMP1: orb +; JUMP1: jne entry: - %tmp = tail call i32 (...) @bar( ) ; <i32> [#uses=0] - %tmp.upgrd.1 = icmp eq i32 %X, 0 ; <i1> [#uses=1] - %tmp3 = icmp slt i32 %Y, 5 ; <i1> [#uses=1] - %tmp4 = or i1 %tmp3, %tmp.upgrd.1 ; <i1> [#uses=1] - br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock + %tmp1 = icmp eq i32 %X, 0 + %tmp3 = icmp slt i32 %Y, 5 + %tmp4 = or i1 %tmp3, %tmp1 + br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock -cond_true: ; preds = %entry - %tmp5 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] - ret void +cond_true: + %tmp5 = tail call i32 (...) @bar( ) + ret void -UnifiedReturnBlock: ; preds = %entry - ret void +UnifiedReturnBlock: + ret void } declare i32 @bar(...) diff --git a/test/CodeGen/X86/pr23900.ll b/test/CodeGen/X86/pr23900.ll new file mode 100644 index 0000000000000..cbc77161c0428 --- /dev/null +++ b/test/CodeGen/X86/pr23900.ll @@ -0,0 +1,29 @@ +; RUN: llc -filetype=obj %s -o %t.o +; RUN: llvm-nm %t.o | FileCheck %s + +; Test that it doesn't crash (and produces an object file). +; This use to pass a symbol with a null name to code that expected a valid +; C string. + +; CHECK: U __CxxFrameHandler3 +; CHECK: T f +; CHECK: t f.cleanup +; CHECK: U g +; CHECK: U h + + +target triple = "x86_64-pc-windows-msvc18.0.0" +define void @f(i32 %x) personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { + invoke void @h() + to label %invoke.cont unwind label %lpad +invoke.cont: + ret void +lpad: + landingpad { i8*, i32 } + cleanup + call void @g(i32 %x) + ret void +} +declare void @h() +declare i32 @__CxxFrameHandler3(...) +declare void @g(i32 %x) diff --git a/test/CodeGen/X86/recip-fastmath.ll b/test/CodeGen/X86/recip-fastmath.ll index 7f1521a83bcfd..8e02dad9d5aee 100644 --- a/test/CodeGen/X86/recip-fastmath.ll +++ b/test/CodeGen/X86/recip-fastmath.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 -recip=!divf,!vec-divf | FileCheck %s --check-prefix=NORECIP ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -recip=divf,vec-divf | FileCheck %s --check-prefix=RECIP ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -recip=divf:2,vec-divf:2 | FileCheck %s --check-prefix=REFINE @@ -14,11 +14,11 @@ define float @reciprocal_estimate(float %x) #0 { %div = fdiv fast float 1.0, %x ret float %div -; CHECK-LABEL: reciprocal_estimate: -; CHECK: movss -; CHECK-NEXT: divss -; CHECK-NEXT: movaps -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_estimate: +; NORECIP: movss +; NORECIP-NEXT: divss +; NORECIP-NEXT: movaps +; NORECIP-NEXT: retq ; RECIP-LABEL: reciprocal_estimate: ; RECIP: vrcpss @@ -45,11 +45,11 @@ define <4 x float> @reciprocal_estimate_v4f32(<4 x float> %x) #0 { %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %x ret <4 x float> %div -; CHECK-LABEL: reciprocal_estimate_v4f32: -; CHECK: movaps -; CHECK-NEXT: divps -; CHECK-NEXT: movaps -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_estimate_v4f32: +; NORECIP: movaps +; NORECIP-NEXT: divps +; NORECIP-NEXT: movaps +; NORECIP-NEXT: retq ; RECIP-LABEL: reciprocal_estimate_v4f32: ; RECIP: vrcpps @@ -76,14 +76,14 @@ define <8 x float> @reciprocal_estimate_v8f32(<8 x float> %x) #0 { %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x ret <8 x float> %div -; CHECK-LABEL: reciprocal_estimate_v8f32: -; CHECK: movaps -; CHECK: movaps -; CHECK-NEXT: divps -; CHECK-NEXT: divps -; CHECK-NEXT: movaps -; CHECK-NEXT: movaps -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_estimate_v8f32: +; NORECIP: movaps +; NORECIP: movaps +; NORECIP-NEXT: divps +; NORECIP-NEXT: divps +; NORECIP-NEXT: movaps +; NORECIP-NEXT: movaps +; NORECIP-NEXT: retq ; RECIP-LABEL: reciprocal_estimate_v8f32: ; RECIP: vrcpps diff --git a/test/CodeGen/X86/rrlist-livereg-corrutpion.ll b/test/CodeGen/X86/rrlist-livereg-corrutpion.ll new file mode 100644 index 0000000000000..7191e0453a668 --- /dev/null +++ b/test/CodeGen/X86/rrlist-livereg-corrutpion.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK-LABEL: test +define i64 @test(i64 %a, i256 %b, i1 %c) { + %u = zext i64 %a to i256 + %s = add i256 %u, 1 + %o = trunc i256 %s to i1 + %j = add i256 %s, 1 + %i = icmp ule i64 %a, 1 + %f = select i1 %o, i256 undef, i256 %j + %d = select i1 %i, i256 %f, i256 1 + %e = add i256 %b, 1 + %n = select i1 %c, i256 %e, i256 %b + %m = trunc i256 %n to i64 + %h = add i64 %m, 1 + %r = zext i64 %h to i256 + %v = lshr i256 %d, %r + %t = trunc i256 %v to i1 + %q = shl i256 1, %r + %p = and i256 %d, %q + %w = icmp ule i256 %n, 1 + %y = select i1 %t, i256 undef, i256 %p + %x = select i1 %w, i256 %y, i256 %d + %z = trunc i256 %x to i64 + ret i64 %z +} diff --git a/test/CodeGen/X86/sdiv-exact.ll b/test/CodeGen/X86/sdiv-exact.ll index 4f8d3f05351b2..a6ace5bc31c1a 100644 --- a/test/CodeGen/X86/sdiv-exact.ll +++ b/test/CodeGen/X86/sdiv-exact.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 < %s | FileCheck %s +; RUN: llc -march=x86 -mattr=+sse2 < %s | FileCheck %s define i32 @test1(i32 %x) { %div = sdiv exact i32 %x, 25 @@ -16,3 +16,14 @@ define i32 @test2(i32 %x) { ; CHECK-NEXT: imull $-1431655765 ; CHECK-NEXT: ret } + +define <4 x i32> @test3(<4 x i32> %x) { + %div = sdiv exact <4 x i32> %x, <i32 24, i32 24, i32 24, i32 24> + ret <4 x i32> %div +; CHECK-LABEL: test3: +; CHECK: psrad $3, +; CHECK: pmuludq +; CHECK: pmuludq +; CHECK-NOT: psrad +; CHECK: ret +} diff --git a/test/CodeGen/X86/seh-catch-all-win32.ll b/test/CodeGen/X86/seh-catch-all-win32.ll index 28b0bca962ea8..423b9914e99d2 100644 --- a/test/CodeGen/X86/seh-catch-all-win32.ll +++ b/test/CodeGen/X86/seh-catch-all-win32.ll @@ -12,7 +12,7 @@ declare i32 @llvm.eh.typeid.for(i8*) declare i8* @llvm.frameaddress(i32) declare i8* @llvm.framerecover(i8*, i8*, i32) declare void @llvm.frameescape(...) -declare i8* @llvm.x86.seh.exceptioninfo(i8*, i8*) +declare i8* @llvm.x86.seh.recoverfp(i8*, i8*) define i32 @main() personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) { entry: @@ -43,14 +43,16 @@ eh.resume: ; preds = %lpad define internal i32 @"filt$main"() { entry: - %0 = tail call i8* @llvm.frameaddress(i32 1) - %1 = tail call i8* @llvm.framerecover(i8* bitcast (i32 ()* @main to i8*), i8* %0, i32 0) - %__exceptioncode = bitcast i8* %1 to i32* - %2 = tail call i8* @llvm.x86.seh.exceptioninfo(i8* bitcast (i32 ()* @main to i8*), i8* %0) - %3 = bitcast i8* %2 to i32** - %4 = load i32*, i32** %3, align 4 - %5 = load i32, i32* %4, align 4 - store i32 %5, i32* %__exceptioncode, align 4 + %ebp = tail call i8* @llvm.frameaddress(i32 1) + %parentfp = tail call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @main to i8*), i8* %ebp) + %code.i8 = tail call i8* @llvm.framerecover(i8* bitcast (i32 ()* @main to i8*), i8* %parentfp, i32 0) + %__exceptioncode = bitcast i8* %code.i8 to i32* + %info.addr = getelementptr inbounds i8, i8* %ebp, i32 -20 + %0 = bitcast i8* %info.addr to i32*** + %1 = load i32**, i32*** %0, align 4 + %2 = load i32*, i32** %1, align 4 + %3 = load i32, i32* %2, align 4 + store i32 %3, i32* %__exceptioncode, align 4 ret i32 1 } @@ -76,10 +78,17 @@ entry: ; CHECK: calll _printf ; CHECK: .section .xdata,"dr" +; CHECK: Lmain$parent_frame_offset = Lmain$frame_escape_1 ; CHECK: L__ehtable$main ; CHECK-NEXT: .long -1 ; CHECK-NEXT: .long _filt$main ; CHECK-NEXT: .long Ltmp{{[0-9]+}} ; CHECK-LABEL: _filt$main: -; CHECK: movl +; CHECK: pushl %ebp +; CHECK: movl %esp, %ebp +; CHECK: movl (%ebp), %[[oldebp:[a-z]+]] +; CHECK: movl -20(%[[oldebp]]), %[[ehinfo:[a-z]+]] +; CHECK: movl (%[[ehinfo]]), %[[ehrec:[a-z]+]] +; CHECK: movl (%[[ehrec]]), %[[ehcode:[a-z]+]] +; CHECK: movl %[[ehcode]], {{.*}}(%{{.*}}) diff --git a/test/CodeGen/X86/seh-filter-no-personality.ll b/test/CodeGen/X86/seh-filter-no-personality.ll new file mode 100644 index 0000000000000..87bc9c93f4004 --- /dev/null +++ b/test/CodeGen/X86/seh-filter-no-personality.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=i686-windows-msvc < %s | FileCheck %s + +; Mostly make sure that llvm.x86.seh.recoverfp doesn't crash if the parent +; function lacks a personality. + +declare i8* @llvm.frameaddress(i32) +declare i8* @llvm.x86.seh.recoverfp(i8*, i8*) + +define i32 @main() { +entry: + ret i32 0 +} + +define internal i32 @"filt$main"() { +entry: + %ebp = tail call i8* @llvm.frameaddress(i32 1) + %parentfp = tail call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @main to i8*), i8* %ebp) + %info.addr = getelementptr inbounds i8, i8* %ebp, i32 -20 + %0 = bitcast i8* %info.addr to i32*** + %1 = load i32**, i32*** %0, align 4 + %2 = load i32*, i32** %1, align 4 + %3 = load i32, i32* %2, align 4 + %matches = icmp eq i32 %3, u0xC0000005 + %r = zext i1 %matches to i32 + ret i32 %r +} + +; CHECK: _main: +; CHECK: xorl %eax, %eax +; CHECK: retl + +; CHECK: _filt$main: +; CHECK: retl diff --git a/test/CodeGen/X86/seh-safe-div-win32.ll b/test/CodeGen/X86/seh-safe-div-win32.ll index 0f76ec07a6b61..b1bcde2c7ff3b 100644 --- a/test/CodeGen/X86/seh-safe-div-win32.ll +++ b/test/CodeGen/X86/seh-safe-div-win32.ll @@ -122,27 +122,30 @@ entry: ; ... ; } EXCEPTION_RECORD; -; FIXME: Use llvm.eh.exceptioninfo for this. -declare i32 @safe_div_filt0() -declare i32 @safe_div_filt1() -; define i32 @safe_div_filt0() { -; %eh_ptrs_c = bitcast i8* %eh_ptrs to i32** -; %eh_rec = load i32*, i32** %eh_ptrs_c -; %eh_code = load i32, i32* %eh_rec -; ; EXCEPTION_ACCESS_VIOLATION = 0xC0000005 -; %cmp = icmp eq i32 %eh_code, 3221225477 -; %filt.res = zext i1 %cmp to i32 -; ret i32 %filt.res -; } -; define i32 @safe_div_filt1() { -; %eh_ptrs_c = bitcast i8* %eh_ptrs to i32** -; %eh_rec = load i32*, i32** %eh_ptrs_c -; %eh_code = load i32, i32* %eh_rec -; ; EXCEPTION_INT_DIVIDE_BY_ZERO = 0xC0000094 -; %cmp = icmp eq i32 %eh_code, 3221225620 -; %filt.res = zext i1 %cmp to i32 -; ret i32 %filt.res -; } +define i32 @safe_div_filt0() { + %ebp = call i8* @llvm.frameaddress(i32 1) + %eh_ptrs.addr.i8 = getelementptr inbounds i8, i8* %ebp, i32 -20 + %eh_ptrs.addr = bitcast i8* %eh_ptrs.addr.i8 to i32*** + %eh_ptrs = load i32**, i32*** %eh_ptrs.addr + %eh_rec = load i32*, i32** %eh_ptrs + %eh_code = load i32, i32* %eh_rec + ; EXCEPTION_ACCESS_VIOLATION = 0xC0000005 + %cmp = icmp eq i32 %eh_code, 3221225477 + %filt.res = zext i1 %cmp to i32 + ret i32 %filt.res +} +define i32 @safe_div_filt1() { + %ebp = call i8* @llvm.frameaddress(i32 1) + %eh_ptrs.addr.i8 = getelementptr inbounds i8, i8* %ebp, i32 -20 + %eh_ptrs.addr = bitcast i8* %eh_ptrs.addr.i8 to i32*** + %eh_ptrs = load i32**, i32*** %eh_ptrs.addr + %eh_rec = load i32*, i32** %eh_ptrs + %eh_code = load i32, i32* %eh_rec + ; EXCEPTION_INT_DIVIDE_BY_ZERO = 0xC0000094 + %cmp = icmp eq i32 %eh_code, 3221225620 + %filt.res = zext i1 %cmp to i32 + ret i32 %filt.res +} @str_result = internal constant [21 x i8] c"safe_div result: %d\0A\00" @@ -170,3 +173,4 @@ declare i32 @llvm.eh.typeid.for(i8*) readnone nounwind declare void @puts(i8*) declare void @printf(i8*, ...) declare void @abort() +declare i8* @llvm.frameaddress(i32) diff --git a/test/CodeGen/X86/shift-combine.ll b/test/CodeGen/X86/shift-combine.ll index ec62bcdcdba1b..43301041a0b69 100644 --- a/test/CodeGen/X86/shift-combine.ll +++ b/test/CodeGen/X86/shift-combine.ll @@ -17,3 +17,62 @@ entry: ret i32 %tmp5 } +define i32* @test_exact1(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact1: +; CHECK: sarl % + + %sub = sub i32 %b, %a + %shr = ashr exact i32 %sub, 3 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} + +define i32* @test_exact2(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact2: +; CHECK: sarl % + + %sub = sub i32 %b, %a + %shr = ashr exact i32 %sub, 3 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} + +define i32* @test_exact3(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact3: +; CHECK-NOT: sarl + + %sub = sub i32 %b, %a + %shr = ashr exact i32 %sub, 2 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} + +define i32* @test_exact4(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact4: +; CHECK: shrl % + + %sub = sub i32 %b, %a + %shr = lshr exact i32 %sub, 3 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} + +define i32* @test_exact5(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact5: +; CHECK: shrl % + + %sub = sub i32 %b, %a + %shr = lshr exact i32 %sub, 3 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} + +define i32* @test_exact6(i32 %a, i32 %b, i32* %x) { +; CHECK-LABEL: test_exact6: +; CHECK-NOT: shrl + + %sub = sub i32 %b, %a + %shr = lshr exact i32 %sub, 2 + %gep = getelementptr inbounds i32, i32* %x, i32 %shr + ret i32* %gep +} diff --git a/test/CodeGen/X86/sqrt-fastmath.ll b/test/CodeGen/X86/sqrt-fastmath.ll index 373fa53c970f8..0f8d9f4d713fa 100644 --- a/test/CodeGen/X86/sqrt-fastmath.ll +++ b/test/CodeGen/X86/sqrt-fastmath.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 -recip=!sqrtf,!vec-sqrtf,!divf,!vec-divf | FileCheck %s --check-prefix=NORECIP ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -recip=sqrtf,vec-sqrtf | FileCheck %s --check-prefix=ESTIMATE declare double @__sqrt_finite(double) #0 @@ -10,10 +10,10 @@ declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #0 define double @fd(double %d) #0 { -; CHECK-LABEL: fd: -; CHECK: # BB#0: -; CHECK-NEXT: sqrtsd %xmm0, %xmm0 -; CHECK-NEXT: retq +; NORECIP-LABEL: fd: +; NORECIP: # BB#0: +; NORECIP-NEXT: sqrtsd %xmm0, %xmm0 +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: fd: ; ESTIMATE: # BB#0: @@ -25,10 +25,10 @@ define double @fd(double %d) #0 { define float @ff(float %f) #0 { -; CHECK-LABEL: ff: -; CHECK: # BB#0: -; CHECK-NEXT: sqrtss %xmm0, %xmm0 -; CHECK-NEXT: retq +; NORECIP-LABEL: ff: +; NORECIP: # BB#0: +; NORECIP-NEXT: sqrtss %xmm0, %xmm0 +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: ff: ; ESTIMATE: # BB#0: @@ -49,11 +49,11 @@ define float @ff(float %f) #0 { define x86_fp80 @fld(x86_fp80 %ld) #0 { -; CHECK-LABEL: fld: -; CHECK: # BB#0: -; CHECK-NEXT: fldt {{[0-9]+}}(%rsp) -; CHECK-NEXT: fsqrt -; CHECK-NEXT: retq +; NORECIP-LABEL: fld: +; NORECIP: # BB#0: +; NORECIP-NEXT: fldt {{[0-9]+}}(%rsp) +; NORECIP-NEXT: fsqrt +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: fld: ; ESTIMATE: # BB#0: @@ -67,12 +67,12 @@ define x86_fp80 @fld(x86_fp80 %ld) #0 { define float @reciprocal_square_root(float %x) #0 { -; CHECK-LABEL: reciprocal_square_root: -; CHECK: # BB#0: -; CHECK-NEXT: sqrtss %xmm0, %xmm1 -; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; CHECK-NEXT: divss %xmm1, %xmm0 -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_square_root: +; NORECIP: # BB#0: +; NORECIP-NEXT: sqrtss %xmm0, %xmm1 +; NORECIP-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; NORECIP-NEXT: divss %xmm1, %xmm0 +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: reciprocal_square_root: ; ESTIMATE: # BB#0: @@ -89,12 +89,12 @@ define float @reciprocal_square_root(float %x) #0 { } define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 { -; CHECK-LABEL: reciprocal_square_root_v4f32: -; CHECK: # BB#0: -; CHECK-NEXT: sqrtps %xmm0, %xmm1 -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] -; CHECK-NEXT: divps %xmm1, %xmm0 -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_square_root_v4f32: +; NORECIP: # BB#0: +; NORECIP-NEXT: sqrtps %xmm0, %xmm1 +; NORECIP-NEXT: movaps {{.*#+}} xmm0 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] +; NORECIP-NEXT: divps %xmm1, %xmm0 +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: reciprocal_square_root_v4f32: ; ESTIMATE: # BB#0: @@ -111,15 +111,15 @@ define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 { } define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 { -; CHECK-LABEL: reciprocal_square_root_v8f32: -; CHECK: # BB#0: -; CHECK-NEXT: sqrtps %xmm1, %xmm2 -; CHECK-NEXT: sqrtps %xmm0, %xmm3 -; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] -; CHECK-NEXT: movaps %xmm1, %xmm0 -; CHECK-NEXT: divps %xmm3, %xmm0 -; CHECK-NEXT: divps %xmm2, %xmm1 -; CHECK-NEXT: retq +; NORECIP-LABEL: reciprocal_square_root_v8f32: +; NORECIP: # BB#0: +; NORECIP-NEXT: sqrtps %xmm1, %xmm2 +; NORECIP-NEXT: sqrtps %xmm0, %xmm3 +; NORECIP-NEXT: movaps {{.*#+}} xmm1 = [1.000000e+00,1.000000e+00,1.000000e+00,1.000000e+00] +; NORECIP-NEXT: movaps %xmm1, %xmm0 +; NORECIP-NEXT: divps %xmm3, %xmm0 +; NORECIP-NEXT: divps %xmm2, %xmm1 +; NORECIP-NEXT: retq ; ; ESTIMATE-LABEL: reciprocal_square_root_v8f32: ; ESTIMATE: # BB#0: diff --git a/test/CodeGen/X86/stack-folding-fp-sse42.ll b/test/CodeGen/X86/stack-folding-fp-sse42.ll index 95f0c3d3a188b..63acf5f4f96f4 100644 --- a/test/CodeGen/X86/stack-folding-fp-sse42.ll +++ b/test/CodeGen/X86/stack-folding-fp-sse42.ll @@ -314,7 +314,13 @@ define i64 @stack_fold_cvtsd2si64_int(<2 x double> %a0) { } declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone -; TODO stack_fold_cvtsd2ss +define float @stack_fold_cvtsd2ss(double %a0) optsize { + ;CHECK-LABEL: stack_fold_cvtsd2ss + ;CHECK: cvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() + %2 = fptrunc double %a0 to float + ret float %2 +} define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) optsize { ;CHECK-LABEL: stack_fold_cvtsd2ss_int diff --git a/test/CodeGen/X86/stack-folding-int-avx2.ll b/test/CodeGen/X86/stack-folding-int-avx2.ll index e930d244638a8..a164fbbc7a6ae 100644 --- a/test/CodeGen/X86/stack-folding-int-avx2.ll +++ b/test/CodeGen/X86/stack-folding-int-avx2.ll @@ -867,9 +867,21 @@ define <8 x i32> @stack_fold_pshufd(<8 x i32> %a0) { ret <8 x i32> %2 } -; TODO stack_fold_pshufhw +define <16 x i16> @stack_fold_vpshufhw(<16 x i16> %a0) { + ;CHECK-LABEL: stack_fold_vpshufhw + ;CHECK: vpshufhw $27, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() + %2 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 5, i32 4, i32 8, i32 9, i32 10, i32 11, i32 15, i32 14, i32 13, i32 12> + ret <16 x i16> %2 +} -; TODO stack_fold_pshuflw +define <16 x i16> @stack_fold_vpshuflw(<16 x i16> %a0) { + ;CHECK-LABEL: stack_fold_vpshuflw + ;CHECK: vpshuflw $27, {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() + %2 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7, i32 11, i32 10, i32 9, i32 8, i32 12, i32 13, i32 14, i32 15> + ret <16 x i16> %2 +} define <32 x i8> @stack_fold_psignb(<32 x i8> %a0, <32 x i8> %a1) { ;CHECK-LABEL: stack_fold_psignb diff --git a/test/CodeGen/X86/statepoint-stackmap-format.ll b/test/CodeGen/X86/statepoint-stackmap-format.ll index 6bb0d8980e5bd..e18476cee53c5 100644 --- a/test/CodeGen/X86/statepoint-stackmap-format.ll +++ b/test/CodeGen/X86/statepoint-stackmap-format.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -mtriple="x86_64-pc-linux-gnu" | FileCheck %s +; RUN: llc < %s -mtriple="x86_64-pc-win64-coff" | FileCheck %s + ; This test is a sanity check to ensure statepoints are generating StackMap ; sections correctly. This is not intended to be a rigorous test of the ; StackMap format (see the stackmap tests for that). target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-pc-linux-gnu" declare zeroext i1 @return_i1() diff --git a/test/CodeGen/X86/system-intrinsics-64.ll b/test/CodeGen/X86/system-intrinsics-64.ll new file mode 100644 index 0000000000000..96c4417733902 --- /dev/null +++ b/test/CodeGen/X86/system-intrinsics-64.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s + +define void @test_fxsave(i8* %ptr) { +; CHECK-LABEL: test_fxsave +; CHECK: fxsave + call void @llvm.x86.fxsave(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxsave(i8*) + +define void @test_fxsave64(i8* %ptr) { +; CHECK-LABEL: test_fxsave64 +; CHECK: fxsave64 + call void @llvm.x86.fxsave64(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxsave64(i8*) + +define void @test_fxrstor(i8* %ptr) { +; CHECK-LABEL: test_fxrstor +; CHECK: fxrstor + call void @llvm.x86.fxrstor(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxrstor(i8*) + +define void @test_fxrstor64(i8* %ptr) { +; CHECK-LABEL: test_fxrstor64 +; CHECK: fxrstor64 + call void @llvm.x86.fxrstor64(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxrstor64(i8*) diff --git a/test/CodeGen/X86/system-intrinsics.ll b/test/CodeGen/X86/system-intrinsics.ll new file mode 100644 index 0000000000000..84fcd052d7dbf --- /dev/null +++ b/test/CodeGen/X86/system-intrinsics.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s + +define void @test_fxsave(i8* %ptr) { +; CHECK-LABEL: test_fxsave +; CHECK: fxsave + call void @llvm.x86.fxsave(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxsave(i8*) + +define void @test_fxrstor(i8* %ptr) { +; CHECK-LABEL: test_fxrstor +; CHECK: fxrstor + call void @llvm.x86.fxrstor(i8* %ptr) + ret void; +} +declare void @llvm.x86.fxrstor(i8*) diff --git a/test/CodeGen/X86/twoaddr-lea.ll b/test/CodeGen/X86/twoaddr-lea.ll index b5ca0275d8d69..5779cf33ac84c 100644 --- a/test/CodeGen/X86/twoaddr-lea.ll +++ b/test/CodeGen/X86/twoaddr-lea.ll @@ -25,8 +25,7 @@ define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind { entry: ; CHECK-LABEL: test2: ; CHECK: leal -; CHECK-NOT: leal -; CHECK-NOT: mov +; CHECK-NEXT: addl ; CHECK-NEXT: addl ; CHECK-NEXT: ret %add = add i32 %b, %a diff --git a/test/CodeGen/X86/vec_int_to_fp.ll b/test/CodeGen/X86/vec_int_to_fp.ll index 8dded07af7d4d..ca8be65075b90 100644 --- a/test/CodeGen/X86/vec_int_to_fp.ll +++ b/test/CodeGen/X86/vec_int_to_fp.ll @@ -50,31 +50,15 @@ define <2 x double> @sitofp_2vf64_i32(<4 x i32> %a) { define <2 x double> @sitofp_2vf64_i16(<8 x i16> %a) { ; SSE2-LABEL: sitofp_2vf64_i16: ; SSE2: # BB#0: -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; SSE2-NEXT: movd %xmm1, %rax -; SSE2-NEXT: movswq %ax, %rax -; SSE2-NEXT: movd %xmm0, %rcx -; SSE2-NEXT: movswq %cx, %rcx -; SSE2-NEXT: xorps %xmm0, %xmm0 -; SSE2-NEXT: cvtsi2sdq %rcx, %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 -; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] +; SSE2-NEXT: psrad $16, %xmm0 +; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: retq ; ; AVX-LABEL: sitofp_2vf64_i16: ; AVX: # BB#0: -; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero -; AVX-NEXT: vmovq %xmm0, %rax -; AVX-NEXT: movswq %ax, %rax -; AVX-NEXT: vpextrq $1, %xmm0, %rcx -; AVX-NEXT: movswq %cx, %rcx -; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; AVX-NEXT: vcvtsi2sdq %rcx, %xmm0, %xmm0 -; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 -; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX-NEXT: vpmovsxwd %xmm0, %xmm0 +; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX-NEXT: retq %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1> %cvt = sitofp <2 x i16> %shuf to <2 x double> @@ -86,30 +70,14 @@ define <2 x double> @sitofp_2vf64_i8(<16 x i8> %a) { ; SSE2: # BB#0: ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] -; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0,0,1,1] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; SSE2-NEXT: movd %xmm1, %rax -; SSE2-NEXT: movsbq %al, %rax -; SSE2-NEXT: movd %xmm0, %rcx -; SSE2-NEXT: movsbq %cl, %rcx -; SSE2-NEXT: xorps %xmm0, %xmm0 -; SSE2-NEXT: cvtsi2sdq %rcx, %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 -; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: psrad $24, %xmm0 +; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: retq ; ; AVX-LABEL: sitofp_2vf64_i8: ; AVX: # BB#0: -; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero -; AVX-NEXT: vmovq %xmm0, %rax -; AVX-NEXT: movsbq %al, %rax -; AVX-NEXT: vpextrq $1, %xmm0, %rcx -; AVX-NEXT: movsbq %cl, %rcx -; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; AVX-NEXT: vcvtsi2sdq %rcx, %xmm0, %xmm0 -; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 -; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX-NEXT: vpmovsxbd %xmm0, %xmm0 +; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX-NEXT: retq %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1> %cvt = sitofp <2 x i8> %shuf to <2 x double> diff --git a/test/CodeGen/X86/vec_shift8.ll b/test/CodeGen/X86/vec_shift8.ll deleted file mode 100644 index 9d19f667ea9b2..0000000000000 --- a/test/CodeGen/X86/vec_shift8.ll +++ /dev/null @@ -1,527 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX - -; -; Vectorized integer shifts -; - -define <2 x i64> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind readnone ssp { -entry: -; ALL-NOT: shll -; -; SSE2: psllw $12, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psllw $8, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psllw $4, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psllw $2, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm0, %xmm2 -; SSE2-NEXT: psllw $1, %xmm0 -; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: psllw $12, %xmm0 -; SSE41-NEXT: psllw $4, %xmm1 -; SSE41-NEXT: por %xmm0, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm3 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm2, %xmm4 -; SSE41-NEXT: psllw $8, %xmm4 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm4, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psllw $4, %xmm1 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psllw $2, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psllw $1, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $12, %xmm1, %xmm2 -; AVX-NEXT: vpsllw $4, %xmm1, %xmm1 -; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 -; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm2 -; AVX-NEXT: vpsllw $8, %xmm0, %xmm3 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsllw $4, %xmm0, %xmm1 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsllw $2, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsllw $1, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq - %shl = shl <8 x i16> %r, %a - %tmp2 = bitcast <8 x i16> %shl to <2 x i64> - ret <2 x i64> %tmp2 -} - -define <2 x i64> @shl_16i8(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp { -entry: -; SSE2: psllw $5, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm2 -; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pandn %xmm0, %xmm4 -; SSE2-NEXT: psllw $4, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: paddb %xmm1, %xmm1 -; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pandn %xmm0, %xmm4 -; SSE2-NEXT: psllw $2, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: paddb %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm1 -; SSE2-NEXT: pandn %xmm0, %xmm1 -; SSE2-NEXT: paddb %xmm0, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm1, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: psllw $5, %xmm1 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psllw $4, %xmm3 -; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psllw $2, %xmm3 -; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE41-NEXT: paddb %xmm1, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: paddb %xmm3, %xmm3 -; SSE41-NEXT: paddb %xmm1, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $5, %xmm1, %xmm1 -; AVX-NEXT: vpsllw $4, %xmm0, %xmm2 -; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpsllw $2, %xmm0, %xmm2 -; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm2 -; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: retq - %shl = shl <16 x i8> %r, %a - %tmp2 = bitcast <16 x i8> %shl to <2 x i64> - ret <2 x i64> %tmp2 -} - -define <2 x i64> @ashr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind readnone ssp { -entry: -; ALL-NOT: sarw -; -; SSE2: psllw $12, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psraw $8, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psraw $4, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psraw $2, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm0, %xmm2 -; SSE2-NEXT: psraw $1, %xmm0 -; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: psllw $12, %xmm0 -; SSE41-NEXT: psllw $4, %xmm1 -; SSE41-NEXT: por %xmm0, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm3 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm2, %xmm4 -; SSE41-NEXT: psraw $8, %xmm4 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm4, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psraw $4, %xmm1 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psraw $2, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psraw $1, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $12, %xmm1, %xmm2 -; AVX-NEXT: vpsllw $4, %xmm1, %xmm1 -; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 -; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm2 -; AVX-NEXT: vpsraw $8, %xmm0, %xmm3 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsraw $4, %xmm0, %xmm1 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsraw $2, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsraw $1, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq - %ashr = ashr <8 x i16> %r, %a - %tmp2 = bitcast <8 x i16> %ashr to <2 x i64> - ret <2 x i64> %tmp2 -} - -define <2 x i64> @ashr_16i8(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp { -entry: -; ALL-NOT: sarb -; -; SSE2: punpckhbw {{.*#}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] -; SSE2-NEXT: psllw $5, %xmm1 -; SSE2-NEXT: punpckhbw {{.*#}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15] -; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm6 -; SSE2-NEXT: pandn %xmm2, %xmm6 -; SSE2-NEXT: psraw $4, %xmm2 -; SSE2-NEXT: pand %xmm5, %xmm2 -; SSE2-NEXT: por %xmm6, %xmm2 -; SSE2-NEXT: paddw %xmm4, %xmm4 -; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm6 -; SSE2-NEXT: pandn %xmm2, %xmm6 -; SSE2-NEXT: psraw $2, %xmm2 -; SSE2-NEXT: pand %xmm5, %xmm2 -; SSE2-NEXT: por %xmm6, %xmm2 -; SSE2-NEXT: paddw %xmm4, %xmm4 -; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm4 -; SSE2-NEXT: pandn %xmm2, %xmm4 -; SSE2-NEXT: psraw $1, %xmm2 -; SSE2-NEXT: pand %xmm5, %xmm2 -; SSE2-NEXT: por %xmm4, %xmm2 -; SSE2-NEXT: psrlw $8, %xmm2 -; SSE2-NEXT: punpcklbw {{.*#}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; SSE2-NEXT: punpcklbw {{.*#}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pcmpgtw %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm5 -; SSE2-NEXT: pandn %xmm0, %xmm5 -; SSE2-NEXT: psraw $4, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 -; SSE2-NEXT: por %xmm5, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pcmpgtw %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm5 -; SSE2-NEXT: pandn %xmm0, %xmm5 -; SSE2-NEXT: psraw $2, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 -; SSE2-NEXT: por %xmm5, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtw %xmm1, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm1 -; SSE2-NEXT: pandn %xmm0, %xmm1 -; SSE2-NEXT: psraw $1, %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm1, %xmm0 -; SSE2-NEXT: psrlw $8, %xmm0 -; SSE2-NEXT: packuswb %xmm2, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: psllw $5, %xmm1 -; SSE41-NEXT: punpckhbw {{.*#}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] -; SSE41-NEXT: punpckhbw {{.*#}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: psraw $4, %xmm4 -; SSE41-NEXT: pblendvb %xmm4, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: psraw $2, %xmm4 -; SSE41-NEXT: paddw %xmm0, %xmm0 -; SSE41-NEXT: pblendvb %xmm4, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: psraw $1, %xmm4 -; SSE41-NEXT: paddw %xmm0, %xmm0 -; SSE41-NEXT: pblendvb %xmm4, %xmm3 -; SSE41-NEXT: psrlw $8, %xmm3 -; SSE41-NEXT: punpcklbw {{.*#}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; SSE41-NEXT: punpcklbw {{.*#}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; SSE41-NEXT: movdqa %xmm1, %xmm2 -; SSE41-NEXT: psraw $4, %xmm2 -; SSE41-NEXT: pblendvb %xmm2, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm2 -; SSE41-NEXT: psraw $2, %xmm2 -; SSE41-NEXT: paddw %xmm0, %xmm0 -; SSE41-NEXT: pblendvb %xmm2, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm2 -; SSE41-NEXT: psraw $1, %xmm2 -; SSE41-NEXT: paddw %xmm0, %xmm0 -; SSE41-NEXT: pblendvb %xmm2, %xmm1 -; SSE41-NEXT: psrlw $8, %xmm1 -; SSE41-NEXT: packuswb %xmm3, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $5, %xmm1, %xmm1 -; AVX-NEXT: vpunpckhbw {{.*#}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] -; AVX-NEXT: vpunpckhbw {{.*#}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] -; AVX-NEXT: vpsraw $4, %xmm3, %xmm4 -; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 -; AVX-NEXT: vpsraw $2, %xmm3, %xmm4 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 -; AVX-NEXT: vpsraw $1, %xmm3, %xmm4 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2 -; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2 -; AVX-NEXT: vpunpcklbw {{.*#}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX-NEXT: vpunpcklbw {{.*#}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] -; AVX-NEXT: vpsraw $4, %xmm0, %xmm3 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsraw $2, %xmm0, %xmm3 -; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsraw $1, %xmm0, %xmm3 -; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 -; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 -; AVX-NEXT: retq - %ashr = ashr <16 x i8> %r, %a - %tmp2 = bitcast <16 x i8> %ashr to <2 x i64> - ret <2 x i64> %tmp2 -} - -define <2 x i64> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind readnone ssp { -entry: -; ALL-NOT: shrl -; -; SSE2: psllw $12, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psrlw $8, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psrlw $4, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm0, %xmm3 -; SSE2-NEXT: psrlw $2, %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm3, %xmm0 -; SSE2-NEXT: paddw %xmm1, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm0, %xmm2 -; SSE2-NEXT: psrlw $1, %xmm0 -; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: psllw $12, %xmm0 -; SSE41-NEXT: psllw $4, %xmm1 -; SSE41-NEXT: por %xmm0, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm3 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm2, %xmm4 -; SSE41-NEXT: psrlw $8, %xmm4 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm4, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psrlw $4, %xmm1 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psrlw $2, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psrlw $1, %xmm1 -; SSE41-NEXT: paddw %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pblendvb %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $12, %xmm1, %xmm2 -; AVX-NEXT: vpsllw $4, %xmm1, %xmm1 -; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 -; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm2 -; AVX-NEXT: vpsrlw $8, %xmm0, %xmm3 -; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $4, %xmm0, %xmm1 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $2, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1 -; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq - %lshr = lshr <8 x i16> %r, %a - %tmp2 = bitcast <8 x i16> %lshr to <2 x i64> - ret <2 x i64> %tmp2 -} - -define <2 x i64> @lshr_16i8(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp { -entry: -; ALL-NOT: shrb -; -; SSE2: psllw $5, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm2 -; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pandn %xmm0, %xmm4 -; SSE2-NEXT: psrlw $4, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: paddb %xmm1, %xmm1 -; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pandn %xmm0, %xmm4 -; SSE2-NEXT: psrlw $2, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: paddb %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm1 -; SSE2-NEXT: pandn %xmm0, %xmm1 -; SSE2-NEXT: psrlw $1, %xmm0 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE2-NEXT: pand %xmm2, %xmm0 -; SSE2-NEXT: por %xmm1, %xmm0 -; SSE2-NEXT: retq -; -; SSE41: movdqa %xmm0, %xmm2 -; SSE41-NEXT: psllw $5, %xmm1 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psrlw $4, %xmm3 -; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psrlw $2, %xmm3 -; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE41-NEXT: paddb %xmm1, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psrlw $1, %xmm3 -; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE41-NEXT: paddb %xmm1, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pblendvb %xmm3, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpsllw $5, %xmm1, %xmm1 -; AVX-NEXT: vpsrlw $4, %xmm0, %xmm2 -; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $2, %xmm0, %xmm2 -; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpsrlw $1, %xmm0, %xmm2 -; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 -; AVX-NEXT: retq - %lshr = lshr <16 x i8> %r, %a - %tmp2 = bitcast <16 x i8> %lshr to <2 x i64> - ret <2 x i64> %tmp2 -} diff --git a/test/CodeGen/X86/vector-sext.ll b/test/CodeGen/X86/vector-sext.ll index e6acc7efaf394..aafc05b2ed4ce 100644 --- a/test/CodeGen/X86/vector-sext.ll +++ b/test/CodeGen/X86/vector-sext.ll @@ -117,6 +117,46 @@ entry: ret <4 x i64>%B } +define i32 @sext_2i8_to_i32(<16 x i8> %A) nounwind uwtable readnone ssp { +; SSE2-LABEL: sext_2i8_to_i32: +; SSE2: # BB#0: # %entry +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: psraw $8, %xmm0 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: retq +; +; SSSE3-LABEL: sext_2i8_to_i32: +; SSSE3: # BB#0: # %entry +; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSSE3-NEXT: psraw $8, %xmm0 +; SSSE3-NEXT: movd %xmm0, %eax +; SSSE3-NEXT: retq +; +; SSE41-LABEL: sext_2i8_to_i32: +; SSE41: # BB#0: # %entry +; SSE41-NEXT: pmovsxbw %xmm0, %xmm0 +; SSE41-NEXT: movd %xmm0, %eax +; SSE41-NEXT: retq +; +; AVX-LABEL: sext_2i8_to_i32: +; AVX: # BB#0: # %entry +; AVX-NEXT: vpmovsxbw %xmm0, %xmm0 +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: retq +; +; X32-SSE41-LABEL: sext_2i8_to_i32: +; X32-SSE41: # BB#0: # %entry +; X32-SSE41: pmovsxbw %xmm0, %xmm0 +; X32-SSE41-NEXT: movd %xmm0, %eax +; X32-SSE41-NEXT: popl %edx +; X32-SSE41-NEXT: retl +entry: + %Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1> + %Ex = sext <2 x i8> %Shuf to <2 x i16> + %Bc = bitcast <2 x i16> %Ex to i32 + ret i32 %Bc +} + define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) { ; SSE2-LABEL: load_sext_test1: ; SSE2: # BB#0: # %entry diff --git a/test/CodeGen/X86/vector-shift-ashr-128.ll b/test/CodeGen/X86/vector-shift-ashr-128.ll new file mode 100644 index 0000000000000..4fd2f8b51b8b2 --- /dev/null +++ b/test/CodeGen/X86/vector-shift-ashr-128.ll @@ -0,0 +1,1041 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: var_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: movd %xmm1, %rcx +; SSE2-NEXT: sarq %cl, %rax +; SSE2-NEXT: movd %rax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rcx +; SSE2-NEXT: sarq %cl, %rax +; SSE2-NEXT: movd %rax, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: pextrq $1, %xmm1, %rcx +; SSE41-NEXT: sarq %cl, %rax +; SSE41-NEXT: movd %rax, %xmm2 +; SSE41-NEXT: movd %xmm0, %rax +; SSE41-NEXT: movd %xmm1, %rcx +; SSE41-NEXT: sarq %cl, %rax +; SSE41-NEXT: movd %rax, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; SSE41-NEXT: retq +; +; AVX-LABEL: var_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpextrq $1, %xmm0, %rax +; AVX-NEXT: vpextrq $1, %xmm1, %rcx +; AVX-NEXT: sarq %cl, %rax +; AVX-NEXT: vmovq %rax, %xmm2 +; AVX-NEXT: vmovq %xmm0, %rax +; AVX-NEXT: vmovq %xmm1, %rcx +; AVX-NEXT: sarq %cl, %rax +; AVX-NEXT: vmovq %rax, %xmm0 +; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX-NEXT: retq + %shift = ashr <2 x i64> %a, %b + ret <2 x i64> %shift +} + +define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: var_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] +; SSE2-NEXT: movd %xmm2, %ecx +; SSE2-NEXT: sarl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,2,3] +; SSE2-NEXT: movd %xmm3, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3] +; SSE2-NEXT: movd %xmm3, %ecx +; SSE2-NEXT: sarl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm3 +; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: movd %xmm1, %ecx +; SSE2-NEXT: sarl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: sarl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pextrd $1, %xmm0, %eax +; SSE41-NEXT: pextrd $1, %xmm1, %ecx +; SSE41-NEXT: sarl %cl, %eax +; SSE41-NEXT: movd %xmm0, %edx +; SSE41-NEXT: movd %xmm1, %ecx +; SSE41-NEXT: sarl %cl, %edx +; SSE41-NEXT: movd %edx, %xmm2 +; SSE41-NEXT: pinsrd $1, %eax, %xmm2 +; SSE41-NEXT: pextrd $2, %xmm0, %eax +; SSE41-NEXT: pextrd $2, %xmm1, %ecx +; SSE41-NEXT: sarl %cl, %eax +; SSE41-NEXT: pinsrd $2, %eax, %xmm2 +; SSE41-NEXT: pextrd $3, %xmm0, %eax +; SSE41-NEXT: pextrd $3, %xmm1, %ecx +; SSE41-NEXT: sarl %cl, %eax +; SSE41-NEXT: pinsrd $3, %eax, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: vpextrd $1, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vmovd %xmm0, %edx +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: vpextrd $2, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: vpextrd $3, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = ashr <4 x i32> %a, %b + ret <4 x i32> %shift +} + +define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: var_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $12, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psraw $8, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psraw $4, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psraw $2, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: psraw $15, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psraw $1, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: psllw $12, %xmm0 +; SSE41-NEXT: psllw $4, %xmm1 +; SSE41-NEXT: por %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psraw $8, %xmm4 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psraw $4, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psraw $2, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psraw $1, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v8i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpsraw $8, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero +; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 +; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %shift = ashr <8 x i16> %a, %b + ret <8 x i16> %shift +} + +define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: var_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] +; SSE2-NEXT: psllw $5, %xmm1 +; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15] +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm2, %xmm6 +; SSE2-NEXT: psraw $4, %xmm2 +; SSE2-NEXT: pand %xmm5, %xmm2 +; SSE2-NEXT: por %xmm6, %xmm2 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm2, %xmm6 +; SSE2-NEXT: psraw $2, %xmm2 +; SSE2-NEXT: pand %xmm5, %xmm2 +; SSE2-NEXT: por %xmm6, %xmm2 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm4 +; SSE2-NEXT: pandn %xmm2, %xmm4 +; SSE2-NEXT: psraw $1, %xmm2 +; SSE2-NEXT: pand %xmm5, %xmm2 +; SSE2-NEXT: por %xmm4, %xmm2 +; SSE2-NEXT: psrlw $8, %xmm2 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm1, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $4, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm1, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $2, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: pcmpgtw %xmm1, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: pandn %xmm0, %xmm1 +; SSE2-NEXT: psraw $1, %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: packuswb %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $4, %xmm4 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $2, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $1, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: psrlw $8, %xmm3 +; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $4, %xmm2 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $2, %xmm2 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $1, %xmm2 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: psrlw $8, %xmm1 +; SSE41-NEXT: packuswb %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: var_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX-NEXT: vpsraw $4, %xmm3, %xmm4 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX-NEXT: vpsraw $2, %xmm3, %xmm4 +; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX-NEXT: vpsraw $1, %xmm3, %xmm4 +; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2 +; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsraw $2, %xmm0, %xmm3 +; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsraw $1, %xmm0, %xmm3 +; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = ashr <16 x i8> %a, %b + ret <16 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: splatvar_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,0,1] +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: movd %xmm2, %rcx +; SSE2-NEXT: sarq %cl, %rax +; SSE2-NEXT: movd %rax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rcx +; SSE2-NEXT: sarq %cl, %rax +; SSE2-NEXT: movd %rax, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: pextrq $1, %xmm1, %rcx +; SSE41-NEXT: sarq %cl, %rax +; SSE41-NEXT: movd %rax, %xmm2 +; SSE41-NEXT: movd %xmm0, %rax +; SSE41-NEXT: movd %xmm1, %rcx +; SSE41-NEXT: sarq %cl, %rax +; SSE41-NEXT: movd %rax, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; SSE41-NEXT: retq +; +; AVX1-LABEL: splatvar_shift_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: vpextrq $1, %xmm1, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: vmovq %xmm1, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1 +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: vpextrq $1, %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: vmovq %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX2-NEXT: retq + %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer + %shift = ashr <2 x i64> %a, %splat + ret <2 x i64> %shift +} + +define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: splatvar_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] +; SSE2-NEXT: psrad %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; SSE41-NEXT: psrad %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer + %shift = ashr <4 x i32> %a, %splat + ret <4 x i32> %shift +} + +define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: splatvar_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: movzwl %ax, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: psraw %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; SSE41-NEXT: psraw %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer + %shift = ashr <8 x i16> %a, %splat + ret <8 x i16> %shift +} + +define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: splatvar_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm1[0,1,2,3,4,4,4,4] +; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] +; SSE2-NEXT: psllw $5, %xmm3 +; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm1, %xmm6 +; SSE2-NEXT: psraw $4, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm6, %xmm1 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm1, %xmm6 +; SSE2-NEXT: psraw $2, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm6, %xmm1 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm4 +; SSE2-NEXT: pandn %xmm1, %xmm4 +; SSE2-NEXT: psraw $1, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm4, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $4, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm3, %xmm3 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $2, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psraw $1, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pshufb %xmm0, %xmm1 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $4, %xmm4 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $2, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psraw $1, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm3 +; SSE41-NEXT: psrlw $8, %xmm3 +; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $4, %xmm2 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $2, %xmm2 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $1, %xmm2 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: psrlw $8, %xmm1 +; SSE41-NEXT: packuswb %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: splatvar_shift_v16i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX1-NEXT: vpsraw $4, %xmm3, %xmm4 +; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $2, %xmm3, %xmm4 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $1, %xmm3, %xmm4 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm3 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm3 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1 +; AVX2-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsraw $4, %xmm3, %xmm4 +; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX2-NEXT: vpsraw $2, %xmm3, %xmm4 +; AVX2-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX2-NEXT: vpsraw $1, %xmm3, %xmm4 +; AVX2-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2 +; AVX2-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX2-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpsraw $2, %xmm0, %xmm3 +; AVX2-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpsraw $1, %xmm0, %xmm3 +; AVX2-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer + %shift = ashr <16 x i8> %a, %splat + ret <16 x i8> %shift +} + +; +; Constant Shifts +; + +define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) { +; SSE2-LABEL: constant_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: sarq %rax +; SSE2-NEXT: movd %rax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: sarq $7, %rax +; SSE2-NEXT: movd %rax, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: sarq $7, %rax +; SSE41-NEXT: movd %rax, %xmm1 +; SSE41-NEXT: movd %xmm0, %rax +; SSE41-NEXT: sarq %rax +; SSE41-NEXT: movd %rax, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: retq +; +; AVX-LABEL: constant_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpextrq $1, %xmm0, %rax +; AVX-NEXT: sarq $7, %rax +; AVX-NEXT: vmovq %rax, %xmm1 +; AVX-NEXT: vmovq %xmm0, %rax +; AVX-NEXT: sarq %rax +; AVX-NEXT: vmovq %rax, %xmm0 +; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; AVX-NEXT: retq + %shift = ashr <2 x i64> %a, <i64 1, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) { +; SSE2-LABEL: constant_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3] +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: sarl $7, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3] +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: sarl $5, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: sarl $4, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: sarl $6, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pextrd $1, %xmm0, %eax +; SSE41-NEXT: sarl $5, %eax +; SSE41-NEXT: movd %xmm0, %ecx +; SSE41-NEXT: sarl $4, %ecx +; SSE41-NEXT: movd %ecx, %xmm1 +; SSE41-NEXT: pinsrd $1, %eax, %xmm1 +; SSE41-NEXT: pextrd $2, %xmm0, %eax +; SSE41-NEXT: sarl $6, %eax +; SSE41-NEXT: pinsrd $2, %eax, %xmm1 +; SSE41-NEXT: pextrd $3, %xmm0, %eax +; SSE41-NEXT: sarl $7, %eax +; SSE41-NEXT: pinsrd $3, %eax, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: sarl $5, %eax +; AVX1-NEXT: vmovd %xmm0, %ecx +; AVX1-NEXT: sarl $4, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm1 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: sarl $6, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: sarl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7> + ret <4 x i32> %shift +} + +define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) { +; SSE2-LABEL: constant_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psraw $4, %xmm1 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3] +; SSE2-NEXT: psraw $2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,0,65535,0,65535,0,65535,0] +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: pand %xmm0, %xmm1 +; SSE2-NEXT: psraw $1, %xmm2 +; SSE2-NEXT: pandn %xmm2, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $8, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,4112,8224,12336,16448,20560,24672,28784] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $4, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,8224,16448,24672,32896,41120,49344,57568] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $2, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,16448,32896,49344,256,16704,33152,49600] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psraw $1, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,32896,256,33152,512,33408,768,33664] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v8i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsraw $8, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,4112,8224,12336,16448,20560,24672,28784] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,8224,16448,24672,32896,41120,49344,57568] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,16448,32896,49344,256,16704,33152,49600] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,32896,256,33152,512,33408,768,33664] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v8i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero +; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> + ret <8 x i16> %shift +} + +define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) { +; SSE2-LABEL: constant_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE2-NEXT: psllw $5, %xmm3 +; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm1, %xmm6 +; SSE2-NEXT: psraw $4, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm6, %xmm1 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm6 +; SSE2-NEXT: pandn %xmm1, %xmm6 +; SSE2-NEXT: psraw $2, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm6, %xmm1 +; SSE2-NEXT: paddw %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm4, %xmm5 +; SSE2-NEXT: movdqa %xmm5, %xmm4 +; SSE2-NEXT: pandn %xmm1, %xmm4 +; SSE2-NEXT: psraw $1, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 +; SSE2-NEXT: por %xmm4, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $4, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm3, %xmm3 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm0, %xmm5 +; SSE2-NEXT: psraw $2, %xmm0 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: paddw %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtw %xmm3, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psraw $1, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE41-NEXT: psllw $5, %xmm3 +; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15] +; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psraw $4, %xmm4 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psraw $2, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psraw $1, %xmm4 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: psrlw $8, %xmm2 +; SSE41-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] +; SSE41-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: psraw $4, %xmm3 +; SSE41-NEXT: pblendvb %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: psraw $2, %xmm3 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: psraw $1, %xmm3 +; SSE41-NEXT: paddw %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm1 +; SSE41-NEXT: psrlw $8, %xmm1 +; SSE41-NEXT: packuswb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: constant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX-NEXT: vpsraw $4, %xmm3, %xmm4 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX-NEXT: vpsraw $2, %xmm3, %xmm4 +; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm3 +; AVX-NEXT: vpsraw $1, %xmm3, %xmm4 +; AVX-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm2, %xmm4, %xmm3, %xmm2 +; AVX-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsraw $2, %xmm0, %xmm3 +; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsraw $1, %xmm0, %xmm3 +; AVX-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <16 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) { +; SSE2-LABEL: splatconstant_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: sarq $7, %rax +; SSE2-NEXT: movd %rax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %rax +; SSE2-NEXT: sarq $7, %rax +; SSE2-NEXT: movd %rax, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatconstant_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: sarq $7, %rax +; SSE41-NEXT: movd %rax, %xmm1 +; SSE41-NEXT: movd %xmm0, %rax +; SSE41-NEXT: sarq $7, %rax +; SSE41-NEXT: movd %rax, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpextrq $1, %xmm0, %rax +; AVX-NEXT: sarq $7, %rax +; AVX-NEXT: vmovq %rax, %xmm1 +; AVX-NEXT: vmovq %xmm0, %rax +; AVX-NEXT: sarq $7, %rax +; AVX-NEXT: vmovq %rax, %xmm0 +; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; AVX-NEXT: retq + %shift = ashr <2 x i64> %a, <i64 7, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) { +; SSE-LABEL: splatconstant_shift_v4i32: +; SSE: # BB#0: +; SSE-NEXT: psrad $5, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpsrad $5, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = ashr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %shift +} + +define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) { +; SSE-LABEL: splatconstant_shift_v8i16: +; SSE: # BB#0: +; SSE-NEXT: psraw $3, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsraw $3, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <8 x i16> %shift +} + +define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) { +; SSE-LABEL: splatconstant_shift_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $3, %xmm0 +; SSE-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] +; SSE-NEXT: pxor %xmm1, %xmm0 +; SSE-NEXT: psubb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] +; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <16 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shift-ashr-256.ll b/test/CodeGen/X86/vector-shift-ashr-256.ll new file mode 100644 index 0000000000000..3fc377af56500 --- /dev/null +++ b/test/CodeGen/X86/vector-shift-ashr-256.ll @@ -0,0 +1,767 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: var_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpextrq $1, %xmm2, %rax +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpextrq $1, %xmm3, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm4 +; AVX1-NEXT: vmovq %xmm2, %rax +; AVX1-NEXT: vmovq %xmm3, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0] +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: vpextrq $1, %xmm1, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm3 +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: vmovq %xmm1, %rcx +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-NEXT: vpextrq $1, %xmm2, %rax +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3 +; AVX2-NEXT: vpextrq $1, %xmm3, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm4 +; AVX2-NEXT: vmovq %xmm2, %rax +; AVX2-NEXT: vmovq %xmm3, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0] +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: vpextrq $1, %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm3 +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: vmovq %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] +; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <4 x i64> %a, %b + ret <4 x i64> %shift +} + +define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: var_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpextrd $1, %xmm2, %eax +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpextrd $1, %xmm3, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vmovd %xmm2, %edx +; AVX1-NEXT: vmovd %xmm3, %ecx +; AVX1-NEXT: sarl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm4 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4 +; AVX1-NEXT: vpextrd $2, %xmm2, %eax +; AVX1-NEXT: vpextrd $2, %xmm3, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4 +; AVX1-NEXT: vpextrd $3, %xmm2, %eax +; AVX1-NEXT: vpextrd $3, %xmm3, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm4, %xmm2 +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: vpextrd $1, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vmovd %xmm0, %edx +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm3 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: vpextrd $2, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: vpextrd $3, %xmm1, %ecx +; AVX1-NEXT: sarl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <8 x i32> %a, %b + ret <8 x i32> %shift +} + +define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: var_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm2, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2 +; AVX1-NEXT: vpor %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vpsraw $8, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm2 +; AVX1-NEXT: vpsraw $4, %xmm2, %xmm4 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsraw $2, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsraw $1, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm3 +; AVX1-NEXT: vpsraw $8, %xmm0, %xmm4 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <16 x i16> %a, %b + ret <16 x i16> %shift +} + +define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: var_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpsllw $5, %xmm2, %xmm2 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm0[8],xmm4[8],xmm0[9],xmm4[9],xmm0[10],xmm4[10],xmm0[11],xmm4[11],xmm0[12],xmm4[12],xmm0[13],xmm4[13],xmm0[14],xmm4[14],xmm0[15],xmm4[15] +; AVX1-NEXT: vpsraw $4, %xmm5, %xmm6 +; AVX1-NEXT: vpblendvb %xmm3, %xmm6, %xmm5, %xmm5 +; AVX1-NEXT: vpsraw $2, %xmm5, %xmm6 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm6, %xmm5, %xmm5 +; AVX1-NEXT: vpsraw $1, %xmm5, %xmm6 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm6, %xmm5, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] +; AVX1-NEXT: vpsraw $4, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $2, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $1, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX1-NEXT: vpsraw $4, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm3, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $2, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $1, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm5, %xmm4, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm4 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm4 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm4 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31] +; AVX2-NEXT: vpsraw $4, %ymm3, %ymm4 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $2, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $1, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2 +; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23] +; AVX2-NEXT: vpsraw $4, %ymm0, %ymm3 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $2, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $1, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <32 x i8> %a, %b + ret <32 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: splatvar_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpextrq $1, %xmm2, %rdx +; AVX1-NEXT: vpextrq $1, %xmm1, %rax +; AVX1-NEXT: movb %al, %cl +; AVX1-NEXT: sarq %cl, %rdx +; AVX1-NEXT: vmovq %rdx, %xmm3 +; AVX1-NEXT: vmovq %xmm2, %rsi +; AVX1-NEXT: vmovq %xmm1, %rdx +; AVX1-NEXT: movb %dl, %cl +; AVX1-NEXT: sarq %cl, %rsi +; AVX1-NEXT: vmovq %rsi, %xmm1 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] +; AVX1-NEXT: vpextrq $1, %xmm0, %rsi +; AVX1-NEXT: movb %al, %cl +; AVX1-NEXT: sarq %cl, %rsi +; AVX1-NEXT: vmovq %rsi, %xmm2 +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: movb %dl, %cl +; AVX1-NEXT: sarq %cl, %rax +; AVX1-NEXT: vmovq %rax, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-NEXT: vpextrq $1, %xmm2, %rax +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3 +; AVX2-NEXT: vpextrq $1, %xmm3, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm4 +; AVX2-NEXT: vmovq %xmm2, %rax +; AVX2-NEXT: vmovq %xmm3, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0] +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: vpextrq $1, %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm3 +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: vmovq %xmm1, %rcx +; AVX2-NEXT: sarq %cl, %rax +; AVX2-NEXT: vmovq %rax, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] +; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer + %shift = ashr <4 x i64> %a, %splat + ret <4 x i64> %shift +} + +define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: splatvar_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrad %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer + %shift = ashr <8 x i32> %a, %splat + ret <8 x i32> %shift +} + +define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: splatvar_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vmovd %xmm1, %eax +; AVX1-NEXT: movzwl %ax, %eax +; AVX1-NEXT: vmovd %eax, %xmm1 +; AVX1-NEXT: vpsraw %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vmovd %xmm1, %eax +; AVX2-NEXT: movzwl %ax, %eax +; AVX2-NEXT: vmovd %eax, %xmm1 +; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer + %shift = ashr <16 x i16> %a, %splat + ret <16 x i16> %shift +} + +define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: splatvar_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15] +; AVX1-NEXT: vpsraw $4, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $2, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $1, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm6, %xmm6, %xmm9 +; AVX1-NEXT: vpblendvb %xmm9, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm8 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] +; AVX1-NEXT: vpsraw $4, %xmm3, %xmm5 +; AVX1-NEXT: vpblendvb %xmm1, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $2, %xmm3, %xmm5 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm4 +; AVX1-NEXT: vpblendvb %xmm4, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $1, %xmm3, %xmm5 +; AVX1-NEXT: vpaddw %xmm4, %xmm4, %xmm7 +; AVX1-NEXT: vpblendvb %xmm7, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 +; AVX1-NEXT: vpackuswb %xmm8, %xmm3, %xmm8 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX1-NEXT: vpsraw $4, %xmm5, %xmm3 +; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm5, %xmm2 +; AVX1-NEXT: vpsraw $2, %xmm2, %xmm3 +; AVX1-NEXT: vpblendvb %xmm6, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsraw $1, %xmm2, %xmm3 +; AVX1-NEXT: vpblendvb %xmm9, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm7, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm8, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31] +; AVX2-NEXT: vpsraw $4, %ymm3, %ymm4 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $2, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $1, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2 +; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23] +; AVX2-NEXT: vpsraw $4, %ymm0, %ymm3 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $2, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $1, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer + %shift = ashr <32 x i8> %a, %splat + ret <32 x i8> %shift +} + +; +; Constant Shifts +; + +define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: constant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrq $1, %xmm1, %rax +; AVX1-NEXT: sarq $62, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vmovq %xmm1, %rax +; AVX1-NEXT: sarq $31, %rax +; AVX1-NEXT: vmovq %rax, %xmm1 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: sarq $7, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: sarq %rax +; AVX1-NEXT: vmovq %rax, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpextrq $1, %xmm1, %rax +; AVX2-NEXT: sarq $62, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vmovq %xmm1, %rax +; AVX2-NEXT: sarq $31, %rax +; AVX2-NEXT: vmovq %rax, %xmm1 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: sarq $7, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: sarq %rax +; AVX2-NEXT: vmovq %rax, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> + ret <4 x i64> %shift +} + +define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: constant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrd $1, %xmm1, %eax +; AVX1-NEXT: sarl $9, %eax +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: sarl $8, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm1, %eax +; AVX1-NEXT: sarl $8, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm1, %eax +; AVX1-NEXT: sarl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1 +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: sarl $5, %eax +; AVX1-NEXT: vmovd %xmm0, %ecx +; AVX1-NEXT: sarl $4, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: sarl $6, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: sarl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> + ret <8 x i32> %shift +} + +define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: constant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsraw $8, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [32896,37008,41120,45232,49344,53456,57568,61680] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsraw $4, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [256,8480,16704,24928,33152,41376,49600,57824] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsraw $2, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [512,16960,33408,49856,768,17216,33664,50112] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsraw $1, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1024,33920,1280,34176,1536,34432,1792,34688] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsraw $8, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,4112,8224,12336,16448,20560,24672,28784] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,8224,16448,24672,32896,41120,49344,57568] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,16448,32896,49344,256,16704,33152,49600] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,32896,256,33152,512,33408,768,33664] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsravd %ymm3, %ymm4, %ymm3 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> + ret <16 x i16> %shift +} + +define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: constant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15] +; AVX1-NEXT: vpsraw $4, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $2, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsraw $1, %xmm4, %xmm5 +; AVX1-NEXT: vpaddw %xmm6, %xmm6, %xmm9 +; AVX1-NEXT: vpblendvb %xmm9, %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm8 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] +; AVX1-NEXT: vpsraw $4, %xmm3, %xmm5 +; AVX1-NEXT: vpblendvb %xmm1, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $2, %xmm3, %xmm5 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm4 +; AVX1-NEXT: vpblendvb %xmm4, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $1, %xmm3, %xmm5 +; AVX1-NEXT: vpaddw %xmm4, %xmm4, %xmm7 +; AVX1-NEXT: vpblendvb %xmm7, %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 +; AVX1-NEXT: vpackuswb %xmm8, %xmm3, %xmm8 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] +; AVX1-NEXT: vpsraw $4, %xmm5, %xmm3 +; AVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm5, %xmm2 +; AVX1-NEXT: vpsraw $2, %xmm2, %xmm3 +; AVX1-NEXT: vpblendvb %xmm6, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsraw $1, %xmm2, %xmm3 +; AVX1-NEXT: vpblendvb %xmm9, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; AVX1-NEXT: vpsraw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsraw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm7, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm8, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31] +; AVX2-NEXT: vpsraw $4, %ymm3, %ymm4 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $2, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3 +; AVX2-NEXT: vpsraw $1, %ymm3, %ymm4 +; AVX2-NEXT: vpaddw %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2 +; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23] +; AVX2-NEXT: vpsraw $4, %ymm0, %ymm3 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $2, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsraw $1, %ymm0, %ymm3 +; AVX2-NEXT: vpaddw %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <32 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: splatconstant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrq $1, %xmm1, %rax +; AVX1-NEXT: sarq $7, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vmovq %xmm1, %rax +; AVX1-NEXT: sarq $7, %rax +; AVX1-NEXT: vmovq %rax, %xmm1 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: sarq $7, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: sarq $7, %rax +; AVX1-NEXT: vmovq %rax, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpextrq $1, %xmm1, %rax +; AVX2-NEXT: sarq $7, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vmovq %xmm1, %rax +; AVX2-NEXT: sarq $7, %rax +; AVX2-NEXT: vmovq %rax, %xmm1 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: sarq $7, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: sarq $7, %rax +; AVX2-NEXT: vmovq %rax, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7> + ret <4 x i64> %shift +} + +define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: splatconstant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrad $5, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrad $5, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrad $5, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> + ret <8 x i32> %shift +} + +define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: splatconstant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsraw $3, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsraw $3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpsraw $3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <16 x i16> %shift +} + +define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: splatconstant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsrlw $3, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31] +; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] +; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] +; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsubb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <32 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shift-lshr-128.ll b/test/CodeGen/X86/vector-shift-lshr-128.ll new file mode 100644 index 0000000000000..f5a7e28383fe5 --- /dev/null +++ b/test/CodeGen/X86/vector-shift-lshr-128.ll @@ -0,0 +1,778 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: var_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psrlq %xmm3, %xmm2 +; SSE2-NEXT: psrlq %xmm1, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] +; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psrlq %xmm1, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; SSE41-NEXT: psrlq %xmm1, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7] +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = lshr <2 x i64> %a, %b + ret <2 x i64> %shift +} + +define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: var_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] +; SSE2-NEXT: movd %xmm2, %ecx +; SSE2-NEXT: shrl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,2,3] +; SSE2-NEXT: movd %xmm3, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3] +; SSE2-NEXT: movd %xmm3, %ecx +; SSE2-NEXT: shrl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm3 +; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: movd %xmm1, %ecx +; SSE2-NEXT: shrl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %ecx +; SSE2-NEXT: shrl %cl, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pextrd $1, %xmm0, %eax +; SSE41-NEXT: pextrd $1, %xmm1, %ecx +; SSE41-NEXT: shrl %cl, %eax +; SSE41-NEXT: movd %xmm0, %edx +; SSE41-NEXT: movd %xmm1, %ecx +; SSE41-NEXT: shrl %cl, %edx +; SSE41-NEXT: movd %edx, %xmm2 +; SSE41-NEXT: pinsrd $1, %eax, %xmm2 +; SSE41-NEXT: pextrd $2, %xmm0, %eax +; SSE41-NEXT: pextrd $2, %xmm1, %ecx +; SSE41-NEXT: shrl %cl, %eax +; SSE41-NEXT: pinsrd $2, %eax, %xmm2 +; SSE41-NEXT: pextrd $3, %xmm0, %eax +; SSE41-NEXT: pextrd $3, %xmm1, %ecx +; SSE41-NEXT: shrl %cl, %eax +; SSE41-NEXT: pinsrd $3, %eax, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: vpextrd $1, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vmovd %xmm0, %edx +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: vpextrd $2, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: vpextrd $3, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = lshr <4 x i32> %a, %b + ret <4 x i32> %shift +} + +define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: var_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $12, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psrlw $4, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psrlw $2, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: psraw $15, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: psllw $12, %xmm0 +; SSE41-NEXT: psllw $4, %xmm1 +; SSE41-NEXT: por %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psrlw $8, %xmm4 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psrlw $4, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psrlw $2, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psrlw $1, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v8i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %shift = lshr <8 x i16> %a, %b + ret <8 x i16> %shift +} + +define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: var_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $5, %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm1, %xmm1 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: pandn %xmm0, %xmm1 +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psrlw $4, %xmm3 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psrlw $2, %xmm3 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 +; SSE41-NEXT: paddb %xmm1, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psrlw $1, %xmm3 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 +; SSE41-NEXT: paddb %xmm1, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: var_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpsrlw $4, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $2, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = lshr <16 x i8> %a, %b + ret <16 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: splatvar_shift_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer + %shift = lshr <2 x i64> %a, %splat + ret <2 x i64> %shift +} + +define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: splatvar_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] +; SSE2-NEXT: psrld %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; SSE41-NEXT: psrld %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer + %shift = lshr <4 x i32> %a, %splat + ret <4 x i32> %shift +} + +define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: splatvar_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: movzwl %ax, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: psrlw %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; SSE41-NEXT: psrlw %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer + %shift = lshr <8 x i16> %a, %splat + ret <8 x i16> %shift +} + +define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: splatvar_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,4,4,4] +; SSE2-NEXT: psllw $5, %xmm2 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pshufb %xmm0, %xmm1 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: paddb %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psrlw $4, %xmm4 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm4 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psrlw $2, %xmm1 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psrlw $1, %xmm1 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE41-NEXT: paddb %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: splatvar_shift_v16i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1 +; AVX2-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX2-NEXT: vpsrlw $4, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpsrlw $2, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpsrlw $1, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer + %shift = lshr <16 x i8> %a, %splat + ret <16 x i8> %shift +} + +; +; Constant Shifts +; + +define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) { +; SSE2-LABEL: constant_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrlq $7, %xmm1 +; SSE2-NEXT: psrlq $1, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrlq $7, %xmm1 +; SSE41-NEXT: psrlq $1, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm1 +; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = lshr <2 x i64> %a, <i64 1, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) { +; SSE2-LABEL: constant_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3] +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: shrl $7, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3] +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: shrl $5, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: shrl $4, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: shrl $6, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pextrd $1, %xmm0, %eax +; SSE41-NEXT: shrl $5, %eax +; SSE41-NEXT: movd %xmm0, %ecx +; SSE41-NEXT: shrl $4, %ecx +; SSE41-NEXT: movd %ecx, %xmm1 +; SSE41-NEXT: pinsrd $1, %eax, %xmm1 +; SSE41-NEXT: pextrd $2, %xmm0, %eax +; SSE41-NEXT: shrl $6, %eax +; SSE41-NEXT: pinsrd $2, %eax, %xmm1 +; SSE41-NEXT: pextrd $3, %xmm0, %eax +; SSE41-NEXT: shrl $7, %eax +; SSE41-NEXT: pinsrd $3, %eax, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: shrl $5, %eax +; AVX1-NEXT: vmovd %xmm0, %ecx +; AVX1-NEXT: shrl $4, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm1 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: shrl $6, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: shrl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7> + ret <4 x i32> %shift +} + +define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) { +; SSE2-LABEL: constant_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrlw $4, %xmm1 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3] +; SSE2-NEXT: psrlw $2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,0,65535,0,65535,0,65535,0] +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: pand %xmm0, %xmm1 +; SSE2-NEXT: psrlw $1, %xmm2 +; SSE2-NEXT: pandn %xmm2, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $8, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,4112,8224,12336,16448,20560,24672,28784] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $4, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,8224,16448,24672,32896,41120,49344,57568] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $2, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,16448,32896,49344,256,16704,33152,49600] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $1, %xmm2 +; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,32896,256,33152,512,33408,768,33664] +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v8i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,4112,8224,12336,16448,20560,24672,28784] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,8224,16448,24672,32896,41120,49344,57568] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,16448,32896,49344,256,16704,33152,49600] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm2 # xmm2 = [0,32896,256,33152,512,33408,768,33664] +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v8i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero +; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> + ret <8 x i16> %shift +} + +define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) { +; SSE2-LABEL: constant_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE2-NEXT: psllw $5, %xmm2 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psrlw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE41-NEXT: psllw $5, %xmm0 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $4, %xmm2 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $2, %xmm2 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE41-NEXT: paddb %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psrlw $1, %xmm2 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE41-NEXT: paddb %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: constant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpsrlw $4, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $2, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <16 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) { +; SSE-LABEL: splatconstant_shift_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq $7, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq $7, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = lshr <2 x i64> %a, <i64 7, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) { +; SSE-LABEL: splatconstant_shift_v4i32: +; SSE: # BB#0: +; SSE-NEXT: psrld $5, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpsrld $5, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = lshr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %shift +} + +define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) { +; SSE-LABEL: splatconstant_shift_v8i16: +; SSE: # BB#0: +; SSE-NEXT: psrlw $3, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <8 x i16> %shift +} + +define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) { +; SSE-LABEL: splatconstant_shift_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $3, %xmm0 +; SSE-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $3, %xmm0 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm0 +; AVX-NEXT: retq + %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <16 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shift-lshr-256.ll b/test/CodeGen/X86/vector-shift-lshr-256.ll new file mode 100644 index 0000000000000..d200abd5f8755 --- /dev/null +++ b/test/CodeGen/X86/vector-shift-lshr-256.ll @@ -0,0 +1,548 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: var_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsrlq %xmm2, %xmm3, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] +; AVX1-NEXT: vpsrlq %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <4 x i64> %a, %b + ret <4 x i64> %shift +} + +define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: var_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpextrd $1, %xmm2, %eax +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpextrd $1, %xmm3, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vmovd %xmm2, %edx +; AVX1-NEXT: vmovd %xmm3, %ecx +; AVX1-NEXT: shrl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm4 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4 +; AVX1-NEXT: vpextrd $2, %xmm2, %eax +; AVX1-NEXT: vpextrd $2, %xmm3, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4 +; AVX1-NEXT: vpextrd $3, %xmm2, %eax +; AVX1-NEXT: vpextrd $3, %xmm3, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm4, %xmm2 +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: vpextrd $1, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vmovd %xmm0, %edx +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %edx +; AVX1-NEXT: vmovd %edx, %xmm3 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: vpextrd $2, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: vpextrd $3, %xmm1, %ecx +; AVX1-NEXT: shrl %cl, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <8 x i32> %a, %b + ret <8 x i32> %shift +} + +define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: var_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm2, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2 +; AVX1-NEXT: vpor %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm4 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm4 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <16 x i16> %a, %b + ret <16 x i16> %shift +} + +define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: var_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63] +; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX1-NEXT: vpand %xmm7, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm7, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <32 x i8> %a, %b + ret <32 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: splatvar_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrlq %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer + %shift = lshr <4 x i64> %a, %splat + ret <4 x i64> %shift +} + +define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: splatvar_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrld %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer + %shift = lshr <8 x i32> %a, %splat + ret <8 x i32> %shift +} + +define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: splatvar_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vmovd %xmm1, %eax +; AVX1-NEXT: movzwl %ax, %eax +; AVX1-NEXT: vmovd %eax, %xmm1 +; AVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vmovd %xmm1, %eax +; AVX2-NEXT: movzwl %ax, %eax +; AVX2-NEXT: vmovd %eax, %xmm1 +; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer + %shift = lshr <16 x i16> %a, %splat + ret <16 x i16> %shift +} + +define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: splatvar_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63] +; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX1-NEXT: vpand %xmm7, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm4 +; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm8, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm6, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpand %xmm7, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 +; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer + %shift = lshr <32 x i8> %a, %splat + ret <32 x i8> %shift +} + +; +; Constant Shifts +; + +define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: constant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsrlq $62, %xmm1, %xmm2 +; AVX1-NEXT: vpsrlq $31, %xmm1, %xmm1 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm2 +; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> + ret <4 x i64> %shift +} + +define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: constant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrd $1, %xmm1, %eax +; AVX1-NEXT: shrl $9, %eax +; AVX1-NEXT: vmovd %xmm1, %ecx +; AVX1-NEXT: shrl $8, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm1, %eax +; AVX1-NEXT: shrl $8, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm1, %eax +; AVX1-NEXT: shrl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1 +; AVX1-NEXT: vpextrd $1, %xmm0, %eax +; AVX1-NEXT: shrl $5, %eax +; AVX1-NEXT: vmovd %xmm0, %ecx +; AVX1-NEXT: shrl $4, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm2 +; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $2, %xmm0, %eax +; AVX1-NEXT: shrl $6, %eax +; AVX1-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX1-NEXT: vpextrd $3, %xmm0, %eax +; AVX1-NEXT: shrl $7, %eax +; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> + ret <8 x i32> %shift +} + +define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: constant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [32896,37008,41120,45232,49344,53456,57568,61680] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [256,8480,16704,24928,33152,41376,49600,57824] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [512,16960,33408,49856,768,17216,33664,50112] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1024,33920,1280,34176,1536,34432,1792,34688] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,4112,8224,12336,16448,20560,24672,28784] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,8224,16448,24672,32896,41120,49344,57568] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,16448,32896,49344,256,16704,33152,49600] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,32896,256,33152,512,33408,768,33664] +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> + ret <16 x i16> %shift +} + +define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: constant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm8, %xmm2, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX1-NEXT: vpsllw $5, %xmm4, %xmm4 +; AVX1-NEXT: vpblendvb %xmm4, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63] +; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX1-NEXT: vpand %xmm7, %xmm2, %xmm2 +; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 +; AVX1-NEXT: vpand %xmm8, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm4, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm2 +; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm6, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 +; AVX1-NEXT: vpand %xmm7, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <32 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: splatconstant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlq $7, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7> + ret <4 x i64> %shift +} + +define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: splatconstant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrld $5, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrld $5, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrld $5, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> + ret <8 x i32> %shift +} + +define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: splatconstant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <16 x i16> %shift +} + +define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: splatconstant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsrlw $3, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31] +; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrlw $3, %ymm0 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0 +; AVX2-NEXT: retq + %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <32 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shift-shl-128.ll b/test/CodeGen/X86/vector-shift-shl-128.ll new file mode 100644 index 0000000000000..3ac31ea636765 --- /dev/null +++ b/test/CodeGen/X86/vector-shift-shl-128.ll @@ -0,0 +1,639 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: var_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psllq %xmm3, %xmm2 +; SSE2-NEXT: psllq %xmm1, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] +; SSE2-NEXT: movapd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psllq %xmm1, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; SSE41-NEXT: psllq %xmm1, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7] +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = shl <2 x i64> %a, %b + ret <2 x i64> %shift +} + +define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: var_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: pslld $23, %xmm1 +; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1 +; SSE2-NEXT: cvttps2dq %xmm1, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pslld $23, %xmm1 +; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1 +; SSE41-NEXT: cvttps2dq %xmm1, %xmm1 +; SSE41-NEXT: pmulld %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpslld $23, %xmm1, %xmm1 +; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1 +; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1 +; AVX1-NEXT: vpmulld %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = shl <4 x i32> %a, %b + ret <4 x i32> %shift +} + +define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: var_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $12, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psllw $4, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: psllw $2, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: paddw %xmm1, %xmm1 +; SSE2-NEXT: psraw $15, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psllw $1, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: psllw $12, %xmm0 +; SSE41-NEXT: psllw $4, %xmm1 +; SSE41-NEXT: por %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psllw $8, %xmm4 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psllw $4, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psllw $2, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psllw $1, %xmm1 +; SSE41-NEXT: paddw %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: var_shift_v8i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpsllw $8, %xmm0, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %shift = shl <8 x i16> %a, %b + ret <8 x i16> %shift +} + +define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: var_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $5, %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm1, %xmm1 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: pandn %xmm0, %xmm1 +; SSE2-NEXT: paddb %xmm0, %xmm0 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: var_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psllw $4, %xmm3 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psllw $2, %xmm3 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm3 +; SSE41-NEXT: paddb %xmm1, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: paddb %xmm3, %xmm3 +; SSE41-NEXT: paddb %xmm1, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm3, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: var_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpsllw $4, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsllw $2, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <16 x i8> %a, %b + ret <16 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: splatvar_shift_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psllq %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer + %shift = shl <2 x i64> %a, %splat + ret <2 x i64> %shift +} + +define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: splatvar_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] +; SSE2-NEXT: pslld %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; SSE41-NEXT: pslld %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer + %shift = shl <4 x i32> %a, %splat + ret <4 x i32> %shift +} + +define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) { +; SSE2-LABEL: splatvar_shift_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: movd %xmm1, %eax +; SSE2-NEXT: movzwl %ax, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: psllw %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: pxor %xmm2, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; SSE41-NEXT: psllw %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: splatvar_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] +; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer + %shift = shl <8 x i16> %a, %splat + ret <8 x i16> %shift +} + +define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) { +; SSE2-LABEL: splatvar_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,4,4,4] +; SSE2-NEXT: psllw $5, %xmm2 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: paddb %xmm0, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: splatvar_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pshufb %xmm0, %xmm1 +; SSE41-NEXT: psllw $5, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm3 +; SSE41-NEXT: paddb %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psllw $4, %xmm4 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm4 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: pblendvb %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: psllw $2, %xmm1 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: paddb %xmm1, %xmm1 +; SSE41-NEXT: paddb %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, %xmm0 +; SSE41-NEXT: pblendvb %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: splatvar_shift_v16i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm1 +; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1 +; AVX2-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX2-NEXT: vpsllw $4, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpsllw $2, %xmm0, %xmm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX2-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm2 +; AVX2-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer + %shift = shl <16 x i8> %a, %splat + ret <16 x i8> %shift +} + +; +; Constant Shifts +; + +define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) { +; SSE2-LABEL: constant_shift_v2i64: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psllq $7, %xmm1 +; SSE2-NEXT: psllq $1, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v2i64: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psllq $7, %xmm1 +; SSE41-NEXT: psllq $1, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllq $7, %xmm0, %xmm1 +; AVX1-NEXT: vpsllq $1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = shl <2 x i64> %a, <i64 1, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) { +; SSE2-LABEL: constant_shift_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,32,64,128] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: constant_shift_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq + %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7> + ret <4 x i32> %shift +} + +define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) { +; SSE-LABEL: constant_shift_v8i16: +; SSE: # BB#0: +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: constant_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> + ret <8 x i16> %shift +} + +define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) { +; SSE2-LABEL: constant_shift_v16i8: +; SSE2: # BB#0: +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE2-NEXT: psllw $5, %xmm2 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $4, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: psllw $2, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: paddb %xmm0, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: constant_shift_v16i8: +; SSE41: # BB#0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; SSE41-NEXT: psllw $5, %xmm0 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psllw $4, %xmm2 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: psllw $2, %xmm2 +; SSE41-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE41-NEXT: paddb %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm2 +; SSE41-NEXT: paddb %xmm2, %xmm2 +; SSE41-NEXT: paddb %xmm0, %xmm0 +; SSE41-NEXT: pblendvb %xmm2, %xmm1 +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: constant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX-NEXT: vpsllw $4, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsllw $2, %xmm0, %xmm2 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm2 +; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <16 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) { +; SSE-LABEL: splatconstant_shift_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psllq $7, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsllq $7, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <2 x i64> %a, <i64 7, i64 7> + ret <2 x i64> %shift +} + +define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) { +; SSE-LABEL: splatconstant_shift_v4i32: +; SSE: # BB#0: +; SSE-NEXT: pslld $5, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpslld $5, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %shift +} + +define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) { +; SSE-LABEL: splatconstant_shift_v8i16: +; SSE: # BB#0: +; SSE-NEXT: psllw $3, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsllw $3, %xmm0, %xmm0 +; AVX-NEXT: retq + %shift = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <8 x i16> %shift +} + +define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) { +; SSE-LABEL: splatconstant_shift_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psllw $3, %xmm0 +; SSE-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: splatconstant_shift_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsllw $3, %xmm0 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm0 +; AVX-NEXT: retq + %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <16 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shift-shl-256.ll b/test/CodeGen/X86/vector-shift-shl-256.ll new file mode 100644 index 0000000000000..7c13c0ae4716d --- /dev/null +++ b/test/CodeGen/X86/vector-shift-shl-256.ll @@ -0,0 +1,459 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 + +; +; Variable Shifts +; + +define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: var_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] +; AVX1-NEXT: vpsllq %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <4 x i64> %a, %b + ret <4 x i64> %shift +} + +define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: var_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpslld $23, %xmm2, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] +; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vcvttps2dq %xmm2, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vpmulld %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpslld $23, %xmm1, %xmm1 +; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1 +; AVX1-NEXT: vpmulld %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <8 x i32> %a, %b + ret <8 x i32> %shift +} + +define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: var_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm2, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2 +; AVX1-NEXT: vpor %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vpsllw $8, %xmm4, %xmm5 +; AVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm4, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm4 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $2, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $1, %xmm2, %xmm4 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $12, %xmm1, %xmm3 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpor %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm3 +; AVX1-NEXT: vpsllw $8, %xmm0, %xmm4 +; AVX1-NEXT: vpblendvb %xmm1, %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddw %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] +; AVX2-NEXT: vpsllvd %ymm3, %ymm4, %ymm3 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,8,8,9,9,10,10,11,11] +; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <16 x i16> %a, %b + ret <16 x i16> %shift +} + +define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: var_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsllw $5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $2, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] +; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm3 +; AVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5 +; AVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: var_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <32 x i8> %a, %b + ret <32 x i8> %shift +} + +; +; Uniform Variable Shifts +; + +define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: splatvar_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsllq %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer + %shift = shl <4 x i64> %a, %splat + ret <4 x i64> %shift +} + +define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) { +; AVX1-LABEL: splatvar_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpslld %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer + %shift = shl <8 x i32> %a, %splat + ret <8 x i32> %shift +} + +define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) { +; AVX1-LABEL: splatvar_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vmovd %xmm1, %eax +; AVX1-NEXT: movzwl %ax, %eax +; AVX1-NEXT: vmovd %eax, %xmm1 +; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vmovd %xmm1, %eax +; AVX2-NEXT: movzwl %ax, %eax +; AVX2-NEXT: vmovd %eax, %xmm1 +; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer + %shift = shl <16 x i16> %a, %splat + ret <16 x i16> %shift +} + +define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) { +; AVX1-LABEL: splatvar_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpsllw $5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $2, %xmm2, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] +; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm3 +; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm7 +; AVX1-NEXT: vpblendvb %xmm7, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm3 +; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm1 +; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpblendvb %xmm6, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm1 +; AVX1-NEXT: vpblendvb %xmm7, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatvar_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 +; AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %splat = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer + %shift = shl <32 x i8> %a, %splat + ret <32 x i8> %shift +} + +; +; Constant Shifts +; + +define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: constant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsllq $62, %xmm1, %xmm2 +; AVX1-NEXT: vpsllq $31, %xmm1, %xmm1 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vpsllq $7, %xmm0, %xmm2 +; AVX1-NEXT: vpsllq $1, %xmm0, %xmm0 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> + ret <4 x i64> %shift +} + +define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: constant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> + ret <8 x i32> %shift +} + +define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: constant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> + ret <16 x i16> %shift +} + +define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: constant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsllw $4, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] +; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vmovdqa {{.*}}(%rip), %xmm4 # xmm4 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX1-NEXT: vpsllw $5, %xmm4, %xmm4 +; AVX1-NEXT: vpblendvb %xmm4, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $2, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] +; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm6 +; AVX1-NEXT: vpblendvb %xmm6, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm7 +; AVX1-NEXT: vpblendvb %xmm7, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $4, %xmm0, %xmm2 +; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm4, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsllw $2, %xmm0, %xmm2 +; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpblendvb %xmm6, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vpblendvb %xmm7, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: constant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0] +; AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 +; AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2 +; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> + ret <32 x i8> %shift +} + +; +; Uniform Constant Shifts +; + +define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) { +; AVX1-LABEL: splatconstant_shift_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllq $7, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsllq $7, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7> + ret <4 x i64> %shift +} + +define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) { +; AVX1-LABEL: splatconstant_shift_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpslld $5, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpslld $5, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpslld $5, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> + ret <8 x i32> %shift +} + +define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) { +; AVX1-LABEL: splatconstant_shift_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vpsllw $3, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpsllw $3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + ret <16 x i16> %shift +} + +define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) { +; AVX1-LABEL: splatconstant_shift_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsllw $3, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248] +; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsllw $3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splatconstant_shift_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 +; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 +; AVX2-NEXT: retq + %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + ret <32 x i8> %shift +} diff --git a/test/CodeGen/X86/vector-shuffle-128-v16.ll b/test/CodeGen/X86/vector-shuffle-128-v16.ll index 53d13c86657b5..124d6e8c8ba2a 100644 --- a/test/CodeGen/X86/vector-shuffle-128-v16.ll +++ b/test/CodeGen/X86/vector-shuffle-128-v16.ll @@ -653,28 +653,28 @@ define <16 x i8> @shuffle_v16i8_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz( define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(i8 %i) { ; SSE2-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSE2: # BB#0: -; SSE2-NEXT: shll $8, %edi -; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: shll $8, %edi +; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pinsrw $2, %edi, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSSE3: # BB#0: -; SSSE3-NEXT: shll $8, %edi -; SSSE3-NEXT: pxor %xmm0, %xmm0 +; SSSE3-NEXT: shll $8, %edi +; SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSSE3-NEXT: pinsrw $2, %edi, %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSE41: # BB#0: -; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pinsrb $5, %edi, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrb $5, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrb $5, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <16 x i8> undef, i8 %i, i32 0 %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> @@ -684,28 +684,28 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz( define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(i8 %i) { ; SSE2-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16: ; SSE2: # BB#0: -; SSE2-NEXT: shll $8, %edi -; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: shll $8, %edi +; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pinsrw $7, %edi, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16: ; SSSE3: # BB#0: -; SSSE3-NEXT: shll $8, %edi -; SSSE3-NEXT: pxor %xmm0, %xmm0 +; SSSE3-NEXT: shll $8, %edi +; SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSSE3-NEXT: pinsrw $7, %edi, %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16: ; SSE41: # BB#0: -; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pinsrb $15, %edi, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrb $15, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <16 x i8> undef, i8 %i, i32 0 %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16> @@ -716,27 +716,27 @@ define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz( ; SSE2-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSE2: # BB#0: ; SSE2-NEXT: movzbl %dil, %eax -; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pinsrw $1, %eax, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSSE3: # BB#0: ; SSSE3-NEXT: movzbl %dil, %eax -; SSSE3-NEXT: pxor %xmm0, %xmm0 +; SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSSE3-NEXT: pinsrw $1, %eax, %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; SSE41: # BB#0: -; SSE41-NEXT: pxor %xmm0, %xmm0 +; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pinsrb $2, %edi, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrb $2, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <16 x i8> undef, i8 %i, i32 3 %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 19, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -1341,12 +1341,12 @@ define <16 x i8> @shuffle_v16i8_uu_02_03_zz_uu_06_07_zz_uu_10_11_zz_uu_14_15_zz( define <16 x i8> @shuffle_v16i8_bitcast_unpack(<16 x i8> %a, <16 x i8> %b) { ; SSE-LABEL: shuffle_v16i8_bitcast_unpack: ; SSE: # BB#0: -; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE-NEXT: retq ; ; AVX-LABEL: shuffle_v16i8_bitcast_unpack: ; AVX: # BB#0: -; AVX-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX-NEXT: retq %shuffle8 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 7, i32 23, i32 6, i32 22, i32 5, i32 21, i32 4, i32 20, i32 3, i32 19, i32 2, i32 18, i32 1, i32 17, i32 0, i32 16> %bitcast32 = bitcast <16 x i8> %shuffle8 to <4 x float> diff --git a/test/CodeGen/X86/vector-shuffle-128-v8.ll b/test/CodeGen/X86/vector-shuffle-128-v8.ll index 4007f0b2b13bf..6a29d33d6c5e7 100644 --- a/test/CodeGen/X86/vector-shuffle-128-v8.ll +++ b/test/CodeGen/X86/vector-shuffle-128-v8.ll @@ -1384,14 +1384,14 @@ define <8 x i16> @shuffle_v8i16_8zzzzzzz(i16 %i) { define <8 x i16> @shuffle_v8i16_z8zzzzzz(i16 %i) { ; SSE-LABEL: shuffle_v8i16_z8zzzzzz: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm0, %xmm0 ; SSE-NEXT: pinsrw $1, %edi, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: shuffle_v8i16_z8zzzzzz: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrw $1, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <8 x i16> undef, i16 %i, i32 0 %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 2, i32 8, i32 3, i32 7, i32 6, i32 5, i32 4, i32 3> @@ -1401,14 +1401,14 @@ define <8 x i16> @shuffle_v8i16_z8zzzzzz(i16 %i) { define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) { ; SSE-LABEL: shuffle_v8i16_zzzzz8zz: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm0, %xmm0 ; SSE-NEXT: pinsrw $5, %edi, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: shuffle_v8i16_zzzzz8zz: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrw $5, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <8 x i16> undef, i16 %i, i32 0 %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 0, i32 0> @@ -1418,14 +1418,14 @@ define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) { define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) { ; SSE-LABEL: shuffle_v8i16_zuuzuuz8: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm0, %xmm0 ; SSE-NEXT: pinsrw $7, %edi, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: shuffle_v8i16_zuuzuuz8: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrw $7, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <8 x i16> undef, i16 %i, i32 0 %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 8> @@ -1435,14 +1435,14 @@ define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) { define <8 x i16> @shuffle_v8i16_zzBzzzzz(i16 %i) { ; SSE-LABEL: shuffle_v8i16_zzBzzzzz: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm0, %xmm0 ; SSE-NEXT: pinsrw $2, %edi, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: shuffle_v8i16_zzBzzzzz: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm0, %xmm0 -; AVX-NEXT: vpinsrw $2, %edi, %xmm0 +; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0 ; AVX-NEXT: retq %a = insertelement <8 x i16> undef, i16 %i, i32 3 %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 11, i32 3, i32 4, i32 5, i32 6, i32 7> diff --git a/test/CodeGen/X86/vector-shuffle-256-v4.ll b/test/CodeGen/X86/vector-shuffle-256-v4.ll index 944ec4b8d3ac7..62bf288a870d1 100644 --- a/test/CodeGen/X86/vector-shuffle-256-v4.ll +++ b/test/CodeGen/X86/vector-shuffle-256-v4.ll @@ -810,30 +810,20 @@ define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) { } define <4 x i64> @insert_reg_and_zero_v4i64(i64 %a) { -; AVX1-LABEL: insert_reg_and_zero_v4i64: -; AVX1: # BB#0: -; AVX1-NEXT: vmovq %rdi, %xmm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: insert_reg_and_zero_v4i64: -; AVX2: # BB#0: -; AVX2-NEXT: vmovq %rdi, %xmm0 -; AVX2-NEXT: retq +; ALL-LABEL: insert_reg_and_zero_v4i64: +; ALL: # BB#0: +; ALL-NEXT: vmovq %rdi, %xmm0 +; ALL-NEXT: retq %v = insertelement <4 x i64> undef, i64 %a, i64 0 %shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7> ret <4 x i64> %shuffle } define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) { -; AVX1-LABEL: insert_mem_and_zero_v4i64: -; AVX1: # BB#0: -; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero -; AVX1-NEXT: retq -; -; AVX2-LABEL: insert_mem_and_zero_v4i64: -; AVX2: # BB#0: -; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero -; AVX2-NEXT: retq +; ALL-LABEL: insert_mem_and_zero_v4i64: +; ALL: # BB#0: +; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; ALL-NEXT: retq %a = load i64, i64* %ptr %v = insertelement <4 x i64> undef, i64 %a, i64 0 %shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7> @@ -874,15 +864,10 @@ define <4 x double> @splat_mem_v4f64(double* %ptr) { } define <4 x i64> @splat_mem_v4i64(i64* %ptr) { -; AVX1-LABEL: splat_mem_v4i64: -; AVX1: # BB#0: -; AVX1-NEXT: vbroadcastsd (%rdi), %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: splat_mem_v4i64: -; AVX2: # BB#0: -; AVX2-NEXT: vbroadcastsd (%rdi), %ymm0 -; AVX2-NEXT: retq +; ALL-LABEL: splat_mem_v4i64: +; ALL: # BB#0: +; ALL-NEXT: vbroadcastsd (%rdi), %ymm0 +; ALL-NEXT: retq %a = load i64, i64* %ptr %v = insertelement <4 x i64> undef, i64 %a, i64 0 %shuffle = shufflevector <4 x i64> %v, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0> @@ -915,6 +900,60 @@ define <4 x double> @splat_v4f64(<2 x double> %r) { ret <4 x double> %1 } +define <4 x i64> @splat_mem_v4i64_from_v2i64(<2 x i64>* %ptr) { +; AVX1-LABEL: splat_mem_v4i64_from_v2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splat_mem_v4i64_from_v2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vbroadcastsd (%rdi), %ymm0 +; AVX2-NEXT: retq + %v = load <2 x i64>, <2 x i64>* %ptr + %shuffle = shufflevector <2 x i64> %v, <2 x i64> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x i64> %shuffle +} + +define <4 x double> @splat_mem_v4f64_from_v2f64(<2 x double>* %ptr) { +; AVX1-LABEL: splat_mem_v4f64_from_v2f64: +; AVX1: # BB#0: +; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: splat_mem_v4f64_from_v2f64: +; AVX2: # BB#0: +; AVX2-NEXT: vbroadcastsd (%rdi), %ymm0 +; AVX2-NEXT: retq + %v = load <2 x double>, <2 x double>* %ptr + %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x double> %shuffle +} + +define <4 x i64> @splat128_mem_v4i64_from_v2i64(<2 x i64>* %ptr) { +; ALL-LABEL: splat128_mem_v4i64_from_v2i64: +; ALL: # BB#0: +; ALL-NEXT: vmovaps (%rdi), %xmm0 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: retq + %v = load <2 x i64>, <2 x i64>* %ptr + %shuffle = shufflevector <2 x i64> %v, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + ret <4 x i64> %shuffle +} + +define <4 x double> @splat128_mem_v4f64_from_v2f64(<2 x double>* %ptr) { +; ALL-LABEL: splat128_mem_v4f64_from_v2f64: +; ALL: # BB#0: +; ALL-NEXT: vmovaps (%rdi), %xmm0 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: retq + %v = load <2 x double>, <2 x double>* %ptr + %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + ret <4 x double> %shuffle +} + define <4 x double> @bitcast_v4f64_0426(<4 x double> %a, <4 x double> %b) { ; AVX1-LABEL: bitcast_v4f64_0426: ; AVX1: # BB#0: @@ -923,7 +962,7 @@ define <4 x double> @bitcast_v4f64_0426(<4 x double> %a, <4 x double> %b) { ; ; AVX2-LABEL: bitcast_v4f64_0426: ; AVX2: # BB#0: -; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] +; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; AVX2-NEXT: retq %shuffle64 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2> %bitcast32 = bitcast <4 x double> %shuffle64 to <8 x float> diff --git a/test/CodeGen/X86/vector-shuffle-256-v8.ll b/test/CodeGen/X86/vector-shuffle-256-v8.ll index bb07077b5559c..bc72e0a661777 100644 --- a/test/CodeGen/X86/vector-shuffle-256-v8.ll +++ b/test/CodeGen/X86/vector-shuffle-256-v8.ll @@ -2088,15 +2088,10 @@ entry: } define <8 x i32> @insert_mem_and_zero_v8i32(i32* %ptr) { -; AVX1-LABEL: insert_mem_and_zero_v8i32: -; AVX1: # BB#0: -; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero -; AVX1-NEXT: retq -; -; AVX2-LABEL: insert_mem_and_zero_v8i32: -; AVX2: # BB#0: -; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero -; AVX2-NEXT: retq +; ALL-LABEL: insert_mem_and_zero_v8i32: +; ALL: # BB#0: +; ALL-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; ALL-NEXT: retq %a = load i32, i32* %ptr %v = insertelement <8 x i32> undef, i32 %a, i32 0 %shuffle = shufflevector <8 x i32> %v, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> diff --git a/test/CodeGen/X86/vector-shuffle-512-v8.ll b/test/CodeGen/X86/vector-shuffle-512-v8.ll index 2c6c8a3e7ade3..62d4af7809b6b 100644 --- a/test/CodeGen/X86/vector-shuffle-512-v8.ll +++ b/test/CodeGen/X86/vector-shuffle-512-v8.ll @@ -15,8 +15,9 @@ define <8 x double> @shuffle_v8f64_00000000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00000010(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00000010: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm1 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0> ret <8 x double> %shuffle @@ -25,8 +26,9 @@ define <8 x double> @shuffle_v8f64_00000010(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00000200(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00000200: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm1 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0> ret <8 x double> %shuffle @@ -35,8 +37,9 @@ define <8 x double> @shuffle_v8f64_00000200(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00003000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00003000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm1 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0> ret <8 x double> %shuffle @@ -45,8 +48,11 @@ define <8 x double> @shuffle_v8f64_00003000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00040000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00040000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vbroadcastsd %xmm1, %ymm1 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vblendpd {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0> ret <8 x double> %shuffle @@ -55,8 +61,11 @@ define <8 x double> @shuffle_v8f64_00040000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00500000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00500000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,1,0] +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x double> %shuffle @@ -65,8 +74,11 @@ define <8 x double> @shuffle_v8f64_00500000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_06000000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2],ymm0[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,0,0] +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x double> %shuffle @@ -75,11 +87,11 @@ define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_70000000: ; ALL: # BB#0: -; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1 -; ALL-NEXT: movl $7, %eax -; ALL-NEXT: vpinsrq $0, %rax, %xmm1, %xmm2 -; ALL-NEXT: vinserti32x4 $0, %xmm2, %zmm1, %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[3,0,0,0] +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x double> %shuffle @@ -88,7 +100,10 @@ define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_01014545(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_01014545: ; ALL: # BB#0: -; ALL-NEXT: vshuff64x2 $160, %zmm0, %zmm0, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5> ret <8 x double> %shuffle @@ -97,8 +112,9 @@ define <8 x double> @shuffle_v8f64_01014545(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00112233(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00112233: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,0,1,1] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,2,3,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3> ret <8 x double> %shuffle @@ -107,8 +123,9 @@ define <8 x double> @shuffle_v8f64_00112233(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00001111(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00001111: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm1 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,1,1,1] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1> ret <8 x double> %shuffle @@ -117,7 +134,11 @@ define <8 x double> @shuffle_v8f64_00001111(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_81a3c5e7(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_81a3c5e7: ; ALL: # BB#0: -; ALL-NEXT: vshufpd $170, %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> ret <8 x double> %shuffle @@ -126,9 +147,10 @@ define <8 x double> @shuffle_v8f64_81a3c5e7(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_08080808(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_08080808: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vbroadcastsd %xmm1, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8> ret <8 x double> %shuffle @@ -137,9 +159,15 @@ define <8 x double> @shuffle_v8f64_08080808(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_08084c4c(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_08084c4c: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vbroadcastsd %xmm3, %ymm3 +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm2[0],ymm3[1],ymm2[2],ymm3[3] +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vbroadcastsd %xmm1, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12> ret <8 x double> %shuffle @@ -148,9 +176,13 @@ define <8 x double> @shuffle_v8f64_08084c4c(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_8823cc67(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_8823cc67: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vbroadcastsd %xmm3, %ymm3 +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3] +; ALL-NEXT: vbroadcastsd %xmm1, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 8, i32 8, i32 2, i32 3, i32 12, i32 12, i32 6, i32 7> ret <8 x double> %shuffle @@ -159,9 +191,13 @@ define <8 x double> @shuffle_v8f64_8823cc67(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_9832dc76(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_9832dc76: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm1[0,1],ymm0[2,3] +; ALL-NEXT: vpermilpd {{.*#+}} ymm2 = ymm2[1,0,3,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm1 +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6> ret <8 x double> %shuffle @@ -170,9 +206,13 @@ define <8 x double> @shuffle_v8f64_9832dc76(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_9810dc54(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_9810dc54: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm2 +; ALL-NEXT: vpermilpd {{.*#+}} ymm2 = ymm2[1,0,3,2] +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm1 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 8, i32 1, i32 0, i32 13, i32 12, i32 5, i32 4> ret <8 x double> %shuffle @@ -181,9 +221,15 @@ define <8 x double> @shuffle_v8f64_9810dc54(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_08194c5d(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_08194c5d: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,0,2,1] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm3 +; ALL-NEXT: vpermpd {{.*#+}} ymm3 = ymm3[0,1,1,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13> ret <8 x double> %shuffle @@ -192,9 +238,15 @@ define <8 x double> @shuffle_v8f64_08194c5d(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_2a3b6e7f(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_2a3b6e7f: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,2,2,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm3 +; ALL-NEXT: vpermpd {{.*#+}} ymm3 = ymm3[2,1,3,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,2,3] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,1,3,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15> ret <8 x double> %shuffle @@ -203,9 +255,13 @@ define <8 x double> @shuffle_v8f64_2a3b6e7f(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_08192a3b(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_08192a3b: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm2 = ymm1[0,2,2,3] +; ALL-NEXT: vpermpd {{.*#+}} ymm3 = ymm0[2,1,3,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,0,2,1] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> ret <8 x double> %shuffle @@ -214,9 +270,11 @@ define <8 x double> @shuffle_v8f64_08192a3b(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_08991abb(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_08991abb: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm2 = ymm1[0,0,1,1] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm0[0],ymm2[1,2,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,3,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11> ret <8 x double> %shuffle @@ -225,9 +283,12 @@ define <8 x double> @shuffle_v8f64_08991abb(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_091b2d3f(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_091b2d3f: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermpd {{.*#+}} ymm3 = ymm0[2,1,3,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1],ymm3[2],ymm2[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15> ret <8 x double> %shuffle @@ -236,9 +297,11 @@ define <8 x double> @shuffle_v8f64_091b2d3f(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_09ab1def(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_09ab1def: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermilpd {{.*#+}} ymm3 = ymm0[1,0,2,2] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm3[0],ymm2[1,2,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15> ret <8 x double> %shuffle @@ -247,7 +310,10 @@ define <8 x double> @shuffle_v8f64_09ab1def(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00014445(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00014445: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $64, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,0,0,1] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,0,1] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 4, i32 4, i32 4, i32 5> ret <8 x double> %shuffle @@ -256,7 +322,10 @@ define <8 x double> @shuffle_v8f64_00014445(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00204464(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00204464: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $32, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,0,2,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,2,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 4, i32 6, i32 4> ret <8 x double> %shuffle @@ -265,7 +334,10 @@ define <8 x double> @shuffle_v8f64_00204464(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_03004744(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_03004744: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $12, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,3,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 7, i32 4, i32 4> ret <8 x double> %shuffle @@ -274,7 +346,10 @@ define <8 x double> @shuffle_v8f64_03004744(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10005444(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10005444: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $1, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[1,0,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,0,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4> ret <8 x double> %shuffle @@ -283,7 +358,10 @@ define <8 x double> @shuffle_v8f64_10005444(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_22006644(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_22006644: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $10, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[2,2,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,2,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 6, i32 4, i32 4> ret <8 x double> %shuffle @@ -292,7 +370,10 @@ define <8 x double> @shuffle_v8f64_22006644(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_33307774(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_33307774: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $63, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[3,3,3,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,3,3,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 7, i32 7, i32 4> ret <8 x double> %shuffle @@ -301,7 +382,10 @@ define <8 x double> @shuffle_v8f64_33307774(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_32107654(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_32107654: ; ALL: # BB#0: -; ALL-NEXT: vpermpd $27, %zmm0, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[3,2,1,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,2,1,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x double> %shuffle @@ -310,7 +394,10 @@ define <8 x double> @shuffle_v8f64_32107654(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00234467(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00234467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $136, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[0,0,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7> ret <8 x double> %shuffle @@ -319,7 +406,10 @@ define <8 x double> @shuffle_v8f64_00234467(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00224466(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00224466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $0, %zmm0, %zmm0 +; ALL-NEXT: vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> ret <8 x double> %shuffle @@ -328,7 +418,10 @@ define <8 x double> @shuffle_v8f64_00224466(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10325476(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10325476: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $85, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x double> %shuffle @@ -337,7 +430,10 @@ define <8 x double> @shuffle_v8f64_10325476(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_11335577(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_11335577: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $255, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> ret <8 x double> %shuffle @@ -346,7 +442,10 @@ define <8 x double> @shuffle_v8f64_11335577(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10235467(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10235467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $153, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,0,2,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7> ret <8 x double> %shuffle @@ -355,7 +454,10 @@ define <8 x double> @shuffle_v8f64_10235467(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10225466(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10225466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $17, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,0,2,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 2, i32 5, i32 4, i32 6, i32 6> ret <8 x double> %shuffle @@ -364,8 +466,10 @@ define <8 x double> @shuffle_v8f64_10225466(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00015444(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00015444: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,0,0,1] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,0,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4> ret <8 x double> %shuffle @@ -374,8 +478,10 @@ define <8 x double> @shuffle_v8f64_00015444(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00204644(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00204644: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,0,2,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4> ret <8 x double> %shuffle @@ -384,8 +490,10 @@ define <8 x double> @shuffle_v8f64_00204644(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_03004474(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_03004474: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[0,3,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,3,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4> ret <8 x double> %shuffle @@ -394,8 +502,10 @@ define <8 x double> @shuffle_v8f64_03004474(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10004444(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10004444: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[1,0,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> ret <8 x double> %shuffle @@ -404,8 +514,10 @@ define <8 x double> @shuffle_v8f64_10004444(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_22006446(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_22006446: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[2,2,0,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,0,0,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6> ret <8 x double> %shuffle @@ -414,8 +526,10 @@ define <8 x double> @shuffle_v8f64_22006446(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_33307474(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_33307474: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[3,3,3,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,3,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4> ret <8 x double> %shuffle @@ -424,8 +538,9 @@ define <8 x double> @shuffle_v8f64_33307474(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_32104567(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_32104567: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[3,2,1,0] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7> ret <8 x double> %shuffle @@ -434,8 +549,10 @@ define <8 x double> @shuffle_v8f64_32104567(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00236744(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00236744: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[0,0,2,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4> ret <8 x double> %shuffle @@ -444,8 +561,10 @@ define <8 x double> @shuffle_v8f64_00236744(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00226644(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00226644: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,2,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4> ret <8 x double> %shuffle @@ -454,7 +573,9 @@ define <8 x double> @shuffle_v8f64_00226644(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_10324567(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_10324567: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $165, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7> ret <8 x double> %shuffle @@ -463,7 +584,9 @@ define <8 x double> @shuffle_v8f64_10324567(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_11334567(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_11334567: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $175, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x double> %shuffle @@ -472,7 +595,9 @@ define <8 x double> @shuffle_v8f64_11334567(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_01235467(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_01235467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $154, %zmm0, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7> ret <8 x double> %shuffle @@ -481,7 +606,9 @@ define <8 x double> @shuffle_v8f64_01235467(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_01235466(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_01235466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $26, %zmm0, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6> ret <8 x double> %shuffle @@ -490,8 +617,10 @@ define <8 x double> @shuffle_v8f64_01235466(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_002u6u44(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_002u6u44: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vmovddup {{.*#+}} ymm1 = ymm0[0,0,2,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,1,0,0] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 4, i32 4> ret <8 x double> %shuffle @@ -500,8 +629,10 @@ define <8 x double> @shuffle_v8f64_002u6u44(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_00uu66uu(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_00uu66uu: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vbroadcastsd %xmm0, %ymm1 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,2,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 6, i32 6, i32 undef, i32 undef> ret <8 x double> %shuffle @@ -510,7 +641,9 @@ define <8 x double> @shuffle_v8f64_00uu66uu(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_103245uu(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_103245uu: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $37, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,0,3,2] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef> ret <8 x double> %shuffle @@ -519,7 +652,9 @@ define <8 x double> @shuffle_v8f64_103245uu(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_1133uu67(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_1133uu67: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $143, %zmm0, %zmm0 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm0[1,1,3,3] +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7> ret <8 x double> %shuffle @@ -528,7 +663,9 @@ define <8 x double> @shuffle_v8f64_1133uu67(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_0uu354uu(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_0uu354uu: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $24, %zmm0, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpermilpd {{.*#+}} ymm1 = ymm1[1,0,2,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 5, i32 4, i32 undef, i32 undef> ret <8 x double> %shuffle @@ -537,7 +674,9 @@ define <8 x double> @shuffle_v8f64_0uu354uu(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_uuu3uu66(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_uuu3uu66: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $8, %zmm0, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vmovddup {{.*#+}} ymm1 = ymm1[0,0,2,2] +; ALL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 6> ret <8 x double> %shuffle @@ -546,9 +685,16 @@ define <8 x double> @shuffle_v8f64_uuu3uu66(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_c348cda0: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm2[0,1] +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vbroadcastsd %xmm1, %ymm4 +; ALL-NEXT: vblendpd {{.*#+}} ymm4 = ymm3[0,1,2],ymm4[3] +; ALL-NEXT: vblendpd {{.*#+}} ymm2 = ymm4[0],ymm2[1,2],ymm4[3] +; ALL-NEXT: vblendpd {{.*#+}} ymm1 = ymm3[0,1],ymm1[2],ymm3[3] +; ALL-NEXT: vbroadcastsd %xmm0, %ymm0 +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3] +; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 12, i32 3, i32 4, i32 8, i32 12, i32 13, i32 10, i32 0> ret <8 x double> %shuffle @@ -557,9 +703,17 @@ define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) { define <8 x double> @shuffle_v8f64_f511235a(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_f511235a: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2pd %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vblendpd {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2,3] +; ALL-NEXT: vpermpd {{.*#+}} ymm3 = ymm3[2,3,1,3] +; ALL-NEXT: vmovddup {{.*#+}} ymm4 = ymm1[0,0,2,2] +; ALL-NEXT: vblendpd {{.*#+}} ymm3 = ymm3[0,1,2],ymm4[3] +; ALL-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,1] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2,3] +; ALL-NEXT: vextractf64x4 $1, %zmm1, %ymm1 +; ALL-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[3,1,2,3] +; ALL-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] +; ALL-NEXT: vinsertf64x4 $1, %ymm3, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 15, i32 5, i32 1, i32 1, i32 2, i32 3, i32 5, i32 10> ret <8 x double> %shuffle @@ -577,8 +731,9 @@ define <8 x i64> @shuffle_v8i64_00000000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00000010(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00000010: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,1,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0> ret <8 x i64> %shuffle @@ -587,8 +742,9 @@ define <8 x i64> @shuffle_v8i64_00000010(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00000200(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00000200: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0> ret <8 x i64> %shuffle @@ -597,8 +753,9 @@ define <8 x i64> @shuffle_v8i64_00000200(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00003000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00003000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,0,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0> ret <8 x i64> %shuffle @@ -607,8 +764,11 @@ define <8 x i64> @shuffle_v8i64_00003000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00040000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00040000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpbroadcastq %xmm1, %ymm1 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm0 +; ALL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0> ret <8 x i64> %shuffle @@ -617,8 +777,11 @@ define <8 x i64> @shuffle_v8i64_00040000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00500000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00500000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,1,0] +; ALL-NEXT: vpbroadcastq %xmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x i64> %shuffle @@ -627,8 +790,11 @@ define <8 x i64> @shuffle_v8i64_00500000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_06000000: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,0,0] +; ALL-NEXT: vpbroadcastq %xmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x i64> %shuffle @@ -637,11 +803,11 @@ define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_70000000: ; ALL: # BB#0: -; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1 -; ALL-NEXT: movl $7, %eax -; ALL-NEXT: vpinsrq $0, %rax, %xmm1, %xmm2 -; ALL-NEXT: vinserti32x4 $0, %xmm2, %zmm1, %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[3,0,0,0] +; ALL-NEXT: vpbroadcastq %xmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> ret <8 x i64> %shuffle @@ -650,7 +816,10 @@ define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_01014545(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_01014545: ; ALL: # BB#0: -; ALL-NEXT: vshufi64x2 $160, %zmm0, %zmm0, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1 +; ALL-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5> ret <8 x i64> %shuffle @@ -659,8 +828,9 @@ define <8 x i64> @shuffle_v8i64_01014545(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00112233(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00112233: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,1,1] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,3,3] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3> ret <8 x i64> %shuffle @@ -669,8 +839,9 @@ define <8 x i64> @shuffle_v8i64_00112233(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00001111(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00001111: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,1,1,1] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1> ret <8 x i64> %shuffle @@ -679,7 +850,11 @@ define <8 x i64> @shuffle_v8i64_00001111(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_81a3c5e7(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_81a3c5e7: ; ALL: # BB#0: -; ALL-NEXT: vshufpd $170, %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 5, i32 14, i32 7> ret <8 x i64> %shuffle @@ -688,9 +863,10 @@ define <8 x i64> @shuffle_v8i64_81a3c5e7(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_08080808(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_08080808: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vpbroadcastq %xmm1, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8> ret <8 x i64> %shuffle @@ -699,9 +875,15 @@ define <8 x i64> @shuffle_v8i64_08080808(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_08084c4c(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_08084c4c: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vinserti128 $1, %xmm2, %ymm2, %ymm2 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vpbroadcastq %xmm3, %ymm3 +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1],ymm3[2,3],ymm2[4,5],ymm3[6,7] +; ALL-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 +; ALL-NEXT: vpbroadcastq %xmm1, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12> ret <8 x i64> %shuffle @@ -710,9 +892,13 @@ define <8 x i64> @shuffle_v8i64_08084c4c(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_8823cc67(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_8823cc67: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm2 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm3 +; ALL-NEXT: vpbroadcastq %xmm3, %ymm3 +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] +; ALL-NEXT: vpbroadcastq %xmm1, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 8, i32 8, i32 2, i32 3, i32 12, i32 12, i32 6, i32 7> ret <8 x i64> %shuffle @@ -721,9 +907,13 @@ define <8 x i64> @shuffle_v8i64_8823cc67(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_9832dc76(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_9832dc76: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; ALL-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,3,0,1,6,7,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm1 +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; ALL-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6> ret <8 x i64> %shuffle @@ -732,9 +922,13 @@ define <8 x i64> @shuffle_v8i64_9832dc76(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_9810dc54(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_9810dc54: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm2 +; ALL-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,3,0,1,6,7,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm1 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 9, i32 8, i32 1, i32 0, i32 13, i32 12, i32 5, i32 4> ret <8 x i64> %shuffle @@ -743,9 +937,15 @@ define <8 x i64> @shuffle_v8i64_9810dc54(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_08194c5d(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_08194c5d: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,0,2,1] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm3 +; ALL-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,1,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13> ret <8 x i64> %shuffle @@ -754,9 +954,15 @@ define <8 x i64> @shuffle_v8i64_08194c5d(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_2a3b6e7f(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_2a3b6e7f: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm3 +; ALL-NEXT: vpermq {{.*#+}} ymm3 = ymm3[2,1,3,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,3,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15> ret <8 x i64> %shuffle @@ -765,9 +971,13 @@ define <8 x i64> @shuffle_v8i64_2a3b6e7f(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_08192a3b(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_08192a3b: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm2 = ymm1[0,2,2,3] +; ALL-NEXT: vpermq {{.*#+}} ymm3 = ymm0[2,1,3,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,0,2,1] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> ret <8 x i64> %shuffle @@ -776,9 +986,11 @@ define <8 x i64> @shuffle_v8i64_08192a3b(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_08991abb(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_08991abb: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm2 = ymm1[0,0,1,1] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm0[0,1],ymm2[2,3,4,5,6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5,6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,2,3,3] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11> ret <8 x i64> %shuffle @@ -787,9 +999,12 @@ define <8 x i64> @shuffle_v8i64_08991abb(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_091b2d3f(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_091b2d3f: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm1, %zmm0, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpermq {{.*#+}} ymm3 = ymm0[2,1,3,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3],ymm3[4,5],ymm2[6,7] +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,3] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15> ret <8 x i64> %shuffle @@ -798,9 +1013,11 @@ define <8 x i64> @shuffle_v8i64_091b2d3f(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_09ab1def(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_09ab1def: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpshufd {{.*#+}} ymm3 = ymm0[2,3,2,3,6,7,6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1],ymm2[2,3,4,5,6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15> ret <8 x i64> %shuffle @@ -809,7 +1026,10 @@ define <8 x i64> @shuffle_v8i64_09ab1def(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00014445(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00014445: ; ALL: # BB#0: -; ALL-NEXT: vpermq $64, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,0,1] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,0,1] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 4, i32 4, i32 4, i32 5> ret <8 x i64> %shuffle @@ -818,7 +1038,10 @@ define <8 x i64> @shuffle_v8i64_00014445(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00204464(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00204464: ; ALL: # BB#0: -; ALL-NEXT: vpermq $32, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,2,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 4, i32 6, i32 4> ret <8 x i64> %shuffle @@ -827,7 +1050,10 @@ define <8 x i64> @shuffle_v8i64_00204464(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_03004744(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_03004744: ; ALL: # BB#0: -; ALL-NEXT: vpermq $12, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,3,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 7, i32 4, i32 4> ret <8 x i64> %shuffle @@ -836,7 +1062,10 @@ define <8 x i64> @shuffle_v8i64_03004744(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10005444(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10005444: ; ALL: # BB#0: -; ALL-NEXT: vpermq $1, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,0,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 5, i32 4, i32 4, i32 4> ret <8 x i64> %shuffle @@ -845,7 +1074,10 @@ define <8 x i64> @shuffle_v8i64_10005444(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_22006644(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_22006644: ; ALL: # BB#0: -; ALL-NEXT: vpermq $10, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,2,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 6, i32 4, i32 4> ret <8 x i64> %shuffle @@ -854,7 +1086,10 @@ define <8 x i64> @shuffle_v8i64_22006644(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_33307774(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_33307774: ; ALL: # BB#0: -; ALL-NEXT: vpermq $63, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,3,3,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,3,3,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 7, i32 7, i32 4> ret <8 x i64> %shuffle @@ -863,7 +1098,10 @@ define <8 x i64> @shuffle_v8i64_33307774(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_32107654(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_32107654: ; ALL: # BB#0: -; ALL-NEXT: vpermq $27, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x i64> %shuffle @@ -872,7 +1110,10 @@ define <8 x i64> @shuffle_v8i64_32107654(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00234467(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00234467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $136, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,2,3] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,3] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7> ret <8 x i64> %shuffle @@ -881,7 +1122,10 @@ define <8 x i64> @shuffle_v8i64_00234467(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00224466(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00224466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $0, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> ret <8 x i64> %shuffle @@ -890,7 +1134,10 @@ define <8 x i64> @shuffle_v8i64_00224466(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10325476(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10325476: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $85, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x i64> %shuffle @@ -899,7 +1146,10 @@ define <8 x i64> @shuffle_v8i64_10325476(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_11335577(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_11335577: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $255, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,2,3,6,7,6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> ret <8 x i64> %shuffle @@ -908,7 +1158,10 @@ define <8 x i64> @shuffle_v8i64_11335577(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10235467(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10235467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $153, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,0,2,3] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,3] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7> ret <8 x i64> %shuffle @@ -917,7 +1170,10 @@ define <8 x i64> @shuffle_v8i64_10235467(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10225466(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10225466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $17, %zmm0, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,0,2,2] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,2,2] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 2, i32 2, i32 5, i32 4, i32 6, i32 6> ret <8 x i64> %shuffle @@ -926,8 +1182,10 @@ define <8 x i64> @shuffle_v8i64_10225466(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00015444(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00015444: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,0,1] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4> ret <8 x i64> %shuffle @@ -936,8 +1194,10 @@ define <8 x i64> @shuffle_v8i64_00015444(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00204644(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00204644: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,2,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4> ret <8 x i64> %shuffle @@ -946,8 +1206,10 @@ define <8 x i64> @shuffle_v8i64_00204644(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_03004474(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_03004474: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,3,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,3,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4> ret <8 x i64> %shuffle @@ -956,8 +1218,10 @@ define <8 x i64> @shuffle_v8i64_03004474(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10004444(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10004444: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,0,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> ret <8 x i64> %shuffle @@ -966,8 +1230,10 @@ define <8 x i64> @shuffle_v8i64_10004444(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_22006446(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_22006446: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,2,0,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,0,0,2] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6> ret <8 x i64> %shuffle @@ -976,8 +1242,10 @@ define <8 x i64> @shuffle_v8i64_22006446(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_33307474(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_33307474: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,3,3,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,0,3,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4> ret <8 x i64> %shuffle @@ -986,8 +1254,9 @@ define <8 x i64> @shuffle_v8i64_33307474(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_32104567(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_32104567: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[3,2,1,0] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7> ret <8 x i64> %shuffle @@ -996,8 +1265,10 @@ define <8 x i64> @shuffle_v8i64_32104567(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00236744(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00236744: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,0,2,3] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4> ret <8 x i64> %shuffle @@ -1006,8 +1277,10 @@ define <8 x i64> @shuffle_v8i64_00236744(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00226644(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00226644: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4> ret <8 x i64> %shuffle @@ -1016,7 +1289,9 @@ define <8 x i64> @shuffle_v8i64_00226644(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_10324567(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_10324567: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $165, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7> ret <8 x i64> %shuffle @@ -1025,7 +1300,9 @@ define <8 x i64> @shuffle_v8i64_10324567(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_11334567(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_11334567: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $175, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i64> %shuffle @@ -1034,7 +1311,9 @@ define <8 x i64> @shuffle_v8i64_11334567(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_01235467(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_01235467: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $154, %zmm0, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[1,0,2,3] +; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7> ret <8 x i64> %shuffle @@ -1043,7 +1322,9 @@ define <8 x i64> @shuffle_v8i64_01235467(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_01235466(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_01235466: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $26, %zmm0, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[1,0,2,2] +; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6> ret <8 x i64> %shuffle @@ -1052,8 +1333,10 @@ define <8 x i64> @shuffle_v8i64_01235466(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_002u6u44(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_002u6u44: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[0,1,0,1,4,5,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,1,0,0] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 4, i32 4> ret <8 x i64> %shuffle @@ -1062,8 +1345,10 @@ define <8 x i64> @shuffle_v8i64_002u6u44(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_00uu66uu(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_00uu66uu: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm1 -; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpbroadcastq %xmm0, %ymm1 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,2,2,3] +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 6, i32 6, i32 undef, i32 undef> ret <8 x i64> %shuffle @@ -1072,7 +1357,9 @@ define <8 x i64> @shuffle_v8i64_00uu66uu(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_103245uu(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_103245uu: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $37, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,0,1,6,7,4,5] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 undef, i32 undef> ret <8 x i64> %shuffle @@ -1081,7 +1368,9 @@ define <8 x i64> @shuffle_v8i64_103245uu(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_1133uu67(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_1133uu67: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $143, %zmm0, %zmm0 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[2,3,2,3,6,7,6,7] +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 6, i32 7> ret <8 x i64> %shuffle @@ -1090,7 +1379,9 @@ define <8 x i64> @shuffle_v8i64_1133uu67(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_0uu354uu(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_0uu354uu: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $24, %zmm0, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,0,1,6,7,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 5, i32 4, i32 undef, i32 undef> ret <8 x i64> %shuffle @@ -1099,7 +1390,9 @@ define <8 x i64> @shuffle_v8i64_0uu354uu(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_uuu3uu66(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_uuu3uu66: ; ALL: # BB#0: -; ALL-NEXT: vpermilpd $8, %zmm0, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,4,5] +; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 6> ret <8 x i64> %shuffle @@ -1108,9 +1401,15 @@ define <8 x i64> @shuffle_v8i64_uuu3uu66(<8 x i64> %a, <8 x i64> %b) { define <8 x i64> @shuffle_v8i64_6caa87e5(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_6caa87e5: ; ALL: # BB#0: -; ALL-NEXT: vmovdqa64 {{.*}}(%rip), %zmm2 -; ALL-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 -; ALL-NEXT: vmovaps %zmm2, %zmm0 +; ALL-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; ALL-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3,0,1] +; ALL-NEXT: vextracti64x4 $1, %zmm1, %ymm2 +; ALL-NEXT: vpblendd {{.*#+}} ymm3 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1],ymm0[2,3],ymm3[4,5],ymm0[6,7] +; ALL-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] +; ALL-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,4,5] +; ALL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7] +; ALL-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 ; ALL-NEXT: retq %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 6, i32 12, i32 10, i32 10, i32 8, i32 7, i32 14, i32 5> ret <8 x i64> %shuffle diff --git a/test/CodeGen/X86/widen_conv-3.ll b/test/CodeGen/X86/widen_conv-3.ll index a2f3d7b82b369..0a6eea049d372 100644 --- a/test/CodeGen/X86/widen_conv-3.ll +++ b/test/CodeGen/X86/widen_conv-3.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s -; CHECK: cvtsi2ss +; CHECK: cvtdq2ps ; sign to float v2i16 to v2f32 diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll index 9718c86300c25..a0b552d4d5847 100644 --- a/test/CodeGen/X86/win64_params.ll +++ b/test/CodeGen/X86/win64_params.ll @@ -7,8 +7,7 @@ define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind re entry: ; CHECK: movl 48(%rsp), %eax ; CHECK: addl 40(%rsp), %eax -; LINUX: addl %r9d, %r8d -; LINUX: movl %r8d, %eax +; LINUX: leal (%r8,%r9), %eax %add = add nsw i32 %p6, %p5 ret i32 %add } @@ -27,10 +26,8 @@ entry: ; on other platforms here (note the x86_64_sysvcc calling convention). define x86_64_sysvcc i32 @f8(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize { entry: -; CHECK: addl %r9d, %r8d -; CHECK: movl %r8d, %eax -; LINUX: addl %r9d, %r8d -; LINUX: movl %r8d, %eax +; CHECK: leal (%r8,%r9), %eax +; LINUX: leal (%r8,%r9), %eax %add = add nsw i32 %p6, %p5 ret i32 %add } diff --git a/test/CodeGen/X86/win_cst_pool.ll b/test/CodeGen/X86/win_cst_pool.ll index 199557dac2061..77c37b4d348e2 100644 --- a/test/CodeGen/X86/win_cst_pool.ll +++ b/test/CodeGen/X86/win_cst_pool.ll @@ -64,3 +64,16 @@ define <4 x float> @undef1() { ; CHECK: movaps __xmm@00000000000000003f8000003f800000(%rip), %xmm0 ; CHECK-NEXT: ret } + +define float @pr23966(i32 %a) { + %tobool = icmp ne i32 %a, 0 + %sel = select i1 %tobool, float -1.000000e+00, float 1.000000e+00 + ret float %sel +} + +; CHECK: .globl __real@bf8000003f800000 +; CHECK-NEXT: .section .rdata,"dr",discard,__real@bf8000003f800000 +; CHECK-NEXT: .align 4 +; CHECK-NEXT: __real@bf8000003f800000: +; CHECK-NEXT: .long 1065353216 +; CHECK-NEXT: .long 3212836864 diff --git a/test/CodeGen/X86/win_ftol2.ll b/test/CodeGen/X86/win_ftol2.ll index 14591248f354e..dfa6e3aa76bdd 100644 --- a/test/CodeGen/X86/win_ftol2.ll +++ b/test/CodeGen/X86/win_ftol2.ll @@ -142,3 +142,25 @@ define i64 @double_ui64_5(double %X) { %tmp.1 = fptoui double %X to i64 ret i64 %tmp.1 } + +define double @pr23957_32(double %A) { +; FTOL-LABEL: @pr23957_32 +; FTOL: fldl +; FTOL-NEXT: fld %st(0) +; FTOL-NEXT: calll __ftol2 + %B = fptoui double %A to i32 + %C = uitofp i32 %B to double + %D = fsub double %C, %A + ret double %D +} + +define double @pr23957_64(double %A) { +; FTOL-LABEL: @pr23957_64 +; FTOL: fldl +; FTOL-NEXT: fld %st(0) +; FTOL-NEXT: calll __ftol2 + %B = fptoui double %A to i64 + %C = uitofp i64 %B to double + %D = fsub double %C, %A + ret double %D +} diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index 829be41e51279..f78fe27578651 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s -check-prefix=X64 @@ -193,3 +193,22 @@ define i32 @test11(i32 %b) { ; X32: movl $-2, %[[REG:.*]] ; X32: roll %{{.*}}, %[[REG]] } + +%struct.ref_s = type { %union.v, i16, i16 } +%union.v = type { i64 } + +define %struct.ref_s* @test12(%struct.ref_s* %op, i64 %osbot, i64 %intval) { + %neg = shl i64 %intval, 32 + %sext = xor i64 %neg, -4294967296 + %idx.ext = ashr exact i64 %sext, 32 + %add.ptr = getelementptr inbounds %struct.ref_s, %struct.ref_s* %op, i64 %idx.ext + ret %struct.ref_s* %add.ptr +; X64-LABEL: test12: +; X64: shlq $32, %[[REG:.*]] +; X64-NOT: not +; X64: sarq $28, %[[REG]] +; X32-LABEL: test12: +; X32: leal +; X32-NOT: not +; X32: shll $2, %eax +} diff --git a/test/DebugInfo/AArch64/bitfields.ll b/test/DebugInfo/AArch64/bitfields.ll new file mode 100644 index 0000000000000..5f0caab286b8e --- /dev/null +++ b/test/DebugInfo/AArch64/bitfields.ll @@ -0,0 +1,73 @@ +; RUN: llc -mtriple aarch64_be-gnu-linux -O0 -filetype=obj -o %t_be.o %s +; RUN: llvm-dwarfdump -debug-dump=info %t_be.o | FileCheck %s + +; Produced at -O0 from: +; struct bitfield { +; int a : 2; +; int b : 32; +; int c : 1; +; int d : 28; +; }; +; struct bitfield b; + +; Note that DWARF 2 counts bit offsets backwards from the high end of +; the storage unit to the high end of the bit field. + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"a" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x02) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x00) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 00 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"b" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_data_member_location {{.*}} 04 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"c" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x01) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x00) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 08 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"d" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x1c) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x01) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 08 + +; ModuleID = 'bitfields.c' +target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64_be--linux-gnu" + +%struct.bitfield = type <{ i8, [3 x i8], i64 }> + +@b = common global %struct.bitfield zeroinitializer, align 4 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!13, !14, !15} +!llvm.ident = !{!16} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2) +!1 = !DIFile(filename: "bitfields.c", directory: "/") +!2 = !{} +!3 = !{!4} +!4 = !DIGlobalVariable(name: "b", scope: !0, file: !5, line: 8, type: !6, isLocal: false, isDefinition: true, variable: %struct.bitfield* @b) +!5 = !DIFile(filename: "bitfields.c", directory: "/") +!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "bitfield", file: !5, line: 1, size: 96, align: 32, elements: !7) +!7 = !{!8, !10, !11, !12} +!8 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !6, file: !5, line: 2, baseType: !9, size: 2, align: 32) +!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!10 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !6, file: !5, line: 3, baseType: !9, size: 32, align: 32, offset: 32) +!11 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !6, file: !5, line: 4, baseType: !9, size: 1, align: 32, offset: 64) +!12 = !DIDerivedType(tag: DW_TAG_member, name: "d", scope: !6, file: !5, line: 5, baseType: !9, size: 28, align: 32, offset: 65) +!13 = !{i32 2, !"Dwarf Version", i32 2} +!14 = !{i32 2, !"Debug Info Version", i32 3} +!15 = !{i32 1, !"PIC Level", i32 2} +!16 = !{!"clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)"} diff --git a/test/DebugInfo/ARM/bitfield.ll b/test/DebugInfo/ARM/bitfield.ll new file mode 100644 index 0000000000000..9b41e4e4f7bc1 --- /dev/null +++ b/test/DebugInfo/ARM/bitfield.ll @@ -0,0 +1,45 @@ +; RUN: %llc_dwarf -O0 -filetype=obj -o %t.o %s +; RUN: llvm-dwarfdump -debug-dump=info %t.o | FileCheck %s +; REQUIRES: object-emission +; +; Generated from: +; struct { +; char c; +; int : 4; +; int reserved : 28; +; } a; +; +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "reserved" +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK: DW_AT_bit_size {{.*}} (0x1c) +; CHECK: DW_AT_bit_offset {{.*}} (0x18) +; CHECK: DW_AT_data_member_location {{.*}}00 +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios" + +%struct.anon = type { i8, [5 x i8] } + +@a = common global %struct.anon zeroinitializer, align 1 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!11, !12, !13, !14, !15} +!llvm.ident = !{!16} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2) +!1 = !DIFile(filename: "test.i", directory: "/") +!2 = !{} +!3 = !{!4} +!4 = !DIGlobalVariable(name: "a", scope: !0, file: !1, line: 5, type: !5, isLocal: false, isDefinition: true, variable: %struct.anon* @a) +!5 = !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 1, size: 48, align: 8, elements: !6) +!6 = !{!7, !9} +!7 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !5, file: !1, line: 2, baseType: !8, size: 8, align: 8) +!8 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!9 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", scope: !5, file: !1, line: 4, baseType: !10, size: 28, align: 32, offset: 12) +!10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!11 = !{i32 2, !"Dwarf Version", i32 2} +!12 = !{i32 2, !"Debug Info Version", i32 3} +!13 = !{i32 1, !"wchar_size", i32 4} +!14 = !{i32 1, !"min_enum_size", i32 4} +!15 = !{i32 1, !"PIC Level", i32 2} +!16 = !{!"clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)"} diff --git a/test/DebugInfo/X86/DIModule.ll b/test/DebugInfo/X86/DIModule.ll new file mode 100644 index 0000000000000..daed43a58cda7 --- /dev/null +++ b/test/DebugInfo/X86/DIModule.ll @@ -0,0 +1,25 @@ +; ModuleID = '/Volumes/Data/apple-internal/llvm/tools/clang/test/Modules/debug-info-moduleimport.m' +; RUN: llc %s -o %t -filetype=obj +; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s +; CHECK: DW_TAG_module +; CHECK-NEXT: DW_AT_name {{.*}}"DebugModule" +; CHECK-NEXT: DW_AT_LLVM_config_macros {{.*}}"-DMODULES=0" +; CHECK-NEXT: DW_AT_LLVM_include_path {{.*}}"/llvm/tools/clang/test/Modules/Inputs" +; CHECK-NEXT: DW_AT_LLVM_isysroot {{.*}}"/" + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!6, !7} +!llvm.ident = !{!8} + +!0 = distinct !DICompileUnit(language: DW_LANG_ObjC, file: !1, producer: "LLVM version 3.7.0", isOptimized: false, runtimeVersion: 2, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !3) +!1 = !DIFile(filename: "/llvm/tools/clang/test/Modules/<stdin>", directory: "/") +!2 = !{} +!3 = !{!4} +!4 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !0, entity: !5, line: 5) +!5 = !DIModule(scope: null, name: "DebugModule", configMacros: "-DMODULES=0", includePath: "/llvm/tools/clang/test/Modules/Inputs", isysroot: "/") +!6 = !{i32 2, !"Dwarf Version", i32 4} +!7 = !{i32 2, !"Debug Info Version", i32 3} +!8 = !{!"LLVM version 3.7.0"} diff --git a/test/DebugInfo/X86/asm-macro-line-number.s b/test/DebugInfo/X86/asm-macro-line-number.s index 0f51dbb6440a2..8b0843d06138b 100644 --- a/test/DebugInfo/X86/asm-macro-line-number.s +++ b/test/DebugInfo/X86/asm-macro-line-number.s @@ -3,12 +3,18 @@ # 1 "reduced.S" # 1 "<built-in>" 1 # 1 "reduced.S" 2 +# 200 "macros.h" .macro return arg movl %eax, \arg retl .endm + .macro return2 arg + return \arg + .endm + +# 7 "reduced.S" function: return 0 @@ -18,3 +24,11 @@ function: # CHECK: .loc 2 8 0 # CHECK: retl +# 42 "reduced.S" +function2: + return2 0 + +# CHECK: .loc 2 43 0 +# CHECK: movl %eax, 0 +# CHECK: .loc 2 43 0 +# CHECK: retl diff --git a/test/DebugInfo/X86/bitfields.ll b/test/DebugInfo/X86/bitfields.ll new file mode 100644 index 0000000000000..e895fd67e03de --- /dev/null +++ b/test/DebugInfo/X86/bitfields.ll @@ -0,0 +1,73 @@ +; RUN: llc -mtriple x86_64-apple-macosx -O0 -filetype=obj -o %t_le.o %s +; RUN: llvm-dwarfdump -debug-dump=info %t_le.o | FileCheck %s + +; Produced at -O0 from: +; struct bitfield { +; int a : 2; +; int b : 32; +; int c : 1; +; int d : 28; +; }; +; struct bitfield b; + +; Note that DWARF 2 counts bit offsets backwards from the high end of +; the storage unit to the high end of the bit field. + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"a" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x02) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x1e) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 00 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"b" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_data_member_location {{.*}} 04 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"c" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x01) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x1f) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 08 + +; CHECK: DW_TAG_member +; CHECK-NEXT: DW_AT_name{{.*}}"d" +; CHECK-NOT: DW_TAG_member +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK-NEXT: DW_AT_bit_size {{.*}} (0x1c) +; CHECK-NEXT: DW_AT_bit_offset {{.*}} (0x03) +; CHECK-NEXT: DW_AT_data_member_location {{.*}} 08 + +; ModuleID = 'bitfields.c' +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +%struct.bitfield = type <{ i8, [3 x i8], i64 }> + +@b = common global %struct.bitfield zeroinitializer, align 4 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!13, !14, !15} +!llvm.ident = !{!16} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2) +!1 = !DIFile(filename: "bitfields.c", directory: "/") +!2 = !{} +!3 = !{!4} +!4 = !DIGlobalVariable(name: "b", scope: !0, file: !5, line: 8, type: !6, isLocal: false, isDefinition: true, variable: %struct.bitfield* @b) +!5 = !DIFile(filename: "bitfields.c", directory: "/") +!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "bitfield", file: !5, line: 1, size: 96, align: 32, elements: !7) +!7 = !{!8, !10, !11, !12} +!8 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !6, file: !5, line: 2, baseType: !9, size: 2, align: 32) +!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!10 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !6, file: !5, line: 3, baseType: !9, size: 32, align: 32, offset: 32) +!11 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !6, file: !5, line: 4, baseType: !9, size: 1, align: 32, offset: 64) +!12 = !DIDerivedType(tag: DW_TAG_member, name: "d", scope: !6, file: !5, line: 5, baseType: !9, size: 28, align: 32, offset: 65) +!13 = !{i32 2, !"Dwarf Version", i32 2} +!14 = !{i32 2, !"Debug Info Version", i32 3} +!15 = !{i32 1, !"PIC Level", i32 2} +!16 = !{!"clang version 3.7.0 (trunk 240548) (llvm/trunk 240554)"} diff --git a/test/DebugInfo/X86/debug-info-packed-struct.ll b/test/DebugInfo/X86/debug-info-packed-struct.ll new file mode 100644 index 0000000000000..6829c2d137403 --- /dev/null +++ b/test/DebugInfo/X86/debug-info-packed-struct.ll @@ -0,0 +1,198 @@ +; Generated from tools/clang/test/CodeGen/debug-info-packed-struct.c +; ModuleID = 'llvm/tools/clang/test/CodeGen/debug-info-packed-struct.c' +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin" + +; RUN: %llc_dwarf -O0 -filetype=obj -o %t.o %s +; RUN: llvm-dwarfdump -debug-dump=info %t.o | FileCheck %s +; REQUIRES: object-emission + +; // --------------------------------------------------------------------- +; // Not packed. +; // --------------------------------------------------------------------- +; struct size8 { +; int i : 4; +; long long l : 60; +; }; +; struct layout0 { +; char l0_ofs0; +; struct size8 l0_ofs8; +; int l0_ofs16 : 1; +; } l0; + +%struct.layout0 = type { i8, %struct.size8, i8 } +%struct.size8 = type { i64 } +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name {{.*}} "layout0" +; CHECK: DW_AT_byte_size {{.*}} (0x18) +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l0_ofs0" +; CHECK: DW_AT_data_member_location {{.*}}00 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l0_ofs8" +; CHECK: DW_AT_data_member_location {{.*}}08 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l0_ofs16" +; CHECK: DW_AT_bit_size {{.*}} (0x01) +; CHECK: DW_AT_bit_offset {{.*}} (0x1f) +; CHECK: DW_AT_data_member_location {{.*}}10 + + +; // --------------------------------------------------------------------- +; // Implicitly packed. +; // --------------------------------------------------------------------- +; struct size8_anon { +; int : 4; +; long long : 60; +; }; +; struct layout1 { +; char l1_ofs0; +; struct size8_anon l1_ofs1; +; int l1_ofs9 : 1; +; } l1; + +%struct.layout1 = type <{ i8, %struct.size8_anon, i8, [2 x i8] }> +%struct.size8_anon = type { i64 } + +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name {{.*}} "layout1" +; CHECK: DW_AT_byte_size {{.*}} (0x0c) +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l1_ofs0" +; CHECK: DW_AT_data_member_location {{.*}}00 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l1_ofs1" +; CHECK: DW_AT_data_member_location {{.*}}01 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l1_ofs9" +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK: DW_AT_bit_size {{.*}} (0x01) +; CHECK: DW_AT_bit_offset {{.*}} (0x17) +; CHECK: DW_AT_data_member_location {{.*}}08 + +; // --------------------------------------------------------------------- +; // Explicitly packed. +; // --------------------------------------------------------------------- +; #pragma pack(1) +; struct size8_pack1 { +; int i : 4; +; long long l : 60; +; }; +; struct layout2 { +; char l2_ofs0; +; struct size8_pack1 l2_ofs1; +; int l2_ofs9 : 1; +; } l2; +; #pragma pack() + +%struct.layout2 = type <{ i8, %struct.size8_pack1, i8 }> +%struct.size8_pack1 = type { i64 } + +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name {{.*}} "layout2" +; CHECK: DW_AT_byte_size {{.*}} (0x0a) +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l2_ofs0" +; CHECK: DW_AT_data_member_location {{.*}}00 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l2_ofs1" +; CHECK: DW_AT_data_member_location {{.*}}01 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l2_ofs9" +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK: DW_AT_bit_size {{.*}} (0x01) +; CHECK: DW_AT_bit_offset {{.*}} (0x17) +; CHECK: DW_AT_data_member_location {{.*}}08 + +; // --------------------------------------------------------------------- +; // Explicitly packed with different alignment. +; // --------------------------------------------------------------------- +; #pragma pack(4) +; struct size8_pack4 { +; int i : 4; +; long long l : 60; +; }; +; struct layout3 { +; char l3_ofs0; +; struct size8_pack4 l3_ofs4; +; int l3_ofs12 : 1; +; } l 3; +; #pragma pack() + + +%struct.layout3 = type <{ i8, [3 x i8], %struct.size8_pack4, i8, [3 x i8] }> +%struct.size8_pack4 = type { i64 } + +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name {{.*}} "layout3" +; CHECK: DW_AT_byte_size {{.*}} (0x10) +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l3_ofs0" +; CHECK: DW_AT_data_member_location {{.*}}00 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l3_ofs4" +; CHECK: DW_AT_data_member_location {{.*}}04 +; CHECK: DW_TAG_member +; CHECK: DW_AT_name {{.*}} "l3_ofs12" +; CHECK: DW_AT_byte_size {{.*}} (0x04) +; CHECK: DW_AT_bit_size {{.*}} (0x01) +; CHECK: DW_AT_bit_offset {{.*}} (0x1f) +; CHECK: DW_AT_data_member_location {{.*}}0c + +@l0 = common global %struct.layout0 zeroinitializer, align 8 +@l1 = common global %struct.layout1 zeroinitializer, align 4 +@l2 = common global %struct.layout2 zeroinitializer, align 1 +@l3 = common global %struct.layout3 zeroinitializer, align 4 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!45, !46} +!llvm.ident = !{!47} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (trunk 240791) (llvm/trunk 240790)", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !3, imports: !2) +!1 = !DIFile(filename: "/llvm/tools/clang/test/CodeGen/<stdin>", directory: "/llvm/_build.ninja.release") +!2 = !{} +!3 = !{!4, !18, !25, !35} +!4 = !DIGlobalVariable(name: "l0", scope: !0, file: !5, line: 88, type: !6, isLocal: false, isDefinition: true, variable: %struct.layout0* @l0) +!5 = !DIFile(filename: "/llvm/tools/clang/test/CodeGen/debug-info-packed-struct.c", directory: "/llvm/_build.ninja.release") +!6 = !DICompositeType(tag: DW_TAG_structure_type, name: "layout0", file: !5, line: 15, size: 192, align: 64, elements: !7) +!7 = !{!8, !10, !17} +!8 = !DIDerivedType(tag: DW_TAG_member, name: "l0_ofs0", scope: !6, file: !5, line: 16, baseType: !9, size: 8, align: 8) +!9 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!10 = !DIDerivedType(tag: DW_TAG_member, name: "l0_ofs8", scope: !6, file: !5, line: 17, baseType: !11, size: 64, align: 64, offset: 64) +!11 = !DICompositeType(tag: DW_TAG_structure_type, name: "size8", file: !5, line: 11, size: 64, align: 64, elements: !12) +!12 = !{!13, !15} +!13 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !11, file: !5, line: 12, baseType: !14, size: 4, align: 32) +!14 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!15 = !DIDerivedType(tag: DW_TAG_member, name: "l", scope: !11, file: !5, line: 13, baseType: !16, size: 60, offset: 4) +!16 = !DIBasicType(name: "long long int", size: 64, align: 64, encoding: DW_ATE_signed) +!17 = !DIDerivedType(tag: DW_TAG_member, name: "l0_ofs16", scope: !6, file: !5, line: 18, baseType: !14, size: 1, align: 32, offset: 128) +!18 = !DIGlobalVariable(name: "l1", scope: !0, file: !5, line: 89, type: !19, isLocal: false, isDefinition: true, variable: %struct.layout1* @l1) +!19 = !DICompositeType(tag: DW_TAG_structure_type, name: "layout1", file: !5, line: 34, size: 96, align: 32, elements: !20) +!20 = !{!21, !22, !24} +!21 = !DIDerivedType(tag: DW_TAG_member, name: "l1_ofs0", scope: !19, file: !5, line: 35, baseType: !9, size: 8, align: 8) +!22 = !DIDerivedType(tag: DW_TAG_member, name: "l1_ofs1", scope: !19, file: !5, line: 36, baseType: !23, size: 64, align: 8, offset: 8) +!23 = !DICompositeType(tag: DW_TAG_structure_type, name: "size8_anon", file: !5, line: 30, size: 64, align: 8, elements: !2) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "l1_ofs9", scope: !19, file: !5, line: 37, baseType: !14, size: 1, align: 32, offset: 72) +!25 = !DIGlobalVariable(name: "l2", scope: !0, file: !5, line: 90, type: !26, isLocal: false, isDefinition: true, variable: %struct.layout2* @l2) +!26 = !DICompositeType(tag: DW_TAG_structure_type, name: "layout2", file: !5, line: 54, size: 80, align: 8, elements: !27) +!27 = !{!28, !29, !34} +!28 = !DIDerivedType(tag: DW_TAG_member, name: "l2_ofs0", scope: !26, file: !5, line: 55, baseType: !9, size: 8, align: 8) +!29 = !DIDerivedType(tag: DW_TAG_member, name: "l2_ofs1", scope: !26, file: !5, line: 56, baseType: !30, size: 64, align: 8, offset: 8) +!30 = !DICompositeType(tag: DW_TAG_structure_type, name: "size8_pack1", file: !5, line: 50, size: 64, align: 8, elements: !31) +!31 = !{!32, !33} +!32 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !30, file: !5, line: 51, baseType: !14, size: 4, align: 32) +!33 = !DIDerivedType(tag: DW_TAG_member, name: "l", scope: !30, file: !5, line: 52, baseType: !16, size: 60, offset: 4) +!34 = !DIDerivedType(tag: DW_TAG_member, name: "l2_ofs9", scope: !26, file: !5, line: 57, baseType: !14, size: 1, align: 32, offset: 72) +!35 = !DIGlobalVariable(name: "l3", scope: !0, file: !5, line: 91, type: !36, isLocal: false, isDefinition: true, variable: %struct.layout3* @l3) +!36 = !DICompositeType(tag: DW_TAG_structure_type, name: "layout3", file: !5, line: 76, size: 128, align: 32, elements: !37) +!37 = !{!38, !39, !44} +!38 = !DIDerivedType(tag: DW_TAG_member, name: "l3_ofs0", scope: !36, file: !5, line: 77, baseType: !9, size: 8, align: 8) +!39 = !DIDerivedType(tag: DW_TAG_member, name: "l3_ofs4", scope: !36, file: !5, line: 78, baseType: !40, size: 64, align: 32, offset: 32) +!40 = !DICompositeType(tag: DW_TAG_structure_type, name: "size8_pack4", file: !5, line: 72, size: 64, align: 32, elements: !41) +!41 = !{!42, !43} +!42 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !40, file: !5, line: 73, baseType: !14, size: 4, align: 32) +!43 = !DIDerivedType(tag: DW_TAG_member, name: "l", scope: !40, file: !5, line: 74, baseType: !16, size: 60, offset: 4) +!44 = !DIDerivedType(tag: DW_TAG_member, name: "l3_ofs12", scope: !36, file: !5, line: 79, baseType: !14, size: 1, align: 32, offset: 96) +!45 = !{i32 2, !"Dwarf Version", i32 2} +!46 = !{i32 2, !"Debug Info Version", i32 3} +!47 = !{!"clang version 3.7.0 (trunk 240791) (llvm/trunk 240790)"} diff --git a/test/DebugInfo/X86/debug-loc-empty-entries.ll b/test/DebugInfo/X86/debug-loc-empty-entries.ll new file mode 100644 index 0000000000000..3b997fd35e068 --- /dev/null +++ b/test/DebugInfo/X86/debug-loc-empty-entries.ll @@ -0,0 +1,66 @@ +; RUN: llc -mtriple=x86_64-apple-macosx <%s | FileCheck %s +; Test that we don't generate empty .debug_loc entries. Originally, there were +; two empty .debug_loc entries for 'a' in an otherwise empty .debug_loc list. +; +; CHECK: .section __DWARF,__debug_loc,regular,debug +; CHECK-NEXT: Lsection_debug_loc: +; CHECK-NEXT: .section __DWARF,__debug_abbrev,regular,debug +; +; Test that the variable stuck around. +; CHECK: .section __DWARF,__debug_info,regular,debug +; CHECK: DW_TAG_variable +; CHECK-NOT: DW_AT_location + +; Generated using clang -cc1 with the following args: +; +; -triple x86_64-apple-macosx -emit-llvm -gdwarf-4 -O1 +; +; From this testcase: +; +;; void fn1() { +;; float a = 1; +;; for (;;) +;; a = 0; +;; } + +; Function Attrs: noreturn nounwind readnone +define void @_Z3fn1v() #0 { +entry: + tail call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !9, metadata !14), !dbg !15 + br label %for.cond, !dbg !16 + +for.cond: ; preds = %for.cond, %entry + tail call void @llvm.dbg.value(metadata float 0.000000e+00, i64 0, metadata !9, metadata !14), !dbg !15 + br label %for.cond, !dbg !17 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 + +attributes #0 = { noreturn nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!11, !12} +!llvm.ident = !{!13} + +!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.7.0 (trunk 238517) (llvm/trunk 238524)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "<stdin>", directory: "/Users/dexonsmith/data/llvm/bootstrap/play/delta2/testcase") +!2 = !{} +!3 = !{!4} +!4 = !DISubprogram(name: "fn1", linkageName: "_Z3fn1v", scope: !5, file: !5, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @_Z3fn1v, variables: !8) +!5 = !DIFile(filename: "t.cpp", directory: "/Users/dexonsmith/data/llvm/bootstrap/play/delta2/testcase") +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !{!9} +!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "a", scope: !4, file: !5, line: 2, type: !10) +!10 = !DIBasicType(name: "float", size: 32, align: 32, encoding: DW_ATE_float) +!11 = !{i32 2, !"Dwarf Version", i32 4} +!12 = !{i32 2, !"Debug Info Version", i32 3} +!13 = !{!"clang version 3.7.0 (trunk 238517) (llvm/trunk 238524)"} +!14 = !DIExpression() +!15 = !DILocation(line: 2, scope: !4) +!16 = !DILocation(line: 3, scope: !4) +!17 = !DILocation(line: 3, scope: !18) +!18 = distinct !DILexicalBlock(scope: !19, file: !5, line: 3) +!19 = distinct !DILexicalBlock(scope: !4, file: !5, line: 3) diff --git a/test/DebugInfo/X86/dwarf-public-names.ll b/test/DebugInfo/X86/dwarf-public-names.ll index 48f13fd1e07bc..c72da38832ee5 100644 --- a/test/DebugInfo/X86/dwarf-public-names.ll +++ b/test/DebugInfo/X86/dwarf-public-names.ll @@ -39,11 +39,11 @@ ; Darwin and PS4 shouldn't be generating the section by default ; NOPUB: debug_pubnames -; NOPUB: {{^$}} +; NOPUB-NEXT: {{^$}} ; Skip the output to the header of the pubnames section. ; LINUX: debug_pubnames -; LINUX: unit_size = 0x00000128 +; LINUX-NEXT: unit_size = 0x00000128 ; Check for each name in the output. ; LINUX-DAG: "ns" diff --git a/test/DebugInfo/dwarfdump-invalid.test b/test/DebugInfo/dwarfdump-invalid.test index da5b23e30ceb9..a36ad2f412e6a 100644 --- a/test/DebugInfo/dwarfdump-invalid.test +++ b/test/DebugInfo/dwarfdump-invalid.test @@ -1,6 +1,6 @@ ; Verify that llvm-dwarfdump doesn't crash on broken input files. -RUN: llvm-dwarfdump %p/Inputs/invalid.elf 2>&1 | FileCheck %s --check-prefix=INVALID-ELF -RUN: llvm-dwarfdump %p/Inputs/invalid.elf.2 2>&1 | FileCheck %s --check-prefix=INVALID-ELF -RUN: llvm-dwarfdump %p/Inputs/invalid.elf.3 2>&1 | FileCheck %s --check-prefix=INVALID-ELF +RUN: not llvm-dwarfdump %p/Inputs/invalid.elf 2>&1 | FileCheck %s --check-prefix=INVALID-ELF +RUN: not llvm-dwarfdump %p/Inputs/invalid.elf.2 2>&1 | FileCheck %s --check-prefix=INVALID-ELF +RUN: not llvm-dwarfdump %p/Inputs/invalid.elf.3 2>&1 | FileCheck %s --check-prefix=INVALID-ELF INVALID-ELF: Invalid data was encountered while parsing the file diff --git a/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll b/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll new file mode 100644 index 0000000000000..7827f3fbf278a --- /dev/null +++ b/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll @@ -0,0 +1,56 @@ +; RUN: opt < %s -asan -S -o %t.ll +; RUN: FileCheck %s < %t.ll + +; Don't do stack malloc on functions containing inline assembly on 64-bit +; platforms. It makes LLVM run out of registers. + +; CHECK-LABEL: define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h) +; CHECK: %MyAlloca +; CHECK-NOT: call {{.*}} @__asan_stack_malloc + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.10.0" + +define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h) #0 { +entry: + %S.addr = alloca i8*, align 8 + %pS.addr = alloca i32, align 4 + %D.addr = alloca i8*, align 8 + %pD.addr = alloca i32, align 4 + %h.addr = alloca i32, align 4 + %sr = alloca i32, align 4 + %pDiffD = alloca i32, align 4 + %pDiffS = alloca i32, align 4 + %flagSA = alloca i8, align 1 + %flagDA = alloca i8, align 1 + store i8* %S, i8** %S.addr, align 8 + store i32 %pS, i32* %pS.addr, align 4 + store i8* %D, i8** %D.addr, align 8 + store i32 %pD, i32* %pD.addr, align 4 + store i32 %h, i32* %h.addr, align 4 + store i32 4, i32* %sr, align 4 + %0 = load i32, i32* %pD.addr, align 4 + %sub = sub i32 %0, 5 + store i32 %sub, i32* %pDiffD, align 4 + %1 = load i32, i32* %pS.addr, align 4 + %shl = shl i32 %1, 1 + %sub1 = sub i32 %shl, 5 + store i32 %sub1, i32* %pDiffS, align 4 + %2 = load i32, i32* %pS.addr, align 4 + %and = and i32 %2, 15 + %cmp = icmp eq i32 %and, 0 + %conv = zext i1 %cmp to i32 + %conv2 = trunc i32 %conv to i8 + store i8 %conv2, i8* %flagSA, align 1 + %3 = load i32, i32* %pD.addr, align 4 + %and3 = and i32 %3, 15 + %cmp4 = icmp eq i32 %and3, 0 + %conv5 = zext i1 %cmp4 to i32 + %conv6 = trunc i32 %conv5 to i8 + store i8 %conv6, i8* %flagDA, align 1 + call void asm sideeffect "mov\09\09\09$0,\09\09\09\09\09\09\09\09\09\09%rsi\0Amov\09\09\09$2,\09\09\09\09\09\09\09\09\09\09%rcx\0Amov\09\09\09$1,\09\09\09\09\09\09\09\09\09\09%rdi\0Amov\09\09\09$8,\09\09\09\09\09\09\09\09\09\09%rax\0A", "*m,*m,*m,*m,*m,*m,*m,*m,*m,~{rsi},~{rdi},~{rax},~{rcx},~{rdx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8** %S.addr, i8** %D.addr, i32* %pS.addr, i32* %pDiffS, i32* %pDiffD, i32* %sr, i8* %flagSA, i8* %flagDA, i32* %h.addr) #1 + ret void +} + +attributes #0 = { nounwind sanitize_address } +attributes #1 = { nounwind } diff --git a/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata-darwin.ll b/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata-darwin.ll index 7617dbde0b7e3..f67155a29c2a8 100644 --- a/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata-darwin.ll +++ b/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata-darwin.ll @@ -1,12 +1,15 @@ -; This test checks that we are not instrumenting globals in llvm.metadata. +; This test checks that we are not instrumenting globals in llvm.metadata +; and other llvm internal globals. ; RUN: opt < %s -asan -asan-module -S | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0" @.str_noinst = private unnamed_addr constant [4 x i8] c"aaa\00", section "llvm.metadata" +@.str_noinst_prof = private unnamed_addr constant [4 x i8] c"aaa\00", section "__DATA,__llvm_covmap" @.str_inst = private unnamed_addr constant [4 x i8] c"aaa\00" ; CHECK-NOT: {{asan_gen.*str_noinst}} +; CHECK-NOT: {{asan_gen.*str_noinst_prof}} ; CHECK: {{asan_gen.*str_inst}} ; CHECK: @asan.module_ctor diff --git a/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata.ll b/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata.ll index d02f12aec98d0..93eca5bfd824b 100644 --- a/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata.ll +++ b/test/Instrumentation/AddressSanitizer/do-not-instrument-llvm-metadata.ll @@ -1,12 +1,15 @@ -; This test checks that we are not instrumenting globals in llvm.metadata. +; This test checks that we are not instrumenting globals in llvm.metadata +; and other llvm internal globals. ; RUN: opt < %s -asan -asan-module -S | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @.str_noinst = private unnamed_addr constant [4 x i8] c"aaa\00", section "llvm.metadata" +@.str_noinst_prof = private unnamed_addr constant [4 x i8] c"aaa\00", section "__llvm_prf_data" @.str_inst = private unnamed_addr constant [4 x i8] c"aaa\00" ; CHECK-NOT: {{asan_gen.*str_noinst}} +; CHECK-NOT: {{asan_gen.*str_noinst_prof}} ; CHECK: {{asan_gen.*str_inst}} ; CHECK: @asan.module_ctor diff --git a/test/Instrumentation/SanitizerCoverage/coverage.ll b/test/Instrumentation/SanitizerCoverage/coverage.ll index b2f0ab0680bf3..659c03040f2f9 100644 --- a/test/Instrumentation/SanitizerCoverage/coverage.ll +++ b/test/Instrumentation/SanitizerCoverage/coverage.ll @@ -119,3 +119,12 @@ entry: ; CHECK4: call void @__sanitizer_cov_indir_call16({{.*}},[[CACHE:.*]]) ; CHECK4-NOT: call void @__sanitizer_cov_indir_call16({{.*}},[[CACHE]]) ; CHECK4: ret void + +define void @call_unreachable() uwtable sanitize_address { +entry: + unreachable +} + +; CHECK4-LABEL: define void @call_unreachable +; CHECK4-NOT: __sanitizer_cov +; CHECK4: unreachable diff --git a/test/Instrumentation/ThreadSanitizer/atomic.ll b/test/Instrumentation/ThreadSanitizer/atomic.ll index 1d6ac3851e23f..db01bab8fe53c 100644 --- a/test/Instrumentation/ThreadSanitizer/atomic.ll +++ b/test/Instrumentation/ThreadSanitizer/atomic.ll @@ -4,1984 +4,1995 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define i8 @atomic8_load_unordered(i8* %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a unordered, align 1 - ret i8 %0 + %0 = load atomic i8, i8* %a unordered, align 1, !dbg !7 + ret i8 %0, !dbg !7 } -; CHECK: atomic8_load_unordered -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0) +; CHECK-LABEL: atomic8_load_unordered +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0), !dbg define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a monotonic, align 1 - ret i8 %0 + %0 = load atomic i8, i8* %a monotonic, align 1, !dbg !7 + ret i8 %0, !dbg !7 } -; CHECK: atomic8_load_monotonic -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0) +; CHECK-LABEL: atomic8_load_monotonic +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0), !dbg define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a acquire, align 1 - ret i8 %0 + %0 = load atomic i8, i8* %a acquire, align 1, !dbg !7 + ret i8 %0, !dbg !7 } -; CHECK: atomic8_load_acquire -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 2) +; CHECK-LABEL: atomic8_load_acquire +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 2), !dbg define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a seq_cst, align 1 - ret i8 %0 + %0 = load atomic i8, i8* %a seq_cst, align 1, !dbg !7 + ret i8 %0, !dbg !7 } -; CHECK: atomic8_load_seq_cst -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 5) +; CHECK-LABEL: atomic8_load_seq_cst +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 5), !dbg define void @atomic8_store_unordered(i8* %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a unordered, align 1 - ret void + store atomic i8 0, i8* %a unordered, align 1, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_store_unordered -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_store_unordered +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0), !dbg define void @atomic8_store_monotonic(i8* %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a monotonic, align 1 - ret void + store atomic i8 0, i8* %a monotonic, align 1, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_store_monotonic -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_store_monotonic +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0), !dbg define void @atomic8_store_release(i8* %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a release, align 1 - ret void + store atomic i8 0, i8* %a release, align 1, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_store_release -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_store_release +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 3), !dbg define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a seq_cst, align 1 - ret void + store atomic i8 0, i8* %a seq_cst, align 1, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_store_seq_cst -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_store_seq_cst +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 5), !dbg define void @atomic8_xchg_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 monotonic - ret void + atomicrmw xchg i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xchg_monotonic -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_xchg_monotonic +; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 0), !dbg define void @atomic8_add_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 monotonic - ret void + atomicrmw add i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_add_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_add_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 0), !dbg define void @atomic8_sub_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 monotonic - ret void + atomicrmw sub i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_sub_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_sub_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 0), !dbg define void @atomic8_and_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 monotonic - ret void + atomicrmw and i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_and_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_and_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 0), !dbg define void @atomic8_or_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 monotonic - ret void + atomicrmw or i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_or_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_or_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 0), !dbg define void @atomic8_xor_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 monotonic - ret void + atomicrmw xor i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xor_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_xor_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 0), !dbg define void @atomic8_nand_monotonic(i8* %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 monotonic - ret void + atomicrmw nand i8* %a, i8 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_nand_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 0) +; CHECK-LABEL: atomic8_nand_monotonic +; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 0), !dbg define void @atomic8_xchg_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 acquire - ret void + atomicrmw xchg i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xchg_acquire -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_xchg_acquire +; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 2), !dbg define void @atomic8_add_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 acquire - ret void + atomicrmw add i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_add_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_add_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 2), !dbg define void @atomic8_sub_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 acquire - ret void + atomicrmw sub i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_sub_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_sub_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 2), !dbg define void @atomic8_and_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 acquire - ret void + atomicrmw and i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_and_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_and_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 2), !dbg define void @atomic8_or_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 acquire - ret void + atomicrmw or i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_or_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_or_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 2), !dbg define void @atomic8_xor_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 acquire - ret void + atomicrmw xor i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xor_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_xor_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 2), !dbg define void @atomic8_nand_acquire(i8* %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 acquire - ret void + atomicrmw nand i8* %a, i8 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_nand_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 2) +; CHECK-LABEL: atomic8_nand_acquire +; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 2), !dbg define void @atomic8_xchg_release(i8* %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 release - ret void + atomicrmw xchg i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xchg_release -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_xchg_release +; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 3), !dbg define void @atomic8_add_release(i8* %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 release - ret void + atomicrmw add i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_add_release -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_add_release +; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 3), !dbg define void @atomic8_sub_release(i8* %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 release - ret void + atomicrmw sub i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_sub_release -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_sub_release +; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 3), !dbg define void @atomic8_and_release(i8* %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 release - ret void + atomicrmw and i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_and_release -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_and_release +; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 3), !dbg define void @atomic8_or_release(i8* %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 release - ret void + atomicrmw or i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_or_release -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_or_release +; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 3), !dbg define void @atomic8_xor_release(i8* %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 release - ret void + atomicrmw xor i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xor_release -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_xor_release +; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 3), !dbg define void @atomic8_nand_release(i8* %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 release - ret void + atomicrmw nand i8* %a, i8 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_nand_release -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 3) +; CHECK-LABEL: atomic8_nand_release +; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 3), !dbg define void @atomic8_xchg_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 acq_rel - ret void + atomicrmw xchg i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xchg_acq_rel -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_xchg_acq_rel +; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 4), !dbg define void @atomic8_add_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 acq_rel - ret void + atomicrmw add i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_add_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_add_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 4), !dbg define void @atomic8_sub_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 acq_rel - ret void + atomicrmw sub i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_sub_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_sub_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 4), !dbg define void @atomic8_and_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 acq_rel - ret void + atomicrmw and i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_and_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_and_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 4), !dbg define void @atomic8_or_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 acq_rel - ret void + atomicrmw or i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_or_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_or_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 4), !dbg define void @atomic8_xor_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 acq_rel - ret void + atomicrmw xor i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xor_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_xor_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 4), !dbg define void @atomic8_nand_acq_rel(i8* %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 acq_rel - ret void + atomicrmw nand i8* %a, i8 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_nand_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 4) +; CHECK-LABEL: atomic8_nand_acq_rel +; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 4), !dbg define void @atomic8_xchg_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 seq_cst - ret void + atomicrmw xchg i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xchg_seq_cst -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_xchg_seq_cst +; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 5), !dbg define void @atomic8_add_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 seq_cst - ret void + atomicrmw add i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_add_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_add_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 5), !dbg define void @atomic8_sub_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 seq_cst - ret void + atomicrmw sub i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_sub_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_sub_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 5), !dbg define void @atomic8_and_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 seq_cst - ret void + atomicrmw and i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_and_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_and_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 5), !dbg define void @atomic8_or_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 seq_cst - ret void + atomicrmw or i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_or_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_or_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 5), !dbg define void @atomic8_xor_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 seq_cst - ret void + atomicrmw xor i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_xor_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_xor_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 5), !dbg define void @atomic8_nand_seq_cst(i8* %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 seq_cst - ret void + atomicrmw nand i8* %a, i8 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_nand_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 5) +; CHECK-LABEL: atomic8_nand_seq_cst +; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 5), !dbg define void @atomic8_cas_monotonic(i8* %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 monotonic monotonic - ret void + cmpxchg i8* %a, i8 0, i8 1 monotonic monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_cas_monotonic -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 0, i32 0) +; CHECK-LABEL: atomic8_cas_monotonic +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 0, i32 0), !dbg define void @atomic8_cas_acquire(i8* %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 acquire acquire - ret void + cmpxchg i8* %a, i8 0, i8 1 acquire acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_cas_acquire -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 2, i32 2) +; CHECK-LABEL: atomic8_cas_acquire +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 2, i32 2), !dbg define void @atomic8_cas_release(i8* %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 release monotonic - ret void + cmpxchg i8* %a, i8 0, i8 1 release monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_cas_release -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 3, i32 0) +; CHECK-LABEL: atomic8_cas_release +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 3, i32 0), !dbg define void @atomic8_cas_acq_rel(i8* %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire - ret void + cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_cas_acq_rel -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 4, i32 2) +; CHECK-LABEL: atomic8_cas_acq_rel +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 4, i32 2), !dbg define void @atomic8_cas_seq_cst(i8* %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 seq_cst seq_cst - ret void + cmpxchg i8* %a, i8 0, i8 1 seq_cst seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic8_cas_seq_cst -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 5, i32 5) +; CHECK-LABEL: atomic8_cas_seq_cst +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 5, i32 5), !dbg define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a unordered, align 2 - ret i16 %0 + %0 = load atomic i16, i16* %a unordered, align 2, !dbg !7 + ret i16 %0, !dbg !7 } -; CHECK: atomic16_load_unordered -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0) +; CHECK-LABEL: atomic16_load_unordered +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0), !dbg define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a monotonic, align 2 - ret i16 %0 + %0 = load atomic i16, i16* %a monotonic, align 2, !dbg !7 + ret i16 %0, !dbg !7 } -; CHECK: atomic16_load_monotonic -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0) +; CHECK-LABEL: atomic16_load_monotonic +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0), !dbg define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a acquire, align 2 - ret i16 %0 + %0 = load atomic i16, i16* %a acquire, align 2, !dbg !7 + ret i16 %0, !dbg !7 } -; CHECK: atomic16_load_acquire -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 2) +; CHECK-LABEL: atomic16_load_acquire +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 2), !dbg define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a seq_cst, align 2 - ret i16 %0 + %0 = load atomic i16, i16* %a seq_cst, align 2, !dbg !7 + ret i16 %0, !dbg !7 } -; CHECK: atomic16_load_seq_cst -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 5) +; CHECK-LABEL: atomic16_load_seq_cst +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 5), !dbg define void @atomic16_store_unordered(i16* %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a unordered, align 2 - ret void + store atomic i16 0, i16* %a unordered, align 2, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_store_unordered -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_store_unordered +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0), !dbg define void @atomic16_store_monotonic(i16* %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a monotonic, align 2 - ret void + store atomic i16 0, i16* %a monotonic, align 2, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_store_monotonic -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_store_monotonic +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0), !dbg define void @atomic16_store_release(i16* %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a release, align 2 - ret void + store atomic i16 0, i16* %a release, align 2, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_store_release -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_store_release +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 3), !dbg define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a seq_cst, align 2 - ret void + store atomic i16 0, i16* %a seq_cst, align 2, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_store_seq_cst -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_store_seq_cst +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 5), !dbg define void @atomic16_xchg_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 monotonic - ret void + atomicrmw xchg i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xchg_monotonic -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_xchg_monotonic +; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 0), !dbg define void @atomic16_add_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 monotonic - ret void + atomicrmw add i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_add_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_add_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 0), !dbg define void @atomic16_sub_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 monotonic - ret void + atomicrmw sub i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_sub_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_sub_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 0), !dbg define void @atomic16_and_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 monotonic - ret void + atomicrmw and i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_and_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_and_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 0), !dbg define void @atomic16_or_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 monotonic - ret void + atomicrmw or i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_or_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_or_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 0), !dbg define void @atomic16_xor_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 monotonic - ret void + atomicrmw xor i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xor_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_xor_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 0), !dbg define void @atomic16_nand_monotonic(i16* %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 monotonic - ret void + atomicrmw nand i16* %a, i16 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_nand_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 0) +; CHECK-LABEL: atomic16_nand_monotonic +; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 0), !dbg define void @atomic16_xchg_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 acquire - ret void + atomicrmw xchg i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xchg_acquire -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_xchg_acquire +; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 2), !dbg define void @atomic16_add_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 acquire - ret void + atomicrmw add i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_add_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_add_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 2), !dbg define void @atomic16_sub_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 acquire - ret void + atomicrmw sub i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_sub_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_sub_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 2), !dbg define void @atomic16_and_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 acquire - ret void + atomicrmw and i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_and_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_and_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 2), !dbg define void @atomic16_or_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 acquire - ret void + atomicrmw or i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_or_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_or_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 2), !dbg define void @atomic16_xor_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 acquire - ret void + atomicrmw xor i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xor_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_xor_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 2), !dbg define void @atomic16_nand_acquire(i16* %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 acquire - ret void + atomicrmw nand i16* %a, i16 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_nand_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 2) +; CHECK-LABEL: atomic16_nand_acquire +; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 2), !dbg define void @atomic16_xchg_release(i16* %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 release - ret void + atomicrmw xchg i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xchg_release -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_xchg_release +; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 3), !dbg define void @atomic16_add_release(i16* %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 release - ret void + atomicrmw add i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_add_release -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_add_release +; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 3), !dbg define void @atomic16_sub_release(i16* %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 release - ret void + atomicrmw sub i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_sub_release -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_sub_release +; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 3), !dbg define void @atomic16_and_release(i16* %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 release - ret void + atomicrmw and i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_and_release -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_and_release +; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 3), !dbg define void @atomic16_or_release(i16* %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 release - ret void + atomicrmw or i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_or_release -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_or_release +; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 3), !dbg define void @atomic16_xor_release(i16* %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 release - ret void + atomicrmw xor i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xor_release -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_xor_release +; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 3), !dbg define void @atomic16_nand_release(i16* %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 release - ret void + atomicrmw nand i16* %a, i16 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_nand_release -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 3) +; CHECK-LABEL: atomic16_nand_release +; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 3), !dbg define void @atomic16_xchg_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 acq_rel - ret void + atomicrmw xchg i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xchg_acq_rel -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_xchg_acq_rel +; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 4), !dbg define void @atomic16_add_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 acq_rel - ret void + atomicrmw add i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_add_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_add_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 4), !dbg define void @atomic16_sub_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 acq_rel - ret void + atomicrmw sub i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_sub_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_sub_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 4), !dbg define void @atomic16_and_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 acq_rel - ret void + atomicrmw and i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_and_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_and_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 4), !dbg define void @atomic16_or_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 acq_rel - ret void + atomicrmw or i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_or_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_or_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 4), !dbg define void @atomic16_xor_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 acq_rel - ret void + atomicrmw xor i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xor_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_xor_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 4), !dbg define void @atomic16_nand_acq_rel(i16* %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 acq_rel - ret void + atomicrmw nand i16* %a, i16 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_nand_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 4) +; CHECK-LABEL: atomic16_nand_acq_rel +; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 4), !dbg define void @atomic16_xchg_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 seq_cst - ret void + atomicrmw xchg i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xchg_seq_cst -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_xchg_seq_cst +; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 5), !dbg define void @atomic16_add_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 seq_cst - ret void + atomicrmw add i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_add_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_add_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 5), !dbg define void @atomic16_sub_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 seq_cst - ret void + atomicrmw sub i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_sub_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_sub_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 5), !dbg define void @atomic16_and_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 seq_cst - ret void + atomicrmw and i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_and_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_and_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 5), !dbg define void @atomic16_or_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 seq_cst - ret void + atomicrmw or i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_or_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_or_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 5), !dbg define void @atomic16_xor_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 seq_cst - ret void + atomicrmw xor i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_xor_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_xor_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 5), !dbg define void @atomic16_nand_seq_cst(i16* %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 seq_cst - ret void + atomicrmw nand i16* %a, i16 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_nand_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 5) +; CHECK-LABEL: atomic16_nand_seq_cst +; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 5), !dbg define void @atomic16_cas_monotonic(i16* %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 monotonic monotonic - ret void + cmpxchg i16* %a, i16 0, i16 1 monotonic monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_cas_monotonic -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 0, i32 0) +; CHECK-LABEL: atomic16_cas_monotonic +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 0, i32 0), !dbg define void @atomic16_cas_acquire(i16* %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 acquire acquire - ret void + cmpxchg i16* %a, i16 0, i16 1 acquire acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_cas_acquire -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 2, i32 2) +; CHECK-LABEL: atomic16_cas_acquire +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 2, i32 2), !dbg define void @atomic16_cas_release(i16* %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 release monotonic - ret void + cmpxchg i16* %a, i16 0, i16 1 release monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_cas_release -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 3, i32 0) +; CHECK-LABEL: atomic16_cas_release +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 3, i32 0), !dbg define void @atomic16_cas_acq_rel(i16* %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 acq_rel acquire - ret void + cmpxchg i16* %a, i16 0, i16 1 acq_rel acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_cas_acq_rel -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 4, i32 2) +; CHECK-LABEL: atomic16_cas_acq_rel +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 4, i32 2), !dbg define void @atomic16_cas_seq_cst(i16* %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 seq_cst seq_cst - ret void + cmpxchg i16* %a, i16 0, i16 1 seq_cst seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic16_cas_seq_cst -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 5, i32 5) +; CHECK-LABEL: atomic16_cas_seq_cst +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 5, i32 5), !dbg define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a unordered, align 4 - ret i32 %0 + %0 = load atomic i32, i32* %a unordered, align 4, !dbg !7 + ret i32 %0, !dbg !7 } -; CHECK: atomic32_load_unordered -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0) +; CHECK-LABEL: atomic32_load_unordered +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0), !dbg define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a monotonic, align 4 - ret i32 %0 + %0 = load atomic i32, i32* %a monotonic, align 4, !dbg !7 + ret i32 %0, !dbg !7 } -; CHECK: atomic32_load_monotonic -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0) +; CHECK-LABEL: atomic32_load_monotonic +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0), !dbg define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a acquire, align 4 - ret i32 %0 + %0 = load atomic i32, i32* %a acquire, align 4, !dbg !7 + ret i32 %0, !dbg !7 } -; CHECK: atomic32_load_acquire -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 2) +; CHECK-LABEL: atomic32_load_acquire +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 2), !dbg define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a seq_cst, align 4 - ret i32 %0 + %0 = load atomic i32, i32* %a seq_cst, align 4, !dbg !7 + ret i32 %0, !dbg !7 } -; CHECK: atomic32_load_seq_cst -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 5) +; CHECK-LABEL: atomic32_load_seq_cst +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 5), !dbg define void @atomic32_store_unordered(i32* %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a unordered, align 4 - ret void + store atomic i32 0, i32* %a unordered, align 4, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_store_unordered -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_store_unordered +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0), !dbg define void @atomic32_store_monotonic(i32* %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a monotonic, align 4 - ret void + store atomic i32 0, i32* %a monotonic, align 4, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_store_monotonic -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_store_monotonic +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0), !dbg define void @atomic32_store_release(i32* %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a release, align 4 - ret void + store atomic i32 0, i32* %a release, align 4, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_store_release -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_store_release +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 3), !dbg define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a seq_cst, align 4 - ret void + store atomic i32 0, i32* %a seq_cst, align 4, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_store_seq_cst -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_store_seq_cst +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 5), !dbg define void @atomic32_xchg_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 monotonic - ret void + atomicrmw xchg i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xchg_monotonic -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_xchg_monotonic +; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 0), !dbg define void @atomic32_add_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 monotonic - ret void + atomicrmw add i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_add_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_add_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 0), !dbg define void @atomic32_sub_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 monotonic - ret void + atomicrmw sub i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_sub_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_sub_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 0), !dbg define void @atomic32_and_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 monotonic - ret void + atomicrmw and i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_and_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_and_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 0), !dbg define void @atomic32_or_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 monotonic - ret void + atomicrmw or i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_or_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_or_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 0), !dbg define void @atomic32_xor_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 monotonic - ret void + atomicrmw xor i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xor_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_xor_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 0), !dbg define void @atomic32_nand_monotonic(i32* %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 monotonic - ret void + atomicrmw nand i32* %a, i32 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_nand_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 0) +; CHECK-LABEL: atomic32_nand_monotonic +; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 0), !dbg define void @atomic32_xchg_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 acquire - ret void + atomicrmw xchg i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xchg_acquire -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_xchg_acquire +; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 2), !dbg define void @atomic32_add_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 acquire - ret void + atomicrmw add i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_add_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_add_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 2), !dbg define void @atomic32_sub_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 acquire - ret void + atomicrmw sub i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_sub_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_sub_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 2), !dbg define void @atomic32_and_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 acquire - ret void + atomicrmw and i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_and_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_and_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 2), !dbg define void @atomic32_or_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 acquire - ret void + atomicrmw or i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_or_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_or_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 2), !dbg define void @atomic32_xor_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 acquire - ret void + atomicrmw xor i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xor_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_xor_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 2), !dbg define void @atomic32_nand_acquire(i32* %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 acquire - ret void + atomicrmw nand i32* %a, i32 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_nand_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 2) +; CHECK-LABEL: atomic32_nand_acquire +; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 2), !dbg define void @atomic32_xchg_release(i32* %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 release - ret void + atomicrmw xchg i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xchg_release -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_xchg_release +; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 3), !dbg define void @atomic32_add_release(i32* %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 release - ret void + atomicrmw add i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_add_release -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_add_release +; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 3), !dbg define void @atomic32_sub_release(i32* %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 release - ret void + atomicrmw sub i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_sub_release -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_sub_release +; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 3), !dbg define void @atomic32_and_release(i32* %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 release - ret void + atomicrmw and i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_and_release -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_and_release +; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 3), !dbg define void @atomic32_or_release(i32* %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 release - ret void + atomicrmw or i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_or_release -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_or_release +; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 3), !dbg define void @atomic32_xor_release(i32* %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 release - ret void + atomicrmw xor i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xor_release -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_xor_release +; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 3), !dbg define void @atomic32_nand_release(i32* %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 release - ret void + atomicrmw nand i32* %a, i32 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_nand_release -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 3) +; CHECK-LABEL: atomic32_nand_release +; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 3), !dbg define void @atomic32_xchg_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 acq_rel - ret void + atomicrmw xchg i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xchg_acq_rel -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_xchg_acq_rel +; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 4), !dbg define void @atomic32_add_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 acq_rel - ret void + atomicrmw add i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_add_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_add_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 4), !dbg define void @atomic32_sub_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 acq_rel - ret void + atomicrmw sub i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_sub_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_sub_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 4), !dbg define void @atomic32_and_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 acq_rel - ret void + atomicrmw and i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_and_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_and_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 4), !dbg define void @atomic32_or_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 acq_rel - ret void + atomicrmw or i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_or_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_or_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 4), !dbg define void @atomic32_xor_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 acq_rel - ret void + atomicrmw xor i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xor_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_xor_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 4), !dbg define void @atomic32_nand_acq_rel(i32* %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 acq_rel - ret void + atomicrmw nand i32* %a, i32 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_nand_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 4) +; CHECK-LABEL: atomic32_nand_acq_rel +; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 4), !dbg define void @atomic32_xchg_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 seq_cst - ret void + atomicrmw xchg i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xchg_seq_cst -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_xchg_seq_cst +; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 5), !dbg define void @atomic32_add_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 seq_cst - ret void + atomicrmw add i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_add_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_add_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 5), !dbg define void @atomic32_sub_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 seq_cst - ret void + atomicrmw sub i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_sub_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_sub_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 5), !dbg define void @atomic32_and_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 seq_cst - ret void + atomicrmw and i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_and_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_and_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 5), !dbg define void @atomic32_or_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 seq_cst - ret void + atomicrmw or i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_or_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_or_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 5), !dbg define void @atomic32_xor_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 seq_cst - ret void + atomicrmw xor i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_xor_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_xor_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 5), !dbg define void @atomic32_nand_seq_cst(i32* %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 seq_cst - ret void + atomicrmw nand i32* %a, i32 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_nand_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 5) +; CHECK-LABEL: atomic32_nand_seq_cst +; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 5), !dbg define void @atomic32_cas_monotonic(i32* %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 monotonic monotonic - ret void + cmpxchg i32* %a, i32 0, i32 1 monotonic monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_cas_monotonic -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 0, i32 0) +; CHECK-LABEL: atomic32_cas_monotonic +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 0, i32 0), !dbg define void @atomic32_cas_acquire(i32* %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 acquire acquire - ret void + cmpxchg i32* %a, i32 0, i32 1 acquire acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_cas_acquire -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 2, i32 2) +; CHECK-LABEL: atomic32_cas_acquire +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 2, i32 2), !dbg define void @atomic32_cas_release(i32* %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 release monotonic - ret void + cmpxchg i32* %a, i32 0, i32 1 release monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_cas_release -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 3, i32 0) +; CHECK-LABEL: atomic32_cas_release +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 3, i32 0), !dbg define void @atomic32_cas_acq_rel(i32* %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 acq_rel acquire - ret void + cmpxchg i32* %a, i32 0, i32 1 acq_rel acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_cas_acq_rel -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 4, i32 2) +; CHECK-LABEL: atomic32_cas_acq_rel +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 4, i32 2), !dbg define void @atomic32_cas_seq_cst(i32* %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 seq_cst seq_cst - ret void + cmpxchg i32* %a, i32 0, i32 1 seq_cst seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic32_cas_seq_cst -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 5, i32 5) +; CHECK-LABEL: atomic32_cas_seq_cst +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 5, i32 5), !dbg define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a unordered, align 8 - ret i64 %0 + %0 = load atomic i64, i64* %a unordered, align 8, !dbg !7 + ret i64 %0, !dbg !7 } -; CHECK: atomic64_load_unordered -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0) +; CHECK-LABEL: atomic64_load_unordered +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0), !dbg define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a monotonic, align 8 - ret i64 %0 + %0 = load atomic i64, i64* %a monotonic, align 8, !dbg !7 + ret i64 %0, !dbg !7 } -; CHECK: atomic64_load_monotonic -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0) +; CHECK-LABEL: atomic64_load_monotonic +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0), !dbg define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a acquire, align 8 - ret i64 %0 + %0 = load atomic i64, i64* %a acquire, align 8, !dbg !7 + ret i64 %0, !dbg !7 } -; CHECK: atomic64_load_acquire -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 2) +; CHECK-LABEL: atomic64_load_acquire +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 2), !dbg define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a seq_cst, align 8 - ret i64 %0 + %0 = load atomic i64, i64* %a seq_cst, align 8, !dbg !7 + ret i64 %0, !dbg !7 } -; CHECK: atomic64_load_seq_cst -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 5) +; CHECK-LABEL: atomic64_load_seq_cst +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 5), !dbg define void @atomic64_store_unordered(i64* %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a unordered, align 8 - ret void + store atomic i64 0, i64* %a unordered, align 8, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_store_unordered -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_store_unordered +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0), !dbg define void @atomic64_store_monotonic(i64* %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a monotonic, align 8 - ret void + store atomic i64 0, i64* %a monotonic, align 8, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_store_monotonic -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_store_monotonic +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0), !dbg define void @atomic64_store_release(i64* %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a release, align 8 - ret void + store atomic i64 0, i64* %a release, align 8, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_store_release -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_store_release +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 3), !dbg define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a seq_cst, align 8 - ret void + store atomic i64 0, i64* %a seq_cst, align 8, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_store_seq_cst -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_store_seq_cst +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 5), !dbg define void @atomic64_xchg_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 monotonic - ret void + atomicrmw xchg i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xchg_monotonic -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_xchg_monotonic +; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 0), !dbg define void @atomic64_add_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 monotonic - ret void + atomicrmw add i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_add_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_add_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 0), !dbg define void @atomic64_sub_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 monotonic - ret void + atomicrmw sub i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_sub_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_sub_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 0), !dbg define void @atomic64_and_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 monotonic - ret void + atomicrmw and i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_and_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_and_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 0), !dbg define void @atomic64_or_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 monotonic - ret void + atomicrmw or i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_or_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_or_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 0), !dbg define void @atomic64_xor_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 monotonic - ret void + atomicrmw xor i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xor_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_xor_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 0), !dbg define void @atomic64_nand_monotonic(i64* %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 monotonic - ret void + atomicrmw nand i64* %a, i64 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_nand_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 0) +; CHECK-LABEL: atomic64_nand_monotonic +; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 0), !dbg define void @atomic64_xchg_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 acquire - ret void + atomicrmw xchg i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xchg_acquire -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_xchg_acquire +; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 2), !dbg define void @atomic64_add_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 acquire - ret void + atomicrmw add i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_add_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_add_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 2), !dbg define void @atomic64_sub_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 acquire - ret void + atomicrmw sub i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_sub_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_sub_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 2), !dbg define void @atomic64_and_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 acquire - ret void + atomicrmw and i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_and_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_and_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 2), !dbg define void @atomic64_or_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 acquire - ret void + atomicrmw or i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_or_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_or_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 2), !dbg define void @atomic64_xor_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 acquire - ret void + atomicrmw xor i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xor_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_xor_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 2), !dbg define void @atomic64_nand_acquire(i64* %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 acquire - ret void + atomicrmw nand i64* %a, i64 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_nand_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 2) +; CHECK-LABEL: atomic64_nand_acquire +; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 2), !dbg define void @atomic64_xchg_release(i64* %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 release - ret void + atomicrmw xchg i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xchg_release -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_xchg_release +; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 3), !dbg define void @atomic64_add_release(i64* %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 release - ret void + atomicrmw add i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_add_release -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_add_release +; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 3), !dbg define void @atomic64_sub_release(i64* %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 release - ret void + atomicrmw sub i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_sub_release -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_sub_release +; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 3), !dbg define void @atomic64_and_release(i64* %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 release - ret void + atomicrmw and i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_and_release -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_and_release +; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 3), !dbg define void @atomic64_or_release(i64* %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 release - ret void + atomicrmw or i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_or_release -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_or_release +; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 3), !dbg define void @atomic64_xor_release(i64* %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 release - ret void + atomicrmw xor i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xor_release -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_xor_release +; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 3), !dbg define void @atomic64_nand_release(i64* %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 release - ret void + atomicrmw nand i64* %a, i64 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_nand_release -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 3) +; CHECK-LABEL: atomic64_nand_release +; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 3), !dbg define void @atomic64_xchg_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 acq_rel - ret void + atomicrmw xchg i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xchg_acq_rel -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_xchg_acq_rel +; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 4), !dbg define void @atomic64_add_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 acq_rel - ret void + atomicrmw add i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_add_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_add_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 4), !dbg define void @atomic64_sub_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 acq_rel - ret void + atomicrmw sub i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_sub_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_sub_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 4), !dbg define void @atomic64_and_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 acq_rel - ret void + atomicrmw and i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_and_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_and_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 4), !dbg define void @atomic64_or_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 acq_rel - ret void + atomicrmw or i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_or_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_or_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 4), !dbg define void @atomic64_xor_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 acq_rel - ret void + atomicrmw xor i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xor_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_xor_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 4), !dbg define void @atomic64_nand_acq_rel(i64* %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 acq_rel - ret void + atomicrmw nand i64* %a, i64 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_nand_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 4) +; CHECK-LABEL: atomic64_nand_acq_rel +; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 4), !dbg define void @atomic64_xchg_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 seq_cst - ret void + atomicrmw xchg i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xchg_seq_cst -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_xchg_seq_cst +; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 5), !dbg define void @atomic64_add_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 seq_cst - ret void + atomicrmw add i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_add_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_add_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 5), !dbg define void @atomic64_sub_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 seq_cst - ret void + atomicrmw sub i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_sub_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_sub_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 5), !dbg define void @atomic64_and_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 seq_cst - ret void + atomicrmw and i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_and_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_and_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 5), !dbg define void @atomic64_or_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 seq_cst - ret void + atomicrmw or i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_or_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_or_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 5), !dbg define void @atomic64_xor_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 seq_cst - ret void + atomicrmw xor i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_xor_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_xor_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 5), !dbg define void @atomic64_nand_seq_cst(i64* %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 seq_cst - ret void + atomicrmw nand i64* %a, i64 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_nand_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 5) +; CHECK-LABEL: atomic64_nand_seq_cst +; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 5), !dbg define void @atomic64_cas_monotonic(i64* %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 monotonic monotonic - ret void + cmpxchg i64* %a, i64 0, i64 1 monotonic monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_cas_monotonic -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 0, i32 0) +; CHECK-LABEL: atomic64_cas_monotonic +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 0, i32 0), !dbg define void @atomic64_cas_acquire(i64* %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 acquire acquire - ret void + cmpxchg i64* %a, i64 0, i64 1 acquire acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_cas_acquire -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 2, i32 2) +; CHECK-LABEL: atomic64_cas_acquire +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 2, i32 2), !dbg define void @atomic64_cas_release(i64* %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 release monotonic - ret void + cmpxchg i64* %a, i64 0, i64 1 release monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_cas_release -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 3, i32 0) +; CHECK-LABEL: atomic64_cas_release +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 3, i32 0), !dbg define void @atomic64_cas_acq_rel(i64* %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 acq_rel acquire - ret void + cmpxchg i64* %a, i64 0, i64 1 acq_rel acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_cas_acq_rel -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 4, i32 2) +; CHECK-LABEL: atomic64_cas_acq_rel +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 4, i32 2), !dbg define void @atomic64_cas_seq_cst(i64* %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 seq_cst seq_cst - ret void + cmpxchg i64* %a, i64 0, i64 1 seq_cst seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic64_cas_seq_cst -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 5, i32 5) +; CHECK-LABEL: atomic64_cas_seq_cst +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 5, i32 5), !dbg define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a unordered, align 16 - ret i128 %0 + %0 = load atomic i128, i128* %a unordered, align 16, !dbg !7 + ret i128 %0, !dbg !7 } -; CHECK: atomic128_load_unordered -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0) +; CHECK-LABEL: atomic128_load_unordered +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0), !dbg define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a monotonic, align 16 - ret i128 %0 + %0 = load atomic i128, i128* %a monotonic, align 16, !dbg !7 + ret i128 %0, !dbg !7 } -; CHECK: atomic128_load_monotonic -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0) +; CHECK-LABEL: atomic128_load_monotonic +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0), !dbg define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a acquire, align 16 - ret i128 %0 + %0 = load atomic i128, i128* %a acquire, align 16, !dbg !7 + ret i128 %0, !dbg !7 } -; CHECK: atomic128_load_acquire -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 2) +; CHECK-LABEL: atomic128_load_acquire +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 2), !dbg define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a seq_cst, align 16 - ret i128 %0 + %0 = load atomic i128, i128* %a seq_cst, align 16, !dbg !7 + ret i128 %0, !dbg !7 } -; CHECK: atomic128_load_seq_cst -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 5) +; CHECK-LABEL: atomic128_load_seq_cst +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 5), !dbg define void @atomic128_store_unordered(i128* %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a unordered, align 16 - ret void + store atomic i128 0, i128* %a unordered, align 16, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_store_unordered -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_store_unordered +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0), !dbg define void @atomic128_store_monotonic(i128* %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a monotonic, align 16 - ret void + store atomic i128 0, i128* %a monotonic, align 16, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_store_monotonic -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_store_monotonic +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0), !dbg define void @atomic128_store_release(i128* %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a release, align 16 - ret void + store atomic i128 0, i128* %a release, align 16, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_store_release -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_store_release +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 3), !dbg define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a seq_cst, align 16 - ret void + store atomic i128 0, i128* %a seq_cst, align 16, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_store_seq_cst -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_store_seq_cst +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 5), !dbg define void @atomic128_xchg_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 monotonic - ret void + atomicrmw xchg i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xchg_monotonic -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_xchg_monotonic +; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 0), !dbg define void @atomic128_add_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 monotonic - ret void + atomicrmw add i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_add_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_add_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 0), !dbg define void @atomic128_sub_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 monotonic - ret void + atomicrmw sub i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_sub_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_sub_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 0), !dbg define void @atomic128_and_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 monotonic - ret void + atomicrmw and i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_and_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_and_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 0), !dbg define void @atomic128_or_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 monotonic - ret void + atomicrmw or i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_or_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_or_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 0), !dbg define void @atomic128_xor_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 monotonic - ret void + atomicrmw xor i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xor_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_xor_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 0), !dbg define void @atomic128_nand_monotonic(i128* %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 monotonic - ret void + atomicrmw nand i128* %a, i128 0 monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_nand_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 0) +; CHECK-LABEL: atomic128_nand_monotonic +; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 0), !dbg define void @atomic128_xchg_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 acquire - ret void + atomicrmw xchg i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xchg_acquire -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_xchg_acquire +; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 2), !dbg define void @atomic128_add_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 acquire - ret void + atomicrmw add i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_add_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_add_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 2), !dbg define void @atomic128_sub_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 acquire - ret void + atomicrmw sub i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_sub_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_sub_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 2), !dbg define void @atomic128_and_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 acquire - ret void + atomicrmw and i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_and_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_and_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 2), !dbg define void @atomic128_or_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 acquire - ret void + atomicrmw or i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_or_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_or_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 2), !dbg define void @atomic128_xor_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 acquire - ret void + atomicrmw xor i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xor_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_xor_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 2), !dbg define void @atomic128_nand_acquire(i128* %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 acquire - ret void + atomicrmw nand i128* %a, i128 0 acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_nand_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 2) +; CHECK-LABEL: atomic128_nand_acquire +; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 2), !dbg define void @atomic128_xchg_release(i128* %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 release - ret void + atomicrmw xchg i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xchg_release -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_xchg_release +; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 3), !dbg define void @atomic128_add_release(i128* %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 release - ret void + atomicrmw add i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_add_release -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_add_release +; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 3), !dbg define void @atomic128_sub_release(i128* %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 release - ret void + atomicrmw sub i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_sub_release -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_sub_release +; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 3), !dbg define void @atomic128_and_release(i128* %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 release - ret void + atomicrmw and i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_and_release -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_and_release +; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 3), !dbg define void @atomic128_or_release(i128* %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 release - ret void + atomicrmw or i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_or_release -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_or_release +; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 3), !dbg define void @atomic128_xor_release(i128* %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 release - ret void + atomicrmw xor i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xor_release -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_xor_release +; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 3), !dbg define void @atomic128_nand_release(i128* %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 release - ret void + atomicrmw nand i128* %a, i128 0 release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_nand_release -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 3) +; CHECK-LABEL: atomic128_nand_release +; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 3), !dbg define void @atomic128_xchg_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 acq_rel - ret void + atomicrmw xchg i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xchg_acq_rel -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_xchg_acq_rel +; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 4), !dbg define void @atomic128_add_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 acq_rel - ret void + atomicrmw add i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_add_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_add_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 4), !dbg define void @atomic128_sub_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 acq_rel - ret void + atomicrmw sub i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_sub_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_sub_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 4), !dbg define void @atomic128_and_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 acq_rel - ret void + atomicrmw and i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_and_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_and_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 4), !dbg define void @atomic128_or_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 acq_rel - ret void + atomicrmw or i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_or_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_or_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 4), !dbg define void @atomic128_xor_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 acq_rel - ret void + atomicrmw xor i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xor_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_xor_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 4), !dbg define void @atomic128_nand_acq_rel(i128* %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 acq_rel - ret void + atomicrmw nand i128* %a, i128 0 acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_nand_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 4) +; CHECK-LABEL: atomic128_nand_acq_rel +; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 4), !dbg define void @atomic128_xchg_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 seq_cst - ret void + atomicrmw xchg i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xchg_seq_cst -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_xchg_seq_cst +; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 5), !dbg define void @atomic128_add_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 seq_cst - ret void + atomicrmw add i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_add_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_add_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 5), !dbg define void @atomic128_sub_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 seq_cst - ret void + atomicrmw sub i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_sub_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_sub_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 5), !dbg define void @atomic128_and_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 seq_cst - ret void + atomicrmw and i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_and_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_and_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 5), !dbg define void @atomic128_or_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 seq_cst - ret void + atomicrmw or i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_or_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_or_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 5), !dbg define void @atomic128_xor_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 seq_cst - ret void + atomicrmw xor i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_xor_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_xor_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 5), !dbg define void @atomic128_nand_seq_cst(i128* %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 seq_cst - ret void + atomicrmw nand i128* %a, i128 0 seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_nand_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 5) +; CHECK-LABEL: atomic128_nand_seq_cst +; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 5), !dbg define void @atomic128_cas_monotonic(i128* %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 monotonic monotonic - ret void + cmpxchg i128* %a, i128 0, i128 1 monotonic monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_cas_monotonic -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 0, i32 0) +; CHECK-LABEL: atomic128_cas_monotonic +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 0, i32 0), !dbg define void @atomic128_cas_acquire(i128* %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 acquire acquire - ret void + cmpxchg i128* %a, i128 0, i128 1 acquire acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_cas_acquire -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 2, i32 2) +; CHECK-LABEL: atomic128_cas_acquire +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 2, i32 2), !dbg define void @atomic128_cas_release(i128* %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 release monotonic - ret void + cmpxchg i128* %a, i128 0, i128 1 release monotonic, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_cas_release -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 3, i32 0) +; CHECK-LABEL: atomic128_cas_release +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 3, i32 0), !dbg define void @atomic128_cas_acq_rel(i128* %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 acq_rel acquire - ret void + cmpxchg i128* %a, i128 0, i128 1 acq_rel acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_cas_acq_rel -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 4, i32 2) +; CHECK-LABEL: atomic128_cas_acq_rel +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 4, i32 2), !dbg define void @atomic128_cas_seq_cst(i128* %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 seq_cst seq_cst - ret void + cmpxchg i128* %a, i128 0, i128 1 seq_cst seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic128_cas_seq_cst -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 5, i32 5) +; CHECK-LABEL: atomic128_cas_seq_cst +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 5, i32 5), !dbg define void @atomic_signal_fence_acquire() nounwind uwtable { entry: - fence singlethread acquire - ret void + fence singlethread acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_signal_fence_acquire -; CHECK: call void @__tsan_atomic_signal_fence(i32 2) +; CHECK-LABEL: atomic_signal_fence_acquire +; CHECK: call void @__tsan_atomic_signal_fence(i32 2), !dbg define void @atomic_thread_fence_acquire() nounwind uwtable { entry: - fence acquire - ret void + fence acquire, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_thread_fence_acquire -; CHECK: call void @__tsan_atomic_thread_fence(i32 2) +; CHECK-LABEL: atomic_thread_fence_acquire +; CHECK: call void @__tsan_atomic_thread_fence(i32 2), !dbg define void @atomic_signal_fence_release() nounwind uwtable { entry: - fence singlethread release - ret void + fence singlethread release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_signal_fence_release -; CHECK: call void @__tsan_atomic_signal_fence(i32 3) +; CHECK-LABEL: atomic_signal_fence_release +; CHECK: call void @__tsan_atomic_signal_fence(i32 3), !dbg define void @atomic_thread_fence_release() nounwind uwtable { entry: - fence release - ret void + fence release, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_thread_fence_release -; CHECK: call void @__tsan_atomic_thread_fence(i32 3) +; CHECK-LABEL: atomic_thread_fence_release +; CHECK: call void @__tsan_atomic_thread_fence(i32 3), !dbg define void @atomic_signal_fence_acq_rel() nounwind uwtable { entry: - fence singlethread acq_rel - ret void + fence singlethread acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_signal_fence_acq_rel -; CHECK: call void @__tsan_atomic_signal_fence(i32 4) +; CHECK-LABEL: atomic_signal_fence_acq_rel +; CHECK: call void @__tsan_atomic_signal_fence(i32 4), !dbg define void @atomic_thread_fence_acq_rel() nounwind uwtable { entry: - fence acq_rel - ret void + fence acq_rel, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_thread_fence_acq_rel -; CHECK: call void @__tsan_atomic_thread_fence(i32 4) +; CHECK-LABEL: atomic_thread_fence_acq_rel +; CHECK: call void @__tsan_atomic_thread_fence(i32 4), !dbg define void @atomic_signal_fence_seq_cst() nounwind uwtable { entry: - fence singlethread seq_cst - ret void + fence singlethread seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_signal_fence_seq_cst -; CHECK: call void @__tsan_atomic_signal_fence(i32 5) +; CHECK-LABEL: atomic_signal_fence_seq_cst +; CHECK: call void @__tsan_atomic_signal_fence(i32 5), !dbg define void @atomic_thread_fence_seq_cst() nounwind uwtable { entry: - fence seq_cst - ret void + fence seq_cst, !dbg !7 + ret void, !dbg !7 } -; CHECK: atomic_thread_fence_seq_cst -; CHECK: call void @__tsan_atomic_thread_fence(i32 5) +; CHECK-LABEL: atomic_thread_fence_seq_cst +; CHECK: call void @__tsan_atomic_thread_fence(i32 5), !dbg + +!llvm.module.flags = !{!0, !1, !2} +!0 = !{i32 2, !"Dwarf Version", i32 4} +!1 = !{i32 2, !"Debug Info Version", i32 3} +!2 = !{i32 1, !"PIC Level", i32 2} + +!3 = !{} +!4 = !DISubroutineType(types: !3) +!5 = !DIFile(filename: "atomic.cpp", directory: "/tmp") +!6 = !DISubprogram(name: "test", scope: !5, file: !5, line: 99, type: !4, isLocal: false, isDefinition: true, scopeLine: 100, flags: DIFlagPrototyped, isOptimized: false, variables: !3) +!7 = !DILocation(line: 100, column: 1, scope: !6) diff --git a/test/Linker/comdat10.ll b/test/Linker/comdat10.ll new file mode 100644 index 0000000000000..8a32c4267393e --- /dev/null +++ b/test/Linker/comdat10.ll @@ -0,0 +1,6 @@ +; RUN: llvm-link %s /dev/null -S -o - | FileCheck %s + +$c = comdat largest + +; CHECK: @c = global i32 0, comdat +@c = global i32 0, comdat diff --git a/test/MC/AArch64/alias-addsubimm.s b/test/MC/AArch64/alias-addsubimm.s new file mode 100644 index 0000000000000..75e0a185572e0 --- /dev/null +++ b/test/MC/AArch64/alias-addsubimm.s @@ -0,0 +1,94 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s + +// CHECK: sub w0, w2, #2, lsl #12 +// CHECK: sub w0, w2, #2, lsl #12 + sub w0, w2, #2, lsl 12 + add w0, w2, #-2, lsl 12 +// CHECK: sub x1, x3, #2, lsl #12 +// CHECK: sub x1, x3, #2, lsl #12 + sub x1, x3, #2, lsl 12 + add x1, x3, #-2, lsl 12 +// CHECK: sub x1, x3, #4 +// CHECK: sub x1, x3, #4 + sub x1, x3, #4 + add x1, x3, #-4 +// CHECK: sub x1, x3, #4095 +// CHECK: sub x1, x3, #4095 + sub x1, x3, #4095, lsl 0 + add x1, x3, #-4095, lsl 0 +// CHECK: sub x3, x4, #0 + sub x3, x4, #0 + +// CHECK: add w0, w2, #2, lsl #12 +// CHECK: add w0, w2, #2, lsl #12 + add w0, w2, #2, lsl 12 + sub w0, w2, #-2, lsl 12 +// CHECK: add x1, x3, #2, lsl #12 +// CHECK: add x1, x3, #2, lsl #12 + add x1, x3, #2, lsl 12 + sub x1, x3, #-2, lsl 12 +// CHECK: add x1, x3, #4 +// CHECK: add x1, x3, #4 + add x1, x3, #4 + sub x1, x3, #-4 +// CHECK: add x1, x3, #4095 +// CHECK: add x1, x3, #4095 + add x1, x3, #4095, lsl 0 + sub x1, x3, #-4095, lsl 0 +// CHECK: add x2, x5, #0 + add x2, x5, #0 + +// CHECK: subs w0, w2, #2, lsl #12 +// CHECK: subs w0, w2, #2, lsl #12 + subs w0, w2, #2, lsl 12 + adds w0, w2, #-2, lsl 12 +// CHECK: subs x1, x3, #2, lsl #12 +// CHECK: subs x1, x3, #2, lsl #12 + subs x1, x3, #2, lsl 12 + adds x1, x3, #-2, lsl 12 +// CHECK: subs x1, x3, #4 +// CHECK: subs x1, x3, #4 + subs x1, x3, #4 + adds x1, x3, #-4 +// CHECK: subs x1, x3, #4095 +// CHECK: subs x1, x3, #4095 + subs x1, x3, #4095, lsl 0 + adds x1, x3, #-4095, lsl 0 +// CHECK: subs x3, x4, #0 + subs x3, x4, #0 + +// CHECK: adds w0, w2, #2, lsl #12 +// CHECK: adds w0, w2, #2, lsl #12 + adds w0, w2, #2, lsl 12 + subs w0, w2, #-2, lsl 12 +// CHECK: adds x1, x3, #2, lsl #12 +// CHECK: adds x1, x3, #2, lsl #12 + adds x1, x3, #2, lsl 12 + subs x1, x3, #-2, lsl 12 +// CHECK: adds x1, x3, #4 +// CHECK: adds x1, x3, #4 + adds x1, x3, #4 + subs x1, x3, #-4 +// CHECK: adds x1, x3, #4095 +// CHECK: adds x1, x3, #4095 + adds x1, x3, #4095, lsl 0 + subs x1, x3, #-4095, lsl 0 +// CHECK: adds x2, x5, #0 + adds x2, x5, #0 + +// CHECK: {{adds xzr,|cmn}} x5, #5 +// CHECK: {{adds xzr,|cmn}} x5, #5 + cmn x5, #5 + cmp x5, #-5 +// CHECK: {{subs xzr,|cmp}} x6, #4095 +// CHECK: {{subs xzr,|cmp}} x6, #4095 + cmp x6, #4095 + cmn x6, #-4095 +// CHECK: {{adds wzr,|cmn}} w7, #5 +// CHECK: {{adds wzr,|cmn}} w7, #5 + cmn w7, #5 + cmp w7, #-5 +// CHECK: {{subs wzr,|cmp}} w8, #4095 +// CHECK: {{subs wzr,|cmp}} w8, #4095 + cmp w8, #4095 + cmn w8, #-4095 diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index bf7db132b44ab..0c2bc689663c8 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -75,19 +75,19 @@ // Add/sub (immediate) //------------------------------------------------------------------------------ -// Out of range immediates: < 0 or more than 12 bits - add w4, w5, #-1 +// Out of range immediates: more than 12 bits + add w4, w5, #-4096 add w5, w6, #0x1000 - add w4, w5, #-1, lsl #12 + add w4, w5, #-4096, lsl #12 add w5, w6, #0x1000, lsl #12 // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: add w4, w5, #-1 +// CHECK-ERROR-NEXT: add w4, w5, #-4096 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-AARCH64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-AARCH64-NEXT: add w5, w6, #0x1000 // CHECK-ERROR-AARCH64-NEXT: ^ // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: add w4, w5, #-1, lsl #12 +// CHECK-ERROR-NEXT: add w4, w5, #-4096, lsl #12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w5, w6, #0x1000, lsl #12 diff --git a/test/MC/AMDGPU/hsa.s b/test/MC/AMDGPU/hsa.s new file mode 100644 index 0000000000000..7dfea0fe787e7 --- /dev/null +++ b/test/MC/AMDGPU/hsa.s @@ -0,0 +1,233 @@ +// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM +// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF + +// ELF: SHT_NOTE +// ELF: 0000: 04000000 08000000 01000000 414D4400 +// ELF: 0010: 01000000 00000000 04000000 1B000000 +// ELF: 0020: 03000000 414D4400 04000700 07000000 +// ELF: 0030: 00000000 00000000 414D4400 414D4447 +// ELF: 0040: 50550000 + +.hsa_code_object_version 1,0 +// ASM: .hsa_code_object_version 1,0 + +.hsa_code_object_isa 7,0,0,"AMD","AMDGPU" +// ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" + +.text +amd_kernel_code_t_test_all: +; Test all amd_kernel_code_t members with non-default values. +.amd_kernel_code_t + kernel_code_version_major = 100 + kernel_code_version_minor = 100 + machine_kind = 0 + machine_version_major = 5 + machine_version_minor = 5 + machine_version_stepping = 5 + kernel_code_entry_byte_offset = 512 + kernel_code_prefetch_byte_size = 1 + max_scratch_backing_memory_byte_size = 1 + compute_pgm_rsrc1_vgprs = 1 + compute_pgm_rsrc1_sgprs = 1 + compute_pgm_rsrc1_priority = 1 + compute_pgm_rsrc1_float_mode = 1 + compute_pgm_rsrc1_priv = 1 + compute_pgm_rsrc1_dx10_clamp = 1 + compute_pgm_rsrc1_debug_mode = 1 + compute_pgm_rsrc1_ieee_mode = 1 + compute_pgm_rsrc2_scratch_en = 1 + compute_pgm_rsrc2_user_sgpr = 1 + compute_pgm_rsrc2_tgid_x_en = 1 + compute_pgm_rsrc2_tgid_y_en = 1 + compute_pgm_rsrc2_tgid_z_en = 1 + compute_pgm_rsrc2_tg_size_en = 1 + compute_pgm_rsrc2_tidig_comp_cnt = 1 + compute_pgm_rsrc2_excp_en_msb = 1 + compute_pgm_rsrc2_lds_size = 1 + compute_pgm_rsrc2_excp_en = 1 + enable_sgpr_private_segment_buffer = 1 + enable_sgpr_dispatch_ptr = 1 + enable_sgpr_queue_ptr = 1 + enable_sgpr_kernarg_segment_ptr = 1 + enable_sgpr_dispatch_id = 1 + enable_sgpr_flat_scratch_init = 1 + enable_sgpr_private_segment_size = 1 + enable_sgpr_grid_workgroup_count_x = 1 + enable_sgpr_grid_workgroup_count_y = 1 + enable_sgpr_grid_workgroup_count_z = 1 + enable_ordered_append_gds = 1 + private_element_size = 1 + is_ptr64 = 1 + is_dynamic_callstack = 1 + is_debug_enabled = 1 + is_xnack_enabled = 1 + workitem_private_segment_byte_size = 1 + workgroup_group_segment_byte_size = 1 + gds_segment_byte_size = 1 + kernarg_segment_byte_size = 1 + workgroup_fbarrier_count = 1 + wavefront_sgpr_count = 1 + workitem_vgpr_count = 1 + reserved_vgpr_first = 1 + reserved_vgpr_count = 1 + reserved_sgpr_first = 1 + reserved_sgpr_count = 1 + debug_wavefront_private_segment_offset_sgpr = 1 + debug_private_segment_buffer_sgpr = 1 + kernarg_segment_alignment = 5 + group_segment_alignment = 5 + private_segment_alignment = 5 + wavefront_size = 5 + call_convention = 1 + runtime_loader_kernel_symbol = 1 +.end_amd_kernel_code_t + +// ASM-LABEL: {{^}}amd_kernel_code_t_test_all: +// ASM: .amd_kernel_code_t +// ASM: kernel_code_version_major = 100 +// ASM: kernel_code_version_minor = 100 +// ASM: machine_kind = 0 +// ASM: machine_version_major = 5 +// ASM: machine_version_minor = 5 +// ASM: machine_version_stepping = 5 +// ASM: kernel_code_entry_byte_offset = 512 +// ASM: kernel_code_prefetch_byte_size = 1 +// ASM: max_scratch_backing_memory_byte_size = 1 +// ASM: compute_pgm_rsrc1_vgprs = 1 +// ASM: compute_pgm_rsrc1_sgprs = 1 +// ASM: compute_pgm_rsrc1_priority = 1 +// ASM: compute_pgm_rsrc1_float_mode = 1 +// ASM: compute_pgm_rsrc1_priv = 1 +// ASM: compute_pgm_rsrc1_dx10_clamp = 1 +// ASM: compute_pgm_rsrc1_debug_mode = 1 +// ASM: compute_pgm_rsrc1_ieee_mode = 1 +// ASM: compute_pgm_rsrc2_scratch_en = 1 +// ASM: compute_pgm_rsrc2_user_sgpr = 1 +// ASM: compute_pgm_rsrc2_tgid_x_en = 1 +// ASM: compute_pgm_rsrc2_tgid_y_en = 1 +// ASM: compute_pgm_rsrc2_tgid_z_en = 1 +// ASM: compute_pgm_rsrc2_tg_size_en = 1 +// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 1 +// ASM: compute_pgm_rsrc2_excp_en_msb = 1 +// ASM: compute_pgm_rsrc2_lds_size = 1 +// ASM: compute_pgm_rsrc2_excp_en = 1 +// ASM: enable_sgpr_private_segment_buffer = 1 +// ASM: enable_sgpr_dispatch_ptr = 1 +// ASM: enable_sgpr_queue_ptr = 1 +// ASM: enable_sgpr_kernarg_segment_ptr = 1 +// ASM: enable_sgpr_dispatch_id = 1 +// ASM: enable_sgpr_flat_scratch_init = 1 +// ASM: enable_sgpr_private_segment_size = 1 +// ASM: enable_sgpr_grid_workgroup_count_x = 1 +// ASM: enable_sgpr_grid_workgroup_count_y = 1 +// ASM: enable_sgpr_grid_workgroup_count_z = 1 +// ASM: enable_ordered_append_gds = 1 +// ASM: private_element_size = 1 +// ASM: is_ptr64 = 1 +// ASM: is_dynamic_callstack = 1 +// ASM: is_debug_enabled = 1 +// ASM: is_xnack_enabled = 1 +// ASM: workitem_private_segment_byte_size = 1 +// ASM: workgroup_group_segment_byte_size = 1 +// ASM: gds_segment_byte_size = 1 +// ASM: kernarg_segment_byte_size = 1 +// ASM: workgroup_fbarrier_count = 1 +// ASM: wavefront_sgpr_count = 1 +// ASM: workitem_vgpr_count = 1 +// ASM: reserved_vgpr_first = 1 +// ASM: reserved_vgpr_count = 1 +// ASM: reserved_sgpr_first = 1 +// ASM: reserved_sgpr_count = 1 +// ASM: debug_wavefront_private_segment_offset_sgpr = 1 +// ASM: debug_private_segment_buffer_sgpr = 1 +// ASM: kernarg_segment_alignment = 5 +// ASM: group_segment_alignment = 5 +// ASM: private_segment_alignment = 5 +// ASM: wavefront_size = 5 +// ASM: call_convention = 1 +// ASM: runtime_loader_kernel_symbol = 1 +// ASM: .end_amd_kernel_code_t + +amd_kernel_code_t_minimal: +.amd_kernel_code_t + enable_sgpr_kernarg_segment_ptr = 1 + is_ptr64 = 1 + compute_pgm_rsrc1_vgprs = 1 + compute_pgm_rsrc1_sgprs = 1 + compute_pgm_rsrc2_user_sgpr = 2 + kernarg_segment_byte_size = 16 + wavefront_sgpr_count = 8 +// wavefront_sgpr_count = 7 +; wavefront_sgpr_count = 7 +// Make sure a blank line won't break anything: + +// Make sure a line with whitespace won't break anything: + + workitem_vgpr_count = 16 +.end_amd_kernel_code_t + +// ASM-LABEL: {{^}}amd_kernel_code_t_minimal: +// ASM: .amd_kernel_code_t +// ASM: kernel_code_version_major = 1 +// ASM: kernel_code_version_minor = 0 +// ASM: machine_kind = 1 +// ASM: machine_version_major = 7 +// ASM: machine_version_minor = 0 +// ASM: machine_version_stepping = 0 +// ASM: kernel_code_entry_byte_offset = 256 +// ASM: kernel_code_prefetch_byte_size = 0 +// ASM: max_scratch_backing_memory_byte_size = 0 +// ASM: compute_pgm_rsrc1_vgprs = 1 +// ASM: compute_pgm_rsrc1_sgprs = 1 +// ASM: compute_pgm_rsrc1_priority = 0 +// ASM: compute_pgm_rsrc1_float_mode = 0 +// ASM: compute_pgm_rsrc1_priv = 0 +// ASM: compute_pgm_rsrc1_dx10_clamp = 0 +// ASM: compute_pgm_rsrc1_debug_mode = 0 +// ASM: compute_pgm_rsrc1_ieee_mode = 0 +// ASM: compute_pgm_rsrc2_scratch_en = 0 +// ASM: compute_pgm_rsrc2_user_sgpr = 2 +// ASM: compute_pgm_rsrc2_tgid_x_en = 0 +// ASM: compute_pgm_rsrc2_tgid_y_en = 0 +// ASM: compute_pgm_rsrc2_tgid_z_en = 0 +// ASM: compute_pgm_rsrc2_tg_size_en = 0 +// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 0 +// ASM: compute_pgm_rsrc2_excp_en_msb = 0 +// ASM: compute_pgm_rsrc2_lds_size = 0 +// ASM: compute_pgm_rsrc2_excp_en = 0 +// ASM: enable_sgpr_private_segment_buffer = 0 +// ASM: enable_sgpr_dispatch_ptr = 0 +// ASM: enable_sgpr_queue_ptr = 0 +// ASM: enable_sgpr_kernarg_segment_ptr = 1 +// ASM: enable_sgpr_dispatch_id = 0 +// ASM: enable_sgpr_flat_scratch_init = 0 +// ASM: enable_sgpr_private_segment_size = 0 +// ASM: enable_sgpr_grid_workgroup_count_x = 0 +// ASM: enable_sgpr_grid_workgroup_count_y = 0 +// ASM: enable_sgpr_grid_workgroup_count_z = 0 +// ASM: enable_ordered_append_gds = 0 +// ASM: private_element_size = 0 +// ASM: is_ptr64 = 1 +// ASM: is_dynamic_callstack = 0 +// ASM: is_debug_enabled = 0 +// ASM: is_xnack_enabled = 0 +// ASM: workitem_private_segment_byte_size = 0 +// ASM: workgroup_group_segment_byte_size = 0 +// ASM: gds_segment_byte_size = 0 +// ASM: kernarg_segment_byte_size = 16 +// ASM: workgroup_fbarrier_count = 0 +// ASM: wavefront_sgpr_count = 8 +// ASM: workitem_vgpr_count = 16 +// ASM: reserved_vgpr_first = 0 +// ASM: reserved_vgpr_count = 0 +// ASM: reserved_sgpr_first = 0 +// ASM: reserved_sgpr_count = 0 +// ASM: debug_wavefront_private_segment_offset_sgpr = 0 +// ASM: debug_private_segment_buffer_sgpr = 0 +// ASM: kernarg_segment_alignment = 4 +// ASM: group_segment_alignment = 4 +// ASM: private_segment_alignment = 4 +// ASM: wavefront_size = 6 +// ASM: call_convention = 0 +// ASM: runtime_loader_kernel_symbol = 0 +// ASM: .end_amd_kernel_code_t diff --git a/test/MC/AMDGPU/hsa_code_object_isa_noargs.s b/test/MC/AMDGPU/hsa_code_object_isa_noargs.s new file mode 100644 index 0000000000000..85f53bb697bcd --- /dev/null +++ b/test/MC/AMDGPU/hsa_code_object_isa_noargs.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM +// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF + +// ELF: SHT_NOTE +// ELF: 0000: 04000000 08000000 01000000 414D4400 +// ELF: 0010: 01000000 00000000 04000000 1B000000 +// ELF: 0020: 03000000 414D4400 04000700 07000000 +// ELF: 0030: 00000000 00000000 414D4400 414D4447 +// ELF: 0040: 50550000 + +.hsa_code_object_version 1,0 +// ASM: .hsa_code_object_version 1,0 + +.hsa_code_object_isa +// ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" + diff --git a/test/MC/ARM/directive-fpu-multiple.s b/test/MC/ARM/directive-fpu-multiple.s index 66fc274159638..50389a1153294 100644 --- a/test/MC/ARM/directive-fpu-multiple.s +++ b/test/MC/ARM/directive-fpu-multiple.s @@ -10,7 +10,11 @@ .fpu vfp .fpu vfpv2 .fpu vfpv3 + .fpu vfpv3-fp16 .fpu vfpv3-d16 + .fpu vfpv3-d16-fp16 + .fpu vfpv3xd + .fpu vfpv3xd-fp16 .fpu vfpv4 .fpu vfpv4-d16 .fpu fpv4-sp-d16 @@ -18,6 +22,7 @@ .fpu fpv5-sp-d16 .fpu fp-armv8 .fpu neon + .fpu neon-fp16 .fpu neon-vfpv4 .fpu neon-fp-armv8 .fpu crypto-neon-fp-armv8 diff --git a/test/MC/ARM/directive-type-diagnostics.s b/test/MC/ARM/directive-type-diagnostics.s new file mode 100644 index 0000000000000..b166ffd06aab3 --- /dev/null +++ b/test/MC/ARM/directive-type-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple arm-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple armeb-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumb-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumbeb-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + + .type symbol 32 +// CHECK: error: expected STT_<TYPE_IN_UPPER_CASE>, '#<type>', '%<type>' or "<type>" +// CHECK: .type symbol 32 +// CHECK: ^ + diff --git a/test/MC/ARM/thumb_set-diagnostics.s b/test/MC/ARM/thumb_set-diagnostics.s index 5f1844de01ff7..86f1ee5245c22 100644 --- a/test/MC/ARM/thumb_set-diagnostics.s +++ b/test/MC/ARM/thumb_set-diagnostics.s @@ -41,3 +41,31 @@ @ CHECK: .thumb_set trailer_trash, 0x11fe1e55, @ CHECK: ^ + .type alpha,%function +alpha: + nop + + .type beta,%function +beta: + bkpt + + .thumb_set beta, alpha + +@ CHECK: error: redefinition of 'beta' +@ CHECK: .thumb_set beta, alpha +@ CHECK: ^ + + .type recursive_use,%function + .thumb_set recursive_use, recursive_use + 1 + +@ CHECK: error: Recursive use of 'recursive_use' +@ CHECK: .thumb_set recursive_use, recursive_use + 1 +@ CHECK: ^ + + variable_result = alpha + 1 + .long variable_result + .thumb_set variable_result, 1 + +@ CHECK: error: invalid reassignment of non-absolute variable 'variable_result' +@ CHECK: .thumb_set variable_result, 1 +@ CHECK: ^
\ No newline at end of file diff --git a/test/MC/ARM/thumb_set.s b/test/MC/ARM/thumb_set.s index d2a0dc04730c1..00b3e53e7241b 100644 --- a/test/MC/ARM/thumb_set.s +++ b/test/MC/ARM/thumb_set.s @@ -54,8 +54,6 @@ alpha: nop .type beta,%function -beta: - bkpt .thumb_set beta, alpha diff --git a/test/MC/COFF/ARM/directive-type-diagnostics.s b/test/MC/COFF/ARM/directive-type-diagnostics.s new file mode 100644 index 0000000000000..f8a52cd43e420 --- /dev/null +++ b/test/MC/COFF/ARM/directive-type-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple arm-coff -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple armeb-coff -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumb-coff -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumbeb-coff -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + + .type symbol 32 +// CHECK: error: expected STT_<TYPE_IN_UPPER_CASE>, '#<type>', '%<type>' or "<type>" +// CHECK: .type symbol 32 +// CHECK: ^ + diff --git a/test/MC/COFF/ARM/lit.local.cfg b/test/MC/COFF/ARM/lit.local.cfg new file mode 100644 index 0000000000000..98c6700c209d7 --- /dev/null +++ b/test/MC/COFF/ARM/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'ARM' in config.root.targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt index 637e88928e7b5..5809ac28113c7 100644 --- a/test/MC/Disassembler/Mips/micromips.txt +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -336,3 +336,7 @@ 0x46 0xce # CHECK: sdbbp16 14 0x84 0x34 # CHECK: movep $5, $6, $2, $3 + +0x00 0x00 0x57 0x7c # CHECK: ei + +0x00 0x0a 0x57 0x7c # CHECK: ei $10 diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index 47c4d080f0a27..a2691ee6bc3a7 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -38,6 +38,12 @@ 0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2 +0x00 0x00 0x00 0x07 # CHECK: break + +0x00 0x07 0x00 0x07 # CHECK: break 7 + +0x00 0x07 0x01 0x47 # CHECK: break 7, 5 + 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5) 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5 @@ -48,6 +54,12 @@ 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 +0x00 0x00 0x18 0x00 # CHECK: ehb + +0x00 0x00 0x57 0x7c # CHECK: ei + +0x00 0x0a 0x57 0x7c # CHECK: ei $10 + 0x00 0x00 0xf3 0x7c # CHECK: eret 0x00 0x01 0xf3 0x7c # CHECK: eretnc @@ -72,6 +84,8 @@ 0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5 +0x00 0x00 0x00 0x00 # CHECK: nop + 0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5 0x00,0xa4,0x1a,0x90 # CHECK: or $3, $4, $5 @@ -84,6 +98,8 @@ 0x00 0x83 0x11 0x80 # CHECK: selnez $2, $3, $4 +0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7 + 0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5 0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5 diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt index 3899c510330ed..3058bd0610661 100644 --- a/test/MC/Disassembler/Mips/micromips_le.txt +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -336,3 +336,7 @@ 0xce 0x46 # CHECK: sdbbp16 14 0x34 0x84 # CHECK: movep $5, $6, $2, $3 + +0x00 0x00 0x7c 0x57 # CHECK: ei + +0x0a 0x00 0x7c 0x57 # CHECK: ei $10 diff --git a/test/MC/Disassembler/Mips/mips1/valid-mips1.txt b/test/MC/Disassembler/Mips/mips1/valid-mips1.txt index 1a4f94f083e7f..59e702e17e1c6 100644 --- a/test/MC/Disassembler/Mips/mips1/valid-mips1.txt +++ b/test/MC/Disassembler/Mips/mips1/valid-mips1.txt @@ -1,116 +1,110 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips1 | FileCheck %s # CHECK: .text -0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 -0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 +0x00 0x00 0x88 0x12 # CHECK: mflo $17 +0x00 0x00 0x98 0x10 # CHECK: mfhi $19 +0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp +0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 +0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 +0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 +0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 +0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 +0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 +0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 +0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 +0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp +0x02 0x20 0x00 0x11 # CHECK: mthi $17 0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5 -0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 -0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 -0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 +0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 +0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 +0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 +0x03 0x20 0x00 0x13 # CHECK: mtlo $25 +0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 +0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 +0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp +0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 +0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x04 0x11 0x14 0x9b # CHECK: bal 21104 +0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 +0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 +0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 +0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 0x21 0xc9 0x3b 0x48 # CHECK: addi $9, $14, 15176 +0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 0x23 0x18 0xe3 0xe7 # CHECK: addi $24, $24, -7193 -0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 -0x45 0x00 0x00 0x01 # CHECK: bc1f 8 +0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 +0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 +0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 -0x45 0x01 0x00 0x01 # CHECK: bc1t 8 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 -0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 -0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 -0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 +0x42 0x00 0x00 0x01 # CHECK: tlbr +0x42 0x00 0x00 0x02 # CHECK: tlbwi +0x42 0x00 0x00 0x06 # CHECK: tlbwr +0x42 0x00 0x00 0x08 # CHECK: tlbp +0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 +0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 +0x45 0x00 0x00 0x01 # CHECK: bc1f 8 +0x45 0x01 0x00 0x01 # CHECK: bc1t 8 +0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 +0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 +0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 +0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 -0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 +0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 +0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 +0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 +0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8 -0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 -0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 -0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 +0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 +0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 +0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 +0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 +0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 -0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 -0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 +0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 +0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 +0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 0x81 0x58 0xc7 0x4d # CHECK: lb $24, -14515($10) -0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) 0x86 0xab 0xde 0x94 # CHECK: lh $11, -8556($21) -0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2) -0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 -0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 -0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) -0xc7 0x50 0x27 0xf1 # CHECK: lwc1 $f16, 10225($26) -0xc8 0xd2 0xfc 0xb7 # CHECK: lwc2 $18, -841($6) -0xcf 0x4a 0x81 0xf7 # CHECK: lwc3 $10, -32265($26) 0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) +0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) +0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) +0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2) 0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) -0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 -0x00 0x00 0x98 0x10 # CHECK: mfhi $19 -0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp -0x00 0x00 0x88 0x12 # CHECK: mflo $17 -0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 -0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 -0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 -0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 -0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 -0x02 0x20 0x00 0x11 # CHECK: mthi $17 -0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp -0x03 0x20 0x00 0x13 # CHECK: mtlo $25 -0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 -0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 -0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 -0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 -0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 -0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 -0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 -0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 -0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 -0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 -0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) 0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) -0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 -0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 -0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 -0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 -0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 -0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 -0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 -0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 -0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 -0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 -0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 -0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 -0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 +0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) 0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) +0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) +0xc7 0x50 0x27 0xf1 # CHECK: lwc1 $f16, 10225($26) +0xc8 0xd2 0xfc 0xb7 # CHECK: lwc2 $18, -841($6) +0xcf 0x4a 0x81 0xf7 # CHECK: lwc3 $10, -32265($26) 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) 0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) -0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) -0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) -0x42 0x00 0x00 0x08 # CHECK: tlbp -0x42 0x00 0x00 0x01 # CHECK: tlbr -0x42 0x00 0x00 0x02 # CHECK: tlbwi -0x42 0x00 0x00 0x06 # CHECK: tlbwr -0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp diff --git a/test/MC/Disassembler/Mips/mips2.txt b/test/MC/Disassembler/Mips/mips2.txt deleted file mode 100644 index a604055e62ef8..0000000000000 --- a/test/MC/Disassembler/Mips/mips2.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips2 | FileCheck %s - -# CHECK: sdc3 $5, 9154($6) -0xfc 0xc5 0x23 0xc2 - -# CHECK: swc3 $6, 9158($7) -0xec 0xe6 0x23 0xc6 - -# CHECK: ldc3 $7, 9162($8) -0xdd 0x07 0x23 0xca - -# CHECK: lwc3 $8, 9166($9) -0xcd 0x28 0x23 0xce diff --git a/test/MC/Disassembler/Mips/mips2/valid-mips2.txt b/test/MC/Disassembler/Mips/mips2/valid-mips2.txt index 3dc523168ffd6..268bb29009034 100644 --- a/test/MC/Disassembler/Mips/mips2/valid-mips2.txt +++ b/test/MC/Disassembler/Mips/mips2/valid-mips2.txt @@ -1,159 +1,161 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips2 | FileCheck %s # CHECK: .text -0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 -0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x00 0xc0 # CHECK: ehb +0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 +0x00 0x00 0x88 0x12 # CHECK: mflo $17 +0x00 0x00 0x98 0x10 # CHECK: mfhi $19 +0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp +0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 +0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 +0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 +0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 +0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 +0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 +0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 +0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 +0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 +0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 +0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 +0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 +0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 +0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 +0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 +0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 +0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp +0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 +0x02 0x20 0x00 0x11 # CHECK: mthi $17 0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5 +0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 +0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 +0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 +0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 +0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp +0x03 0x20 0x00 0x13 # CHECK: mtlo $25 +0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 +0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 +0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp +0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 +0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x04 0x11 0x14 0x9b # CHECK: bal 21104 +0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 +0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 +0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 +0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 +0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 +0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 0x21 0xc9 0x3b 0x48 # CHECK: addi $9, $14, 15176 +0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 0x23 0x18 0xe3 0xe7 # CHECK: addi $24, $24, -7193 -0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 -0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 -0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 -0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 -0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 +0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 +0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 +0x42 0x00 0x00 0x01 # CHECK: tlbr +0x42 0x00 0x00 0x02 # CHECK: tlbwi +0x42 0x00 0x00 0x06 # CHECK: tlbwr +0x42 0x00 0x00 0x08 # CHECK: tlbp +0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 +0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 +0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 +0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 0x45 0x00 0x00 0x01 # CHECK: bc1f 8 -0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x01 0x00 0x01 # CHECK: bc1t 8 +0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x03 0xf7 0xf4 # CHECK: bc1tl -8236 -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 -0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 -0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 -0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 -0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 -0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 -0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 -0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 -0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 -0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 -0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 +0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 +0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 +0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 -0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 -0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 +0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 +0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 -0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 +0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 +0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 +0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 +0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 +0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 +0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 +0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8 -0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 +0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 -0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 -0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 +0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 +0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 +0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 +0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 +0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 +0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 +0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 -0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 -0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 -0x00 0x00 0x00 0xc0 # CHECK: ehb -0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 -0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 +0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 +0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 +0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 +0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 +0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 +0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x81 0x58 0xc7 0x4d # CHECK: lb $24, -14515($10) -0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) -0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) -0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) -0xde 0x3d 0x90 0x1b # CHECK: ldc3 $29, -28645($17) 0x86 0xab 0xde 0x94 # CHECK: lh $11, -8556($21) +0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) +0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) +0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2) -0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 -0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) +0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) +0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) +0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) +0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) 0xc2 0x42 0xe3 0x67 # CHECK: ll $2, -7321($18) -0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) 0xc7 0x50 0x27 0xf1 # CHECK: lwc1 $f16, 10225($26) 0xc8 0xd2 0xfc 0xb7 # CHECK: lwc2 $18, -841($6) +0xcd 0x28 0x23 0xce # CHECK: lwc3 $8, 9166($9) 0xcf 0x4a 0x81 0xf7 # CHECK: lwc3 $10, -32265($26) -0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) -0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) -0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 -0x00 0x00 0x98 0x10 # CHECK: mfhi $19 -0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp -0x00 0x00 0x88 0x12 # CHECK: mflo $17 -0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 -0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 -0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 -0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 -0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 -0x02 0x20 0x00 0x11 # CHECK: mthi $17 -0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp -0x03 0x20 0x00 0x13 # CHECK: mtlo $25 -0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 -0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 -0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 -0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 -0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 -0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 -0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 -0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 -0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 -0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 -0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 -0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 -0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) +0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) +0xdd 0x07 0x23 0xca # CHECK: ldc3 $7, 9162($8) +0xde 0x3d 0x90 0x1b # CHECK: ldc3 $29, -28645($17) 0xe2 0x6f 0x49 0xd8 # CHECK: sc $15, 18904($19) -0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) -0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) -0xfd 0x4c 0x16 0xcb # CHECK: sdc3 $12, 5835($10) -0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) -0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 -0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 -0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 -0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 -0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 -0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 -0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 -0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 -0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 -0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 -0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 -0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 -0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 -0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 -0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 -0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) 0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) 0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) +0xec 0xe6 0x23 0xc6 # CHECK: swc3 $6, 9158($7) 0xef 0x4a 0x81 0xf7 # CHECK: swc3 $10, -32265($26) -0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) -0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) -0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 -0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 -0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 -0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp -0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 -0x42 0x00 0x00 0x08 # CHECK: tlbp -0x42 0x00 0x00 0x01 # CHECK: tlbr -0x42 0x00 0x00 0x02 # CHECK: tlbwi -0x42 0x00 0x00 0x06 # CHECK: tlbwr -0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 -0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 -0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 -0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 -0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 -0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 -0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 -0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 -0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) +0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) +0xfc 0xc5 0x23 0xc2 # CHECK: sdc3 $5, 9154($6) +0xfd 0x4c 0x16 0xcb # CHECK: sdc3 $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt index 0bec08550b304..2a38b19092f08 100644 --- a/test/MC/Disassembler/Mips/mips3/valid-mips3.txt +++ b/test/MC/Disassembler/Mips/mips3/valid-mips3.txt @@ -1,211 +1,209 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips3 | FileCheck %s # CHECK: .text -0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 -0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x00 0xc0 # CHECK: ehb +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 +0x00 0x00 0x88 0x12 # CHECK: mflo $17 +0x00 0x00 0x98 0x10 # CHECK: mfhi $19 +0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp +0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 +0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 +0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 +0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 +0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 +0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 +0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 +0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 +0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 +0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 +0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 +0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp +0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 +0x02 0x20 0x00 0x11 # CHECK: mthi $17 0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5 +0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 +0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 +0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x03 0x20 0x00 0x13 # CHECK: mtlo $25 +0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 +0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp +0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 +0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x04 0x11 0x14 0x9b # CHECK: bal 21104 +0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 +0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 +0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 +0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 +0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 +0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 0x21 0xc9 0x3b 0x48 # CHECK: addi $9, $14, 15176 +0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 0x23 0x18 0xe3 0xe7 # CHECK: addi $24, $24, -7193 -0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 -0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 -0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 -0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 -0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 +0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 +0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 +0x42 0x00 0x00 0x01 # CHECK: tlbr +0x42 0x00 0x00 0x02 # CHECK: tlbwi +0x42 0x00 0x00 0x06 # CHECK: tlbwr +0x42 0x00 0x00 0x08 # CHECK: tlbp +0x42 0x00 0x00 0x18 # CHECK: eret +0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 +0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 0x45 0x00 0x00 0x01 # CHECK: bc1f 8 -0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x01 0x00 0x01 # CHECK: bc1t 8 +0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x03 0xf7 0xf4 # CHECK: bc1tl -8236 -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 -0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 -0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 -0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 -0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 -0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 -0xbc 0xa1 0x00 0x08 # CHECK: cache 1, 8($5) -0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 -0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 -0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 -0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 -0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 +0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 -0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 +0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 -0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 -0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 +0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 +0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 -0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15 +0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 0x46 0x00 0xea 0xe5 # CHECK: cvt.l.s $f11, $f29 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 +0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 +0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 +0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 +0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 +0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 +0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 +0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8 -0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 +0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 -0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 +0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15 +0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 +0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 +0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 +0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 +0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 +0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 +0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 +0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 +0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 +0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 +0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 +0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 +0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 -0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 -0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 -0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 -0x00 0x00 0x00 0xc0 # CHECK: ehb -0x42 0x00 0x00 0x18 # CHECK: eret -0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 -0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 0x81 0x58 0xc7 0x4d # CHECK: lb $24, -14515($10) -0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) -0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) -0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) 0x86 0xab 0xde 0x94 # CHECK: lh $11, -8556($21) +0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) +0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) +0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2) -0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 -0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) +0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) +0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) +0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) +0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) +0xbc 0xa1 0x00 0x08 # CHECK: cache 1, 8($5) 0xc2 0x42 0xe3 0x67 # CHECK: ll $2, -7321($18) -0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) 0xc7 0x50 0x27 0xf1 # CHECK: lwc1 $f16, 10225($26) 0xc8 0xd2 0xfc 0xb7 # CHECK: lwc2 $18, -841($6) -0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) -0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) -0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 -0x00 0x00 0x98 0x10 # CHECK: mfhi $19 -0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp -0x00 0x00 0x88 0x12 # CHECK: mflo $17 -0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 -0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 -0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 -0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 -0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 -0x02 0x20 0x00 0x11 # CHECK: mthi $17 -0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp -0x03 0x20 0x00 0x13 # CHECK: mtlo $25 -0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 -0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 -0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 -0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 -0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 -0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 -0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 -0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 -0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 -0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 -0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 -0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 -0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) +0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) 0xe2 0x6f 0x49 0xd8 # CHECK: sc $15, 18904($19) +0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) +0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) 0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) -0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) -0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 -0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 -0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 -0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 -0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 -0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 -0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 -0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 -0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 -0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 -0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 -0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 -0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 -0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 -0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 -0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) -0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) -0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) -0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) -0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) -0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 -0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 -0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 -0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp -0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 -0x42 0x00 0x00 0x08 # CHECK: tlbp -0x42 0x00 0x00 0x01 # CHECK: tlbr -0x42 0x00 0x00 0x02 # CHECK: tlbwi -0x42 0x00 0x00 0x06 # CHECK: tlbwr -0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 -0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 -0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 -0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 -0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 -0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 -0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 -0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt deleted file mode 100644 index bd4ae4daad045..0000000000000 --- a/test/MC/Disassembler/Mips/mips32.txt +++ /dev/null @@ -1,451 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s - -# CHECK: abs.d $f12, $f14 -0x46 0x20 0x73 0x05 - -# CHECK: abs.s $f6, $f7 -0x46 0x00 0x39 0x85 - -# CHECK: add $9, $6, $7 -0x00 0xc7 0x48 0x20 - -# CHECK: add.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x00 - -# CHECK: add.s $f9, $f6, $f7 -0x46 0x07 0x32 0x40 - -# CHECK: addi $9, $6, 17767 -0x20 0xc9 0x45 0x67 - -# CHECK: addiu $9, $6, -15001 -0x24 0xc9 0xc5 0x67 - -# CHECK: addu $9, $6, $7 -0x00 0xc7 0x48 0x21 - -# CHECK: and $9, $6, $7 -0x00 0xc7 0x48 0x24 - -# CHECK: andi $9, $6, 17767 -0x30 0xc9 0x45 0x67 - -# CHECK: b 1332 -0x10 0x00 0x01 0x4c - -# CHECK: bc1f 1332 -0x45 0x00 0x01 0x4c - -# CHECK: bc1f $fcc7, 1332 -0x45 0x1c 0x01 0x4c - -# CHECK: bc1t 1332 -0x45 0x01 0x01 0x4c - -# CHECK: bc1t $fcc7, 1332 -0x45 0x1d 0x01 0x4c - -# CHECK: beq $9, $6, 1332 -0x11 0x26 0x01 0x4c - -# CHECK: bgez $6, 1332 -0x04 0xc1 0x01 0x4c - -# CHECK: bgezal $6, 1332 -0x04 0xd1 0x01 0x4c - -# CHECK: bgtz $6, 1332 -0x1c 0xc0 0x01 0x4c - -# CHECK: blez $6, 1332 -0x18 0xc0 0x01 0x4c - -# CHECK: bne $9, $6, 1332 -0x15 0x26 0x01 0x4c - -# CHECK: c.eq.d $f12, $f14 -0x46 0x2e 0x60 0x32 - -# CHECK: c.eq.s $f6, $f7 -0x46 0x07 0x30 0x32 - -# CHECK: c.f.d $f12, $f14 -0x46 0x2e 0x60 0x30 - -# CHECK: c.f.s $f6, $f7 -0x46 0x07 0x30 0x30 - -# CHECK: c.le.d $f12, $f14 -0x46 0x2e 0x60 0x3e - -# CHECK: c.le.s $f6, $f7 -0x46 0x07 0x30 0x3e - -# CHECK: c.lt.d $f12, $f14 -0x46 0x2e 0x60 0x3c - -# CHECK: c.lt.s $f6, $f7 -0x46 0x07 0x30 0x3c - -# CHECK: c.nge.d $f12, $f14 -0x46 0x2e 0x60 0x3d - -# CHECK: c.nge.s $f6, $f7 -0x46 0x07 0x30 0x3d - -# CHECK: c.ngl.d $f12, $f14 -0x46 0x2e 0x60 0x3b - -# CHECK: c.ngl.s $f6, $f7 -0x46 0x07 0x30 0x3b - -# CHECK: c.ngle.d $f12, $f14 -0x46 0x2e 0x60 0x39 - -# CHECK: c.ngle.s $f6, $f7 -0x46 0x07 0x30 0x39 - -# CHECK: c.ngt.d $f12, $f14 -0x46 0x2e 0x60 0x3f - -# CHECK: c.ngt.s $f6, $f7 -0x46 0x07 0x30 0x3f - -# CHECK: c.ole.d $f12, $f14 -0x46 0x2e 0x60 0x36 - -# CHECK: c.ole.s $f6, $f7 -0x46 0x07 0x30 0x36 - -# CHECK: c.olt.d $f12, $f14 -0x46 0x2e 0x60 0x34 - -# CHECK: c.olt.s $f6, $f7 -0x46 0x07 0x30 0x34 - -# CHECK: c.seq.d $f12, $f14 -0x46 0x2e 0x60 0x3a - -# CHECK: c.seq.s $f6, $f7 -0x46 0x07 0x30 0x3a - -# CHECK: c.sf.d $f12, $f14 -0x46 0x2e 0x60 0x38 - -# CHECK: c.sf.s $f6, $f7 -0x46 0x07 0x30 0x38 - -# CHECK: c.ueq.d $f12, $f14 -0x46 0x2e 0x60 0x33 - -# CHECK: c.ueq.s $f28, $f18 -0x46 0x12 0xe0 0x33 - -# CHECK: c.ule.d $f12, $f14 -0x46 0x2e 0x60 0x37 - -# CHECK: c.ule.s $f6, $f7 -0x46 0x07 0x30 0x37 - -# CHECK: c.ult.d $f12, $f14 -0x46 0x2e 0x60 0x35 - -# CHECK: c.ult.s $f6, $f7 -0x46 0x07 0x30 0x35 - -# CHECK: c.un.d $f12, $f14 -0x46 0x2e 0x60 0x31 - -# CHECK: c.un.s $f6, $f7 -0x46 0x07 0x30 0x31 - -# CHECK: ceil.w.d $f12, $f14 -0x46 0x20 0x73 0x0e - -# CHECK: ceil.w.s $f6, $f7 -0x46 0x00 0x39 0x8e - -# CHECK: cfc1 $6, $7 -0x44 0x46 0x38 0x00 - -# CHECK: clo $6, $7 -0x70 0xe6 0x30 0x21 - -# CHECK: clz $6, $7 -0x70 0xe6 0x30 0x20 - -# CHECK: ctc1 $6, $7 -0x44 0xc6 0x38 0x00 - -# CHECK: cvt.d.s $f6, $f7 -0x46 0x00 0x39 0xa1 - -# CHECK: cvt.d.w $f12, $f14 -0x46 0x80 0x73 0x21 - -# CHECK: cvt.s.d $f12, $f14 -0x46 0x20 0x73 0x20 - -# CHECK: cvt.s.w $f6, $f7 -0x46 0x80 0x39 0xa0 - -# CHECK: cvt.w.d $f12, $f14 -0x46 0x20 0x73 0x24 - -# CHECK: cvt.w.s $f6, $f7 -0x46 0x00 0x39 0xa4 - -# CHECK: floor.w.d $f12, $f14 -0x46 0x20 0x73 0x0f - -# CHECK: floor.w.s $f6, $f7 -0x46 0x00 0x39 0x8f - -# CHECK: j 1328 -0x08 0x00 0x01 0x4c - -# CHECK: jal 1328 -0x0c 0x00 0x01 0x4c - -# CHECK: jalx 1328 -0x74 0x00 0x01 0x4c - -# CHECK: jalr $7 -0x00 0xe0 0xf8 0x09 - -# CHECK: jr $7 -0x00 0xe0 0x00 0x08 - -# CHECK: lb $4, 9158($5) -0x80 0xa4 0x23 0xc6 - -# CHECK: lbu $4, 6($5) -0x90 0xa4 0x00 0x06 - -# CHECK: ldc1 $f9, 9158($7) -0xd4 0xe9 0x23 0xc6 - -# CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c - -# CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c - -# CHECK: ll $9, 9158($7) -0xc0 0xe9 0x23 0xc6 - -# CHECK: lui $6, 17767 -0x3c 0x06 0x45 0x67 - -# CHECK: lw $4, 24($5) -0x8c 0xa4 0x00 0x18 - -# CHECK: lwc1 $f9, 9158($7) -0xc4 0xe9 0x23 0xc6 - -# CHECK: lwl $2, 3($4) -0x88 0x82 0x00 0x03 - -# CHECK: lwr $3, 16($5) -0x98 0xa3 0x00 0x10 - -# CHECK: madd $6, $7 -0x70 0xc7 0x00 0x00 - -# CHECK: maddu $6, $7 -0x70 0xc7 0x00 0x01 - -# CHECK: mfc1 $6, $f7 -0x44 0x06 0x38 0x00 - -# CHECK: mfhi $5 -0x00 0x00 0x28 0x10 - -# CHECK: mflo $5 -0x00 0x00 0x28 0x12 - -# CHECK: mov.d $f6, $f8 -0x46 0x20 0x41 0x86 - -# CHECK: mov.s $f6, $f7 -0x46 0x00 0x39 0x86 - -# CHECK: movf $3, $2, $fcc7 -0x00,0x5c,0x18,0x01 - -# CHECK: movf.d $f4, $f2, $fcc7 -0x46,0x3c,0x11,0x11 - -# CHECK: movf.s $f4, $f2, $fcc7 -0x46,0x1c,0x11,0x11 - -# CHECK: movt $3, $2, $fcc7 -0x00,0x5d,0x18,0x01 - -# CHECK: movt.d $f4, $f2, $fcc7 -0x46,0x3d,0x11,0x11 - -# CHECK: movt.s $f4, $f2, $fcc7 -0x46,0x1d,0x11,0x11 - -# CHECK: msub $6, $7 -0x70 0xc7 0x00 0x04 - -# CHECK: msubu $6, $7 -0x70 0xc7 0x00 0x05 - -# CHECK: mtc1 $6, $f7 -0x44 0x86 0x38 0x00 - -# CHECK: mthi $7 -0x00 0xe0 0x00 0x11 - -# CHECK: mtlo $7 -0x00 0xe0 0x00 0x13 - -# CHECK: mul.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x02 - -# CHECK: mul.s $f9, $f6, $f7 -0x46 0x07 0x32 0x42 - -# CHECK: mul $9, $6, $7 -0x70 0xc7 0x48 0x02 - -# CHECK: mult $3, $5 -0x00 0x65 0x00 0x18 - -# CHECK: multu $3, $5 -0x00 0x65 0x00 0x19 - -# CHECK: neg.d $f12, $f14 -0x46 0x20 0x73 0x07 - -# CHECK: neg.s $f6, $f7 -0x46 0x00 0x39 0x87 - -# CHECK: nop -0x00 0x00 0x00 0x00 - -# CHECK: nor $9, $6, $7 -0x00 0xc7 0x48 0x27 - -# CHECK: or $3, $3, $5 -0x00 0x65 0x18 0x25 - -# CHECK: ori $9, $6, 17767 -0x34 0xc9 0x45 0x67 - -# CHECK: round.w.d $f12, $f14 -0x46 0x20 0x73 0x0c - -# CHECK: round.w.s $f6, $f7 -0x46 0x00 0x39 0x8c - -# CHECK: sb $4, 9158($5) -0xa0 0xa4 0x23 0xc6 - -# CHECK: sb $4, 6($5) -0xa0 0xa4 0x00 0x06 - -# CHECK: sc $9, 9158($7) -0xe0 0xe9 0x23 0xc6 - -# CHECK: sdc1 $f9, 9158($7) -0xf4 0xe9 0x23 0xc6 - -# CHECK: sh $4, 9158($5) -0xa4 0xa4 0x23 0xc6 - -# CHECK: sll $4, $3, 7 -0x00 0x03 0x21 0xc0 - -# CHECK: sllv $2, $3, $5 -0x00 0xa3 0x10 0x04 - -# CHECK: slt $3, $3, $5 -0x00 0x65 0x18 0x2a - -# CHECK: slti $3, $3, 103 -0x28 0x63 0x00 0x67 - -# CHECK: sltiu $3, $3, 103 -0x2c 0x63 0x00 0x67 - -# CHECK: sltu $3, $3, $5 -0x00 0x65 0x18 0x2b - -# CHECK: sqrt.d $f12, $f14 -0x46 0x20 0x73 0x04 - -# CHECK: sqrt.s $f6, $f7 -0x46 0x00 0x39 0x84 - -# CHECK: sra $4, $3, 7 -0x00 0x03 0x21 0xc3 - -# CHECK: srav $2, $3, $5 -0x00 0xa3 0x10 0x07 - -# CHECK: srl $4, $3, 7 -0x00 0x03 0x21 0xc2 - -# CHECK: srlv $2, $3, $5 -0x00 0xa3 0x10 0x06 - -# CHECK: sub.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x01 - -# CHECK: sub.s $f9, $f6, $f7 -0x46 0x07 0x32 0x41 - -# CHECK: sub $9, $6, $7 -0x00 0xc7 0x48 0x22 - -# CHECK: subu $4, $3, $5 -0x00 0x65 0x20 0x23 - -# CHECK: sw $4, 24($5) -0xac 0xa4 0x00 0x18 - -# CHECK: swc1 $f9, 9158($7) -0xe4 0xe9 0x23 0xc6 - -# CHECK: swl $4, 16($5) -0xa8 0xa4 0x00 0x10 - -# CHECK: swr $6, 16($7) -0xb8 0xe6 0x00 0x10 - -# CHECK: sync 7 -0x00 0x00 0x01 0xcf - -# CHECK: trunc.w.d $f12, $f14 -0x46 0x20 0x73 0x0d - -# CHECK: trunc.w.s $f6, $f7 -0x46 0x00 0x39 0x8d - -# CHECK: xor $3, $3, $5 -0x00 0x65 0x18 0x26 - -# CHECK: xori $9, $6, 17767 -0x38 0xc9 0x45 0x67 - -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop -0x7c 0x05 0xe8 0x3b - -# CHECK: cache 1, 2($3) -0xbc 0x61 0x00 0x02 - -# CHECK: pref 3, 4($2) -0xcc 0x43 0x00 0x04 - -# CHECK: swc2 $9, 9158($7) -0xe8 0xe9 0x23 0xc6 - -# CHECK: lwc2 $8, 9162($6) -0xc8 0xc8 0x23 0xca diff --git a/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt b/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt index ea209d1ebab9f..f2299732a80e5 100644 --- a/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt +++ b/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt @@ -86,6 +86,7 @@ 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5) 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x12 0x28 0x00 0x00 # CHECK: mflo $5 @@ -93,6 +94,7 @@ 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7 diff --git a/test/MC/Disassembler/Mips/mips32/valid-mips32.txt b/test/MC/Disassembler/Mips/mips32/valid-mips32.txt index 45b672b2d351a..09f1e56fff43a 100644 --- a/test/MC/Disassembler/Mips/mips32/valid-mips32.txt +++ b/test/MC/Disassembler/Mips/mips32/valid-mips32.txt @@ -1,149 +1,158 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x5c 0x18 0x01 # CHECK: movf $3, $2, $fcc7 +0x00 0x5d 0x18 0x01 # CHECK: movt $3, $2, $fcc7 +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x1c 0x11 0x11 # CHECK: movf.s $f4, $f2, $fcc7 +0x46 0x1d 0x11 0x11 # CHECK: movt.s $f4, $f2, $fcc7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x3c 0x11 0x11 # CHECK: movf.d $f4, $f2, $fcc7 +0x46 0x3d 0x11 0x11 # CHECK: movt.d $f4, $f2, $fcc7 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 +0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 +0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 +0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x7c 0x05 0xe8 0x3b # CHECK: .set push + # CHECK: .set mips32r2 + # CHECK: rdhwr $5, $29 + # CHECK: .set pop 0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 -0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 -0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 -0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 -0x7c 0x05 0xe8 0x3b # CHECK: .set push - # CHECK: .set mips32r2 - # CHECK: rdhwr $5, $29 - # CHECK: .set pop 0xbc 0x61 0x00 0x02 # CHECK: cache 1, 2($3) +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xc8 0xc8 0x23 0xca # CHECK: lwc2 $8, 9162($6) 0xcc 0x43 0x00 0x04 # CHECK: pref 3, 4($2) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xe8 0xe9 0x23 0xc6 # CHECK: swc2 $9, 9158($7) -0xc8 0xc8 0x23 0xca # CHECK: lwc2 $8, 9162($6) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 533fc69598c17..c019c41bd1202 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -254,6 +254,9 @@ # CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 +# CHECK: mfc0 $8, $16, 4 +0x04 0x80 0x08 0x40 + # CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 @@ -299,6 +302,9 @@ # CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 +# CHECK: mtc0 $9, $15, 1 +0x01 0x78 0x89 0x40 + # CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt deleted file mode 100644 index 354ef74a75aa2..0000000000000 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ /dev/null @@ -1,453 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s -# CHECK: abs.d $f12, $f14 -0x46 0x20 0x73 0x05 - -# CHECK: abs.s $f6, $f7 -0x46 0x00 0x39 0x85 - -# CHECK: add $9, $6, $7 -0x00 0xc7 0x48 0x20 - -# CHECK: add.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x00 - -# CHECK: add.s $f9, $f6, $f7 -0x46 0x07 0x32 0x40 - -# CHECK: addi $9, $6, 17767 -0x20 0xc9 0x45 0x67 - -# CHECK: addiu $9, $6, -15001 -0x24 0xc9 0xc5 0x67 - -# CHECK: addu $9, $6, $7 -0x00 0xc7 0x48 0x21 - -# CHECK: and $9, $6, $7 -0x00 0xc7 0x48 0x24 - -# CHECK: andi $9, $6, 17767 -0x30 0xc9 0x45 0x67 - -# CHECK: b 1332 -0x10 0x00 0x01 0x4c - -# CHECK: bc1f 1332 -0x45 0x00 0x01 0x4c - -# CHECK: bc1f $fcc7, 1332 -0x45 0x1c 0x01 0x4c - -# CHECK: bc1t 1332 -0x45 0x01 0x01 0x4c - -# CHECK: bc1t $fcc7, 1332 -0x45 0x1d 0x01 0x4c - -# CHECK: beq $9, $6, 1332 -0x11 0x26 0x01 0x4c - -# CHECK: bgez $6, 1332 -0x04 0xc1 0x01 0x4c - -# CHECK: bgezal $6, 1332 -0x04 0xd1 0x01 0x4c - -# CHECK: bgtz $6, 1332 -0x1c 0xc0 0x01 0x4c - -# CHECK: blez $6, 1332 -0x18 0xc0 0x01 0x4c - -# CHECK: bne $9, $6, 1332 -0x15 0x26 0x01 0x4c - -# CHECK: c.eq.d $f12, $f14 -0x46 0x2e 0x60 0x32 - -# CHECK: c.eq.s $f6, $f7 -0x46 0x07 0x30 0x32 - -# CHECK: c.f.d $f12, $f14 -0x46 0x2e 0x60 0x30 - -# CHECK: c.f.s $f6, $f7 -0x46 0x07 0x30 0x30 - -# CHECK: c.le.d $f12, $f14 -0x46 0x2e 0x60 0x3e - -# CHECK: c.le.s $f6, $f7 -0x46 0x07 0x30 0x3e - -# CHECK: c.lt.d $f12, $f14 -0x46 0x2e 0x60 0x3c - -# CHECK: c.lt.s $f6, $f7 -0x46 0x07 0x30 0x3c - -# CHECK: c.nge.d $f12, $f14 -0x46 0x2e 0x60 0x3d - -# CHECK: c.nge.s $f6, $f7 -0x46 0x07 0x30 0x3d - -# CHECK: c.ngl.d $f12, $f14 -0x46 0x2e 0x60 0x3b - -# CHECK: c.ngl.s $f6, $f7 -0x46 0x07 0x30 0x3b - -# CHECK: c.ngle.d $f12, $f14 -0x46 0x2e 0x60 0x39 - -# CHECK: c.ngle.s $f6, $f7 -0x46 0x07 0x30 0x39 - -# CHECK: c.ngt.d $f12, $f14 -0x46 0x2e 0x60 0x3f - -# CHECK: c.ngt.s $f6, $f7 -0x46 0x07 0x30 0x3f - -# CHECK: c.ole.d $f12, $f14 -0x46 0x2e 0x60 0x36 - -# CHECK: c.ole.s $f6, $f7 -0x46 0x07 0x30 0x36 - -# CHECK: c.olt.d $f12, $f14 -0x46 0x2e 0x60 0x34 - -# CHECK: c.olt.s $f6, $f7 -0x46 0x07 0x30 0x34 - -# CHECK: c.seq.d $f12, $f14 -0x46 0x2e 0x60 0x3a - -# CHECK: c.seq.s $f6, $f7 -0x46 0x07 0x30 0x3a - -# CHECK: c.sf.d $f12, $f14 -0x46 0x2e 0x60 0x38 - -# CHECK: c.sf.s $f6, $f7 -0x46 0x07 0x30 0x38 - -# CHECK: c.ueq.d $f12, $f14 -0x46 0x2e 0x60 0x33 - -# CHECK: c.ueq.s $f28, $f18 -0x46 0x12 0xe0 0x33 - -# CHECK: c.ule.d $f12, $f14 -0x46 0x2e 0x60 0x37 - -# CHECK: c.ule.s $f6, $f7 -0x46 0x07 0x30 0x37 - -# CHECK: c.ult.d $f12, $f14 -0x46 0x2e 0x60 0x35 - -# CHECK: c.ult.s $f6, $f7 -0x46 0x07 0x30 0x35 - -# CHECK: c.un.d $f12, $f14 -0x46 0x2e 0x60 0x31 - -# CHECK: c.un.s $f6, $f7 -0x46 0x07 0x30 0x31 - -# CHECK: ceil.w.d $f12, $f14 -0x46 0x20 0x73 0x0e - -# CHECK: ceil.w.s $f6, $f7 -0x46 0x00 0x39 0x8e - -# CHECK: cfc1 $6, $7 -0x44 0x46 0x38 0x00 - -# CHECK: clo $6, $7 -0x70 0xe6 0x30 0x21 - -# CHECK: clz $6, $7 -0x70 0xe6 0x30 0x20 - -# CHECK: ctc1 $6, $7 -0x44 0xc6 0x38 0x00 - -# CHECK: cvt.d.s $f6, $f7 -0x46 0x00 0x39 0xa1 - -# CHECK: cvt.d.w $f12, $f14 -0x46 0x80 0x73 0x21 - -# CHECK: cvt.l.d $f12, $f14 -0x46 0x20 0x73 0x25 - -# CHECK: cvt.l.s $f6, $f7 -0x46 0x00 0x39 0xa5 - -# CHECK: cvt.s.d $f12, $f14 -0x46 0x20 0x73 0x20 - -# CHECK: cvt.s.w $f6, $f7 -0x46 0x80 0x39 0xa0 - -# CHECK: cvt.w.d $f12, $f14 -0x46 0x20 0x73 0x24 - -# CHECK: cvt.w.s $f6, $f7 -0x46 0x00 0x39 0xa4 - -# CHECK: floor.w.d $f12, $f14 -0x46 0x20 0x73 0x0f - -# CHECK: floor.w.s $f6, $f7 -0x46 0x00 0x39 0x8f - -# CHECK: ins $19, $9, 6, 7 -0x7d 0x33 0x61 0x84 - -# CHECK: j 1328 -0x08 0x00 0x01 0x4c - -# CHECK: jal 1328 -0x0c 0x00 0x01 0x4c - -# CHECK: jalx 1328 -0x74 0x00 0x01 0x4c - -# CHECK: jalr $7 -0x00 0xe0 0xf8 0x09 - -# CHECK: jr $7 -0x00 0xe0 0x00 0x08 - -# CHECK: lb $4, 9158($5) -0x80 0xa4 0x23 0xc6 - -# CHECK: lbu $4, 6($5) -0x90 0xa4 0x00 0x06 - -# CHECK: ldc1 $f9, 9158($7) -0xd4 0xe9 0x23 0xc6 - -# CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c - -# CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c - -# CHECK: ll $9, 9158($7) -0xc0 0xe9 0x23 0xc6 - -# CHECK: lui $6, 17767 -0x3c 0x06 0x45 0x67 - -# CHECK: luxc1 $f0, $6($5) -0x4c 0xa6 0x00 0x05 - -# CHECK: lw $4, 24($5) -0x8c 0xa4 0x00 0x18 - -# CHECK: lwc1 $f9, 9158($7) -0xc4 0xe9 0x23 0xc6 - -# CHECK: lwl $2, 3($4) -0x88 0x82 0x00 0x03 - -# CHECK: lwr $3, 16($5) -0x98 0xa3 0x00 0x10 - -# CHECK: lwxc1 $f20, $12($14) -0x4d 0xcc 0x05 0x00 - -# CHECK: madd $6, $7 -0x70 0xc7 0x00 0x00 - -# CHECK: maddu $6, $7 -0x70 0xc7 0x00 0x01 - -# CHECK: mfc1 $6, $f7 -0x44 0x06 0x38 0x00 - -# CHECK: mfhi $5 -0x00 0x00 0x28 0x10 - -# CHECK: mflo $5 -0x00 0x00 0x28 0x12 - -# CHECK: mov.d $f6, $f8 -0x46 0x20 0x41 0x86 - -# CHECK: mov.s $f6, $f7 -0x46 0x00 0x39 0x86 - -# CHECK: msub $6, $7 -0x70 0xc7 0x00 0x04 - -# CHECK: msubu $6, $7 -0x70 0xc7 0x00 0x05 - -# CHECK: mtc1 $6, $f7 -0x44 0x86 0x38 0x00 - -# CHECK: mthi $7 -0x00 0xe0 0x00 0x11 - -# CHECK: mtlo $7 -0x00 0xe0 0x00 0x13 - -# CHECK: mul.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x02 - -# CHECK: mul.s $f9, $f6, $f7 -0x46 0x07 0x32 0x42 - -# CHECK: mul $9, $6, $7 -0x70 0xc7 0x48 0x02 - -# CHECK: mult $3, $5 -0x00 0x65 0x00 0x18 - -# CHECK: multu $3, $5 -0x00 0x65 0x00 0x19 - -# CHECK: neg.d $f12, $f14 -0x46 0x20 0x73 0x07 - -# CHECK: neg.s $f6, $f7 -0x46 0x00 0x39 0x87 - -# CHECK: nop -0x00 0x00 0x00 0x00 - -# CHECK: nor $9, $6, $7 -0x00 0xc7 0x48 0x27 - -# CHECK: or $3, $3, $5 -0x00 0x65 0x18 0x25 - -# CHECK: ori $9, $6, 17767 -0x34 0xc9 0x45 0x67 - -# CHECK: rotr $9, $6, 7 -0x00 0x26 0x49 0xc2 - -# CHECK: rotrv $9, $6, $7 -0x00 0xe6 0x48 0x46 - -# CHECK: round.w.d $f12, $f14 -0x46 0x20 0x73 0x0c - -# CHECK: round.w.s $f6, $f7 -0x46 0x00 0x39 0x8c - -# CHECK: sb $4, 9158($5) -0xa0 0xa4 0x23 0xc6 - -# CHECK: sb $4, 6($5) -0xa0 0xa4 0x00 0x06 - -# CHECK: sc $9, 9158($7) -0xe0 0xe9 0x23 0xc6 - -# CHECK: sdc1 $f9, 9158($7) -0xf4 0xe9 0x23 0xc6 - -# CHECK: seb $6, $7 -0x7c 0x07 0x34 0x20 - -# CHECK: seh $6, $7 -0x7c 0x07 0x36 0x20 - -# CHECK: sh $4, 9158($5) -0xa4 0xa4 0x23 0xc6 - -# CHECK: sll $4, $3, 7 -0x00 0x03 0x21 0xc0 - -# CHECK: sllv $2, $3, $5 -0x00 0xa3 0x10 0x04 - -# CHECK: slt $3, $3, $5 -0x00 0x65 0x18 0x2a - -# CHECK: slti $3, $3, 103 -0x28 0x63 0x00 0x67 - -# CHECK: sltiu $3, $3, 103 -0x2c 0x63 0x00 0x67 - -# CHECK: sltu $3, $3, $5 -0x00 0x65 0x18 0x2b - -# CHECK: sqrt.d $f12, $f14 -0x46 0x20 0x73 0x04 - -# CHECK: sqrt.s $f6, $f7 -0x46 0x00 0x39 0x84 - -# CHECK: sra $4, $3, 7 -0x00 0x03 0x21 0xc3 - -# CHECK: srav $2, $3, $5 -0x00 0xa3 0x10 0x07 - -# CHECK: srl $4, $3, 7 -0x00 0x03 0x21 0xc2 - -# CHECK: srlv $2, $3, $5 -0x00 0xa3 0x10 0x06 - -# CHECK: sub.d $f8, $f12, $f14 -0x46 0x2e 0x62 0x01 - -# CHECK: sub.s $f9, $f6, $f7 -0x46 0x07 0x32 0x41 - -# CHECK: sub $9, $6, $7 -0x00 0xc7 0x48 0x22 - -# CHECK: subu $4, $3, $5 -0x00 0x65 0x20 0x23 - -# CHECK: suxc1 $f4, $24($5) -0x4c 0xb8 0x20 0x0d - -# CHECK: sw $4, 24($5) -0xac 0xa4 0x00 0x18 - -# CHECK: swc1 $f9, 9158($7) -0xe4 0xe9 0x23 0xc6 - -# CHECK: swl $4, 16($5) -0xa8 0xa4 0x00 0x10 - -# CHECK: swr $6, 16($7) -0xb8 0xe6 0x00 0x10 - -# CHECK: swxc1 $f26, $18($22) -0x4e 0xd2 0xd0 0x08 - -# CHECK: sync 7 -0x00 0x00 0x01 0xcf - -# CHECK: trunc.w.d $f12, $f14 -0x46 0x20 0x73 0x0d - -# CHECK: trunc.w.s $f6, $f7 -0x46 0x00 0x39 0x8d - -# CHECK: wsbh $6, $7 -0x7c 0x07 0x30 0xa0 - -# CHECK: xor $3, $3, $5 -0x00 0x65 0x18 0x26 - -# CHECK: xori $9, $6, 17767 -0x38 0xc9 0x45 0x67 - -# CHECK: synci -6137($fp) -0x07 0xdf 0xe8 0x07 diff --git a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt index d0eb13c5afd5e..c487b6d0e9607 100644 --- a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt +++ b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt @@ -101,6 +101,7 @@ 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -111,6 +112,7 @@ 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt index 96378357d19bd..d01384752907d 100644 --- a/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt @@ -2,171 +2,175 @@ # Try a mips64* triple to confirm that mips* vs mips64* triples no longer have # an effect on the disassembler behaviour. # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r2 | FileCheck %s -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 -0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 -0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) -0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) -0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 +0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) -0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 +0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) +0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index 81a05b330fde7..faaed7cb34534 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -269,6 +269,9 @@ # CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 +# CHECK: mfc0 $8, $16, 4 +0x04 0x80 0x08 0x40 + # CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 @@ -290,6 +293,9 @@ # CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 +# CHECK: mtc0 $9, $15, 1 +0x01 0x78 0x89 0x40 + # CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt index 1909e2a212703..37c14de4cb6a8 100644 --- a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt +++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt @@ -98,6 +98,7 @@ 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -108,6 +109,7 @@ 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt index a273c24f9c903..cf9e98675d255 100644 --- a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt +++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt @@ -1,169 +1,171 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 | FileCheck %s -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 -0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 -0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) -0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) -0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 +0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) -0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 +0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) +0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt index 62977dc3266ee..b68089b0a0781 100644 --- a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt +++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt @@ -98,6 +98,7 @@ 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -108,6 +109,7 @@ 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt index 39c46440946ec..282f3a2b05440 100644 --- a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt +++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt @@ -1,169 +1,171 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 | FileCheck %s -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 -0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 -0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) -0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) -0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 +0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) -0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 +0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) +0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) diff --git a/test/MC/Disassembler/Mips/mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6.txt deleted file mode 100644 index afef8ada152bb..0000000000000 --- a/test/MC/Disassembler/Mips/mips32r6.txt +++ /dev/null @@ -1,127 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 | FileCheck %s - -0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 -0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 -0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 -0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 -0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 -0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 - -# FIXME: Don't check the immediate on these for the moment, the encode/decode -# functions are not inverses of eachother. -# The immediate should be 4 but the disassembler currently emits 8 -0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, -0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, -0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, -0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, -# FIXME: Don't check the immediate on these for the moment, the encode/decode -# functions are not inverses of eachother. -# The immediate should be 8 but the disassembler currently emits 12 -0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, -0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, -0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, -0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, - -0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 -# FIXME: Don't check the immediate on the bcczal's for the moment, the -# encode/decode functions are not inverses of eachother. -0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, -0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 -0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, -0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 -0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 -0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 -0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, -0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 -0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 -0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 -0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, -0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 -0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, -0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 -0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 -0x18 0x02 0x01 0x4d # CHECK: blezalc $2, -0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 -0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 -0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 -0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 -0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 -0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 -0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 -0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 -0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 -0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 -0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 -0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 -0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 -0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 -# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 -# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 -0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 -0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 -0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 -0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 -0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 -0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 -0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 -0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 -0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 -0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 -0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 -0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 -0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 -0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 -0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 -0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 -0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 -0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 -0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 -0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 -0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 -0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 -0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) -0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) -0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 -0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt index c10d16699b77f..94dc3a2645d90 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt @@ -83,6 +83,7 @@ 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 3 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4 @@ -93,6 +94,7 @@ 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2 0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2 0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4 diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index 0b78003420b65..e1721b9348357 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -1,148 +1,173 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 | FileCheck %s -0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 -0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 -0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 -0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 -0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0x00 0x00 0x00 0x0e # CHECK: sdbbp +0x00 0x00 0x00 0x0f # CHECK: sync +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x00 0x4f # CHECK: sync 1 +0x00 0x00 0x08 0x8e # CHECK: sdbbp 34 +0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 +0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 +0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 +0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 +0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 +0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 +0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 +0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 +0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 +0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp 0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 -0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 -0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, 8 -0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, 8 -0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, 8 -0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, 8 -0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 -0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 -0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 -0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 -0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 -0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 -0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 -0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 -0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 -0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 -0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 +# FIXME: The encode/decode functions are not inverses of each other. +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 +# FIXME: The encode/decode functions are not inverses of each other. 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 -0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 -0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 -0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 +# FIXME: The encode/decode functions are not inverses of each other. 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 -0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +# FIXME: The encode/decode functions are not inverses of each other. 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 -0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 -0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 -0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 -0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 -0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 -0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 -0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +# FIXME: The encode/decode functions are not inverses of each other. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 +0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 +0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, 8 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 -0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3 -0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 -0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 -0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 -0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 -0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 -0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 -0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 -0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 -0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 -0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 -0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 -0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 -0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 -0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 -0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 -0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 -0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 -0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 -0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 -0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 -0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 -0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) -0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) -0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 -0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x00 0x00 0x00 0x0e # CHECK: sdbbp -0x00 0x00 0x08 0x8e # CHECK: sdbbp 34 -0x00 0x00 0x00 0x0f # CHECK: sync -0x00 0x00 0x00 0x4f # CHECK: sync 1 -0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 -0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 -0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 -0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 -0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp -0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 -0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 -0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 -0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 -0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 -0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 -0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 -0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) -0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) -0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 -0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 +0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) +0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 +0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 +0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 +0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +# FIXME: The encode/decode functions are not inverses of each other. +0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 +0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 +0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) +0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) +0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 +0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 +0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 +0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 diff --git a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt index 2f7cbe9f95302..207f4087791df 100644 --- a/test/MC/Disassembler/Mips/mips4/valid-mips4.txt +++ b/test/MC/Disassembler/Mips/mips4/valid-mips4.txt @@ -1,231 +1,229 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s # CHECK: .text -0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 -0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x00 0xc0 # CHECK: ehb +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 +0x00 0x00 0x88 0x12 # CHECK: mflo $17 +0x00 0x00 0x98 0x10 # CHECK: mfhi $19 +0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp +0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 +0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 +0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 +0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 +0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 +0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 +0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 +0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 +0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 +0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 +0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 +0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 +0x01 0x1c 0xe0 0x01 # CHECK: movf $gp, $8, $fcc7 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 +0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 +0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 +0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp +0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 +0x02 0x20 0x00 0x11 # CHECK: mthi $17 +0x02 0x30 0x18 0x0b # CHECK: movn $3, $17, $16 0x02 0x45 0xb8 0x20 # CHECK: add $23, $18, $5 +0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 +0x02 0x95 0x00 0x01 # CHECK: movt $zero, $20, $fcc5 +0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xc9 0x28 0x0a # CHECK: movz $5, $22, $9 +0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 +0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x03 0x20 0x00 0x13 # CHECK: mtlo $25 +0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 +0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 +0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp +0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 +0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp +0x04 0x11 0x14 0x9b # CHECK: bal 21104 +0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 +0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 +0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 +0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 +0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 +0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 0x21 0xc9 0x3b 0x48 # CHECK: addi $9, $14, 15176 +0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 0x23 0x18 0xe3 0xe7 # CHECK: addi $24, $24, -7193 -0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 -0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 -0x21 0x2d 0x66 0xd2 # CHECK: addi $13, $9, 26322 -0x21 0x08 0xff 0xfe # CHECK: addi $8, $8, -2 -0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6 +0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12 +0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 +0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 +0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 +0x42 0x00 0x00 0x01 # CHECK: tlbr +0x42 0x00 0x00 0x02 # CHECK: tlbwi +0x42 0x00 0x00 0x06 # CHECK: tlbwr +0x42 0x00 0x00 0x08 # CHECK: tlbp +0x42 0x00 0x00 0x18 # CHECK: eret +0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 +0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 0x45 0x00 0x00 0x01 # CHECK: bc1f 8 -0x45 0x04 0x00 0x00 # CHECK: bc1f $fcc1, 4 -0x45 0x1e 0x00 0x06 # CHECK: bc1fl $fcc7, 28 -0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x01 0x00 0x01 # CHECK: bc1t 8 -0x45 0x05 0x00 0x00 # CHECK: bc1t $fcc1, 4 +0x45 0x02 0x00 0x0c # CHECK: bc1fl 52 0x45 0x03 0xf7 0xf4 # CHECK: bc1tl -8236 +0x45 0x04 0x00 0x00 # CHECK: bc1f $fcc1, 4 +0x45 0x05 0x00 0x00 # CHECK: bc1t $fcc1, 4 +0x45 0x1e 0x00 0x06 # CHECK: bc1fl $fcc7, 28 0x45 0x1f 0x00 0x06 # CHECK: bc1tl $fcc7, 28 -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 -0x00 0x00 0x00 0x00 # CHECK: nop -0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 -0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x04 0x83 0xf9 0x4d # CHECK: bgezl $4, -6856 -0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 -0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 -0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 -0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 -0xbc 0xa1 0x00 0x08 # CHECK: cache 1, 8($5) -0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 -0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 -0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 -0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 -0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 +0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 -0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 +0x46 0x00 0x82 0x45 # CHECK: abs.s $f9, $f16 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 -0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21 -0x44 0xc6 0xd0 0x00 # CHECK: ctc1 $6, $26 +0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 +0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 0x46 0x00 0xe5 0xa1 # CHECK: cvt.d.s $f22, $f28 -0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15 +0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 0x46 0x00 0xea 0xe5 # CHECK: cvt.l.s $f11, $f29 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 +0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 +0x46 0x03 0x3e 0x52 # CHECK: movz.s $f25, $f7, $3 +0x46 0x05 0x17 0x91 # CHECK: movt.s $f30, $f2, $fcc1 +0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 +0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 +0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 +0x46 0x17 0x03 0x13 # CHECK: movn.s $f12, $f0, $23 +0x46 0x18 0x2d 0xd1 # CHECK: movf.s $f23, $f5, $fcc6 +0x46 0x18 0xaa 0x00 # CHECK: add.s $f8, $f21, $f24 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 +0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 +0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8 -0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 +0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14 -0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 +0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15 +0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 +0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x20 0xc1 0x85 # CHECK: abs.d $f6, $f24 +0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 +0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 +0x46 0x21 0x10 0x11 # CHECK: movt.d $f0, $f2, $fcc0 +0x46 0x29 0xeb 0x12 # CHECK: movz.d $f12, $f29, $9 +0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 +0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 +0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 +0x46 0x34 0x59 0x91 # CHECK: movf.d $f6, $f11, $fcc5 +0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 +0x46 0x3a 0xae 0xd3 # CHECK: movn.d $f27, $f21, $26 +0x46 0x3c 0x30 0x00 # CHECK: add.d $f0, $f6, $f28 +0x46 0x3c 0xe0 0x3b # CHECK: c.ngl.d $f28, $f28 +0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11 +0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14) +0x4f 0x4c 0x98 0x08 # CHECK: swxc1 $f19, $12($26) +0x4f 0xd1 0x03 0x00 # CHECK: lwxc1 $f12, $17($fp) +0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548 +0x57 0x94 0x04 0xfc # CHECK: bnel $gp, $20, 5108 +0x58 0xc0 0x02 0xe7 # CHECK: blezl $6, 2976 +0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11 -0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26 -0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15 -0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 -0x00 0x00 0x00 0xc0 # CHECK: ehb -0x42 0x00 0x00 0x18 # CHECK: eret -0x46 0x20 0x53 0x8f # CHECK: floor.w.d $f14, $f10 -0x46 0x00 0x4a 0x0f # CHECK: floor.w.s $f8, $f9 -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 0x81 0x58 0xc7 0x4d # CHECK: lb $24, -14515($10) -0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) -0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) -0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) 0x86 0xab 0xde 0x94 # CHECK: lh $11, -8556($21) +0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) +0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) +0x90 0x68 0x75 0xf3 # CHECK: lbu $8, 30195($3) 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2) -0x24 0x01 0x8b 0xb3 # CHECK: addiu $1, $zero, -29773 -0x24 0x00 0x8b 0x3f # CHECK: addiu $zero, $zero, -29889 +0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) +0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) +0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) +0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) +0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) +0xbc 0xa1 0x00 0x08 # CHECK: cache 1, 8($5) 0xc2 0x42 0xe3 0x67 # CHECK: ll $2, -7321($18) -0x8c 0xa8 0x16 0x2a # CHECK: lw $8, 5674($5) 0xc7 0x50 0x27 0xf1 # CHECK: lwc1 $f16, 10225($26) 0xc8 0xd2 0xfc 0xb7 # CHECK: lwc2 $18, -841($6) -0x89 0xf4 0xef 0x79 # CHECK: lwl $20, -4231($15) -0x9b 0x80 0xb5 0x35 # CHECK: lwr $zero, -19147($gp) -0x4f 0xd1 0x03 0x00 # CHECK: lwxc1 $f12, $17($fp) -0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27 -0x00 0x00 0x98 0x10 # CHECK: mfhi $19 -0x00 0x00 0xe8 0x10 # CHECK: mfhi $sp -0x00 0x00 0x88 0x12 # CHECK: mflo $17 -0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14 -0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27 -0x01 0x1c 0xe0 0x01 # CHECK: movf $gp, $8, $fcc7 -0x46 0x34 0x59 0x91 # CHECK: movf.d $f6, $f11, $fcc5 -0x46 0x18 0x2d 0xd1 # CHECK: movf.s $f23, $f5, $fcc6 -0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4 -0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6 -0x02 0x30 0x18 0x0b # CHECK: movn $3, $17, $16 -0x46 0x3a 0xae 0xd3 # CHECK: movn.d $f27, $f21, $26 -0x46 0x17 0x03 0x13 # CHECK: movn.s $f12, $f0, $23 -0x02 0x95 0x00 0x01 # CHECK: movt $zero, $20, $fcc5 -0x46 0x21 0x10 0x11 # CHECK: movt.d $f0, $f2, $fcc0 -0x46 0x05 0x17 0x91 # CHECK: movt.s $f30, $f2, $fcc1 -0x02 0xc9 0x28 0x0a # CHECK: movz $5, $22, $9 -0x46 0x29 0xeb 0x12 # CHECK: movz.d $f12, $f29, $9 -0x46 0x03 0x3e 0x52 # CHECK: movz.s $f25, $f7, $3 -0x44 0x9e 0x48 0x00 # CHECK: mtc1 $fp, $f9 -0x02 0x20 0x00 0x11 # CHECK: mthi $17 -0x03 0xa0 0x00 0x13 # CHECK: mtlo $sp -0x03 0x20 0x00 0x13 # CHECK: mtlo $25 -0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16 -0x46 0x02 0x57 0x82 # CHECK: mul.s $f30, $f10, $f2 -0x03 0xb4 0x00 0x18 # CHECK: mult $sp, $20 -0x03 0xa2 0x00 0x18 # CHECK: mult $sp, $2 -0x03 0x9a 0x00 0x19 # CHECK: multu $gp, $26 -0x01 0x32 0x00 0x19 # CHECK: multu $9, $18 -0x00 0x02 0x10 0x23 # CHECK: negu $2, $2 -0x00 0x03 0x10 0x23 # CHECK: negu $2, $3 -0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18 -0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0x07 0x38 0x27 # CHECK: nor $7, $zero, $7 -0x02 0x1d 0x60 0x25 # CHECK: or $12, $16, $sp -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0xcc 0xa1 0x00 0x08 # CHECK: pref 1, 8($5) -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x21 0x8c # CHECK: round.w.d $f6, $f4 -0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28 -0xa1 0xd6 0xb2 0x6f # CHECK: sb $22, -19857($14) +0xd6 0x0a 0x40 0x07 # CHECK: ldc1 $f10, 16391($16) +0xd8 0x28 0xad 0x43 # CHECK: ldc2 $8, -21181($1) 0xe2 0x6f 0x49 0xd8 # CHECK: sc $15, 18904($19) +0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) +0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) 0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13) 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18) -0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14) -0xa5 0xee 0xe5 0xd0 # CHECK: sh $14, -6704($15) -0x00 0x07 0x3c 0x80 # CHECK: sll $7, $7, 18 -0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9 -0x01 0x7b 0xb8 0x2a # CHECK: slt $23, $11, $27 -0x29 0x51 0x25 0x11 # CHECK: slti $17, $10, 9489 -0x2f 0x39 0xc3 0x55 # CHECK: sltiu $25, $25, -15531 -0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11 -0x2f 0x38 0xc3 0x55 # CHECK: sltiu $24, $25, -15531 -0x46 0x20 0xb4 0x04 # CHECK: sqrt.d $f16, $f22 -0x46 0x00 0x08 0x04 # CHECK: sqrt.s $f0, $f1 -0x00 0x11 0x8b 0xc3 # CHECK: sra $17, $17, 15 -0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15 -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x03 0xb7 0x88 0x07 # CHECK: srav $17, $23, $sp -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x02 0x11 0xc2 # CHECK: srl $2, $2, 7 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4 -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x02 0x6c 0xb0 0x22 # CHECK: sub $22, $19, $12 -0x22 0x36 0x0c 0x36 # CHECK: addi $22, $17, 3126 -0x21 0xad 0xe6 0x90 # CHECK: addi $13, $13, -6512 -0x46 0x30 0x14 0x81 # CHECK: sub.d $f18, $f2, $f16 -0x46 0x16 0xb5 0xc1 # CHECK: sub.s $f23, $f22, $f22 -0x02 0xd6 0xe8 0x23 # CHECK: subu $sp, $22, $22 -0xaf 0xbf 0xd8 0x50 # CHECK: sw $ra, -10160($sp) -0xe7 0x06 0xde 0xef # CHECK: swc1 $f6, -8465($24) -0xea 0x19 0x61 0x30 # CHECK: swc2 $25, 24880($16) -0xaa 0x6f 0x35 0x7e # CHECK: swl $15, 13694($19) -0xb9 0xd1 0x98 0x22 # CHECK: swr $17, -26590($14) -0x4f 0x4c 0x98 0x08 # CHECK: swxc1 $f19, $12($26) -0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 -0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 -0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 -0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp -0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 -0x42 0x00 0x00 0x08 # CHECK: tlbp -0x42 0x00 0x00 0x01 # CHECK: tlbr -0x42 0x00 0x00 0x02 # CHECK: tlbwi -0x42 0x00 0x00 0x06 # CHECK: tlbwr -0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 -0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 -0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 -0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 -0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 -0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x75 0x8d # CHECK: trunc.w.d $f22, $f14 -0x46 0x00 0xf7 0x0d # CHECK: trunc.w.s $f28, $f30 -0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt deleted file mode 100644 index d494df6f9c248..0000000000000 --- a/test/MC/Disassembler/Mips/mips64.txt +++ /dev/null @@ -1,93 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s -# CHECK: daddiu $11, $26, 31949 -0x67 0x4b 0x7c 0xcd - -# CHECK: daddiu $sp, $sp, -32 -0x67 0xbd 0xff 0xe0 - -# CHECK: daddu $26, $1, $11 -0x00 0x2b 0xd0 0x2d - -# CHECK: ddiv $zero, $26, $22 -0x03 0x56 0x00 0x1e - -# CHECK: ddivu $zero, $9, $24 -0x01 0x38 0x00 0x1f - -# CHECK: dmfc1 $2, $f14 -0x44 0x22 0x70 0x00 - -# CHECK: dmtc1 $23, $f5 -0x44 0xb7 0x28 0x00 - -# CHECK: dmult $11, $26 -0x01 0x7a 0x00 0x1c - -# CHECK: dmultu $23, $13 -0x02 0xed 0x00 0x1d - -# CHECK: dsll $3, $24, 17 -0x00 0x18 0x1c 0x78 - -# CHECK: dsllv $gp, $27, $24 -0x03 0x1b 0xe0 0x14 - -# CHECK: dsra $1, $1, 30 -0x00 0x01 0x0f 0xbb - -# CHECK: dsrav $1, $1, $fp -0x03 0xc1 0x08 0x17 - -# CHECK: dsrl $10, $gp, 24 -0x00 0x1c 0x56 0x3a - -# CHECK: dsrlv $gp, $10, $23 -0x02 0xea 0xe0 0x16 - -# CHECK: dsubu $gp, $27, $24 -0x03 0x78 0xe0 0x2f - -# CHECK: lw $27, -15155($1) -0x8c 0x3b 0xc4 0xcd - -# CHECK: lui $1, 1 -0x3c 0x01 0x00 0x01 - -# CHECK: lwu $3, -1746($3) -0x9c 0x63 0xf9 0x2e - -# CHECK: lui $ra, 1 -0x3c 0x1f 0x00 0x01 - -# CHECK: sw $26, -15159($1) -0xac 0x3a 0xc4 0xc9 - -# CHECK: ld $26, 3958($zero) -0xdc 0x1a 0x0f 0x76 - -# CHECK: sd $6, 17767($zero) -0xfc 0x06 0x45 0x67 - -# CHECK: luxc1 $f0, $6($5) -0x4c 0xa6 0x00 0x05 - -# CHECK: lwxc1 $f20, $12($14) -0x4d 0xcc 0x05 0x00 - -# CHECK: suxc1 $f4, $24($5) -0x4c 0xb8 0x20 0x0d - -# CHECK: swxc1 $f26, $18($22) -0x4e 0xd2 0xd0 0x08 - -# CHECK: ldxc1 $f2, $2($10) -0x4d 0x42 0x00 0x81 - -# CHECK: sdxc1 $f8, $4($25) -0x4f 0x24 0x40 0x09 - -# CHECK: sdc2 $9, 9158($7) -0xf8 0xe9 0x23 0xc6 - -# CHECK: ldc2 $3, 9162($8) -0xd9 0x03 0x23 0xca diff --git a/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt b/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt index 698ebfb347997..2d52216fddaad 100644 --- a/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt +++ b/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt @@ -82,7 +82,9 @@ 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6 @@ -142,6 +144,7 @@ 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5) 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x12 0x28 0x00 0x00 # CHECK: mflo $5 @@ -149,6 +152,7 @@ 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7 diff --git a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt index 953e31f94634a..6cbf5d3206b02 100644 --- a/test/MC/Disassembler/Mips/mips64/valid-mips64.txt +++ b/test/MC/Disassembler/Mips/mips64/valid-mips64.txt @@ -1,218 +1,254 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x01 0x0f 0xbb # CHECK: dsra $1, $1, 30 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x18 0x1c 0x78 # CHECK: dsll $3, $24, 17 +0x00 0x1c 0x56 0x3a # CHECK: dsrl $10, $gp, 24 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x2b 0xd0 0x2d # CHECK: daddu $26, $1, $11 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x01 0x38 0x00 0x1f # CHECK: ddivu $zero, $9, $24 +0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23 +0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13 +0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22 +0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24 +0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x01 0x00 0x01 # CHECK: lui $1, 1 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x3c 0x1f 0x00 0x01 # CHECK: lui $ra, 1 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x08 0x80 0x04 # CHECK: mfc0 $8, $16, 4 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x22 0x70 0x00 # CHECK: dmfc1 $2, $f14 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 -0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 -0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 +0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0x42 0x00 0x81 # CHECK: ldxc1 $f2, $2($10) +0x4d 0xbb 0x60 0x0d # CHECK: suxc1 $f12, $27($13) +0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14) +0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0xb6 0x04 0xc5 # CHECK: luxc1 $f19, $22($21) +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x4f 0x4c 0x98 0x08 # CHECK: swxc1 $f19, $12($26) +0x4f 0xd1 0x03 0x00 # CHECK: lwxc1 $f12, $17($fp) +0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 +0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 -0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 -0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6 -0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 -0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 -0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 -0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) +0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 +0x67 0x4b 0x7c 0xcd # CHECK: daddiu $11, $26, 31949 +0x67 0xbd 0xff 0xe0 # CHECK: daddiu $sp, $sp, -32 0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) 0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 -0x4e 0xb6 0x04 0xc5 # CHECK: luxc1 $f19, $22($21) -0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3) -0x4f 0xd1 0x03 0x00 # CHECK: lwxc1 $f12, $17($fp) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) -0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) -0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) -0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) -0x4d 0xca 0x58 0x09 # CHECK: sdxc1 $f11, $10($14) -0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) -0x4d 0xbb 0x60 0x0d # CHECK: suxc1 $f12, $27($13) -0x4f 0x4c 0x98 0x08 # CHECK: swxc1 $f19, $12($26) -0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) -0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6 +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 +0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 0x7c 0x05 0xe8 0x3b # CHECK: .set push # CHECK: .set mips32r2 # CHECK: rdhwr $5, $29 # CHECK: .set pop +0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) +0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0x3b 0xc4 0xcd # CHECK: lw $27, -15155($1) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) +0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) +0x9c 0x63 0xf9 0x2e # CHECK: lwu $3, -1746($3) +0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3) +0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) +0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) +0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0x3a 0xc4 0xc9 # CHECK: sw $26, -15159($1) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) +0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) 0xbc 0x61 0x00 0x02 # CHECK: cache 1, 2($3) +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xc8 0xc8 0x23 0xca # CHECK: lwc2 $8, 9162($6) 0xcc 0x43 0x00 0x04 # CHECK: pref 3, 4($2) +0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xd9 0x03 0x23 0xca # CHECK: ldc2 $3, 9162($8) +0xdc 0x1a 0x0f 0x76 # CHECK: ld $26, 3958($zero) +0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xe8 0xe9 0x23 0xc6 # CHECK: swc2 $9, 9158($7) -0xc8 0xc8 0x23 0xca # CHECK: lwc2 $8, 9162($6) +0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) +0xf8 0xe9 0x23 0xc6 # CHECK: sdc2 $9, 9158($7) +0xfc 0x06 0x45 0x67 # CHECK: sd $6, 17767($zero) +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt deleted file mode 100644 index cee6f3c21f721..0000000000000 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ /dev/null @@ -1,90 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s -# CHECK: daddiu $11, $26, 31949 -0x67 0x4b 0x7c 0xcd - -# CHECK: daddu $26, $1, $11 -0x00 0x2b 0xd0 0x2d - -# CHECK: ddiv $zero, $26, $22 -0x03 0x56 0x00 0x1e - -# CHECK: ddivu $zero, $9, $24 -0x01 0x38 0x00 0x1f - -# CHECK: dmfc1 $2, $f14 -0x44 0x22 0x70 0x00 - -# CHECK: dmtc1 $23, $f5 -0x44 0xb7 0x28 0x00 - -# CHECK: dmult $11, $26 -0x01 0x7a 0x00 0x1c - -# CHECK: dmultu $23, $13 -0x02 0xed 0x00 0x1d - -# CHECK: dsll $3, $24, 17 -0x00 0x18 0x1c 0x78 - -# CHECK: dsllv $gp, $27, $24 -0x03 0x1b 0xe0 0x14 - -# CHECK: dsra $1, $1, 30 -0x00 0x01 0x0f 0xbb - -# CHECK: dsrav $1, $1, $fp -0x03 0xc1 0x08 0x17 - -# CHECK: dsrl $10, $gp, 24 -0x00 0x1c 0x56 0x3a - -# CHECK: dsrlv $gp, $10, $23 -0x02 0xea 0xe0 0x16 - -# CHECK: dsubu $gp, $27, $24 -0x03 0x78 0xe0 0x2f - -# CHECK: lw $27, -15155($1) -0x8c 0x3b 0xc4 0xcd - -# CHECK: lui $1, 1 -0x3c 0x01 0x00 0x01 - -# CHECK: lwu $3, -1746($3) -0x9c 0x63 0xf9 0x2e - -# CHECK: lui $ra, 1 -0x3c 0x1f 0x00 0x01 - -# CHECK: sw $26, -15159($1) -0xac 0x3a 0xc4 0xc9 - -# CHECK: ld $26, 3958($zero) -0xdc 0x1a 0x0f 0x76 - -# CHECK: sd $6, 17767($zero) -0xfc 0x06 0x45 0x67 - -# CHECK: dclo $9, $24 -0x73 0x09 0x48 0x25 - -# CHECK: dclz $26, $9 -0x71 0x3a 0xd0 0x24 - -# CHECK: dext $7, $gp, 29, 31 -0x7f 0x87 0xf7 0x43 - -# CHECK: dins $20, $gp, 15, 1 -0x7f 0x94 0x7b 0xc7 - -# CHECK: dsbh $7, $gp -0x7c 0x1c 0x38 0xa4 - -# CHECK: dshd $3, $14 -0x7c 0x0e 0x19 0x64 - -# CHECK: drotr $20, $27, 6 -0x00 0x3b 0xa1 0xba - -# CHECK: drotrv $24, $23, $5 -0x00 0xb7 0xc0 0x56 diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt index 6509456b07eeb..2c6859f27faa6 100644 --- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt +++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt @@ -88,7 +88,9 @@ 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6 @@ -161,6 +163,7 @@ 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -170,6 +173,7 @@ 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt index 79fcc769063c1..0c6e10ee37ce6 100644 --- a/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt @@ -3,237 +3,271 @@ # an effect on the disassembler behaviour. # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r2 | FileCheck %s # CHECK: .text -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x01 0x0f 0xbb # CHECK: dsra $1, $1, 30 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x18 0x1c 0x78 # CHECK: dsll $3, $24, 17 +0x00 0x1c 0x56 0x3a # CHECK: dsrl $10, $gp, 24 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 +0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x2b 0xd0 0x2d # CHECK: daddu $26, $1, $11 +0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 +0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 +0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xb7 0xc0 0x56 # CHECK: drotrv $24, $23, $5 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x01 0x38 0x00 0x1f # CHECK: ddivu $zero, $9, $24 +0x01 0x7a 0x00 0x1c # CHECK: dmult $11, $26 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x02 0xea 0xe0 0x16 # CHECK: dsrlv $gp, $10, $23 +0x02 0xed 0x00 0x1d # CHECK: dmultu $23, $13 +0x03 0x1b 0xe0 0x14 # CHECK: dsllv $gp, $27, $24 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22 +0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24 +0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x01 0x00 0x01 # CHECK: lui $1, 1 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x3c 0x1f 0x00 0x01 # CHECK: lui $ra, 1 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x22 0x70 0x00 # CHECK: dmfc1 $2, $f14 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 -0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 +0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 +0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 +0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 +0x67 0x4b 0x7c 0xcd # CHECK: daddiu $11, $26, 31949 +0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) +0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 +0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 +0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 +0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6 +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 +0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9 +0x73 0x09 0x48 0x25 # CHECK: dclo $9, $24 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 +0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 +0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14 +0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 +0x7c 0x1c 0x38 0xa4 # CHECK: dsbh $7, $gp 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp -0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 -0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 -0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 -0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 -0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 -0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 -0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 -0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x7f 0x87 0xf7 0x43 # CHECK: dext $7, $gp, 29, 31 +0x7f 0x94 0x7b 0xc7 # CHECK: dins $20, $gp, 15, 1 0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) -0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) -0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 -0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0x3b 0xc4 0xcd # CHECK: lw $27, -15155($1) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) -0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) +0x9c 0x63 0xf9 0x2e # CHECK: lwu $3, -1746($3) 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 -0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 -0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 -0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 -0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 -0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) -0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 -0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0x3a 0xc4 0xc9 # CHECK: sw $26, -15159($1) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xdc 0x1a 0x0f 0x76 # CHECK: ld $26, 3958($zero) +0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) +0xfc 0x06 0x45 0x67 # CHECK: sd $6, 17767($zero) +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt index 52374af28933d..88e9c262a0eea 100644 --- a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt +++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt @@ -85,7 +85,9 @@ 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6 @@ -158,6 +160,7 @@ 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -167,6 +170,7 @@ 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt index acd59fc721e33..82405f357bf4d 100644 --- a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt +++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt @@ -1,236 +1,240 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 | FileCheck %s # CHECK: .text -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 +0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 +0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 -0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 +0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 +0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 +0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 +0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) +0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 +0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 +0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 +0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6 +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 +0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 +0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp -0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 -0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 -0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 -0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 -0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 -0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 -0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 -0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) -0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) -0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 -0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) -0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 -0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 -0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 -0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 -0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 -0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) -0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 -0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt index 3d97a2b30ce3f..bd709d2287940 100644 --- a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt +++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt @@ -85,7 +85,9 @@ 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6 @@ -158,6 +160,7 @@ 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7 0x10 0x28 0x00 0x00 # CHECK: mfhi $5 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24 @@ -167,6 +170,7 @@ 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7 0x11 0x00 0xe0 0x00 # CHECK: mthi $7 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16 diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt index ce414edc345c9..1b30144acab47 100644 --- a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt +++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt @@ -1,236 +1,240 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 | FileCheck %s # CHECK: .text -0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 -0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x00 0x00 0x00 0x00 # CHECK: nop +0x00 0x00 0x01 0xcf # CHECK: sync 7 +0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 +0x00 0x00 0x28 0x10 # CHECK: mfhi $5 +0x00 0x00 0x28 0x12 # CHECK: mflo $5 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 +0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 +0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 +0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 +0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 +0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 +0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 +0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 +0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 +0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 +0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 +0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 +0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 +0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 +0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 +0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 +0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 +0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra +0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 +0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 +0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 +0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 +0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 +0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 +0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 +0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 +0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 +0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 +0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7 -0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 -0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 -0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 -0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7 +0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7 -0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 +0x00 0xe0 0x00 0x08 # CHECK: jr $7 +0x00 0xe0 0x00 0x11 # CHECK: mthi $7 +0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 +0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 +0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 +0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 +0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 +0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 +0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 +0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 +0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 +0x08 0x00 0x01 0x4c # CHECK: j 1328 +0x0c 0x00 0x01 0x4c # CHECK: jal 1328 0x10 0x00 0x01 0x4c # CHECK: b 1332 +0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 +0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 +0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 +0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 +0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767 +0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001 +0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 +0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 +0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767 +0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 +0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 +0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 +0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 +0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 +0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 +0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 +0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 +0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332 -0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x01 0x01 0x4c # CHECK: bc1t 1332 +0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332 0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332 -0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332 -0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332 -0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 -0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332 -0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332 -0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332 -0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 -0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 -0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 +0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 +0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 +0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7 +0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 +0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 +0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 +0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 +0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 +0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 +0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 +0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 +0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7 -0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 -0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 -0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7 +0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 +0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 +0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 +0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 +0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 +0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 +0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 -0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 -0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 -0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 -0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 -0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 -0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 -0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 -0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7 -0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 -0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7 -0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 -0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 -0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 -0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 -0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 +0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 +0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 -0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 -0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7 -0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 -0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 -0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 -0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 -0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 +0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 +0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 +0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 -0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 -0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 -0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 -0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 -0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7 -0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 -0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7 -0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 -0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 -0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7 -0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 -0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 -0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7 -0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra +0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 +0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 +0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 +0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 +0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) +0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 +0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) +0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) +0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) +0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 +0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) +0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 +0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) +0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 +0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 -0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705 +0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 +0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705 -0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 -0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 +0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 +0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 +0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586 +0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) +0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) +0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 +0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 +0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 +0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 +0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6 +0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7 +0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25 -0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19 -0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17 -0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13 -0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14 -0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9 -0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18 -0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18 -0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12 -0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10 -0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10 -0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10 -0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19 -0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23 -0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23 -0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23 -0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20 -0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8 +0x74 0x00 0x01 0x4c # CHECK: jalx 1328 +0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 +0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 +0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp -0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705 -0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705 -0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26 -0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 -0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x41 0x60 0x60 0x00 # CHECK: di -0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15 -0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15 -0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15 -0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15 -0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15 -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x41 0x60 0x60 0x20 # CHECK: ei -0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7 -0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5 -0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 -0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7 0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7 -0x08 0x00 0x01 0x4c # CHECK: j 1328 -0x0c 0x00 0x01 0x4c # CHECK: jal 1328 -0x74 0x00 0x01 0x4c # CHECK: jalx 1328 -0x00 0xe0 0xf8 0x09 # CHECK: jalr $7 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x00 0xe0 0x00 0x08 # CHECK: jr $7 0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5) -0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) -0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) -0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24) -0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20) -0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) -0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5) -0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) -0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) -0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767 -0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) -0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) -0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4) +0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5) +0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5) 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5) -0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14) 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3) -0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7 -0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 -0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7 -0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7 -0x00 0x00 0x28 0x10 # CHECK: mfhi $5 -0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24 -0x00 0x00 0x28 0x12 # CHECK: mflo $5 -0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 -0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7 -0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 -0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7 -0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7 -0x00 0xe0 0x00 0x11 # CHECK: mthi $7 -0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16 -0x00 0xe0 0x00 0x13 # CHECK: mtlo $7 -0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 -0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 -0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7 -0x00 0x65 0x00 0x18 # CHECK: mult $3, $5 -0x00 0x65 0x00 0x19 # CHECK: multu $3, $5 -0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 -0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x00 0x00 0x00 0x00 # CHECK: nop -0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 -0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5 -0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767 -0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7 -0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7 -0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1 -0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5 -0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 -0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7 -0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5) -0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) -0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) -0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) -0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) -0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) -0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) -0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25) -0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7 -0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7 +0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5) 0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5) -0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7 -0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5 -0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5 -0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103 -0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103 -0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5 -0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 -0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7 -0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7 -0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5 -0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7 -0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5 -0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 -0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 -0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7 -0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5 -0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5) -0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) -0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) 0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5) +0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5) +0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp) +0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12) 0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7) -0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22) -0x00 0x00 0x01 0xcf # CHECK: sync 7 -0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23 -0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31 -0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 -0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7 -0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7 -0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5 -0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767 +0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7) +0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7) +0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra) +0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7) +0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17) +0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7) +0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7) +0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp) +0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7) +0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10) diff --git a/test/MC/Disassembler/Mips/mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6.txt deleted file mode 100644 index 3ddef9ab42ab2..0000000000000 --- a/test/MC/Disassembler/Mips/mips64r6.txt +++ /dev/null @@ -1,145 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s - -0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 -0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 -0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 -0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 -0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 -0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 -0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 - -# FIXME: Don't check the immediate on these for the moment, the encode/decode -# functions are not inverses of eachother. -# The immediate should be 4 but the disassembler currently emits 8 -0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, -0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, -0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, -0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, -# FIXME: Don't check the immediate on these for the moment, the encode/decode -# functions are not inverses of eachother. -# The immediate should be 8 but the disassembler currently emits 12 -0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, -0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, -0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, -0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, - -0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 -# FIXME: Don't check the immediate on the bcczal's for the moment, the -# encode/decode functions are not inverses of eachother. -0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, -0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 -0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, -0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 -0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 -0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 -0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, -0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 -0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 -0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 -0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, -0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 -0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, -0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 -0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 -0x18 0x02 0x01 0x4d # CHECK: blezalc $2, -0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 -0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 -0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 -0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 -0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 -0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 -0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 -0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 -0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 -0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 -0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 -0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 -0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 -0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 -0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 -0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 -0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 -0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 -0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 -# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 -# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 -0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 -0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 -0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 -0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 -0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4 -0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4 -0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 -0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 -0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 -0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 -0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 -0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 -0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4 -0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4 -0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4 -0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4 -0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 -0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 -0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 -0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 -0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 -0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 -0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 -0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 -0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 -0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 -0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 -0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 -0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 -0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 -0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 -0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 -0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) -0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) -0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) -0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) -0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 -0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp -0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6 -0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index 4afd9cc5c4f56..157e33593e37d 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -92,8 +92,10 @@ 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4 @@ -119,12 +121,14 @@ 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4 diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index c41ba990122e5..45379d9c8988a 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -1,168 +1,196 @@ # RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s +0x00 0x00 0x00 0x0e # CHECK: sdbbp +0x00 0x00 0x00 0x0f # CHECK: sync +0x00 0x00 0x00 0x40 # CHECK: ssnop +0x00 0x00 0x00 0x4f # CHECK: sync 1 +0x00 0x00 0x08 0x8e # CHECK: sdbbp 34 +0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 +0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 +0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 +0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4 +0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4 +0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4 +0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4 +0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3 +0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4 +0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4 +0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 +0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 +0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 +0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 +0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6 +0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 +0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 +0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 +0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 +0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 +0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 +0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp +0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp +0x04 0x11 0x14 0x9b # CHECK: bal 21104 +0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 +0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 +# FIXME: The encode/decode functions are not inverses of each other. +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 +# FIXME: The encode/decode functions are not inverses of each other. +0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 +0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 +# FIXME: The encode/decode functions are not inverses of each other. +0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 +# FIXME: The encode/decode functions are not inverses of each other. +0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 +0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 +0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +# FIXME: The encode/decode functions are not inverses of each other. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 +0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 +0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 -0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 -0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 -0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 +0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 -0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 -0x04 0x11 0x14 0x9b # CHECK: bal 21104 -0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 -0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 +0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 +0x41 0x60 0x60 0x00 # CHECK: di +0x41 0x60 0x60 0x20 # CHECK: ei +0x41 0x6e 0x60 0x20 # CHECK: ei $14 +0x41 0x7e 0x60 0x00 # CHECK: di $fp +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, 8 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 4 but the disassembler currently emits 8 0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, 8 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 +0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 +0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 +0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 +0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) +0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 +# FIXME: The encode/decode functions are not inverses of each other. +# The immediate should be 8 but the disassembler currently emits 12 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 -0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 -0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 -0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) +0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 -0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 -0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 -0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 -0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 -0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 -0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 -0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 -0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 -0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 -0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +# FIXME: The encode/decode functions are not inverses of each other. 0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 -0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 -0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 -0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 -0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 -0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 -0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) -0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 -0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 -0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 -0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp -0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 -0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 -0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 -0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 -0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 -0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 -0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 -0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 -0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6 -0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 -0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4 -0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4 -0x41 0x60 0x60 0x00 # CHECK: di -0x41 0x7e 0x60 0x00 # CHECK: di $fp -0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 -0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 -0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3 -0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 -0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 -0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4 -0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4 -0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4 -0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4 -0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3 -0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3 -0x41 0x60 0x60 0x20 # CHECK: ei -0x41 0x6e 0x60 0x20 # CHECK: ei $14 -0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 -0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 -0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 -0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 -0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 -0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) -0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 +0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 +0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) +0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) +0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) +0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) 0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) -0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3 -0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 +0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 -0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 -0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 -0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 -0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 -0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 -0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 -0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 -0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 -0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 -0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 -0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 -0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 -0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 -0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 -0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) -0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 -0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 -0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) -0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) -0x00 0x00 0x00 0x0e # CHECK: sdbbp -0x00 0x00 0x08 0x8e # CHECK: sdbbp 34 -0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) -0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 -0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 -0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 -0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 -0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 -0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 -0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 -0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 -0x00 0x00 0x00 0x40 # CHECK: ssnop -0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) -0x00 0x00 0x00 0x0f # CHECK: sync -0x00 0x00 0x00 0x4f # CHECK: sync 1 -0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620 -0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3 -0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340 -0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 -0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 -0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp -0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 -0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133 -0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 -0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 -0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 -0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt index 0e3a83f6d3a53..16ff14c794d66 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -99,6 +99,12 @@ # CHECK: vmrglw 2, 3, 4 0x10 0x43 0x21 0x8c +# CHECK: vmrgew 2, 3, 4 +0x10 0x43 0x27 0x8c + +# CHECK: vmrgow 2, 3, 4 +0x10 0x43 0x26 0x8c + # CHECK: vspltb 2, 3, 1 0x10 0x41 0x1a 0x0c diff --git a/test/MC/Disassembler/X86/x86-16.txt b/test/MC/Disassembler/X86/x86-16.txt index c6844cd3cef44..021cb2371812b 100644 --- a/test/MC/Disassembler/X86/x86-16.txt +++ b/test/MC/Disassembler/X86/x86-16.txt @@ -786,3 +786,5 @@ # CHECK: lretl 0x66 0xcb +# CHECK: callw -1 +0xe8 0xff 0xff diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 830b830663024..c51e0a3dc3798 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -54,6 +54,9 @@ # CHECK: calll -1234 0xe8 0x2e 0xfb 0xff 0xff +# CHECK: callw -1 +0x66 0xe8 0xff 0xff + # CHECK: lfence 0x0f 0xae 0xe8 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index 5699f40d2d331..065b2a57c844e 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -339,3 +339,9 @@ # CHECK: vaddps (%rdx,%xmm1), %zmm20, %zmm15 # FIXME: vaddps (%rdx,%rcx), %zmm20, %zmm15 0x62 0x71 0x5c 0x40 0x58 0x3c 0x0a + +# CHECK: callq 32767 +0xe8 0xff 0x7f 0x00 0x00 + +# CHECK: callq -32769 +0xe8 0xff 0x7f 0xff 0xff diff --git a/test/MC/ELF/discriminator.s b/test/MC/ELF/discriminator.s index 8a695b96ede12..75e4e86cee0f9 100644 --- a/test/MC/ELF/discriminator.s +++ b/test/MC/ELF/discriminator.s @@ -19,12 +19,12 @@ foo: .long .L.debug_abbrev_begin # Offset Into Abbrev. Section .byte 8 # Address Size (in bytes) .byte 1 # Abbrev [1] 0xb:0x1b DW_TAG_compile_unit - .long .Linfo_string0 # DW_AT_producer + .long info_string0 # DW_AT_producer .short 12 # DW_AT_language - .long .Linfo_string1 # DW_AT_name + .long info_string1 # DW_AT_name .quad 0 # DW_AT_low_pc .long 0 # DW_AT_stmt_list - .long .Linfo_string2 # DW_AT_comp_dir + .long info_string2 # DW_AT_comp_dir # DW_AT_APPLE_optimized .section .debug_abbrev,"",@progbits .L.debug_abbrev_begin: diff --git a/test/MC/ELF/many-sections-3.s b/test/MC/ELF/many-sections-3.s new file mode 100644 index 0000000000000..02d30a60523b9 --- /dev/null +++ b/test/MC/ELF/many-sections-3.s @@ -0,0 +1,107 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t +// RUN: llvm-readobj -t %t | FileCheck --check-prefix=SYMBOLS %s +// RUN: llvm-nm %t | FileCheck --check-prefix=NM %s + +// Test that symbol a has a section that could be confused with common (0xFFF2) +// SYMBOLS: Name: a +// SYMBOLS-NEXT: Value: 0x0 +// SYMBOLS-NEXT: Size: 0 +// SYMBOLS-NEXT: Binding: Local (0x0) +// SYMBOLS-NEXT: Type: None (0x0) +// SYMBOLS-NEXT: Other: 0 +// SYMBOLS-NEXT: Section: bar (0xFFF2) +// SYMBOLS-NEXT: } + +// Test that we don't get confused +// NM: 0000000000000000 r a + +.macro gen_sections4 x + .section a\x + .section b\x + .section c\x + .section d\x +.endm + +.macro gen_sections8 x + gen_sections4 a\x + gen_sections4 b\x +.endm + +.macro gen_sections16 x + gen_sections8 a\x + gen_sections8 b\x +.endm + +.macro gen_sections32 x + gen_sections16 a\x + gen_sections16 b\x +.endm + +.macro gen_sections64 x + gen_sections32 a\x + gen_sections32 b\x +.endm + +.macro gen_sections128 x + gen_sections64 a\x + gen_sections64 b\x +.endm + +.macro gen_sections256 x + gen_sections128 a\x + gen_sections128 b\x +.endm + +.macro gen_sections512 x + gen_sections256 a\x + gen_sections256 b\x +.endm + +.macro gen_sections1024 x + gen_sections512 a\x + gen_sections512 b\x +.endm + +.macro gen_sections2048 x + gen_sections1024 a\x + gen_sections1024 b\x +.endm + +.macro gen_sections4096 x + gen_sections2048 a\x + gen_sections2048 b\x +.endm + +.macro gen_sections8192 x + gen_sections4096 a\x + gen_sections4096 b\x +.endm + +.macro gen_sections16384 x + gen_sections8192 a\x + gen_sections8192 b\x +.endm + +.macro gen_sections32768 x + gen_sections16384 a\x + gen_sections16384 b\x +.endm + +gen_sections32768 a +gen_sections16384 b +gen_sections8192 c +gen_sections4096 d +gen_sections2048 e +gen_sections1024 f +gen_sections512 g +gen_sections256 h +gen_sections128 i +gen_sections64 j +gen_sections32 k +gen_sections8 l +gen_sections4 m + + .section foo + .section bar, "a" + +a: diff --git a/test/MC/ELF/relax-arith.s b/test/MC/ELF/relax-arith.s index b8145564db082..d4f37a9ddf9f5 100644 --- a/test/MC/ELF/relax-arith.s +++ b/test/MC/ELF/relax-arith.s @@ -1,17 +1,18 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s // Test that we correctly relax these instructions into versions that use // 16 or 32 bit immediate values. bar: -// CHECK: Name: imul -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6669DB00 0066691C 25000000 00000069 -// CHECK-NEXT: 0010: DB000000 00691C25 00000000 00000000 -// CHECK-NEXT: 0020: 4869DB00 00000048 691C2500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section imul +// CHECK: Disassembly of section imul: +// CHECK-NEXT: imul: +// CHECK-NEXT: 0: 66 69 db 00 00 imulw $0, %bx, %bx +// CHECK-NEXT: 5: 66 69 1c 25 00 00 00 00 00 00 imulw $0, 0, %bx +// CHECK-NEXT: f: 69 db 00 00 00 00 imull $0, %ebx, %ebx +// CHECK-NEXT: 15: 69 1c 25 00 00 00 00 00 00 00 00 imull $0, 0, %ebx +// CHECK-NEXT: 20: 48 69 db 00 00 00 00 imulq $0, %rbx, %rbx +// CHECK-NEXT: 27: 48 69 1c 25 00 00 00 00 00 00 00 00 imulq $0, 0, %rbx + .section imul,"x" imul $foo, %bx, %bx imul $foo, bar, %bx imul $foo, %ebx, %ebx @@ -19,15 +20,15 @@ bar: imul $foo, %rbx, %rbx imul $foo, bar, %rbx - -// CHECK: Name: and -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6681E300 00668124 25000000 00000081 -// CHECK-NEXT: 0010: E3000000 00812425 00000000 00000000 -// CHECK-NEXT: 0020: 4881E300 00000048 81242500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section and +// CHECK: Disassembly of section and: +// CHECK-NEXT: and: +// CHECK-NEXT: 0: 66 81 e3 00 00 andw $0, %bx +// CHECK-NEXT: 5: 66 81 24 25 00 00 00 00 00 00 andw $0, 0 +// CHECK-NEXT: f: 81 e3 00 00 00 00 andl $0, %ebx +// CHECK-NEXT: 15: 81 24 25 00 00 00 00 00 00 00 00 andl $0, 0 +// CHECK-NEXT: 20: 48 81 e3 00 00 00 00 andq $0, %rbx +// CHECK-NEXT: 27: 48 81 24 25 00 00 00 00 00 00 00 00 andq $0, 0 + .section and,"x" and $foo, %bx andw $foo, bar and $foo, %ebx @@ -35,14 +36,15 @@ bar: and $foo, %rbx andq $foo, bar -// CHECK: Name: or -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6681CB00 0066810C 25000000 00000081 -// CHECK-NEXT: 0010: CB000000 00810C25 00000000 00000000 -// CHECK-NEXT: 0020: 4881CB00 00000048 810C2500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section or +// CHECK: Disassembly of section or: +// CHECK-NEXT: or: +// CHECK-NEXT: 0: 66 81 cb 00 00 orw $0, %bx +// CHECK-NEXT: 5: 66 81 0c 25 00 00 00 00 00 00 orw $0, 0 +// CHECK-NEXT: f: 81 cb 00 00 00 00 orl $0, %ebx +// CHECK-NEXT: 15: 81 0c 25 00 00 00 00 00 00 00 00 orl $0, 0 +// CHECK-NEXT: 20: 48 81 cb 00 00 00 00 orq $0, %rbx +// CHECK-NEXT: 27: 48 81 0c 25 00 00 00 00 00 00 00 00 orq $0, 0 + .section or,"x" or $foo, %bx orw $foo, bar or $foo, %ebx @@ -50,14 +52,15 @@ bar: or $foo, %rbx orq $foo, bar -// CHECK: Name: xor -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6681F300 00668134 25000000 00000081 -// CHECK-NEXT: 0010: F3000000 00813425 00000000 00000000 -// CHECK-NEXT: 0020: 4881F300 00000048 81342500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section xor +// CHECK: Disassembly of section xor: +// CHECK-NEXT: xor: +// CHECK-NEXT: 0: 66 81 f3 00 00 xorw $0, %bx +// CHECK-NEXT: 5: 66 81 34 25 00 00 00 00 00 00 xorw $0, 0 +// CHECK-NEXT: f: 81 f3 00 00 00 00 xorl $0, %ebx +// CHECK-NEXT: 15: 81 34 25 00 00 00 00 00 00 00 00 xorl $0, 0 +// CHECK-NEXT: 20: 48 81 f3 00 00 00 00 xorq $0, %rbx +// CHECK-NEXT: 27: 48 81 34 25 00 00 00 00 00 00 00 00 xorq $0, 0 + .section xor,"x" xor $foo, %bx xorw $foo, bar xor $foo, %ebx @@ -65,14 +68,15 @@ bar: xor $foo, %rbx xorq $foo, bar -// CHECK: Name: add -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6681C300 00668104 25000000 00000081 -// CHECK-NEXT: 0010: C3000000 00810425 00000000 00000000 -// CHECK-NEXT: 0020: 4881C300 00000048 81042500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section add +// CHECK: Disassembly of section add: +// CHECK-NEXT: add: +// CHECK-NEXT: 0: 66 81 c3 00 00 addw $0, %bx +// CHECK-NEXT: 5: 66 81 04 25 00 00 00 00 00 00 addw $0, 0 +// CHECK-NEXT: f: 81 c3 00 00 00 00 addl $0, %ebx +// CHECK-NEXT: 15: 81 04 25 00 00 00 00 00 00 00 00 addl $0, 0 +// CHECK-NEXT: 20: 48 81 c3 00 00 00 00 addq $0, %rbx +// CHECK-NEXT: 27: 48 81 04 25 00 00 00 00 00 00 00 00 addq $0, 0 + .section add,"x" add $foo, %bx addw $foo, bar add $foo, %ebx @@ -80,14 +84,15 @@ bar: add $foo, %rbx addq $foo, bar -// CHECK: Name: sub -// CHECK: SectionData ( -// CHECK-NEXT: 000: 6681EB00 0066812C 25000000 00000081 -// CHECK-NEXT: 010: EB000000 00812C25 00000000 00000000 -// CHECK-NEXT: 020: 4881EB00 00000048 812C2500 00000000 -// CHECK-NEXT: 030: 000000 -// CHECK-NEXT: ) - .section sub +// CHECK: Disassembly of section sub: +// CHECK-NEXT: sub: +// CHECK-NEXT: 0: 66 81 eb 00 00 subw $0, %bx +// CHECK-NEXT: 5: 66 81 2c 25 00 00 00 00 00 00 subw $0, 0 +// CHECK-NEXT: f: 81 eb 00 00 00 00 subl $0, %ebx +// CHECK-NEXT: 15: 81 2c 25 00 00 00 00 00 00 00 00 subl $0, 0 +// CHECK-NEXT: 20: 48 81 eb 00 00 00 00 subq $0, %rbx +// CHECK-NEXT: 27: 48 81 2c 25 00 00 00 00 00 00 00 00 subq $0, 0 + .section sub,"x" sub $foo, %bx subw $foo, bar sub $foo, %ebx @@ -95,14 +100,15 @@ bar: sub $foo, %rbx subq $foo, bar -// CHECK: Name: cmp -// CHECK: SectionData ( -// CHECK-NEXT: 0000: 6681FB00 0066813C 25000000 00000081 -// CHECK-NEXT: 0010: FB000000 00813C25 00000000 00000000 -// CHECK-NEXT: 0020: 4881FB00 00000048 813C2500 00000000 -// CHECK-NEXT: 0030: 000000 -// CHECK-NEXT: ) - .section cmp +// CHECK: Disassembly of section cmp: +// CHECK-NEXT: cmp: +// CHECK-NEXT: 0: 66 81 fb 00 00 cmpw $0, %bx +// CHECK-NEXT: 5: 66 81 3c 25 00 00 00 00 00 00 cmpw $0, 0 +// CHECK-NEXT: f: 81 fb 00 00 00 00 cmpl $0, %ebx +// CHECK-NEXT: 15: 81 3c 25 00 00 00 00 00 00 00 00 cmpl $0, 0 +// CHECK-NEXT: 20: 48 81 fb 00 00 00 00 cmpq $0, %rbx +// CHECK-NEXT: 27: 48 81 3c 25 00 00 00 00 00 00 00 00 cmpq $0, 0 + .section cmp,"x" cmp $foo, %bx cmpw $foo, bar cmp $foo, %ebx diff --git a/test/MC/ELF/relax-arith2.s b/test/MC/ELF/relax-arith2.s new file mode 100644 index 0000000000000..a6c55adf894b7 --- /dev/null +++ b/test/MC/ELF/relax-arith2.s @@ -0,0 +1,118 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s + +// Test that we avoid relaxing these instructions and instead generate versions +// that use 8-bit immediate values. + +bar: +// CHECK: Disassembly of section imul: +// CHECK-NEXT: imul: +// CHECK-NEXT: 0: 66 6b db 80 imulw $-128, %bx, %bx +// CHECK-NEXT: 4: 66 6b 1c 25 00 00 00 00 7f imulw $127, 0, %bx +// CHECK-NEXT: d: 6b db 00 imull $0, %ebx, %ebx +// CHECK-NEXT: 10: 6b 1c 25 00 00 00 00 01 imull $1, 0, %ebx +// CHECK-NEXT: 18: 48 6b db ff imulq $-1, %rbx, %rbx +// CHECK-NEXT: 1c: 48 6b 1c 25 00 00 00 00 2a imulq $42, 0, %rbx + .section imul,"x" + imul $-128, %bx, %bx + imul $127, bar, %bx + imul $0, %ebx, %ebx + imul $1, bar, %ebx + imul $-1, %rbx, %rbx + imul $42, bar, %rbx + + +// CHECK: Disassembly of section and: +// CHECK-NEXT: and: +// CHECK-NEXT: 0: 66 83 e3 7f andw $127, %bx +// CHECK-NEXT: 4: 66 83 24 25 00 00 00 00 00 andw $0, 0 +// CHECK-NEXT: d: 83 e3 01 andl $1, %ebx +// CHECK-NEXT: 10: 83 24 25 00 00 00 00 ff andl $-1, 0 +// CHECK-NEXT: 18: 48 83 e3 2a andq $42, %rbx +// CHECK-NEXT: 1c: 48 83 24 25 00 00 00 00 80 andq $-128, 0 + .section and,"x" + and $127, %bx + andw $0, bar + and $1, %ebx + andl $-1, bar + and $42, %rbx + andq $-128, bar + +// CHECK: Disassembly of section or: +// CHECK-NEXT: or: +// CHECK-NEXT: 0: 66 83 cb 00 orw $0, %bx +// CHECK-NEXT: 4: 66 83 0c 25 00 00 00 00 01 orw $1, 0 +// CHECK-NEXT: d: 83 cb ff orl $-1, %ebx +// CHECK-NEXT: 10: 83 0c 25 00 00 00 00 2a orl $42, 0 +// CHECK-NEXT: 18: 48 83 cb 80 orq $-128, %rbx +// CHECK-NEXT: 1c: 48 83 0c 25 00 00 00 00 7f orq $127, 0 + .section or,"x" + or $0, %bx + orw $1, bar + or $-1, %ebx + orl $42, bar + or $-128, %rbx + orq $127, bar + +// CHECK: Disassembly of section xor: +// CHECK-NEXT: xor: +// CHECK-NEXT: 0: 66 83 f3 01 xorw $1, %bx +// CHECK-NEXT: 4: 66 83 34 25 00 00 00 00 ff xorw $-1, 0 +// CHECK-NEXT: d: 83 f3 2a xorl $42, %ebx +// CHECK-NEXT: 10: 83 34 25 00 00 00 00 80 xorl $-128, 0 +// CHECK-NEXT: 18: 48 83 f3 7f xorq $127, %rbx +// CHECK-NEXT: 1c: 48 83 34 25 00 00 00 00 00 xorq $0, 0 + .section xor,"x" + xor $1, %bx + xorw $-1, bar + xor $42, %ebx + xorl $-128, bar + xor $127, %rbx + xorq $0, bar + +// CHECK: Disassembly of section add: +// CHECK-NEXT: add: +// CHECK-NEXT: 0: 66 83 c3 ff addw $-1, %bx +// CHECK-NEXT: 4: 66 83 04 25 00 00 00 00 2a addw $42, 0 +// CHECK-NEXT: d: 83 c3 80 addl $-128, %ebx +// CHECK-NEXT: 10: 83 04 25 00 00 00 00 7f addl $127, 0 +// CHECK-NEXT: 18: 48 83 c3 00 addq $0, %rbx +// CHECK-NEXT: 1c: 48 83 04 25 00 00 00 00 01 addq $1, 0 + .section add,"x" + add $-1, %bx + addw $42, bar + add $-128, %ebx + addl $127, bar + add $0, %rbx + addq $1, bar + +// CHECK: Disassembly of section sub: +// CHECK-NEXT: sub: +// CHECK-NEXT: 0: 66 83 eb 2a subw $42, %bx +// CHECK-NEXT: 4: 66 83 2c 25 00 00 00 00 80 subw $-128, 0 +// CHECK-NEXT: d: 83 eb 7f subl $127, %ebx +// CHECK-NEXT: 10: 83 2c 25 00 00 00 00 00 subl $0, 0 +// CHECK-NEXT: 18: 48 83 eb 01 subq $1, %rbx +// CHECK-NEXT: 1c: 48 83 2c 25 00 00 00 00 ff subq $-1, 0 + .section sub,"x" + sub $42, %bx + subw $-128, bar + sub $127, %ebx + subl $0, bar + sub $1, %rbx + subq $-1, bar + +// CHECK: Disassembly of section cmp: +// CHECK-NEXT: cmp: +// CHECK-NEXT: 0: 66 83 fb 80 cmpw $-128, %bx +// CHECK-NEXT: 4: 66 83 3c 25 00 00 00 00 7f cmpw $127, 0 +// CHECK-NEXT: d: 83 fb 00 cmpl $0, %ebx +// CHECK-NEXT: 10: 83 3c 25 00 00 00 00 01 cmpl $1, 0 +// CHECK-NEXT: 18: 48 83 fb ff cmpq $-1, %rbx +// CHECK-NEXT: 1c: 48 83 3c 25 00 00 00 00 2a cmpq $42, 0 + .section cmp,"x" + cmp $-128, %bx + cmpw $127, bar + cmp $0, %ebx + cmpl $1, bar + cmp $-1, %rbx + cmpq $42, bar diff --git a/test/MC/ELF/relax-arith3.s b/test/MC/ELF/relax-arith3.s new file mode 100644 index 0000000000000..3be8b0ee87038 --- /dev/null +++ b/test/MC/ELF/relax-arith3.s @@ -0,0 +1,76 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s + +// Test that we correctly relax these instructions into versions that use +// 16 or 32 bit immediate values. + +bar: +// CHECK: Disassembly of section imul: +// CHECK-NEXT: imul: +// CHECK-NEXT: 0: 66 69 1d 00 00 00 00 00 00 imulw $0, (%rip), %bx +// CHECK-NEXT: 9: 69 1d 00 00 00 00 00 00 00 00 imull $0, (%rip), %ebx +// CHECK-NEXT: 13: 48 69 1d 00 00 00 00 00 00 00 00 imulq $0, (%rip), %rbx + .section imul,"x" + imul $foo, bar(%rip), %bx + imul $foo, bar(%rip), %ebx + imul $foo, bar(%rip), %rbx + + +// CHECK: Disassembly of section and: +// CHECK-NEXT: and: +// CHECK-NEXT: 0: 66 81 25 00 00 00 00 00 00 andw $0, (%rip) +// CHECK-NEXT: 9: 81 25 00 00 00 00 00 00 00 00 andl $0, (%rip) +// CHECK-NEXT: 13: 48 81 25 00 00 00 00 00 00 00 00 andq $0, (%rip) + .section and,"x" + andw $foo, bar(%rip) + andl $foo, bar(%rip) + andq $foo, bar(%rip) + +// CHECK: Disassembly of section or: +// CHECK-NEXT: or: +// CHECK-NEXT: 0: 66 81 0d 00 00 00 00 00 00 orw $0, (%rip) +// CHECK-NEXT: 9: 81 0d 00 00 00 00 00 00 00 00 orl $0, (%rip) +// CHECK-NEXT: 13: 48 81 0d 00 00 00 00 00 00 00 00 orq $0, (%rip) + .section or,"x" + orw $foo, bar(%rip) + orl $foo, bar(%rip) + orq $foo, bar(%rip) + +// CHECK: Disassembly of section xor: +// CHECK-NEXT: xor: +// CHECK-NEXT: 0: 66 81 35 00 00 00 00 00 00 xorw $0, (%rip) +// CHECK-NEXT: 9: 81 35 00 00 00 00 00 00 00 00 xorl $0, (%rip) +// CHECK-NEXT: 13: 48 81 35 00 00 00 00 00 00 00 00 xorq $0, (%rip) + .section xor,"x" + xorw $foo, bar(%rip) + xorl $foo, bar(%rip) + xorq $foo, bar(%rip) + +// CHECK: Disassembly of section add: +// CHECK-NEXT: add: +// CHECK-NEXT: 0: 66 81 05 00 00 00 00 00 00 addw $0, (%rip) +// CHECK-NEXT: 9: 81 05 00 00 00 00 00 00 00 00 addl $0, (%rip) +// CHECK-NEXT: 13: 48 81 05 00 00 00 00 00 00 00 00 addq $0, (%rip) + .section add,"x" + addw $foo, bar(%rip) + addl $foo, bar(%rip) + addq $foo, bar(%rip) + +// CHECK: Disassembly of section sub: +// CHECK-NEXT: sub: +// CHECK-NEXT: 0: 66 81 2d 00 00 00 00 00 00 subw $0, (%rip) +// CHECK-NEXT: 9: 81 2d 00 00 00 00 00 00 00 00 subl $0, (%rip) +// CHECK-NEXT: 13: 48 81 2d 00 00 00 00 00 00 00 00 subq $0, (%rip) + .section sub,"x" + subw $foo, bar(%rip) + subl $foo, bar(%rip) + subq $foo, bar(%rip) + +// CHECK: Disassembly of section cmp: +// CHECK-NEXT: cmp: +// CHECK-NEXT: 0: 66 81 3d 00 00 00 00 00 00 cmpw $0, (%rip) +// CHECK-NEXT: 9: 81 3d 00 00 00 00 00 00 00 00 cmpl $0, (%rip) +// CHECK-NEXT: 13: 48 81 3d 00 00 00 00 00 00 00 00 cmpq $0, (%rip) + .section cmp,"x" + cmpw $foo, bar(%rip) + cmpl $foo, bar(%rip) + cmpq $foo, bar(%rip) diff --git a/test/MC/ELF/symver-pr23914.s b/test/MC/ELF/symver-pr23914.s new file mode 100644 index 0000000000000..e8b43251010e6 --- /dev/null +++ b/test/MC/ELF/symver-pr23914.s @@ -0,0 +1,16 @@ +// Regression test for PR23914. +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s + +defined: + .symver defined, aaaaaaaaaaaaaaaaaa@@@AAAAAAAAAAAAA + +// CHECK: Symbol { +// CHECK: Name: aaaaaaaaaaaaaaaaaa@@AAAAAAAAAAAAA +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } + diff --git a/test/MC/ELF/undef-temp.s b/test/MC/ELF/undef-temp.s new file mode 100644 index 0000000000000..45537a998e75d --- /dev/null +++ b/test/MC/ELF/undef-temp.s @@ -0,0 +1,4 @@ +// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o - 2>&1 | FileCheck %s + +// CHECK: Undefined temporary + .long .Lfoo diff --git a/test/MC/ELF/undef.s b/test/MC/ELF/undef.s index 9577ea22875b1..47cd85ab4a4f0 100644 --- a/test/MC/ELF/undef.s +++ b/test/MC/ELF/undef.s @@ -2,7 +2,6 @@ // Test which symbols should be in the symbol table - .long .Lsym1 .Lsym2: .Lsym3: .Lsym4 = .Lsym2 - .Lsym3 @@ -42,15 +41,6 @@ test2_b = undef + 1 // CHECK-NEXT: Section: .rodata.str1.1 // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .Lsym1 -// CHECK-NEXT: Value: 0x0 -// CHECK-NEXT: Size: 0 -// CHECK-NEXT: Binding: Global -// CHECK-NEXT: Type: None -// CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: Undefined -// CHECK-NEXT: } -// CHECK-NEXT: Symbol { // CHECK-NEXT: Name: sym6 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 diff --git a/test/MC/ELF/undef2.s b/test/MC/ELF/undef2.s deleted file mode 100644 index 6aa66c05c4bb7..0000000000000 --- a/test/MC/ELF/undef2.s +++ /dev/null @@ -1,18 +0,0 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s - -// Test that this produces an undefined reference to .Lfoo - - je .Lfoo - -// CHECK: Section { -// CHECK: Name: .strtab - -// CHECK: Symbol { -// CHECK: Name: .Lfoo -// CHECK-NEXT: Value: -// CHECK-NEXT: Size: -// CHECK-NEXT: Binding: Global -// CHECK-NEXT: Type: -// CHECK-NEXT: Other: -// CHECK-NEXT: Section: -// CHECK-NEXT: } diff --git a/test/MC/MachO/ARM/directive-type-diagnostics.s b/test/MC/MachO/ARM/directive-type-diagnostics.s new file mode 100644 index 0000000000000..f5f9b45b664a8 --- /dev/null +++ b/test/MC/MachO/ARM/directive-type-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple arm-apple -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple armeb-apple -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumb-apple -filetype asm -o /dev/null %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple thumbeb-apple -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + + .type symbol 32 +// CHECK: error: expected STT_<TYPE_IN_UPPER_CASE>, '#<type>', '%<type>' or "<type>" +// CHECK: .type symbol 32 +// CHECK: ^ + diff --git a/test/MC/MachO/cstexpr-gotpcrel-64.ll b/test/MC/MachO/cstexpr-gotpcrel-64.ll index bf155647f12a8..bafddcb3db698 100644 --- a/test/MC/MachO/cstexpr-gotpcrel-64.ll +++ b/test/MC/MachO/cstexpr-gotpcrel-64.ll @@ -84,3 +84,12 @@ define i32 @t0(i32 %a) { define i32** @t1() { ret i32** @bargotequiv } + +; Do not crash when a pattern cannot be matched as a GOT equivalent + +@a = external global i8 +@b = internal unnamed_addr constant i8* @a + +; X86-LABEL: _c: +; X86: .quad _b +@c = global i8** @b diff --git a/test/MC/Mips/branch-pseudos.s b/test/MC/Mips/branch-pseudos.s index e9b151a593337..d5b06f78d8006 100644 --- a/test/MC/Mips/branch-pseudos.s +++ b/test/MC/Mips/branch-pseudos.s @@ -7,41 +7,41 @@ local_label: blt $7, $8, local_label # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop blt $7, $8, global_label # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop blt $7, $0, local_label # CHECK: bltz $7, local_label # encoding: [0x04,0xe0,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop blt $0, $8, local_label # CHECK: bgtz $8, local_label # encoding: [0x1d,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop blt $0, $0, local_label # CHECK: bltz $zero, local_label # encoding: [0x04,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bltu $7, $8, local_label # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bltu $7, $8, global_label # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bltu $7, $0, local_label # CHECK: nop bltu $0, $8, local_label # CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bltu $0, $0, local_label # CHECK: nop @@ -49,141 +49,141 @@ local_label: ble $7, $8, local_label # CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] # CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop ble $7, $8, global_label # CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] # CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop ble $7, $0, local_label # CHECK: blez $7, local_label # encoding: [0x18,0xe0,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop ble $0, $8, local_label # CHECK: bgez $8, local_label # encoding: [0x05,0x01,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop ble $0, $0, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: blez $zero, local_label # encoding: [0x18,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bleu $7, $8, local_label # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] # CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bleu $7, $8, global_label # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] # CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bleu $7, $0, local_label # CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bleu $0, $8, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: b local_label # encoding: [0x10,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bleu $0, $0, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: b local_label # encoding: [0x10,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bge $7, $8, local_label # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] # CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bge $7, $8, global_label # CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] # CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bge $7, $0, local_label # CHECK: bgez $7, local_label # encoding: [0x04,0xe1,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bge $0, $8, local_label # CHECK: blez $8, local_label # encoding: [0x19,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bge $0, $0, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: bgez $zero, local_label # encoding: [0x04,0x01,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgeu $7, $8, local_label # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] # CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgeu $7, $8, global_label # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] # CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgeu $7, $0, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: b local_label # encoding: [0x10,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgeu $0, $8, local_label # CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgeu $0, $0, local_label # WARNING: :[[@LINE-1]]:3: warning: branch is always taken # CHECK: b local_label # encoding: [0x10,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgt $7, $8, local_label # CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgt $7, $8, global_label # CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgt $7, $0, local_label # CHECK: bgtz $7, local_label # encoding: [0x1c,0xe0,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgt $0, $8, local_label # CHECK: bltz $8, local_label # encoding: [0x05,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgt $0, $0, local_label # CHECK: bgtz $zero, local_label # encoding: [0x1c,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgtu $7, $8, local_label # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] # CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgtu $7, $8, global_label # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] # CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] -# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgtu $7, $0, local_label # CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop bgtu $0, $8, local_label # CHECK: nop bgtu $0, $0, local_label # CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A] -# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16 # CHECK: nop diff --git a/test/MC/Mips/expr1.s b/test/MC/Mips/expr1.s index 7959315a809a7..4af61636355fe 100644 --- a/test/MC/Mips/expr1.s +++ b/test/MC/Mips/expr1.s @@ -16,6 +16,11 @@ # 32R2-EL: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 # 32R2-EL: lw $4, %lo(foo+8)($4) # encoding: [0x08'A',A,0x84,0x8c] # 32R2-EL: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 +# 32R2-EL: lw $4, 10($4) # encoding: [0x0a,0x00,0x84,0x8c] +# 32R2-EL: lw $4, 15($4) # encoding: [0x0f,0x00,0x84,0x8c] +# 32R2-EL: lw $4, 21($4) # encoding: [0x15,0x00,0x84,0x8c] +# 32R2-EL: lw $4, 28($4) # encoding: [0x1c,0x00,0x84,0x8c] +# 32R2-EL: lw $4, 6($4) # encoding: [0x06,0x00,0x84,0x8c] # 32R2-EL: .space 64 # MM-32R2-EL: .text @@ -30,6 +35,11 @@ # MM-32R2-EL: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16 # MM-32R2-EL: lw $4, %lo(foo+8)($4) # encoding: [0x84'A',0xfc'A',0x08,0x00] # MM-32R2-EL: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16 +# MM-32R2-EL: lw $4, 10($4) # encoding: [0x84,0xfc,0x0a,0x00] +# MM-32R2-EL: lw $4, 15($4) # encoding: [0x84,0xfc,0x0f,0x00] +# MM-32R2-EL: lw $4, 21($4) # encoding: [0x84,0xfc,0x15,0x00] +# MM-32R2-EL: lw $4, 28($4) # encoding: [0x84,0xfc,0x1c,0x00] +# MM-32R2-EL: lw $4, 6($4) # encoding: [0x84,0xfc,0x06,0x00] # MM-32R2-EL: .space 64 .globl foo @@ -40,5 +50,10 @@ foo: lw $4,%lo (2 * 4) + foo($4) lw $4,%lo((2 * 4) + foo)($4) lw $4,(((%lo ((2 * 4) + foo))))($4) + lw $4, (((1+2)+3)+4)($4) + lw $4, ((((1+2)+3)+4)+5)($4) + lw $4, (((((1+2)+3)+4)+5)+6)($4) + lw $4, ((((((1+2)+3)+4)+5)+6)+7)($4) + lw $4, (%lo((1+2)+65536)+3)($4) .space 64 .end foo diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s new file mode 100644 index 0000000000000..8ba787ae1aa4d --- /dev/null +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index 94e19f2c46fc2..a49622a507de6 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -20,11 +20,18 @@ balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] + break # CHECK: break # encoding: [0x00,0x00,0x00,0x07] + break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07] + break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c] clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18] divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98] + ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00] + ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] + ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c] + ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] @@ -37,6 +44,7 @@ muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] + nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2] @@ -45,6 +53,7 @@ seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80] + sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00] sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90] subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0] xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] diff --git a/test/MC/Mips/mips-cop0-reginfo.s b/test/MC/Mips/mips-cop0-reginfo.s new file mode 100644 index 0000000000000..0508a37295431 --- /dev/null +++ b/test/MC/Mips/mips-cop0-reginfo.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -filetype=obj %s -o - | \ +# RUN: llvm-readobj -sections -section-data - | \ +# RUN: FileCheck %s -check-prefix=CHECK + mfc0 $16, $15, 1 + mfc0 $16, $16, 1 + + +# Checking for the coprocessor 0's register usage was recorded +# and emitted. +# CHECK: Section { +# CHECK: Index: 5 +# CHECK: Name: .reginfo (27) +# CHECK: Type: SHT_MIPS_REGINFO (0x70000006) +# CHECK: Flags [ (0x2) +# CHECK: SHF_ALLOC (0x2) +# CHECK: ] +# CHECK: Address: 0x0 +# CHECK: Offset: 0x50 +# CHECK: Size: 24 +# CHECK: Link: 0 +# CHECK: Info: 0 +# CHECK: AddressAlignment: 4 +# CHECK: EntrySize: 24 +# CHECK: SectionData ( +# CHECK: 0000: 00010000 00018000 00000000 00000000 |................| +# CHECK: 0010: 00000000 00000000 |........| +# CHECK: ) +# CHECK: } diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s index 6e747c38c3c5f..416cb5f3ba69a 100644 --- a/test/MC/Mips/mips-expansions-bad.s +++ b/test/MC/Mips/mips-expansions-bad.s @@ -18,11 +18,34 @@ la $5, symbol # N64-ONLY: :[[@LINE-1]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol # N32-ONLY-NOT: :[[@LINE-2]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol - # 64-BIT: lui $5, %hi(symbol) - # 64-BIT: ori $5, $5, %lo(symbol) dli $5, 1 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture bne $2, 0x100010001, 1332 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate beq $2, 0x100010001, 1332 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate + .set mips32r6 + ulhu $5, 0 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips32 + ulhu $5, 1 + # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips64r6 + ulhu $5, 2 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + + .set mips32r6 + ulw $5, 0 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips32 + ulw $5, 1 + # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips64r6 + ulw $5, 2 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s index bae446cea2ad1..55de6d046349e 100644 --- a/test/MC/Mips/mips-expansions.s +++ b/test/MC/Mips/mips-expansions.s @@ -1,172 +1,522 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \ -# RUN: FileCheck %s +# RUN: FileCheck %s --check-prefix=CHECK-LE +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ +# RUN: FileCheck %s --check-prefix=CHECK-BE # Check that the IAS expands macro instructions in the same way as GAS. # Load immediate, done by MipsAsmParser::expandLoadImm(): li $5, 123 -# CHECK: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34] +# CHECK-LE: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34] li $6, -2345 -# CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24] +# CHECK-LE: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24] li $7, 65538 -# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] -# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK-LE: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK-LE: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] li $8, ~7 -# CHECK: addiu $8, $zero, -8 # encoding: [0xf8,0xff,0x08,0x24] +# CHECK-LE: addiu $8, $zero, -8 # encoding: [0xf8,0xff,0x08,0x24] li $9, 0x10000 -# CHECK: lui $9, 1 # encoding: [0x01,0x00,0x09,0x3c] -# CHECK-NOT: ori $9, $9, 0 # encoding: [0x00,0x00,0x29,0x35] +# CHECK-LE: lui $9, 1 # encoding: [0x01,0x00,0x09,0x3c] +# CHECK-LE-NOT: ori $9, $9, 0 # encoding: [0x00,0x00,0x29,0x35] li $10, ~(0x101010) -# CHECK: lui $10, 65519 # encoding: [0xef,0xff,0x0a,0x3c] -# CHECK: ori $10, $10, 61423 # encoding: [0xef,0xef,0x4a,0x35] +# CHECK-LE: lui $10, 65519 # encoding: [0xef,0xff,0x0a,0x3c] +# CHECK-LE: ori $10, $10, 61423 # encoding: [0xef,0xef,0x4a,0x35] # Load address, done by MipsAsmParser::expandLoadAddressReg() # and MipsAsmParser::expandLoadAddressImm(): la $4, 20 -# CHECK: ori $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x34] +# CHECK-LE: ori $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x34] la $7, 65538 -# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] -# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK-LE: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK-LE: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] la $4, 20($5) -# CHECK: ori $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x34] +# CHECK-LE: ori $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x34] la $7, 65538($8) -# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] -# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] -# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00] +# CHECK-LE: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK-LE: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK-LE: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00] la $8, 1f -# CHECK: lui $8, %hi($tmp0) # encoding: [A,A,0x08,0x3c] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: ori $8, $8, %lo($tmp0) # encoding: [A,A,0x08,0x35] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $8, %hi($tmp0) # encoding: [A,A,0x08,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: ori $8, $8, %lo($tmp0) # encoding: [A,A,0x08,0x35] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 la $8, symbol -# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 la $8, symbol($9) -# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 -# CHECK: addu $8, $8, $9 # encoding: [0x21,0x40,0x09,0x01] +# CHECK-LE: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: addu $8, $8, $9 # encoding: [0x21,0x40,0x09,0x01] + la $8, symbol($8) +# CHECK-LE: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: ori $1, $1, %lo(symbol) # encoding: [A,A,0x21,0x34] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: addu $8, $1, $8 # encoding: [0x21,0x40,0x28,0x00] + la $8, 20($8) +# CHECK-LE: ori $8, $8, 20 # encoding: [0x14,0x00,0x08,0x35] + la $8, 65538($8) +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 2 # encoding: [0x02,0x00,0x21,0x34] +# CHECK-LE: addu $8, $1, $8 # encoding: [0x21,0x40,0x28,0x00] # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst(): .set noat lw $10, symbol($4) -# CHECK: lui $10, %hi(symbol) # encoding: [A,A,0x0a,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] -# CHECK: lw $10, %lo(symbol)($10) # encoding: [A,A,0x4a,0x8d] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $10, %hi(symbol) # encoding: [A,A,0x0a,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] +# CHECK-LE: lw $10, %lo(symbol)($10) # encoding: [A,A,0x4a,0x8d] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 .set at sw $10, symbol($9) -# CHECK: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] -# CHECK: sw $10, %lo(symbol)($1) # encoding: [A,A,0x2a,0xac] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: sw $10, %lo(symbol)($1) # encoding: [A,A,0x2a,0xac] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 lw $8, 1f -# CHECK: lui $8, %hi($tmp0) # encoding: [A,A,0x08,0x3c] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: lw $8, %lo($tmp0)($8) # encoding: [A,A,0x08,0x8d] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $8, %hi($tmp0) # encoding: [A,A,0x08,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: lw $8, %lo($tmp0)($8) # encoding: [A,A,0x08,0x8d] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 sw $8, 1f -# CHECK: lui $1, %hi($tmp0) # encoding: [A,A,0x01,0x3c] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: sw $8, %lo($tmp0)($1) # encoding: [A,A,0x28,0xac] -# CHECK: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $1, %hi($tmp0) # encoding: [A,A,0x01,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE: sw $8, %lo($tmp0)($1) # encoding: [A,A,0x28,0xac] +# CHECK-LE: # fixup A - offset: 0, value: ($tmp0)@ABS_LO, kind: fixup_Mips_LO16 lw $10, 655483($4) -# CHECK: lui $10, 10 # encoding: [0x0a,0x00,0x0a,0x3c] -# CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] -# CHECK: lw $10, 123($10) # encoding: [0x7b,0x00,0x4a,0x8d] +# CHECK-LE: lui $10, 10 # encoding: [0x0a,0x00,0x0a,0x3c] +# CHECK-LE: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] +# CHECK-LE: lw $10, 123($10) # encoding: [0x7b,0x00,0x4a,0x8d] sw $10, 123456($9) -# CHECK: lui $1, 2 # encoding: [0x02,0x00,0x01,0x3c] -# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] -# CHECK: sw $10, 57920($1) # encoding: [0x40,0xe2,0x2a,0xac] +# CHECK-LE: lui $1, 2 # encoding: [0x02,0x00,0x01,0x3c] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: sw $10, 57920($1) # encoding: [0x40,0xe2,0x2a,0xac] lw $8, symbol -# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK-NOT: move $8, $8 # encoding: [0x21,0x40,0x00,0x01] -# CHECK: lw $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE-NOT: move $8, $8 # encoding: [0x21,0x40,0x00,0x01] +# CHECK-LE: lw $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 sw $8, symbol -# CHECK: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK-NOT: move $1, $1 # encoding: [0x21,0x08,0x20,0x00] -# CHECK: sw $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac] -# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK-LE: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK-LE-NOT: move $1, $1 # encoding: [0x21,0x08,0x20,0x00] +# CHECK-LE: sw $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac] +# CHECK-LE: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 ldc1 $f0, symbol -# CHECK: lui $1, %hi(symbol) -# CHECK: ldc1 $f0, %lo(symbol)($1) +# CHECK-LE: lui $1, %hi(symbol) +# CHECK-LE: ldc1 $f0, %lo(symbol)($1) sdc1 $f0, symbol -# CHECK: lui $1, %hi(symbol) -# CHECK: sdc1 $f0, %lo(symbol)($1) +# CHECK-LE: lui $1, %hi(symbol) +# CHECK-LE: sdc1 $f0, %lo(symbol)($1) # Test BNE with an immediate as the 2nd operand. bne $2, 0, 1332 -# CHECK: bnez $2, 1332 # encoding: [0x4d,0x01,0x40,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: bnez $2, 1332 # encoding: [0x4d,0x01,0x40,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] bne $2, 123, 1332 -# CHECK: ori $1, $zero, 123 # encoding: [0x7b,0x00,0x01,0x34] -# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: ori $1, $zero, 123 # encoding: [0x7b,0x00,0x01,0x34] +# CHECK-LE: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] bne $2, -2345, 1332 -# CHECK: addiu $1, $zero, -2345 # encoding: [0xd7,0xf6,0x01,0x24] -# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: addiu $1, $zero, -2345 # encoding: [0xd7,0xf6,0x01,0x24] +# CHECK-LE: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] bne $2, 65538, 1332 -# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] -# CHECK: ori $1, $1, 2 # encoding: [0x02,0x00,0x21,0x34] -# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 2 # encoding: [0x02,0x00,0x21,0x34] +# CHECK-LE: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] bne $2, ~7, 1332 -# CHECK: addiu $1, $zero, -8 # encoding: [0xf8,0xff,0x01,0x24] -# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: addiu $1, $zero, -8 # encoding: [0xf8,0xff,0x01,0x24] +# CHECK-LE: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] bne $2, 0x10000, 1332 -# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] -# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] # Test BEQ with an immediate as the 2nd operand. beq $2, 0, 1332 -# CHECK: beqz $2, 1332 # encoding: [0x4d,0x01,0x40,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: beqz $2, 1332 # encoding: [0x4d,0x01,0x40,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] beq $2, 123, 1332 -# CHECK: ori $1, $zero, 123 # encoding: [0x7b,0x00,0x01,0x34] -# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: ori $1, $zero, 123 # encoding: [0x7b,0x00,0x01,0x34] +# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] beq $2, -2345, 1332 -# CHECK: addiu $1, $zero, -2345 # encoding: [0xd7,0xf6,0x01,0x24] -# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: addiu $1, $zero, -2345 # encoding: [0xd7,0xf6,0x01,0x24] +# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] beq $2, 65538, 1332 -# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] -# CHECK: ori $1, $1, 2 # encoding: [0x02,0x00,0x21,0x34] -# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 2 # encoding: [0x02,0x00,0x21,0x34] +# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] beq $2, ~7, 1332 -# CHECK: addiu $1, $zero, -8 # encoding: [0xf8,0xff,0x01,0x24] -# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: addiu $1, $zero, -8 # encoding: [0xf8,0xff,0x01,0x24] +# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] beq $2, 0x10000, 1332 -# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] -# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] + +# Test ULHU with immediate operand. + ulhu $8, 0 +# CHECK-BE: lbu $1, 0($zero) # encoding: [0x90,0x01,0x00,0x00] +# CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, 1($zero) # encoding: [0x01,0x00,0x01,0x90] +# CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 2 +# CHECK-BE: lbu $1, 2($zero) # encoding: [0x90,0x01,0x00,0x02] +# CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, 3($zero) # encoding: [0x03,0x00,0x01,0x90] +# CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x8000 +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x8000 +# CHECK-BE: lbu $1, -32768($zero) # encoding: [0x90,0x01,0x80,0x00] +# CHECK-BE: lbu $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, -32767($zero) # encoding: [0x01,0x80,0x01,0x90] +# CHECK-LE: lbu $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x10000 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x18888 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -32769 +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32767 # encoding: [0x34,0x21,0x7f,0xff] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 32767 +# CHECK-BE: ori $1, $zero, 32767 # encoding: [0x34,0x01,0x7f,0xff] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: ori $1, $zero, 32767 # encoding: [0xff,0x7f,0x01,0x34] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ULHU with immediate offset and a source register operand. + ulhu $8, 0($9) +# CHECK-BE: lbu $1, 0($9) # encoding: [0x91,0x21,0x00,0x00] +# CHECK-BE: lbu $8, 1($9) # encoding: [0x91,0x28,0x00,0x01] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, 1($9) # encoding: [0x01,0x00,0x21,0x91] +# CHECK-LE: lbu $8, 0($9) # encoding: [0x00,0x00,0x28,0x91] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 2($9) +# CHECK-BE: lbu $1, 2($9) # encoding: [0x91,0x21,0x00,0x02] +# CHECK-BE: lbu $8, 3($9) # encoding: [0x91,0x28,0x00,0x03] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, 3($9) # encoding: [0x03,0x00,0x21,0x91] +# CHECK-LE: lbu $8, 2($9) # encoding: [0x02,0x00,0x28,0x91] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x8000($9) +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x8000($9) +# CHECK-BE: lbu $1, -32768($9) # encoding: [0x91,0x21,0x80,0x00] +# CHECK-BE: lbu $8, -32767($9) # encoding: [0x91,0x28,0x80,0x01] +# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lbu $1, -32767($9) # encoding: [0x01,0x80,0x21,0x91] +# CHECK-LE: lbu $8, -32768($9) # encoding: [0x00,0x80,0x28,0x91] +# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x10000($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x18888($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -32769($9) +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32767 # encoding: [0x34,0x21,0x7f,0xff] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 32767($9) +# CHECK-BE: ori $1, $zero, 32767 # encoding: [0x34,0x01,0x7f,0xff] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lbu $8, 0($1) # encoding: [0x90,0x28,0x00,0x00] +# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] +# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00] +# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] +# CHECK-LE: ori $1, $zero, 32767 # encoding: [0xff,0x7f,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ULW with immediate operand. + ulw $8, 0 +# CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00] +# CHECK-BE: lwr $8, 3($zero) # encoding: [0x98,0x08,0x00,0x03] +# CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88] +# CHECK-LE: lwr $8, 0($zero) # encoding: [0x00,0x00,0x08,0x98] + + ulw $8, 2 +# CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02] +# CHECK-BE: lwr $8, 5($zero) # encoding: [0x98,0x08,0x00,0x05] +# CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88] +# CHECK-LE: lwr $8, 2($zero) # encoding: [0x02,0x00,0x08,0x98] + + ulw $8, 0x8000 +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x8000 +# CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00] +# CHECK-BE: lwr $8, -32765($zero) # encoding: [0x98,0x08,0x80,0x03] +# CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88] +# CHECK-LE: lwr $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x98] + + ulw $8, 0x10000 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x18888 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -32771 +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 32765 +# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + +# Test ULW with immediate offset and a source register operand. + ulw $8, 0($9) +# CHECK-BE: lwl $8, 0($9) # encoding: [0x89,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($9) # encoding: [0x99,0x28,0x00,0x03] +# CHECK-LE: lwl $8, 3($9) # encoding: [0x03,0x00,0x28,0x89] +# CHECK-LE: lwr $8, 0($9) # encoding: [0x00,0x00,0x28,0x99] + + ulw $8, 2($9) +# CHECK-BE: lwl $8, 2($9) # encoding: [0x89,0x28,0x00,0x02] +# CHECK-BE: lwr $8, 5($9) # encoding: [0x99,0x28,0x00,0x05] +# CHECK-LE: lwl $8, 5($9) # encoding: [0x05,0x00,0x28,0x89] +# CHECK-LE: lwr $8, 2($9) # encoding: [0x02,0x00,0x28,0x99] + + ulw $8, 0x8000($9) +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x8000($9) +# CHECK-BE: lwl $8, -32768($9) # encoding: [0x89,0x28,0x80,0x00] +# CHECK-BE: lwr $8, -32765($9) # encoding: [0x99,0x28,0x80,0x03] +# CHECK-LE: lwl $8, -32765($9) # encoding: [0x03,0x80,0x28,0x89] +# CHECK-LE: lwr $8, -32768($9) # encoding: [0x00,0x80,0x28,0x99] + + ulw $8, 0x10000($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x18888($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -32771($9) +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 32765($9) +# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] 1: add $4, $4, $4 diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index bfaef9ecacc9a..7c49717178129 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -139,7 +139,7 @@ # FP move instructions #------------------------------------------------------------------------------ # CHECK: bc1f $BB_1 # encoding: [A,A,0x00,0x45] -# CHECK: # fixup A - offset: 0, value: ($BB_1), kind: fixup_Mips_PC16 +# CHECK: # fixup A - offset: 0, value: ($BB_1)-4, kind: fixup_Mips_PC16 # CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44] # CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44] diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index 3765044339c92..fbe1551f6c261 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -89,7 +89,7 @@ a: madd $zero,$9 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhi $s3 mfhi $sp @@ -112,7 +112,7 @@ a: movz.s $f25,$f7,$v1 msub $s7,$k1 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthi $s1 mtlo $sp diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index ee7af3f3ec00a..2e4366ab40f1c 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -103,7 +103,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -129,7 +129,7 @@ a: msub.d $f10,$f1,$f31,$f18 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s index 0a4e5b19aeff4..f6ef1d356c1fc 100644 --- a/test/MC/Mips/mips32r3/valid.s +++ b/test/MC/Mips/mips32r3/valid.s @@ -103,7 +103,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -129,7 +129,7 @@ a: msub.d $f10,$f1,$f31,$f18 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s index 036b908c8efce..f12d75113203c 100644 --- a/test/MC/Mips/mips32r5/valid.s +++ b/test/MC/Mips/mips32r5/valid.s @@ -103,7 +103,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -129,7 +129,7 @@ a: msub.d $f10,$f1,$f31,$f18 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips32r6/relocations.s b/test/MC/Mips/mips32r6/relocations.s index 13b3387e59101..eda749707065d 100644 --- a/test/MC/Mips/mips32r6/relocations.s +++ b/test/MC/Mips/mips32r6/relocations.s @@ -10,22 +10,22 @@ # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2 # CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar@PCREL_HI16, diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 2c3a5b2a7a43e..52752c5a6997e 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -108,8 +108,10 @@ a: lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mul $2,$3,$4 # CHECK: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] diff --git a/test/MC/Mips/mips64-expansions.s b/test/MC/Mips/mips64-expansions.s index 620793a64fdd2..a66a520a21170 100644 --- a/test/MC/Mips/mips64-expansions.s +++ b/test/MC/Mips/mips64-expansions.s @@ -271,3 +271,183 @@ # CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] # CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] + +# Test ulhu with 64-bit immediate addresses. + ulhu $8, 0x100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x1000100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x100010001 +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x1000100010001 +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ulhu with source register and 64-bit immediate offset. + ulhu $8, 0x100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x1000100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x100010001($9) +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x1000100010001($9) +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] +# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ulw with 64-bit immediate addresses. + ulw $8, 0x100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x1000100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x100010001 +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x1000100010001 +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + +# Test ulw with source register and 64-bit immediate offset. + ulw $8, 0x100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x1000100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x100010001($9) +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x1000100010001($9) +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 0bb9f17f02b4b..03ea6c15c3334 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -82,7 +82,9 @@ a: div.d $f29,$f20,$f27 div.s $f4,$f5,$f15 divu $zero,$25,$15 + dmfc0 $10, $16, 2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02] dmfc1 $12,$f13 + dmtc0 $4, $10, 0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00] dmtc1 $s0,$f14 dmult $s7,$9 dmultu $a1,$a2 @@ -154,7 +156,7 @@ a: maddu $24,$s2 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0] - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhi $s3 mfhi $sp @@ -181,7 +183,7 @@ a: msubu $15,$a1 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9] msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28] - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthi $s1 mtlo $sp diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index aad8e2850f90c..37753ae0a878f 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -84,7 +84,9 @@ a: div.d $f29,$f20,$f27 div.s $f4,$f5,$f15 divu $zero,$25,$15 + dmfc0 $10,$16,2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02] dmfc1 $12,$f13 + dmtc0 $4,$10,0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00] dmtc1 $s0,$f14 dmult $s7,$9 dmultu $a1,$a2 @@ -169,7 +171,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -196,7 +198,7 @@ a: msub $s7,$k1 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s index 359205500a8fd..c5d4848458d25 100644 --- a/test/MC/Mips/mips64r3/valid.s +++ b/test/MC/Mips/mips64r3/valid.s @@ -84,7 +84,9 @@ a: div.d $f29,$f20,$f27 div.s $f4,$f5,$f15 divu $zero,$25,$15 + dmfc0 $10, $16, 2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02] dmfc1 $12,$f13 + dmtc0 $4, $10, 0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00] dmtc1 $s0,$f14 dmult $s7,$9 dmultu $a1,$a2 @@ -169,7 +171,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -196,7 +198,7 @@ a: msub $s7,$k1 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s index 844663080b35b..d4e52dcca67e7 100644 --- a/test/MC/Mips/mips64r5/valid.s +++ b/test/MC/Mips/mips64r5/valid.s @@ -84,7 +84,9 @@ a: div.d $f29,$f20,$f27 div.s $f4,$f5,$f15 divu $zero,$25,$15 + dmfc0 $10, $16, 2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02] dmfc1 $12,$f13 + dmtc0 $4, $10, 0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00] dmtc1 $s0,$f14 dmult $s7,$9 dmultu $a1,$a2 @@ -169,7 +171,7 @@ a: madd.s $f1,$f31,$f19,$f25 maddu $s3,$gp maddu $24,$s2 - mfc0 $a2,$14,1 + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 mfhc1 $s8,$f24 mfhi $s3 @@ -196,7 +198,7 @@ a: msub $s7,$k1 msub.s $f12,$f19,$f10,$f16 msubu $15,$a1 - mtc0 $9,$29,3 + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips64r6/relocations.s b/test/MC/Mips/mips64r6/relocations.s index 651ebfb6c4c1a..8374cb8eaa58d 100644 --- a/test/MC/Mips/mips64r6/relocations.s +++ b/test/MC/Mips/mips64r6/relocations.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: | FileCheck %s -check-prefix=CHECK-FIXUP -# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \ +# RUN: llvm-mc %s -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \ # RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF #------------------------------------------------------------------------------ # Check that the assembler can handle the documented syntax for fixups. @@ -10,22 +10,22 @@ # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2 # CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2 # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar@PCREL_HI16, @@ -48,18 +48,18 @@ # Check that the appropriate relocations were created. #------------------------------------------------------------------------------ # CHECK-ELF: Relocations [ -# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 -# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 -# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 -# CHECK-ELF: 0x24 R_MIPS_PC18_S3 bar 0x0 -# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 -# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC +# CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: ] addiupc $2,bar diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index cdcb50bb3eadc..3dc771a80d54d 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -117,8 +117,10 @@ a: div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] dlsa $2, $3, $4, 3 # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5] + dmfc0 $10, $16, 2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02] dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] + dmtc0 $4, $10, 0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00] dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdc] dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd] dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9c] @@ -158,8 +160,10 @@ a: min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] + mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] diff --git a/test/MC/Mips/mips_abi_flags_xx.s b/test/MC/Mips/mips_abi_flags_xx.s index cd6c9de4fac45..349b70d609ae4 100644 --- a/test/MC/Mips/mips_abi_flags_xx.s +++ b/test/MC/Mips/mips_abi_flags_xx.s @@ -2,15 +2,15 @@ # RUN: FileCheck %s -check-prefix=CHECK-ASM # # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ -# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \ -# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32r6 -mattr=fpxx -filetype=obj -o - | \ -# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R6 # CHECK-ASM: .module fp=xx @@ -31,12 +31,23 @@ # CHECK-OBJ: EntrySize: 24 # CHECK-OBJ: Relocations [ # CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ-R1: 0000: 00002001 01010005 00000000 00000000 |.. .............| -# CHECK-OBJ-R6: 0000: 00002006 01010005 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000001 00000000 |........| -# CHECK-OBJ: ) # CHECK-OBJ-LABEL: } +# CHECK-OBJ: MIPS ABI Flags { +# CHECK-OBJ-NEXT: Version: 0 +# CHECK-OBJ-R1-NEXT: ISA: {{MIPS32$}} +# CHECK-OBJ-R6-NEXT: ISA: MIPS32r6 +# CHECK-OBJ-NEXT: ISA Extension: None (0x0) +# CHECK-OBJ-NEXT: ASEs [ (0x0) +# CHECK-OBJ-NEXT: ] +# CHECK-OBJ-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5) +# CHECK-OBJ-NEXT: GPR size: 32 +# CHECK-OBJ-NEXT: CPR1 size: 32 +# CHECK-OBJ-NEXT: CPR2 size: 0 +# CHECK-OBJ-NEXT: Flags 1 [ (0x1) +# CHECK-OBJ-NEXT: ODDSPREG (0x1) +# CHECK-OBJ-NEXT: ] +# CHECK-OBJ-NEXT: Flags 2: 0x0 +# CHECK-OBJ-NEXT: } .module fp=xx diff --git a/test/MC/Mips/mips_abi_flags_xx_set.s b/test/MC/Mips/mips_abi_flags_xx_set.s index a548972db0d6c..b31e295f6350f 100644 --- a/test/MC/Mips/mips_abi_flags_xx_set.s +++ b/test/MC/Mips/mips_abi_flags_xx_set.s @@ -2,7 +2,7 @@ # RUN: FileCheck %s -check-prefix=CHECK-ASM # # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ -# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ # CHECK-ASM: .module fp=xx @@ -24,11 +24,22 @@ # CHECK-OBJ: EntrySize: 24 # CHECK-OBJ: Relocations [ # CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000001 00000000 |........| -# CHECK-OBJ: ) # CHECK-OBJ-LABEL: } +# CHECK-OBJ: MIPS ABI Flags { +# CHECK-OBJ-NEXT: Version: 0 +# CHECK-OBJ-NEXT: ISA: {{MIPS32$}} +# CHECK-OBJ-NEXT: ISA Extension: None (0x0) +# CHECK-OBJ-NEXT: ASEs [ (0x0) +# CHECK-OBJ-NEXT: ] +# CHECK-OBJ-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5) +# CHECK-OBJ-NEXT: GPR size: 32 +# CHECK-OBJ-NEXT: CPR1 size: 32 +# CHECK-OBJ-NEXT: CPR2 size: 0 +# CHECK-OBJ-NEXT: Flags 1 [ (0x1) +# CHECK-OBJ-NEXT: ODDSPREG (0x1) +# CHECK-OBJ-NEXT: ] +# CHECK-OBJ-NEXT: Flags 2: 0x0 +# CHECK-OBJ-NEXT: } .module fp=xx .set fp=64 diff --git a/test/MC/Mips/module-hardfloat.s b/test/MC/Mips/module-hardfloat.s new file mode 100644 index 0000000000000..51f72487b3944 --- /dev/null +++ b/test/MC/Mips/module-hardfloat.s @@ -0,0 +1,26 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -mips-abi-flags - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module hardfloat + +# Check if the MIPS.abiflags section was correctly emitted: +# CHECK-OBJ: MIPS ABI Flags { +# CHECK-OBJ: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5) +# CHECK-OBJ: CPR1 size: 32 +# CHECK-OBJ: Flags 1 [ (0x1) +# CHECK-OBJ: ODDSPREG (0x1) +# CHECK-OBJ: ] +# CHECK-OBJ: } + + .module fp=xx + .module oddspreg + .module softfloat + .module hardfloat + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/module-softfloat.s b/test/MC/Mips/module-softfloat.s new file mode 100644 index 0000000000000..18559c5aec189 --- /dev/null +++ b/test/MC/Mips/module-softfloat.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -mips-abi-flags - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module softfloat + +# Check if the MIPS.abiflags section was correctly emitted: +# CHECK-OBJ: MIPS ABI Flags { +# CHECK-OBJ: FP ABI: Soft float (0x3) +# CHECK-OBJ: CPR1 size: 0 +# CHECK-OBJ: } + + .module softfloat + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/relocation.s b/test/MC/Mips/relocation.s index 3a5f5a9e0044b..f8030d16687ee 100644 --- a/test/MC/Mips/relocation.s +++ b/test/MC/Mips/relocation.s @@ -171,12 +171,12 @@ beqzc $2, foo // RELOC: R_MIPS_PC21_S2 foo // ENCBE: beqzc $2, foo # encoding: [0xd8,0b010AAAAA,A,A] // ENCLE: beqzc $2, foo # encoding: [A,A,0b010AAAAA,0xd8] - // FIXUP: # fixup A - offset: 0, value: foo, kind: fixup_MIPS_PC21_S2 + // FIXUP: # fixup A - offset: 0, value: foo-4, kind: fixup_MIPS_PC21_S2 bc foo // RELOC: R_MIPS_PC26_S2 foo // ENCBE: bc foo # encoding: [0b110010AA,A,A,A] // ENCLE: bc foo # encoding: [A,A,A,0b110010AA] - // FIXUP: # fixup A - offset: 0, value: foo, kind: fixup_MIPS_PC26_S2 + // FIXUP: # fixup A - offset: 0, value: foo-4, kind: fixup_MIPS_PC26_S2 .set mips64r6 ldpc $2, foo // RELOC: R_MIPS_PC18_S3 foo diff --git a/test/MC/Mips/set-nomacro.s b/test/MC/Mips/set-nomacro.s index 00d6b2117c021..3f82f81613158 100644 --- a/test/MC/Mips/set-nomacro.s +++ b/test/MC/Mips/set-nomacro.s @@ -60,6 +60,13 @@ bgtu $0, $8, local_label bgtu $0, $0, local_label + ulhu $5, 0 + + ulw $8, 2 + ulw $8, 0x8000 + ulw $8, 2($9) + ulw $8, 0x8000($9) + add $4, $5, $6 .set noreorder @@ -168,5 +175,17 @@ bgtu $0, $0, local_label # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulhu $5, 0 +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + ulw $8, 2 +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 0x8000 +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 2($9) +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 0x8000($9) +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + add $4, $5, $6 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions diff --git a/test/MC/Mips/set-oddspreg-nooddspreg-error.s b/test/MC/Mips/set-oddspreg-nooddspreg-error.s new file mode 100644 index 0000000000000..5fb1308ceb9e4 --- /dev/null +++ b/test/MC/Mips/set-oddspreg-nooddspreg-error.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+nooddspreg 2>%t1 +# RUN: FileCheck %s < %t1 + + .set oddspreg + sub.s $f1, $f2, $f2 + # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers + + .set nooddspreg + sub.s $f1, $f2, $f2 + # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers diff --git a/test/MC/Mips/set-oddspreg-nooddspreg.s b/test/MC/Mips/set-oddspreg-nooddspreg.s new file mode 100644 index 0000000000000..a057c487f794e --- /dev/null +++ b/test/MC/Mips/set-oddspreg-nooddspreg.s @@ -0,0 +1,10 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+nooddspreg | \ +# RUN: FileCheck %s + + .set oddspreg + sub.s $f1, $f2, $f2 + .set nooddspreg + +# CHECK: .set oddspreg +# CHECK: sub.s $f1, $f2, $f2 +# CHECK: .set nooddspreg diff --git a/test/MC/Mips/update-module-level-options.s b/test/MC/Mips/update-module-level-options.s new file mode 100644 index 0000000000000..3d6e97cb597db --- /dev/null +++ b/test/MC/Mips/update-module-level-options.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,-nooddspreg 2>&1 | \ +# RUN: FileCheck %s + + .module nooddspreg + add.s $f1, $f2, $f4 +# CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers + + .set oddspreg + add.s $f1, $f2, $f4 +# CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers + + .set mips0 + add.s $f1, $f2, $f4 +# CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers diff --git a/test/MC/PowerPC/ppc64-encoding-vmx.s b/test/MC/PowerPC/ppc64-encoding-vmx.s index 5c62d2a6c9553..d8825bf334021 100644 --- a/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -1,5 +1,5 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s # RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Vector facility @@ -110,7 +110,13 @@ # CHECK-BE: vmrglw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8c] # CHECK-LE: vmrglw 2, 3, 4 # encoding: [0x8c,0x21,0x43,0x10] vmrglw 2, 3, 4 - +# CHECK-BE: vmrgew 2, 3, 4 # encoding: [0x10,0x43,0x27,0x8c] +# CHECK-LE: vmrgew 2, 3, 4 # encoding: [0x8c,0x27,0x43,0x10] + vmrgew 2, 3, 4 +# CHECK-BE: vmrgow 2, 3, 4 # encoding: [0x10,0x43,0x26,0x8c] +# CHECK-LE: vmrgow 2, 3, 4 # encoding: [0x8c,0x26,0x43,0x10] + vmrgow 2, 3, 4 + # CHECK-BE: vspltb 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x0c] # CHECK-LE: vspltb 2, 3, 1 # encoding: [0x0c,0x1a,0x41,0x10] vspltb 2, 3, 1 diff --git a/test/MC/X86/AlignedBundling/misaligned-bundle-group.s b/test/MC/X86/AlignedBundling/misaligned-bundle-group.s new file mode 100644 index 0000000000000..04b3374716bbe --- /dev/null +++ b/test/MC/X86/AlignedBundling/misaligned-bundle-group.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ +# RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ +# RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s + + .text +foo: + .bundle_align_mode 5 + push %ebp # 1 byte + .align 16 + .bundle_lock align_to_end +# CHECK: 1: nopw %cs:(%eax,%eax) +# CHECK: 10: nopw %cs:(%eax,%eax) +# CHECK-RELAX: 1f: nop +# CHECK-RELAX: 20: nopw %cs:(%eax,%eax) +# CHECK-RELAX: 2f: nopw %cs:(%eax,%eax) +# CHECK-OPT: 1b: calll -4 +# CHECK-RELAX: 3b: calll -4 + calll bar # 5 bytes + .bundle_unlock + ret # 1 byte diff --git a/test/MC/X86/AlignedBundling/misaligned-bundle.s b/test/MC/X86/AlignedBundling/misaligned-bundle.s new file mode 100644 index 0000000000000..08d6161099097 --- /dev/null +++ b/test/MC/X86/AlignedBundling/misaligned-bundle.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ +# RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ +# RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s + + .text +foo: + .bundle_align_mode 5 + push %ebp # 1 byte + .align 16 +# CHECK: 1: nopw %cs:(%eax,%eax) +# CHECK-RELAX: 10: nopw %cs:(%eax,%eax) +# CHECK-RELAX: 1f: nop +# CHECK-OPT: 10: movl $1, (%esp) +# CHECK-RELAX: 20: movl $1, (%esp) + movl $0x1, (%esp) # 7 bytes + movl $0x1, (%esp) # 7 bytes +# CHECK-OPT: 1e: nop + movl $0x2, 0x1(%esp) # 8 bytes + movl $0x2, 0x1(%esp) # 8 bytes +# CHECK-RELAX: 3e: nop +# CHECK-RELAX: 40: movl $2, 1(%esp) + movl $0x2, 0x1(%esp) # 8 bytes + movl $0x2, (%esp) # 7 bytes +# CHECK-OPT: 3f: nop +# CHECK-OPT: 40: movl $3, (%esp) + movl $0x3, (%esp) # 7 bytes + movl $0x3, (%esp) # 7 bytes + ret diff --git a/test/MC/X86/AlignedBundling/rodata-section.s b/test/MC/X86/AlignedBundling/rodata-section.s new file mode 100644 index 0000000000000..21f2c735f8cb4 --- /dev/null +++ b/test/MC/X86/AlignedBundling/rodata-section.s @@ -0,0 +1,30 @@ +# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - \ +# RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s + + .bundle_align_mode 5 + .text + .align 32, 0x90 +# CHECK: 0: movl $14, 8(%esp) + movl $.str2, 8(%esp) +# CHECK: 8: movl $7, 4(%esp) + movl $.str1, 4(%esp) +# CHECK: 10: movl $0, (%esp) + movl $.str, (%esp) + + .type .str,@object + .section .rodata,"a",@progbits +.str: + .asciz "hello1" + .size .str, 7 + + .type .str1,@object +.str1: + .asciz "hello2" + .size .str1, 7 + + .type .str2,@object +.str2: + .asciz "hello3" + .size .str2, 7 diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s index e52dfac1976c9..079cb8850e6c5 100644 --- a/test/MC/X86/avx512-encodings.s +++ b/test/MC/X86/avx512-encodings.s @@ -9290,6 +9290,2671 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2 // CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0xb2,0xf8,0xfb,0xff,0xff] vcvtusi2ssq -1032(%rdx), %xmm22, %xmm14 +// CHECK: vfmadd132ps %zmm25, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0x92,0x5d,0x40,0x98,0xc9] + vfmadd132ps %zmm25, %zmm20, %zmm1 + +// CHECK: vfmadd132ps %zmm25, %zmm20, %zmm1 {%k1} +// CHECK: encoding: [0x62,0x92,0x5d,0x41,0x98,0xc9] + vfmadd132ps %zmm25, %zmm20, %zmm1 {%k1} + +// CHECK: vfmadd132ps %zmm25, %zmm20, %zmm1 {%k1} {z} +// CHECK: encoding: [0x62,0x92,0x5d,0xc1,0x98,0xc9] + vfmadd132ps %zmm25, %zmm20, %zmm1 {%k1} {z} + +// CHECK: vfmadd132ps {rn-sae}, %zmm25, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0x92,0x5d,0x10,0x98,0xc9] + vfmadd132ps {rn-sae}, %zmm25, %zmm20, %zmm1 + +// CHECK: vfmadd132ps {ru-sae}, %zmm25, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0x92,0x5d,0x50,0x98,0xc9] + vfmadd132ps {ru-sae}, %zmm25, %zmm20, %zmm1 + +// CHECK: vfmadd132ps {rd-sae}, %zmm25, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0x92,0x5d,0x30,0x98,0xc9] + vfmadd132ps {rd-sae}, %zmm25, %zmm20, %zmm1 + +// CHECK: vfmadd132ps {rz-sae}, %zmm25, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0x92,0x5d,0x70,0x98,0xc9] + vfmadd132ps {rz-sae}, %zmm25, %zmm20, %zmm1 + +// CHECK: vfmadd132ps (%rcx), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x40,0x98,0x09] + vfmadd132ps (%rcx), %zmm20, %zmm1 + +// CHECK: vfmadd132ps 291(%rax,%r14,8), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x5d,0x40,0x98,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmadd132ps 291(%rax,%r14,8), %zmm20, %zmm1 + +// CHECK: vfmadd132ps (%rcx){1to16}, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x50,0x98,0x09] + vfmadd132ps (%rcx){1to16}, %zmm20, %zmm1 + +// CHECK: vfmadd132ps 8128(%rdx), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x40,0x98,0x4a,0x7f] + vfmadd132ps 8128(%rdx), %zmm20, %zmm1 + +// CHECK: vfmadd132ps 8192(%rdx), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x40,0x98,0x8a,0x00,0x20,0x00,0x00] + vfmadd132ps 8192(%rdx), %zmm20, %zmm1 + +// CHECK: vfmadd132ps -8192(%rdx), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x40,0x98,0x4a,0x80] + vfmadd132ps -8192(%rdx), %zmm20, %zmm1 + +// CHECK: vfmadd132ps -8256(%rdx), %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x40,0x98,0x8a,0xc0,0xdf,0xff,0xff] + vfmadd132ps -8256(%rdx), %zmm20, %zmm1 + +// CHECK: vfmadd132ps 508(%rdx){1to16}, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x50,0x98,0x4a,0x7f] + vfmadd132ps 508(%rdx){1to16}, %zmm20, %zmm1 + +// CHECK: vfmadd132ps 512(%rdx){1to16}, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x50,0x98,0x8a,0x00,0x02,0x00,0x00] + vfmadd132ps 512(%rdx){1to16}, %zmm20, %zmm1 + +// CHECK: vfmadd132ps -512(%rdx){1to16}, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x50,0x98,0x4a,0x80] + vfmadd132ps -512(%rdx){1to16}, %zmm20, %zmm1 + +// CHECK: vfmadd132ps -516(%rdx){1to16}, %zmm20, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x5d,0x50,0x98,0x8a,0xfc,0xfd,0xff,0xff] + vfmadd132ps -516(%rdx){1to16}, %zmm20, %zmm1 + +// CHECK: vfmadd132pd %zmm21, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x40,0x98,0xd5] + vfmadd132pd %zmm21, %zmm16, %zmm26 + +// CHECK: vfmadd132pd %zmm21, %zmm16, %zmm26 {%k5} +// CHECK: encoding: [0x62,0x22,0xfd,0x45,0x98,0xd5] + vfmadd132pd %zmm21, %zmm16, %zmm26 {%k5} + +// CHECK: vfmadd132pd %zmm21, %zmm16, %zmm26 {%k5} {z} +// CHECK: encoding: [0x62,0x22,0xfd,0xc5,0x98,0xd5] + vfmadd132pd %zmm21, %zmm16, %zmm26 {%k5} {z} + +// CHECK: vfmadd132pd {rn-sae}, %zmm21, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x10,0x98,0xd5] + vfmadd132pd {rn-sae}, %zmm21, %zmm16, %zmm26 + +// CHECK: vfmadd132pd {ru-sae}, %zmm21, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x50,0x98,0xd5] + vfmadd132pd {ru-sae}, %zmm21, %zmm16, %zmm26 + +// CHECK: vfmadd132pd {rd-sae}, %zmm21, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x30,0x98,0xd5] + vfmadd132pd {rd-sae}, %zmm21, %zmm16, %zmm26 + +// CHECK: vfmadd132pd {rz-sae}, %zmm21, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x70,0x98,0xd5] + vfmadd132pd {rz-sae}, %zmm21, %zmm16, %zmm26 + +// CHECK: vfmadd132pd (%rcx), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x40,0x98,0x11] + vfmadd132pd (%rcx), %zmm16, %zmm26 + +// CHECK: vfmadd132pd 291(%rax,%r14,8), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x22,0xfd,0x40,0x98,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmadd132pd 291(%rax,%r14,8), %zmm16, %zmm26 + +// CHECK: vfmadd132pd (%rcx){1to8}, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x50,0x98,0x11] + vfmadd132pd (%rcx){1to8}, %zmm16, %zmm26 + +// CHECK: vfmadd132pd 8128(%rdx), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x40,0x98,0x52,0x7f] + vfmadd132pd 8128(%rdx), %zmm16, %zmm26 + +// CHECK: vfmadd132pd 8192(%rdx), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x40,0x98,0x92,0x00,0x20,0x00,0x00] + vfmadd132pd 8192(%rdx), %zmm16, %zmm26 + +// CHECK: vfmadd132pd -8192(%rdx), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x40,0x98,0x52,0x80] + vfmadd132pd -8192(%rdx), %zmm16, %zmm26 + +// CHECK: vfmadd132pd -8256(%rdx), %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x40,0x98,0x92,0xc0,0xdf,0xff,0xff] + vfmadd132pd -8256(%rdx), %zmm16, %zmm26 + +// CHECK: vfmadd132pd 1016(%rdx){1to8}, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x50,0x98,0x52,0x7f] + vfmadd132pd 1016(%rdx){1to8}, %zmm16, %zmm26 + +// CHECK: vfmadd132pd 1024(%rdx){1to8}, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x50,0x98,0x92,0x00,0x04,0x00,0x00] + vfmadd132pd 1024(%rdx){1to8}, %zmm16, %zmm26 + +// CHECK: vfmadd132pd -1024(%rdx){1to8}, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x50,0x98,0x52,0x80] + vfmadd132pd -1024(%rdx){1to8}, %zmm16, %zmm26 + +// CHECK: vfmadd132pd -1032(%rdx){1to8}, %zmm16, %zmm26 +// CHECK: encoding: [0x62,0x62,0xfd,0x50,0x98,0x92,0xf8,0xfb,0xff,0xff] + vfmadd132pd -1032(%rdx){1to8}, %zmm16, %zmm26 + +// CHECK: vfmadd213ps %zmm14, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xc2,0x65,0x40,0xa8,0xe6] + vfmadd213ps %zmm14, %zmm19, %zmm20 + +// CHECK: vfmadd213ps %zmm14, %zmm19, %zmm20 {%k4} +// CHECK: encoding: [0x62,0xc2,0x65,0x44,0xa8,0xe6] + vfmadd213ps %zmm14, %zmm19, %zmm20 {%k4} + +// CHECK: vfmadd213ps %zmm14, %zmm19, %zmm20 {%k4} {z} +// CHECK: encoding: [0x62,0xc2,0x65,0xc4,0xa8,0xe6] + vfmadd213ps %zmm14, %zmm19, %zmm20 {%k4} {z} + +// CHECK: vfmadd213ps {rn-sae}, %zmm14, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xc2,0x65,0x10,0xa8,0xe6] + vfmadd213ps {rn-sae}, %zmm14, %zmm19, %zmm20 + +// CHECK: vfmadd213ps {ru-sae}, %zmm14, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xc2,0x65,0x50,0xa8,0xe6] + vfmadd213ps {ru-sae}, %zmm14, %zmm19, %zmm20 + +// CHECK: vfmadd213ps {rd-sae}, %zmm14, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xc2,0x65,0x30,0xa8,0xe6] + vfmadd213ps {rd-sae}, %zmm14, %zmm19, %zmm20 + +// CHECK: vfmadd213ps {rz-sae}, %zmm14, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xc2,0x65,0x70,0xa8,0xe6] + vfmadd213ps {rz-sae}, %zmm14, %zmm19, %zmm20 + +// CHECK: vfmadd213ps (%rcx), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x40,0xa8,0x21] + vfmadd213ps (%rcx), %zmm19, %zmm20 + +// CHECK: vfmadd213ps 291(%rax,%r14,8), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xa2,0x65,0x40,0xa8,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmadd213ps 291(%rax,%r14,8), %zmm19, %zmm20 + +// CHECK: vfmadd213ps (%rcx){1to16}, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x50,0xa8,0x21] + vfmadd213ps (%rcx){1to16}, %zmm19, %zmm20 + +// CHECK: vfmadd213ps 8128(%rdx), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x40,0xa8,0x62,0x7f] + vfmadd213ps 8128(%rdx), %zmm19, %zmm20 + +// CHECK: vfmadd213ps 8192(%rdx), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x40,0xa8,0xa2,0x00,0x20,0x00,0x00] + vfmadd213ps 8192(%rdx), %zmm19, %zmm20 + +// CHECK: vfmadd213ps -8192(%rdx), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x40,0xa8,0x62,0x80] + vfmadd213ps -8192(%rdx), %zmm19, %zmm20 + +// CHECK: vfmadd213ps -8256(%rdx), %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x40,0xa8,0xa2,0xc0,0xdf,0xff,0xff] + vfmadd213ps -8256(%rdx), %zmm19, %zmm20 + +// CHECK: vfmadd213ps 508(%rdx){1to16}, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x50,0xa8,0x62,0x7f] + vfmadd213ps 508(%rdx){1to16}, %zmm19, %zmm20 + +// CHECK: vfmadd213ps 512(%rdx){1to16}, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x50,0xa8,0xa2,0x00,0x02,0x00,0x00] + vfmadd213ps 512(%rdx){1to16}, %zmm19, %zmm20 + +// CHECK: vfmadd213ps -512(%rdx){1to16}, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x50,0xa8,0x62,0x80] + vfmadd213ps -512(%rdx){1to16}, %zmm19, %zmm20 + +// CHECK: vfmadd213ps -516(%rdx){1to16}, %zmm19, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x65,0x50,0xa8,0xa2,0xfc,0xfd,0xff,0xff] + vfmadd213ps -516(%rdx){1to16}, %zmm19, %zmm20 + +// CHECK: vfmadd213pd %zmm25, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0x82,0xfd,0x40,0xa8,0xd1] + vfmadd213pd %zmm25, %zmm16, %zmm18 + +// CHECK: vfmadd213pd %zmm25, %zmm16, %zmm18 {%k3} +// CHECK: encoding: [0x62,0x82,0xfd,0x43,0xa8,0xd1] + vfmadd213pd %zmm25, %zmm16, %zmm18 {%k3} + +// CHECK: vfmadd213pd %zmm25, %zmm16, %zmm18 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0xfd,0xc3,0xa8,0xd1] + vfmadd213pd %zmm25, %zmm16, %zmm18 {%k3} {z} + +// CHECK: vfmadd213pd {rn-sae}, %zmm25, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0x82,0xfd,0x10,0xa8,0xd1] + vfmadd213pd {rn-sae}, %zmm25, %zmm16, %zmm18 + +// CHECK: vfmadd213pd {ru-sae}, %zmm25, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0x82,0xfd,0x50,0xa8,0xd1] + vfmadd213pd {ru-sae}, %zmm25, %zmm16, %zmm18 + +// CHECK: vfmadd213pd {rd-sae}, %zmm25, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0x82,0xfd,0x30,0xa8,0xd1] + vfmadd213pd {rd-sae}, %zmm25, %zmm16, %zmm18 + +// CHECK: vfmadd213pd {rz-sae}, %zmm25, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0x82,0xfd,0x70,0xa8,0xd1] + vfmadd213pd {rz-sae}, %zmm25, %zmm16, %zmm18 + +// CHECK: vfmadd213pd (%rcx), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xa8,0x11] + vfmadd213pd (%rcx), %zmm16, %zmm18 + +// CHECK: vfmadd213pd 291(%rax,%r14,8), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xa2,0xfd,0x40,0xa8,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmadd213pd 291(%rax,%r14,8), %zmm16, %zmm18 + +// CHECK: vfmadd213pd (%rcx){1to8}, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xa8,0x11] + vfmadd213pd (%rcx){1to8}, %zmm16, %zmm18 + +// CHECK: vfmadd213pd 8128(%rdx), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xa8,0x52,0x7f] + vfmadd213pd 8128(%rdx), %zmm16, %zmm18 + +// CHECK: vfmadd213pd 8192(%rdx), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xa8,0x92,0x00,0x20,0x00,0x00] + vfmadd213pd 8192(%rdx), %zmm16, %zmm18 + +// CHECK: vfmadd213pd -8192(%rdx), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xa8,0x52,0x80] + vfmadd213pd -8192(%rdx), %zmm16, %zmm18 + +// CHECK: vfmadd213pd -8256(%rdx), %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xa8,0x92,0xc0,0xdf,0xff,0xff] + vfmadd213pd -8256(%rdx), %zmm16, %zmm18 + +// CHECK: vfmadd213pd 1016(%rdx){1to8}, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xa8,0x52,0x7f] + vfmadd213pd 1016(%rdx){1to8}, %zmm16, %zmm18 + +// CHECK: vfmadd213pd 1024(%rdx){1to8}, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xa8,0x92,0x00,0x04,0x00,0x00] + vfmadd213pd 1024(%rdx){1to8}, %zmm16, %zmm18 + +// CHECK: vfmadd213pd -1024(%rdx){1to8}, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xa8,0x52,0x80] + vfmadd213pd -1024(%rdx){1to8}, %zmm16, %zmm18 + +// CHECK: vfmadd213pd -1032(%rdx){1to8}, %zmm16, %zmm18 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xa8,0x92,0xf8,0xfb,0xff,0xff] + vfmadd213pd -1032(%rdx){1to8}, %zmm16, %zmm18 + +// CHECK: vfmadd231ps %zmm25, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x02,0x1d,0x40,0xb8,0xd9] + vfmadd231ps %zmm25, %zmm28, %zmm27 + +// CHECK: vfmadd231ps %zmm25, %zmm28, %zmm27 {%k3} +// CHECK: encoding: [0x62,0x02,0x1d,0x43,0xb8,0xd9] + vfmadd231ps %zmm25, %zmm28, %zmm27 {%k3} + +// CHECK: vfmadd231ps %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x1d,0xc3,0xb8,0xd9] + vfmadd231ps %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd231ps {rn-sae}, %zmm25, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x02,0x1d,0x10,0xb8,0xd9] + vfmadd231ps {rn-sae}, %zmm25, %zmm28, %zmm27 + +// CHECK: vfmadd231ps {ru-sae}, %zmm25, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x02,0x1d,0x50,0xb8,0xd9] + vfmadd231ps {ru-sae}, %zmm25, %zmm28, %zmm27 + +// CHECK: vfmadd231ps {rd-sae}, %zmm25, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x02,0x1d,0x30,0xb8,0xd9] + vfmadd231ps {rd-sae}, %zmm25, %zmm28, %zmm27 + +// CHECK: vfmadd231ps {rz-sae}, %zmm25, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x02,0x1d,0x70,0xb8,0xd9] + vfmadd231ps {rz-sae}, %zmm25, %zmm28, %zmm27 + +// CHECK: vfmadd231ps (%rcx), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x40,0xb8,0x19] + vfmadd231ps (%rcx), %zmm28, %zmm27 + +// CHECK: vfmadd231ps 291(%rax,%r14,8), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x22,0x1d,0x40,0xb8,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmadd231ps 291(%rax,%r14,8), %zmm28, %zmm27 + +// CHECK: vfmadd231ps (%rcx){1to16}, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x50,0xb8,0x19] + vfmadd231ps (%rcx){1to16}, %zmm28, %zmm27 + +// CHECK: vfmadd231ps 8128(%rdx), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x40,0xb8,0x5a,0x7f] + vfmadd231ps 8128(%rdx), %zmm28, %zmm27 + +// CHECK: vfmadd231ps 8192(%rdx), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x40,0xb8,0x9a,0x00,0x20,0x00,0x00] + vfmadd231ps 8192(%rdx), %zmm28, %zmm27 + +// CHECK: vfmadd231ps -8192(%rdx), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x40,0xb8,0x5a,0x80] + vfmadd231ps -8192(%rdx), %zmm28, %zmm27 + +// CHECK: vfmadd231ps -8256(%rdx), %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x40,0xb8,0x9a,0xc0,0xdf,0xff,0xff] + vfmadd231ps -8256(%rdx), %zmm28, %zmm27 + +// CHECK: vfmadd231ps 508(%rdx){1to16}, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x50,0xb8,0x5a,0x7f] + vfmadd231ps 508(%rdx){1to16}, %zmm28, %zmm27 + +// CHECK: vfmadd231ps 512(%rdx){1to16}, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x50,0xb8,0x9a,0x00,0x02,0x00,0x00] + vfmadd231ps 512(%rdx){1to16}, %zmm28, %zmm27 + +// CHECK: vfmadd231ps -512(%rdx){1to16}, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x50,0xb8,0x5a,0x80] + vfmadd231ps -512(%rdx){1to16}, %zmm28, %zmm27 + +// CHECK: vfmadd231ps -516(%rdx){1to16}, %zmm28, %zmm27 +// CHECK: encoding: [0x62,0x62,0x1d,0x50,0xb8,0x9a,0xfc,0xfd,0xff,0xff] + vfmadd231ps -516(%rdx){1to16}, %zmm28, %zmm27 + +// CHECK: vfmadd231pd %zmm9, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x42,0xcd,0x48,0xb8,0xf1] + vfmadd231pd %zmm9, %zmm6, %zmm30 + +// CHECK: vfmadd231pd %zmm9, %zmm6, %zmm30 {%k4} +// CHECK: encoding: [0x62,0x42,0xcd,0x4c,0xb8,0xf1] + vfmadd231pd %zmm9, %zmm6, %zmm30 {%k4} + +// CHECK: vfmadd231pd %zmm9, %zmm6, %zmm30 {%k4} {z} +// CHECK: encoding: [0x62,0x42,0xcd,0xcc,0xb8,0xf1] + vfmadd231pd %zmm9, %zmm6, %zmm30 {%k4} {z} + +// CHECK: vfmadd231pd {rn-sae}, %zmm9, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x42,0xcd,0x18,0xb8,0xf1] + vfmadd231pd {rn-sae}, %zmm9, %zmm6, %zmm30 + +// CHECK: vfmadd231pd {ru-sae}, %zmm9, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x42,0xcd,0x58,0xb8,0xf1] + vfmadd231pd {ru-sae}, %zmm9, %zmm6, %zmm30 + +// CHECK: vfmadd231pd {rd-sae}, %zmm9, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x42,0xcd,0x38,0xb8,0xf1] + vfmadd231pd {rd-sae}, %zmm9, %zmm6, %zmm30 + +// CHECK: vfmadd231pd {rz-sae}, %zmm9, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x42,0xcd,0x78,0xb8,0xf1] + vfmadd231pd {rz-sae}, %zmm9, %zmm6, %zmm30 + +// CHECK: vfmadd231pd (%rcx), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xb8,0x31] + vfmadd231pd (%rcx), %zmm6, %zmm30 + +// CHECK: vfmadd231pd 291(%rax,%r14,8), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x22,0xcd,0x48,0xb8,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd231pd 291(%rax,%r14,8), %zmm6, %zmm30 + +// CHECK: vfmadd231pd (%rcx){1to8}, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xb8,0x31] + vfmadd231pd (%rcx){1to8}, %zmm6, %zmm30 + +// CHECK: vfmadd231pd 8128(%rdx), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xb8,0x72,0x7f] + vfmadd231pd 8128(%rdx), %zmm6, %zmm30 + +// CHECK: vfmadd231pd 8192(%rdx), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xb8,0xb2,0x00,0x20,0x00,0x00] + vfmadd231pd 8192(%rdx), %zmm6, %zmm30 + +// CHECK: vfmadd231pd -8192(%rdx), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xb8,0x72,0x80] + vfmadd231pd -8192(%rdx), %zmm6, %zmm30 + +// CHECK: vfmadd231pd -8256(%rdx), %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xb8,0xb2,0xc0,0xdf,0xff,0xff] + vfmadd231pd -8256(%rdx), %zmm6, %zmm30 + +// CHECK: vfmadd231pd 1016(%rdx){1to8}, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xb8,0x72,0x7f] + vfmadd231pd 1016(%rdx){1to8}, %zmm6, %zmm30 + +// CHECK: vfmadd231pd 1024(%rdx){1to8}, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xb8,0xb2,0x00,0x04,0x00,0x00] + vfmadd231pd 1024(%rdx){1to8}, %zmm6, %zmm30 + +// CHECK: vfmadd231pd -1024(%rdx){1to8}, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xb8,0x72,0x80] + vfmadd231pd -1024(%rdx){1to8}, %zmm6, %zmm30 + +// CHECK: vfmadd231pd -1032(%rdx){1to8}, %zmm6, %zmm30 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xb8,0xb2,0xf8,0xfb,0xff,0xff] + vfmadd231pd -1032(%rdx){1to8}, %zmm6, %zmm30 + +// CHECK: vfmsub132ps %zmm16, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x48,0x9a,0xc8] + vfmsub132ps %zmm16, %zmm13, %zmm1 + +// CHECK: vfmsub132ps %zmm16, %zmm13, %zmm1 {%k4} +// CHECK: encoding: [0x62,0xb2,0x15,0x4c,0x9a,0xc8] + vfmsub132ps %zmm16, %zmm13, %zmm1 {%k4} + +// CHECK: vfmsub132ps %zmm16, %zmm13, %zmm1 {%k4} {z} +// CHECK: encoding: [0x62,0xb2,0x15,0xcc,0x9a,0xc8] + vfmsub132ps %zmm16, %zmm13, %zmm1 {%k4} {z} + +// CHECK: vfmsub132ps {rn-sae}, %zmm16, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x18,0x9a,0xc8] + vfmsub132ps {rn-sae}, %zmm16, %zmm13, %zmm1 + +// CHECK: vfmsub132ps {ru-sae}, %zmm16, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x58,0x9a,0xc8] + vfmsub132ps {ru-sae}, %zmm16, %zmm13, %zmm1 + +// CHECK: vfmsub132ps {rd-sae}, %zmm16, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x38,0x9a,0xc8] + vfmsub132ps {rd-sae}, %zmm16, %zmm13, %zmm1 + +// CHECK: vfmsub132ps {rz-sae}, %zmm16, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x78,0x9a,0xc8] + vfmsub132ps {rz-sae}, %zmm16, %zmm13, %zmm1 + +// CHECK: vfmsub132ps (%rcx), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x9a,0x09] + vfmsub132ps (%rcx), %zmm13, %zmm1 + +// CHECK: vfmsub132ps 291(%rax,%r14,8), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xb2,0x15,0x48,0x9a,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmsub132ps 291(%rax,%r14,8), %zmm13, %zmm1 + +// CHECK: vfmsub132ps (%rcx){1to16}, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x9a,0x09] + vfmsub132ps (%rcx){1to16}, %zmm13, %zmm1 + +// CHECK: vfmsub132ps 8128(%rdx), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x9a,0x4a,0x7f] + vfmsub132ps 8128(%rdx), %zmm13, %zmm1 + +// CHECK: vfmsub132ps 8192(%rdx), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x9a,0x8a,0x00,0x20,0x00,0x00] + vfmsub132ps 8192(%rdx), %zmm13, %zmm1 + +// CHECK: vfmsub132ps -8192(%rdx), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x9a,0x4a,0x80] + vfmsub132ps -8192(%rdx), %zmm13, %zmm1 + +// CHECK: vfmsub132ps -8256(%rdx), %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x9a,0x8a,0xc0,0xdf,0xff,0xff] + vfmsub132ps -8256(%rdx), %zmm13, %zmm1 + +// CHECK: vfmsub132ps 508(%rdx){1to16}, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x9a,0x4a,0x7f] + vfmsub132ps 508(%rdx){1to16}, %zmm13, %zmm1 + +// CHECK: vfmsub132ps 512(%rdx){1to16}, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x9a,0x8a,0x00,0x02,0x00,0x00] + vfmsub132ps 512(%rdx){1to16}, %zmm13, %zmm1 + +// CHECK: vfmsub132ps -512(%rdx){1to16}, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x9a,0x4a,0x80] + vfmsub132ps -512(%rdx){1to16}, %zmm13, %zmm1 + +// CHECK: vfmsub132ps -516(%rdx){1to16}, %zmm13, %zmm1 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x9a,0x8a,0xfc,0xfd,0xff,0xff] + vfmsub132ps -516(%rdx){1to16}, %zmm13, %zmm1 + +// CHECK: vfmsub132pd %zmm27, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0x82,0x9d,0x48,0x9a,0xf3] + vfmsub132pd %zmm27, %zmm12, %zmm22 + +// CHECK: vfmsub132pd %zmm27, %zmm12, %zmm22 {%k2} +// CHECK: encoding: [0x62,0x82,0x9d,0x4a,0x9a,0xf3] + vfmsub132pd %zmm27, %zmm12, %zmm22 {%k2} + +// CHECK: vfmsub132pd %zmm27, %zmm12, %zmm22 {%k2} {z} +// CHECK: encoding: [0x62,0x82,0x9d,0xca,0x9a,0xf3] + vfmsub132pd %zmm27, %zmm12, %zmm22 {%k2} {z} + +// CHECK: vfmsub132pd {rn-sae}, %zmm27, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0x82,0x9d,0x18,0x9a,0xf3] + vfmsub132pd {rn-sae}, %zmm27, %zmm12, %zmm22 + +// CHECK: vfmsub132pd {ru-sae}, %zmm27, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0x82,0x9d,0x58,0x9a,0xf3] + vfmsub132pd {ru-sae}, %zmm27, %zmm12, %zmm22 + +// CHECK: vfmsub132pd {rd-sae}, %zmm27, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0x82,0x9d,0x38,0x9a,0xf3] + vfmsub132pd {rd-sae}, %zmm27, %zmm12, %zmm22 + +// CHECK: vfmsub132pd {rz-sae}, %zmm27, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0x82,0x9d,0x78,0x9a,0xf3] + vfmsub132pd {rz-sae}, %zmm27, %zmm12, %zmm22 + +// CHECK: vfmsub132pd (%rcx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x48,0x9a,0x31] + vfmsub132pd (%rcx), %zmm12, %zmm22 + +// CHECK: vfmsub132pd 291(%rax,%r14,8), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xa2,0x9d,0x48,0x9a,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub132pd 291(%rax,%r14,8), %zmm12, %zmm22 + +// CHECK: vfmsub132pd (%rcx){1to8}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x58,0x9a,0x31] + vfmsub132pd (%rcx){1to8}, %zmm12, %zmm22 + +// CHECK: vfmsub132pd 8128(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x48,0x9a,0x72,0x7f] + vfmsub132pd 8128(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsub132pd 8192(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x48,0x9a,0xb2,0x00,0x20,0x00,0x00] + vfmsub132pd 8192(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsub132pd -8192(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x48,0x9a,0x72,0x80] + vfmsub132pd -8192(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsub132pd -8256(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x48,0x9a,0xb2,0xc0,0xdf,0xff,0xff] + vfmsub132pd -8256(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsub132pd 1016(%rdx){1to8}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x58,0x9a,0x72,0x7f] + vfmsub132pd 1016(%rdx){1to8}, %zmm12, %zmm22 + +// CHECK: vfmsub132pd 1024(%rdx){1to8}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x58,0x9a,0xb2,0x00,0x04,0x00,0x00] + vfmsub132pd 1024(%rdx){1to8}, %zmm12, %zmm22 + +// CHECK: vfmsub132pd -1024(%rdx){1to8}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x58,0x9a,0x72,0x80] + vfmsub132pd -1024(%rdx){1to8}, %zmm12, %zmm22 + +// CHECK: vfmsub132pd -1032(%rdx){1to8}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x58,0x9a,0xb2,0xf8,0xfb,0xff,0xff] + vfmsub132pd -1032(%rdx){1to8}, %zmm12, %zmm22 + +// CHECK: vfmsub213ps %zmm10, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x4d,0x40,0xaa,0xf2] + vfmsub213ps %zmm10, %zmm22, %zmm22 + +// CHECK: vfmsub213ps %zmm10, %zmm22, %zmm22 {%k6} +// CHECK: encoding: [0x62,0xc2,0x4d,0x46,0xaa,0xf2] + vfmsub213ps %zmm10, %zmm22, %zmm22 {%k6} + +// CHECK: vfmsub213ps %zmm10, %zmm22, %zmm22 {%k6} {z} +// CHECK: encoding: [0x62,0xc2,0x4d,0xc6,0xaa,0xf2] + vfmsub213ps %zmm10, %zmm22, %zmm22 {%k6} {z} + +// CHECK: vfmsub213ps {rn-sae}, %zmm10, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x4d,0x10,0xaa,0xf2] + vfmsub213ps {rn-sae}, %zmm10, %zmm22, %zmm22 + +// CHECK: vfmsub213ps {ru-sae}, %zmm10, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x4d,0x50,0xaa,0xf2] + vfmsub213ps {ru-sae}, %zmm10, %zmm22, %zmm22 + +// CHECK: vfmsub213ps {rd-sae}, %zmm10, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x4d,0x30,0xaa,0xf2] + vfmsub213ps {rd-sae}, %zmm10, %zmm22, %zmm22 + +// CHECK: vfmsub213ps {rz-sae}, %zmm10, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x4d,0x70,0xaa,0xf2] + vfmsub213ps {rz-sae}, %zmm10, %zmm22, %zmm22 + +// CHECK: vfmsub213ps (%rcx), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x40,0xaa,0x31] + vfmsub213ps (%rcx), %zmm22, %zmm22 + +// CHECK: vfmsub213ps 291(%rax,%r14,8), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xa2,0x4d,0x40,0xaa,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub213ps 291(%rax,%r14,8), %zmm22, %zmm22 + +// CHECK: vfmsub213ps (%rcx){1to16}, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x50,0xaa,0x31] + vfmsub213ps (%rcx){1to16}, %zmm22, %zmm22 + +// CHECK: vfmsub213ps 8128(%rdx), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x40,0xaa,0x72,0x7f] + vfmsub213ps 8128(%rdx), %zmm22, %zmm22 + +// CHECK: vfmsub213ps 8192(%rdx), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x40,0xaa,0xb2,0x00,0x20,0x00,0x00] + vfmsub213ps 8192(%rdx), %zmm22, %zmm22 + +// CHECK: vfmsub213ps -8192(%rdx), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x40,0xaa,0x72,0x80] + vfmsub213ps -8192(%rdx), %zmm22, %zmm22 + +// CHECK: vfmsub213ps -8256(%rdx), %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x40,0xaa,0xb2,0xc0,0xdf,0xff,0xff] + vfmsub213ps -8256(%rdx), %zmm22, %zmm22 + +// CHECK: vfmsub213ps 508(%rdx){1to16}, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x50,0xaa,0x72,0x7f] + vfmsub213ps 508(%rdx){1to16}, %zmm22, %zmm22 + +// CHECK: vfmsub213ps 512(%rdx){1to16}, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x50,0xaa,0xb2,0x00,0x02,0x00,0x00] + vfmsub213ps 512(%rdx){1to16}, %zmm22, %zmm22 + +// CHECK: vfmsub213ps -512(%rdx){1to16}, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x50,0xaa,0x72,0x80] + vfmsub213ps -512(%rdx){1to16}, %zmm22, %zmm22 + +// CHECK: vfmsub213ps -516(%rdx){1to16}, %zmm22, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x4d,0x50,0xaa,0xb2,0xfc,0xfd,0xff,0xff] + vfmsub213ps -516(%rdx){1to16}, %zmm22, %zmm22 + +// CHECK: vfmsub213pd %zmm4, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0xec] + vfmsub213pd %zmm4, %zmm10, %zmm5 + +// CHECK: vfmsub213pd %zmm4, %zmm10, %zmm5 {%k1} +// CHECK: encoding: [0x62,0xf2,0xad,0x49,0xaa,0xec] + vfmsub213pd %zmm4, %zmm10, %zmm5 {%k1} + +// CHECK: vfmsub213pd %zmm4, %zmm10, %zmm5 {%k1} {z} +// CHECK: encoding: [0x62,0xf2,0xad,0xc9,0xaa,0xec] + vfmsub213pd %zmm4, %zmm10, %zmm5 {%k1} {z} + +// CHECK: vfmsub213pd {rn-sae}, %zmm4, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x18,0xaa,0xec] + vfmsub213pd {rn-sae}, %zmm4, %zmm10, %zmm5 + +// CHECK: vfmsub213pd {ru-sae}, %zmm4, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0xec] + vfmsub213pd {ru-sae}, %zmm4, %zmm10, %zmm5 + +// CHECK: vfmsub213pd {rd-sae}, %zmm4, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x38,0xaa,0xec] + vfmsub213pd {rd-sae}, %zmm4, %zmm10, %zmm5 + +// CHECK: vfmsub213pd {rz-sae}, %zmm4, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x78,0xaa,0xec] + vfmsub213pd {rz-sae}, %zmm4, %zmm10, %zmm5 + +// CHECK: vfmsub213pd (%rcx), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0x29] + vfmsub213pd (%rcx), %zmm10, %zmm5 + +// CHECK: vfmsub213pd 291(%rax,%r14,8), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xb2,0xad,0x48,0xaa,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmsub213pd 291(%rax,%r14,8), %zmm10, %zmm5 + +// CHECK: vfmsub213pd (%rcx){1to8}, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0x29] + vfmsub213pd (%rcx){1to8}, %zmm10, %zmm5 + +// CHECK: vfmsub213pd 8128(%rdx), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0x6a,0x7f] + vfmsub213pd 8128(%rdx), %zmm10, %zmm5 + +// CHECK: vfmsub213pd 8192(%rdx), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0xaa,0x00,0x20,0x00,0x00] + vfmsub213pd 8192(%rdx), %zmm10, %zmm5 + +// CHECK: vfmsub213pd -8192(%rdx), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0x6a,0x80] + vfmsub213pd -8192(%rdx), %zmm10, %zmm5 + +// CHECK: vfmsub213pd -8256(%rdx), %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x48,0xaa,0xaa,0xc0,0xdf,0xff,0xff] + vfmsub213pd -8256(%rdx), %zmm10, %zmm5 + +// CHECK: vfmsub213pd 1016(%rdx){1to8}, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0x6a,0x7f] + vfmsub213pd 1016(%rdx){1to8}, %zmm10, %zmm5 + +// CHECK: vfmsub213pd 1024(%rdx){1to8}, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0xaa,0x00,0x04,0x00,0x00] + vfmsub213pd 1024(%rdx){1to8}, %zmm10, %zmm5 + +// CHECK: vfmsub213pd -1024(%rdx){1to8}, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0x6a,0x80] + vfmsub213pd -1024(%rdx){1to8}, %zmm10, %zmm5 + +// CHECK: vfmsub213pd -1032(%rdx){1to8}, %zmm10, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xad,0x58,0xaa,0xaa,0xf8,0xfb,0xff,0xff] + vfmsub213pd -1032(%rdx){1to8}, %zmm10, %zmm5 + +// CHECK: vfmsub231ps %zmm27, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0x92,0x55,0x40,0xba,0xf3] + vfmsub231ps %zmm27, %zmm21, %zmm6 + +// CHECK: vfmsub231ps %zmm27, %zmm21, %zmm6 {%k3} +// CHECK: encoding: [0x62,0x92,0x55,0x43,0xba,0xf3] + vfmsub231ps %zmm27, %zmm21, %zmm6 {%k3} + +// CHECK: vfmsub231ps %zmm27, %zmm21, %zmm6 {%k3} {z} +// CHECK: encoding: [0x62,0x92,0x55,0xc3,0xba,0xf3] + vfmsub231ps %zmm27, %zmm21, %zmm6 {%k3} {z} + +// CHECK: vfmsub231ps {rn-sae}, %zmm27, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0x92,0x55,0x10,0xba,0xf3] + vfmsub231ps {rn-sae}, %zmm27, %zmm21, %zmm6 + +// CHECK: vfmsub231ps {ru-sae}, %zmm27, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0x92,0x55,0x50,0xba,0xf3] + vfmsub231ps {ru-sae}, %zmm27, %zmm21, %zmm6 + +// CHECK: vfmsub231ps {rd-sae}, %zmm27, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0x92,0x55,0x30,0xba,0xf3] + vfmsub231ps {rd-sae}, %zmm27, %zmm21, %zmm6 + +// CHECK: vfmsub231ps {rz-sae}, %zmm27, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0x92,0x55,0x70,0xba,0xf3] + vfmsub231ps {rz-sae}, %zmm27, %zmm21, %zmm6 + +// CHECK: vfmsub231ps (%rcx), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x40,0xba,0x31] + vfmsub231ps (%rcx), %zmm21, %zmm6 + +// CHECK: vfmsub231ps 291(%rax,%r14,8), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xb2,0x55,0x40,0xba,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub231ps 291(%rax,%r14,8), %zmm21, %zmm6 + +// CHECK: vfmsub231ps (%rcx){1to16}, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x50,0xba,0x31] + vfmsub231ps (%rcx){1to16}, %zmm21, %zmm6 + +// CHECK: vfmsub231ps 8128(%rdx), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x40,0xba,0x72,0x7f] + vfmsub231ps 8128(%rdx), %zmm21, %zmm6 + +// CHECK: vfmsub231ps 8192(%rdx), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x40,0xba,0xb2,0x00,0x20,0x00,0x00] + vfmsub231ps 8192(%rdx), %zmm21, %zmm6 + +// CHECK: vfmsub231ps -8192(%rdx), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x40,0xba,0x72,0x80] + vfmsub231ps -8192(%rdx), %zmm21, %zmm6 + +// CHECK: vfmsub231ps -8256(%rdx), %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x40,0xba,0xb2,0xc0,0xdf,0xff,0xff] + vfmsub231ps -8256(%rdx), %zmm21, %zmm6 + +// CHECK: vfmsub231ps 508(%rdx){1to16}, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x50,0xba,0x72,0x7f] + vfmsub231ps 508(%rdx){1to16}, %zmm21, %zmm6 + +// CHECK: vfmsub231ps 512(%rdx){1to16}, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x50,0xba,0xb2,0x00,0x02,0x00,0x00] + vfmsub231ps 512(%rdx){1to16}, %zmm21, %zmm6 + +// CHECK: vfmsub231ps -512(%rdx){1to16}, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x50,0xba,0x72,0x80] + vfmsub231ps -512(%rdx){1to16}, %zmm21, %zmm6 + +// CHECK: vfmsub231ps -516(%rdx){1to16}, %zmm21, %zmm6 +// CHECK: encoding: [0x62,0xf2,0x55,0x50,0xba,0xb2,0xfc,0xfd,0xff,0xff] + vfmsub231ps -516(%rdx){1to16}, %zmm21, %zmm6 + +// CHECK: vfmsub231pd %zmm11, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x9d,0x48,0xba,0xeb] + vfmsub231pd %zmm11, %zmm12, %zmm5 + +// CHECK: vfmsub231pd %zmm11, %zmm12, %zmm5 {%k2} +// CHECK: encoding: [0x62,0xd2,0x9d,0x4a,0xba,0xeb] + vfmsub231pd %zmm11, %zmm12, %zmm5 {%k2} + +// CHECK: vfmsub231pd %zmm11, %zmm12, %zmm5 {%k2} {z} +// CHECK: encoding: [0x62,0xd2,0x9d,0xca,0xba,0xeb] + vfmsub231pd %zmm11, %zmm12, %zmm5 {%k2} {z} + +// CHECK: vfmsub231pd {rn-sae}, %zmm11, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x9d,0x18,0xba,0xeb] + vfmsub231pd {rn-sae}, %zmm11, %zmm12, %zmm5 + +// CHECK: vfmsub231pd {ru-sae}, %zmm11, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x9d,0x58,0xba,0xeb] + vfmsub231pd {ru-sae}, %zmm11, %zmm12, %zmm5 + +// CHECK: vfmsub231pd {rd-sae}, %zmm11, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x9d,0x38,0xba,0xeb] + vfmsub231pd {rd-sae}, %zmm11, %zmm12, %zmm5 + +// CHECK: vfmsub231pd {rz-sae}, %zmm11, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x9d,0x78,0xba,0xeb] + vfmsub231pd {rz-sae}, %zmm11, %zmm12, %zmm5 + +// CHECK: vfmsub231pd (%rcx), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x48,0xba,0x29] + vfmsub231pd (%rcx), %zmm12, %zmm5 + +// CHECK: vfmsub231pd 291(%rax,%r14,8), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xb2,0x9d,0x48,0xba,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmsub231pd 291(%rax,%r14,8), %zmm12, %zmm5 + +// CHECK: vfmsub231pd (%rcx){1to8}, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x58,0xba,0x29] + vfmsub231pd (%rcx){1to8}, %zmm12, %zmm5 + +// CHECK: vfmsub231pd 8128(%rdx), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x48,0xba,0x6a,0x7f] + vfmsub231pd 8128(%rdx), %zmm12, %zmm5 + +// CHECK: vfmsub231pd 8192(%rdx), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x48,0xba,0xaa,0x00,0x20,0x00,0x00] + vfmsub231pd 8192(%rdx), %zmm12, %zmm5 + +// CHECK: vfmsub231pd -8192(%rdx), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x48,0xba,0x6a,0x80] + vfmsub231pd -8192(%rdx), %zmm12, %zmm5 + +// CHECK: vfmsub231pd -8256(%rdx), %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x48,0xba,0xaa,0xc0,0xdf,0xff,0xff] + vfmsub231pd -8256(%rdx), %zmm12, %zmm5 + +// CHECK: vfmsub231pd 1016(%rdx){1to8}, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x58,0xba,0x6a,0x7f] + vfmsub231pd 1016(%rdx){1to8}, %zmm12, %zmm5 + +// CHECK: vfmsub231pd 1024(%rdx){1to8}, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x58,0xba,0xaa,0x00,0x04,0x00,0x00] + vfmsub231pd 1024(%rdx){1to8}, %zmm12, %zmm5 + +// CHECK: vfmsub231pd -1024(%rdx){1to8}, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x58,0xba,0x6a,0x80] + vfmsub231pd -1024(%rdx){1to8}, %zmm12, %zmm5 + +// CHECK: vfmsub231pd -1032(%rdx){1to8}, %zmm12, %zmm5 +// CHECK: encoding: [0x62,0xf2,0x9d,0x58,0xba,0xaa,0xf8,0xfb,0xff,0xff] + vfmsub231pd -1032(%rdx){1to8}, %zmm12, %zmm5 + +// CHECK: vfmaddsub132ps %zmm20, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x48,0x96,0xd4] + vfmaddsub132ps %zmm20, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps %zmm20, %zmm9, %zmm10 {%k3} +// CHECK: encoding: [0x62,0x32,0x35,0x4b,0x96,0xd4] + vfmaddsub132ps %zmm20, %zmm9, %zmm10 {%k3} + +// CHECK: vfmaddsub132ps %zmm20, %zmm9, %zmm10 {%k3} {z} +// CHECK: encoding: [0x62,0x32,0x35,0xcb,0x96,0xd4] + vfmaddsub132ps %zmm20, %zmm9, %zmm10 {%k3} {z} + +// CHECK: vfmaddsub132ps {rn-sae}, %zmm20, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x18,0x96,0xd4] + vfmaddsub132ps {rn-sae}, %zmm20, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps {ru-sae}, %zmm20, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x58,0x96,0xd4] + vfmaddsub132ps {ru-sae}, %zmm20, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps {rd-sae}, %zmm20, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x38,0x96,0xd4] + vfmaddsub132ps {rd-sae}, %zmm20, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps {rz-sae}, %zmm20, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x78,0x96,0xd4] + vfmaddsub132ps {rz-sae}, %zmm20, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps (%rcx), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x48,0x96,0x11] + vfmaddsub132ps (%rcx), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps 291(%rax,%r14,8), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x32,0x35,0x48,0x96,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132ps 291(%rax,%r14,8), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps (%rcx){1to16}, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x58,0x96,0x11] + vfmaddsub132ps (%rcx){1to16}, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps 8128(%rdx), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x48,0x96,0x52,0x7f] + vfmaddsub132ps 8128(%rdx), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps 8192(%rdx), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x48,0x96,0x92,0x00,0x20,0x00,0x00] + vfmaddsub132ps 8192(%rdx), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps -8192(%rdx), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x48,0x96,0x52,0x80] + vfmaddsub132ps -8192(%rdx), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps -8256(%rdx), %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x48,0x96,0x92,0xc0,0xdf,0xff,0xff] + vfmaddsub132ps -8256(%rdx), %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps 508(%rdx){1to16}, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x58,0x96,0x52,0x7f] + vfmaddsub132ps 508(%rdx){1to16}, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps 512(%rdx){1to16}, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x58,0x96,0x92,0x00,0x02,0x00,0x00] + vfmaddsub132ps 512(%rdx){1to16}, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps -512(%rdx){1to16}, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x58,0x96,0x52,0x80] + vfmaddsub132ps -512(%rdx){1to16}, %zmm9, %zmm10 + +// CHECK: vfmaddsub132ps -516(%rdx){1to16}, %zmm9, %zmm10 +// CHECK: encoding: [0x62,0x72,0x35,0x58,0x96,0x92,0xfc,0xfd,0xff,0xff] + vfmaddsub132ps -516(%rdx){1to16}, %zmm9, %zmm10 + +// CHECK: vfmaddsub132pd %zmm21, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x40,0x96,0xe5] + vfmaddsub132pd %zmm21, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd %zmm21, %zmm25, %zmm20 {%k2} +// CHECK: encoding: [0x62,0xa2,0xb5,0x42,0x96,0xe5] + vfmaddsub132pd %zmm21, %zmm25, %zmm20 {%k2} + +// CHECK: vfmaddsub132pd %zmm21, %zmm25, %zmm20 {%k2} {z} +// CHECK: encoding: [0x62,0xa2,0xb5,0xc2,0x96,0xe5] + vfmaddsub132pd %zmm21, %zmm25, %zmm20 {%k2} {z} + +// CHECK: vfmaddsub132pd {rn-sae}, %zmm21, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x10,0x96,0xe5] + vfmaddsub132pd {rn-sae}, %zmm21, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd {ru-sae}, %zmm21, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x50,0x96,0xe5] + vfmaddsub132pd {ru-sae}, %zmm21, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd {rd-sae}, %zmm21, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x30,0x96,0xe5] + vfmaddsub132pd {rd-sae}, %zmm21, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd {rz-sae}, %zmm21, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x70,0x96,0xe5] + vfmaddsub132pd {rz-sae}, %zmm21, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd (%rcx), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x40,0x96,0x21] + vfmaddsub132pd (%rcx), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd 291(%rax,%r14,8), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xa2,0xb5,0x40,0x96,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132pd 291(%rax,%r14,8), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd (%rcx){1to8}, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x50,0x96,0x21] + vfmaddsub132pd (%rcx){1to8}, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd 8128(%rdx), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x40,0x96,0x62,0x7f] + vfmaddsub132pd 8128(%rdx), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd 8192(%rdx), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x40,0x96,0xa2,0x00,0x20,0x00,0x00] + vfmaddsub132pd 8192(%rdx), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd -8192(%rdx), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x40,0x96,0x62,0x80] + vfmaddsub132pd -8192(%rdx), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd -8256(%rdx), %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x40,0x96,0xa2,0xc0,0xdf,0xff,0xff] + vfmaddsub132pd -8256(%rdx), %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd 1016(%rdx){1to8}, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x50,0x96,0x62,0x7f] + vfmaddsub132pd 1016(%rdx){1to8}, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd 1024(%rdx){1to8}, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x50,0x96,0xa2,0x00,0x04,0x00,0x00] + vfmaddsub132pd 1024(%rdx){1to8}, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd -1024(%rdx){1to8}, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x50,0x96,0x62,0x80] + vfmaddsub132pd -1024(%rdx){1to8}, %zmm25, %zmm20 + +// CHECK: vfmaddsub132pd -1032(%rdx){1to8}, %zmm25, %zmm20 +// CHECK: encoding: [0x62,0xe2,0xb5,0x50,0x96,0xa2,0xf8,0xfb,0xff,0xff] + vfmaddsub132pd -1032(%rdx){1to8}, %zmm25, %zmm20 + +// CHECK: vfmaddsub213ps %zmm28, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0x82,0x3d,0x40,0xa6,0xcc] + vfmaddsub213ps %zmm28, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps %zmm28, %zmm24, %zmm17 {%k6} +// CHECK: encoding: [0x62,0x82,0x3d,0x46,0xa6,0xcc] + vfmaddsub213ps %zmm28, %zmm24, %zmm17 {%k6} + +// CHECK: vfmaddsub213ps %zmm28, %zmm24, %zmm17 {%k6} {z} +// CHECK: encoding: [0x62,0x82,0x3d,0xc6,0xa6,0xcc] + vfmaddsub213ps %zmm28, %zmm24, %zmm17 {%k6} {z} + +// CHECK: vfmaddsub213ps {rn-sae}, %zmm28, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0x82,0x3d,0x10,0xa6,0xcc] + vfmaddsub213ps {rn-sae}, %zmm28, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps {ru-sae}, %zmm28, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0x82,0x3d,0x50,0xa6,0xcc] + vfmaddsub213ps {ru-sae}, %zmm28, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps {rd-sae}, %zmm28, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0x82,0x3d,0x30,0xa6,0xcc] + vfmaddsub213ps {rd-sae}, %zmm28, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps {rz-sae}, %zmm28, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0x82,0x3d,0x70,0xa6,0xcc] + vfmaddsub213ps {rz-sae}, %zmm28, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps (%rcx), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x40,0xa6,0x09] + vfmaddsub213ps (%rcx), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps 291(%rax,%r14,8), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xa2,0x3d,0x40,0xa6,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213ps 291(%rax,%r14,8), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps (%rcx){1to16}, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x50,0xa6,0x09] + vfmaddsub213ps (%rcx){1to16}, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps 8128(%rdx), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x40,0xa6,0x4a,0x7f] + vfmaddsub213ps 8128(%rdx), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps 8192(%rdx), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x40,0xa6,0x8a,0x00,0x20,0x00,0x00] + vfmaddsub213ps 8192(%rdx), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps -8192(%rdx), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x40,0xa6,0x4a,0x80] + vfmaddsub213ps -8192(%rdx), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps -8256(%rdx), %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x40,0xa6,0x8a,0xc0,0xdf,0xff,0xff] + vfmaddsub213ps -8256(%rdx), %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps 508(%rdx){1to16}, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x50,0xa6,0x4a,0x7f] + vfmaddsub213ps 508(%rdx){1to16}, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps 512(%rdx){1to16}, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x50,0xa6,0x8a,0x00,0x02,0x00,0x00] + vfmaddsub213ps 512(%rdx){1to16}, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps -512(%rdx){1to16}, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x50,0xa6,0x4a,0x80] + vfmaddsub213ps -512(%rdx){1to16}, %zmm24, %zmm17 + +// CHECK: vfmaddsub213ps -516(%rdx){1to16}, %zmm24, %zmm17 +// CHECK: encoding: [0x62,0xe2,0x3d,0x50,0xa6,0x8a,0xfc,0xfd,0xff,0xff] + vfmaddsub213ps -516(%rdx){1to16}, %zmm24, %zmm17 + +// CHECK: vfmaddsub213pd %zmm10, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x48,0xa6,0xd2] + vfmaddsub213pd %zmm10, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd %zmm10, %zmm6, %zmm26 {%k6} +// CHECK: encoding: [0x62,0x42,0xcd,0x4e,0xa6,0xd2] + vfmaddsub213pd %zmm10, %zmm6, %zmm26 {%k6} + +// CHECK: vfmaddsub213pd %zmm10, %zmm6, %zmm26 {%k6} {z} +// CHECK: encoding: [0x62,0x42,0xcd,0xce,0xa6,0xd2] + vfmaddsub213pd %zmm10, %zmm6, %zmm26 {%k6} {z} + +// CHECK: vfmaddsub213pd {rn-sae}, %zmm10, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x18,0xa6,0xd2] + vfmaddsub213pd {rn-sae}, %zmm10, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd {ru-sae}, %zmm10, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x58,0xa6,0xd2] + vfmaddsub213pd {ru-sae}, %zmm10, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd {rd-sae}, %zmm10, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x38,0xa6,0xd2] + vfmaddsub213pd {rd-sae}, %zmm10, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd {rz-sae}, %zmm10, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x42,0xcd,0x78,0xa6,0xd2] + vfmaddsub213pd {rz-sae}, %zmm10, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd (%rcx), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xa6,0x11] + vfmaddsub213pd (%rcx), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd 291(%rax,%r14,8), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x22,0xcd,0x48,0xa6,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213pd 291(%rax,%r14,8), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd (%rcx){1to8}, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xa6,0x11] + vfmaddsub213pd (%rcx){1to8}, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd 8128(%rdx), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xa6,0x52,0x7f] + vfmaddsub213pd 8128(%rdx), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd 8192(%rdx), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xa6,0x92,0x00,0x20,0x00,0x00] + vfmaddsub213pd 8192(%rdx), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd -8192(%rdx), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xa6,0x52,0x80] + vfmaddsub213pd -8192(%rdx), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd -8256(%rdx), %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x48,0xa6,0x92,0xc0,0xdf,0xff,0xff] + vfmaddsub213pd -8256(%rdx), %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd 1016(%rdx){1to8}, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xa6,0x52,0x7f] + vfmaddsub213pd 1016(%rdx){1to8}, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd 1024(%rdx){1to8}, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xa6,0x92,0x00,0x04,0x00,0x00] + vfmaddsub213pd 1024(%rdx){1to8}, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd -1024(%rdx){1to8}, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xa6,0x52,0x80] + vfmaddsub213pd -1024(%rdx){1to8}, %zmm6, %zmm26 + +// CHECK: vfmaddsub213pd -1032(%rdx){1to8}, %zmm6, %zmm26 +// CHECK: encoding: [0x62,0x62,0xcd,0x58,0xa6,0x92,0xf8,0xfb,0xff,0xff] + vfmaddsub213pd -1032(%rdx){1to8}, %zmm6, %zmm26 + +// CHECK: vfmaddsub231ps %zmm19, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x40,0xb6,0xfb] + vfmaddsub231ps %zmm19, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps %zmm19, %zmm21, %zmm15 {%k6} +// CHECK: encoding: [0x62,0x32,0x55,0x46,0xb6,0xfb] + vfmaddsub231ps %zmm19, %zmm21, %zmm15 {%k6} + +// CHECK: vfmaddsub231ps %zmm19, %zmm21, %zmm15 {%k6} {z} +// CHECK: encoding: [0x62,0x32,0x55,0xc6,0xb6,0xfb] + vfmaddsub231ps %zmm19, %zmm21, %zmm15 {%k6} {z} + +// CHECK: vfmaddsub231ps {rn-sae}, %zmm19, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x10,0xb6,0xfb] + vfmaddsub231ps {rn-sae}, %zmm19, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps {ru-sae}, %zmm19, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x50,0xb6,0xfb] + vfmaddsub231ps {ru-sae}, %zmm19, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps {rd-sae}, %zmm19, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x30,0xb6,0xfb] + vfmaddsub231ps {rd-sae}, %zmm19, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps {rz-sae}, %zmm19, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x70,0xb6,0xfb] + vfmaddsub231ps {rz-sae}, %zmm19, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps (%rcx), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x40,0xb6,0x39] + vfmaddsub231ps (%rcx), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps 291(%rax,%r14,8), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x32,0x55,0x40,0xb6,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231ps 291(%rax,%r14,8), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps (%rcx){1to16}, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x50,0xb6,0x39] + vfmaddsub231ps (%rcx){1to16}, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps 8128(%rdx), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x40,0xb6,0x7a,0x7f] + vfmaddsub231ps 8128(%rdx), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps 8192(%rdx), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x40,0xb6,0xba,0x00,0x20,0x00,0x00] + vfmaddsub231ps 8192(%rdx), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps -8192(%rdx), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x40,0xb6,0x7a,0x80] + vfmaddsub231ps -8192(%rdx), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps -8256(%rdx), %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x40,0xb6,0xba,0xc0,0xdf,0xff,0xff] + vfmaddsub231ps -8256(%rdx), %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps 508(%rdx){1to16}, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x50,0xb6,0x7a,0x7f] + vfmaddsub231ps 508(%rdx){1to16}, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps 512(%rdx){1to16}, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x50,0xb6,0xba,0x00,0x02,0x00,0x00] + vfmaddsub231ps 512(%rdx){1to16}, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps -512(%rdx){1to16}, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x50,0xb6,0x7a,0x80] + vfmaddsub231ps -512(%rdx){1to16}, %zmm21, %zmm15 + +// CHECK: vfmaddsub231ps -516(%rdx){1to16}, %zmm21, %zmm15 +// CHECK: encoding: [0x62,0x72,0x55,0x50,0xb6,0xba,0xfc,0xfd,0xff,0xff] + vfmaddsub231ps -516(%rdx){1to16}, %zmm21, %zmm15 + +// CHECK: vfmaddsub231pd %zmm24, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x12,0xa5,0x40,0xb6,0xc8] + vfmaddsub231pd %zmm24, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd %zmm24, %zmm27, %zmm9 {%k7} +// CHECK: encoding: [0x62,0x12,0xa5,0x47,0xb6,0xc8] + vfmaddsub231pd %zmm24, %zmm27, %zmm9 {%k7} + +// CHECK: vfmaddsub231pd %zmm24, %zmm27, %zmm9 {%k7} {z} +// CHECK: encoding: [0x62,0x12,0xa5,0xc7,0xb6,0xc8] + vfmaddsub231pd %zmm24, %zmm27, %zmm9 {%k7} {z} + +// CHECK: vfmaddsub231pd {rn-sae}, %zmm24, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x12,0xa5,0x10,0xb6,0xc8] + vfmaddsub231pd {rn-sae}, %zmm24, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd {ru-sae}, %zmm24, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x12,0xa5,0x50,0xb6,0xc8] + vfmaddsub231pd {ru-sae}, %zmm24, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd {rd-sae}, %zmm24, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x12,0xa5,0x30,0xb6,0xc8] + vfmaddsub231pd {rd-sae}, %zmm24, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd {rz-sae}, %zmm24, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x12,0xa5,0x70,0xb6,0xc8] + vfmaddsub231pd {rz-sae}, %zmm24, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd (%rcx), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x40,0xb6,0x09] + vfmaddsub231pd (%rcx), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd 291(%rax,%r14,8), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x32,0xa5,0x40,0xb6,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231pd 291(%rax,%r14,8), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd (%rcx){1to8}, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xb6,0x09] + vfmaddsub231pd (%rcx){1to8}, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd 8128(%rdx), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x40,0xb6,0x4a,0x7f] + vfmaddsub231pd 8128(%rdx), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd 8192(%rdx), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x40,0xb6,0x8a,0x00,0x20,0x00,0x00] + vfmaddsub231pd 8192(%rdx), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd -8192(%rdx), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x40,0xb6,0x4a,0x80] + vfmaddsub231pd -8192(%rdx), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd -8256(%rdx), %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x40,0xb6,0x8a,0xc0,0xdf,0xff,0xff] + vfmaddsub231pd -8256(%rdx), %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd 1016(%rdx){1to8}, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xb6,0x4a,0x7f] + vfmaddsub231pd 1016(%rdx){1to8}, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd 1024(%rdx){1to8}, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xb6,0x8a,0x00,0x04,0x00,0x00] + vfmaddsub231pd 1024(%rdx){1to8}, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd -1024(%rdx){1to8}, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xb6,0x4a,0x80] + vfmaddsub231pd -1024(%rdx){1to8}, %zmm27, %zmm9 + +// CHECK: vfmaddsub231pd -1032(%rdx){1to8}, %zmm27, %zmm9 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xb6,0x8a,0xf8,0xfb,0xff,0xff] + vfmaddsub231pd -1032(%rdx){1to8}, %zmm27, %zmm9 + +// CHECK: vfmsubadd132ps %zmm21, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x48,0x97,0xd5] + vfmsubadd132ps %zmm21, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps %zmm21, %zmm13, %zmm2 {%k7} +// CHECK: encoding: [0x62,0xb2,0x15,0x4f,0x97,0xd5] + vfmsubadd132ps %zmm21, %zmm13, %zmm2 {%k7} + +// CHECK: vfmsubadd132ps %zmm21, %zmm13, %zmm2 {%k7} {z} +// CHECK: encoding: [0x62,0xb2,0x15,0xcf,0x97,0xd5] + vfmsubadd132ps %zmm21, %zmm13, %zmm2 {%k7} {z} + +// CHECK: vfmsubadd132ps {rn-sae}, %zmm21, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x18,0x97,0xd5] + vfmsubadd132ps {rn-sae}, %zmm21, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps {ru-sae}, %zmm21, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x58,0x97,0xd5] + vfmsubadd132ps {ru-sae}, %zmm21, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps {rd-sae}, %zmm21, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x38,0x97,0xd5] + vfmsubadd132ps {rd-sae}, %zmm21, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps {rz-sae}, %zmm21, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x78,0x97,0xd5] + vfmsubadd132ps {rz-sae}, %zmm21, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps (%rcx), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x97,0x11] + vfmsubadd132ps (%rcx), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps 291(%rax,%r14,8), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xb2,0x15,0x48,0x97,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132ps 291(%rax,%r14,8), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps (%rcx){1to16}, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x97,0x11] + vfmsubadd132ps (%rcx){1to16}, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps 8128(%rdx), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x97,0x52,0x7f] + vfmsubadd132ps 8128(%rdx), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps 8192(%rdx), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x97,0x92,0x00,0x20,0x00,0x00] + vfmsubadd132ps 8192(%rdx), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps -8192(%rdx), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x97,0x52,0x80] + vfmsubadd132ps -8192(%rdx), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps -8256(%rdx), %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x48,0x97,0x92,0xc0,0xdf,0xff,0xff] + vfmsubadd132ps -8256(%rdx), %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps 508(%rdx){1to16}, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x97,0x52,0x7f] + vfmsubadd132ps 508(%rdx){1to16}, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps 512(%rdx){1to16}, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x97,0x92,0x00,0x02,0x00,0x00] + vfmsubadd132ps 512(%rdx){1to16}, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps -512(%rdx){1to16}, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x97,0x52,0x80] + vfmsubadd132ps -512(%rdx){1to16}, %zmm13, %zmm2 + +// CHECK: vfmsubadd132ps -516(%rdx){1to16}, %zmm13, %zmm2 +// CHECK: encoding: [0x62,0xf2,0x15,0x58,0x97,0x92,0xfc,0xfd,0xff,0xff] + vfmsubadd132ps -516(%rdx){1to16}, %zmm13, %zmm2 + +// CHECK: vfmsubadd132pd %zmm18, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x40,0x97,0xea] + vfmsubadd132pd %zmm18, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd %zmm18, %zmm28, %zmm21 {%k7} +// CHECK: encoding: [0x62,0xa2,0x9d,0x47,0x97,0xea] + vfmsubadd132pd %zmm18, %zmm28, %zmm21 {%k7} + +// CHECK: vfmsubadd132pd %zmm18, %zmm28, %zmm21 {%k7} {z} +// CHECK: encoding: [0x62,0xa2,0x9d,0xc7,0x97,0xea] + vfmsubadd132pd %zmm18, %zmm28, %zmm21 {%k7} {z} + +// CHECK: vfmsubadd132pd {rn-sae}, %zmm18, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x10,0x97,0xea] + vfmsubadd132pd {rn-sae}, %zmm18, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd {ru-sae}, %zmm18, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x50,0x97,0xea] + vfmsubadd132pd {ru-sae}, %zmm18, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd {rd-sae}, %zmm18, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x30,0x97,0xea] + vfmsubadd132pd {rd-sae}, %zmm18, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd {rz-sae}, %zmm18, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x70,0x97,0xea] + vfmsubadd132pd {rz-sae}, %zmm18, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd (%rcx), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x40,0x97,0x29] + vfmsubadd132pd (%rcx), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd 291(%rax,%r14,8), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x9d,0x40,0x97,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132pd 291(%rax,%r14,8), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd (%rcx){1to8}, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x50,0x97,0x29] + vfmsubadd132pd (%rcx){1to8}, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd 8128(%rdx), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x40,0x97,0x6a,0x7f] + vfmsubadd132pd 8128(%rdx), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd 8192(%rdx), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x40,0x97,0xaa,0x00,0x20,0x00,0x00] + vfmsubadd132pd 8192(%rdx), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd -8192(%rdx), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x40,0x97,0x6a,0x80] + vfmsubadd132pd -8192(%rdx), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd -8256(%rdx), %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x40,0x97,0xaa,0xc0,0xdf,0xff,0xff] + vfmsubadd132pd -8256(%rdx), %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd 1016(%rdx){1to8}, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x50,0x97,0x6a,0x7f] + vfmsubadd132pd 1016(%rdx){1to8}, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd 1024(%rdx){1to8}, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x50,0x97,0xaa,0x00,0x04,0x00,0x00] + vfmsubadd132pd 1024(%rdx){1to8}, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd -1024(%rdx){1to8}, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x50,0x97,0x6a,0x80] + vfmsubadd132pd -1024(%rdx){1to8}, %zmm28, %zmm21 + +// CHECK: vfmsubadd132pd -1032(%rdx){1to8}, %zmm28, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x9d,0x50,0x97,0xaa,0xf8,0xfb,0xff,0xff] + vfmsubadd132pd -1032(%rdx){1to8}, %zmm28, %zmm21 + +// CHECK: vfmsubadd213ps %zmm14, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x1d,0x48,0xa7,0xf6] + vfmsubadd213ps %zmm14, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps %zmm14, %zmm12, %zmm22 {%k6} +// CHECK: encoding: [0x62,0xc2,0x1d,0x4e,0xa7,0xf6] + vfmsubadd213ps %zmm14, %zmm12, %zmm22 {%k6} + +// CHECK: vfmsubadd213ps %zmm14, %zmm12, %zmm22 {%k6} {z} +// CHECK: encoding: [0x62,0xc2,0x1d,0xce,0xa7,0xf6] + vfmsubadd213ps %zmm14, %zmm12, %zmm22 {%k6} {z} + +// CHECK: vfmsubadd213ps {rn-sae}, %zmm14, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x1d,0x18,0xa7,0xf6] + vfmsubadd213ps {rn-sae}, %zmm14, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps {ru-sae}, %zmm14, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x1d,0x58,0xa7,0xf6] + vfmsubadd213ps {ru-sae}, %zmm14, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps {rd-sae}, %zmm14, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x1d,0x38,0xa7,0xf6] + vfmsubadd213ps {rd-sae}, %zmm14, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps {rz-sae}, %zmm14, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xc2,0x1d,0x78,0xa7,0xf6] + vfmsubadd213ps {rz-sae}, %zmm14, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps (%rcx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x48,0xa7,0x31] + vfmsubadd213ps (%rcx), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps 291(%rax,%r14,8), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xa2,0x1d,0x48,0xa7,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213ps 291(%rax,%r14,8), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps (%rcx){1to16}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x58,0xa7,0x31] + vfmsubadd213ps (%rcx){1to16}, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps 8128(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x48,0xa7,0x72,0x7f] + vfmsubadd213ps 8128(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps 8192(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x48,0xa7,0xb2,0x00,0x20,0x00,0x00] + vfmsubadd213ps 8192(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps -8192(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x48,0xa7,0x72,0x80] + vfmsubadd213ps -8192(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps -8256(%rdx), %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x48,0xa7,0xb2,0xc0,0xdf,0xff,0xff] + vfmsubadd213ps -8256(%rdx), %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps 508(%rdx){1to16}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x58,0xa7,0x72,0x7f] + vfmsubadd213ps 508(%rdx){1to16}, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps 512(%rdx){1to16}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x58,0xa7,0xb2,0x00,0x02,0x00,0x00] + vfmsubadd213ps 512(%rdx){1to16}, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps -512(%rdx){1to16}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x58,0xa7,0x72,0x80] + vfmsubadd213ps -512(%rdx){1to16}, %zmm12, %zmm22 + +// CHECK: vfmsubadd213ps -516(%rdx){1to16}, %zmm12, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x1d,0x58,0xa7,0xb2,0xfc,0xfd,0xff,0xff] + vfmsubadd213ps -516(%rdx){1to16}, %zmm12, %zmm22 + +// CHECK: vfmsubadd213pd %zmm2, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0xd2] + vfmsubadd213pd %zmm2, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd %zmm2, %zmm23, %zmm2 {%k6} +// CHECK: encoding: [0x62,0xf2,0xc5,0x46,0xa7,0xd2] + vfmsubadd213pd %zmm2, %zmm23, %zmm2 {%k6} + +// CHECK: vfmsubadd213pd %zmm2, %zmm23, %zmm2 {%k6} {z} +// CHECK: encoding: [0x62,0xf2,0xc5,0xc6,0xa7,0xd2] + vfmsubadd213pd %zmm2, %zmm23, %zmm2 {%k6} {z} + +// CHECK: vfmsubadd213pd {rn-sae}, %zmm2, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x10,0xa7,0xd2] + vfmsubadd213pd {rn-sae}, %zmm2, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd {ru-sae}, %zmm2, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0xd2] + vfmsubadd213pd {ru-sae}, %zmm2, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd {rd-sae}, %zmm2, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x30,0xa7,0xd2] + vfmsubadd213pd {rd-sae}, %zmm2, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd {rz-sae}, %zmm2, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x70,0xa7,0xd2] + vfmsubadd213pd {rz-sae}, %zmm2, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd (%rcx), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0x11] + vfmsubadd213pd (%rcx), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd 291(%rax,%r14,8), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xb2,0xc5,0x40,0xa7,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213pd 291(%rax,%r14,8), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd (%rcx){1to8}, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0x11] + vfmsubadd213pd (%rcx){1to8}, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd 8128(%rdx), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0x52,0x7f] + vfmsubadd213pd 8128(%rdx), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd 8192(%rdx), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0x92,0x00,0x20,0x00,0x00] + vfmsubadd213pd 8192(%rdx), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd -8192(%rdx), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0x52,0x80] + vfmsubadd213pd -8192(%rdx), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd -8256(%rdx), %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x40,0xa7,0x92,0xc0,0xdf,0xff,0xff] + vfmsubadd213pd -8256(%rdx), %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd 1016(%rdx){1to8}, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0x52,0x7f] + vfmsubadd213pd 1016(%rdx){1to8}, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd 1024(%rdx){1to8}, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0x92,0x00,0x04,0x00,0x00] + vfmsubadd213pd 1024(%rdx){1to8}, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd -1024(%rdx){1to8}, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0x52,0x80] + vfmsubadd213pd -1024(%rdx){1to8}, %zmm23, %zmm2 + +// CHECK: vfmsubadd213pd -1032(%rdx){1to8}, %zmm23, %zmm2 +// CHECK: encoding: [0x62,0xf2,0xc5,0x50,0xa7,0x92,0xf8,0xfb,0xff,0xff] + vfmsubadd213pd -1032(%rdx){1to8}, %zmm23, %zmm2 + +// CHECK: vfmsubadd231ps %zmm1, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0xc1] + vfmsubadd231ps %zmm1, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps %zmm1, %zmm19, %zmm8 {%k2} +// CHECK: encoding: [0x62,0x72,0x65,0x42,0xb7,0xc1] + vfmsubadd231ps %zmm1, %zmm19, %zmm8 {%k2} + +// CHECK: vfmsubadd231ps %zmm1, %zmm19, %zmm8 {%k2} {z} +// CHECK: encoding: [0x62,0x72,0x65,0xc2,0xb7,0xc1] + vfmsubadd231ps %zmm1, %zmm19, %zmm8 {%k2} {z} + +// CHECK: vfmsubadd231ps {rn-sae}, %zmm1, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x10,0xb7,0xc1] + vfmsubadd231ps {rn-sae}, %zmm1, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps {ru-sae}, %zmm1, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0xc1] + vfmsubadd231ps {ru-sae}, %zmm1, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps {rd-sae}, %zmm1, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x30,0xb7,0xc1] + vfmsubadd231ps {rd-sae}, %zmm1, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps {rz-sae}, %zmm1, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x70,0xb7,0xc1] + vfmsubadd231ps {rz-sae}, %zmm1, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps (%rcx), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0x01] + vfmsubadd231ps (%rcx), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps 291(%rax,%r14,8), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x32,0x65,0x40,0xb7,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231ps 291(%rax,%r14,8), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps (%rcx){1to16}, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0x01] + vfmsubadd231ps (%rcx){1to16}, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps 8128(%rdx), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0x42,0x7f] + vfmsubadd231ps 8128(%rdx), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps 8192(%rdx), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0x82,0x00,0x20,0x00,0x00] + vfmsubadd231ps 8192(%rdx), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps -8192(%rdx), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0x42,0x80] + vfmsubadd231ps -8192(%rdx), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps -8256(%rdx), %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x40,0xb7,0x82,0xc0,0xdf,0xff,0xff] + vfmsubadd231ps -8256(%rdx), %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps 508(%rdx){1to16}, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0x42,0x7f] + vfmsubadd231ps 508(%rdx){1to16}, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps 512(%rdx){1to16}, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0x82,0x00,0x02,0x00,0x00] + vfmsubadd231ps 512(%rdx){1to16}, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps -512(%rdx){1to16}, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0x42,0x80] + vfmsubadd231ps -512(%rdx){1to16}, %zmm19, %zmm8 + +// CHECK: vfmsubadd231ps -516(%rdx){1to16}, %zmm19, %zmm8 +// CHECK: encoding: [0x62,0x72,0x65,0x50,0xb7,0x82,0xfc,0xfd,0xff,0xff] + vfmsubadd231ps -516(%rdx){1to16}, %zmm19, %zmm8 + +// CHECK: vfmsubadd231pd %zmm21, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x40,0xb7,0xc5] + vfmsubadd231pd %zmm21, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd %zmm21, %zmm27, %zmm16 {%k2} +// CHECK: encoding: [0x62,0xa2,0xa5,0x42,0xb7,0xc5] + vfmsubadd231pd %zmm21, %zmm27, %zmm16 {%k2} + +// CHECK: vfmsubadd231pd %zmm21, %zmm27, %zmm16 {%k2} {z} +// CHECK: encoding: [0x62,0xa2,0xa5,0xc2,0xb7,0xc5] + vfmsubadd231pd %zmm21, %zmm27, %zmm16 {%k2} {z} + +// CHECK: vfmsubadd231pd {rn-sae}, %zmm21, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x10,0xb7,0xc5] + vfmsubadd231pd {rn-sae}, %zmm21, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd {ru-sae}, %zmm21, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x50,0xb7,0xc5] + vfmsubadd231pd {ru-sae}, %zmm21, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd {rd-sae}, %zmm21, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x30,0xb7,0xc5] + vfmsubadd231pd {rd-sae}, %zmm21, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd {rz-sae}, %zmm21, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x70,0xb7,0xc5] + vfmsubadd231pd {rz-sae}, %zmm21, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd (%rcx), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x40,0xb7,0x01] + vfmsubadd231pd (%rcx), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd 291(%rax,%r14,8), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xa2,0xa5,0x40,0xb7,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231pd 291(%rax,%r14,8), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd (%rcx){1to8}, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x50,0xb7,0x01] + vfmsubadd231pd (%rcx){1to8}, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd 8128(%rdx), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x40,0xb7,0x42,0x7f] + vfmsubadd231pd 8128(%rdx), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd 8192(%rdx), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x40,0xb7,0x82,0x00,0x20,0x00,0x00] + vfmsubadd231pd 8192(%rdx), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd -8192(%rdx), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x40,0xb7,0x42,0x80] + vfmsubadd231pd -8192(%rdx), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd -8256(%rdx), %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x40,0xb7,0x82,0xc0,0xdf,0xff,0xff] + vfmsubadd231pd -8256(%rdx), %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd 1016(%rdx){1to8}, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x50,0xb7,0x42,0x7f] + vfmsubadd231pd 1016(%rdx){1to8}, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd 1024(%rdx){1to8}, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x50,0xb7,0x82,0x00,0x04,0x00,0x00] + vfmsubadd231pd 1024(%rdx){1to8}, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd -1024(%rdx){1to8}, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x50,0xb7,0x42,0x80] + vfmsubadd231pd -1024(%rdx){1to8}, %zmm27, %zmm16 + +// CHECK: vfmsubadd231pd -1032(%rdx){1to8}, %zmm27, %zmm16 +// CHECK: encoding: [0x62,0xe2,0xa5,0x50,0xb7,0x82,0xf8,0xfb,0xff,0xff] + vfmsubadd231pd -1032(%rdx){1to8}, %zmm27, %zmm16 + +// CHECK: vfnmadd132ps %zmm10, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xc2,0x7d,0x40,0x9c,0xea] + vfnmadd132ps %zmm10, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps %zmm10, %zmm16, %zmm21 {%k5} +// CHECK: encoding: [0x62,0xc2,0x7d,0x45,0x9c,0xea] + vfnmadd132ps %zmm10, %zmm16, %zmm21 {%k5} + +// CHECK: vfnmadd132ps %zmm10, %zmm16, %zmm21 {%k5} {z} +// CHECK: encoding: [0x62,0xc2,0x7d,0xc5,0x9c,0xea] + vfnmadd132ps %zmm10, %zmm16, %zmm21 {%k5} {z} + +// CHECK: vfnmadd132ps {rn-sae}, %zmm10, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xc2,0x7d,0x10,0x9c,0xea] + vfnmadd132ps {rn-sae}, %zmm10, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps {ru-sae}, %zmm10, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xc2,0x7d,0x50,0x9c,0xea] + vfnmadd132ps {ru-sae}, %zmm10, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps {rd-sae}, %zmm10, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xc2,0x7d,0x30,0x9c,0xea] + vfnmadd132ps {rd-sae}, %zmm10, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps {rz-sae}, %zmm10, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xc2,0x7d,0x70,0x9c,0xea] + vfnmadd132ps {rz-sae}, %zmm10, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps (%rcx), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x40,0x9c,0x29] + vfnmadd132ps (%rcx), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps 291(%rax,%r14,8), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x7d,0x40,0x9c,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132ps 291(%rax,%r14,8), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps (%rcx){1to16}, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x50,0x9c,0x29] + vfnmadd132ps (%rcx){1to16}, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps 8128(%rdx), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x40,0x9c,0x6a,0x7f] + vfnmadd132ps 8128(%rdx), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps 8192(%rdx), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x40,0x9c,0xaa,0x00,0x20,0x00,0x00] + vfnmadd132ps 8192(%rdx), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps -8192(%rdx), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x40,0x9c,0x6a,0x80] + vfnmadd132ps -8192(%rdx), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps -8256(%rdx), %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x40,0x9c,0xaa,0xc0,0xdf,0xff,0xff] + vfnmadd132ps -8256(%rdx), %zmm16, %zmm21 + +// CHECK: vfnmadd132ps 508(%rdx){1to16}, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x50,0x9c,0x6a,0x7f] + vfnmadd132ps 508(%rdx){1to16}, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps 512(%rdx){1to16}, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x50,0x9c,0xaa,0x00,0x02,0x00,0x00] + vfnmadd132ps 512(%rdx){1to16}, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps -512(%rdx){1to16}, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x50,0x9c,0x6a,0x80] + vfnmadd132ps -512(%rdx){1to16}, %zmm16, %zmm21 + +// CHECK: vfnmadd132ps -516(%rdx){1to16}, %zmm16, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x7d,0x50,0x9c,0xaa,0xfc,0xfd,0xff,0xff] + vfnmadd132ps -516(%rdx){1to16}, %zmm16, %zmm21 + +// CHECK: vfnmadd132pd %zmm1, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0xe1] + vfnmadd132pd %zmm1, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd %zmm1, %zmm14, %zmm12 {%k7} +// CHECK: encoding: [0x62,0x72,0x8d,0x4f,0x9c,0xe1] + vfnmadd132pd %zmm1, %zmm14, %zmm12 {%k7} + +// CHECK: vfnmadd132pd %zmm1, %zmm14, %zmm12 {%k7} {z} +// CHECK: encoding: [0x62,0x72,0x8d,0xcf,0x9c,0xe1] + vfnmadd132pd %zmm1, %zmm14, %zmm12 {%k7} {z} + +// CHECK: vfnmadd132pd {rn-sae}, %zmm1, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x18,0x9c,0xe1] + vfnmadd132pd {rn-sae}, %zmm1, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd {ru-sae}, %zmm1, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0xe1] + vfnmadd132pd {ru-sae}, %zmm1, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd {rd-sae}, %zmm1, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x38,0x9c,0xe1] + vfnmadd132pd {rd-sae}, %zmm1, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd {rz-sae}, %zmm1, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x78,0x9c,0xe1] + vfnmadd132pd {rz-sae}, %zmm1, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd (%rcx), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0x21] + vfnmadd132pd (%rcx), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd 291(%rax,%r14,8), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x32,0x8d,0x48,0x9c,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132pd 291(%rax,%r14,8), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd (%rcx){1to8}, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0x21] + vfnmadd132pd (%rcx){1to8}, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd 8128(%rdx), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0x62,0x7f] + vfnmadd132pd 8128(%rdx), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd 8192(%rdx), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0xa2,0x00,0x20,0x00,0x00] + vfnmadd132pd 8192(%rdx), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd -8192(%rdx), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0x62,0x80] + vfnmadd132pd -8192(%rdx), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd -8256(%rdx), %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x48,0x9c,0xa2,0xc0,0xdf,0xff,0xff] + vfnmadd132pd -8256(%rdx), %zmm14, %zmm12 + +// CHECK: vfnmadd132pd 1016(%rdx){1to8}, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0x62,0x7f] + vfnmadd132pd 1016(%rdx){1to8}, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd 1024(%rdx){1to8}, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0xa2,0x00,0x04,0x00,0x00] + vfnmadd132pd 1024(%rdx){1to8}, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd -1024(%rdx){1to8}, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0x62,0x80] + vfnmadd132pd -1024(%rdx){1to8}, %zmm14, %zmm12 + +// CHECK: vfnmadd132pd -1032(%rdx){1to8}, %zmm14, %zmm12 +// CHECK: encoding: [0x62,0x72,0x8d,0x58,0x9c,0xa2,0xf8,0xfb,0xff,0xff] + vfnmadd132pd -1032(%rdx){1to8}, %zmm14, %zmm12 + +// CHECK: vfnmadd213ps %zmm6, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0xd6] + vfnmadd213ps %zmm6, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps %zmm6, %zmm10, %zmm26 {%k6} +// CHECK: encoding: [0x62,0x62,0x2d,0x4e,0xac,0xd6] + vfnmadd213ps %zmm6, %zmm10, %zmm26 {%k6} + +// CHECK: vfnmadd213ps %zmm6, %zmm10, %zmm26 {%k6} {z} +// CHECK: encoding: [0x62,0x62,0x2d,0xce,0xac,0xd6] + vfnmadd213ps %zmm6, %zmm10, %zmm26 {%k6} {z} + +// CHECK: vfnmadd213ps {rn-sae}, %zmm6, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x18,0xac,0xd6] + vfnmadd213ps {rn-sae}, %zmm6, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps {ru-sae}, %zmm6, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0xd6] + vfnmadd213ps {ru-sae}, %zmm6, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps {rd-sae}, %zmm6, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x38,0xac,0xd6] + vfnmadd213ps {rd-sae}, %zmm6, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps {rz-sae}, %zmm6, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x78,0xac,0xd6] + vfnmadd213ps {rz-sae}, %zmm6, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps (%rcx), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0x11] + vfnmadd213ps (%rcx), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps 291(%rax,%r14,8), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x22,0x2d,0x48,0xac,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213ps 291(%rax,%r14,8), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps (%rcx){1to16}, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0x11] + vfnmadd213ps (%rcx){1to16}, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps 8128(%rdx), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0x52,0x7f] + vfnmadd213ps 8128(%rdx), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps 8192(%rdx), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0x92,0x00,0x20,0x00,0x00] + vfnmadd213ps 8192(%rdx), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps -8192(%rdx), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0x52,0x80] + vfnmadd213ps -8192(%rdx), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps -8256(%rdx), %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x48,0xac,0x92,0xc0,0xdf,0xff,0xff] + vfnmadd213ps -8256(%rdx), %zmm10, %zmm26 + +// CHECK: vfnmadd213ps 508(%rdx){1to16}, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0x52,0x7f] + vfnmadd213ps 508(%rdx){1to16}, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps 512(%rdx){1to16}, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0x92,0x00,0x02,0x00,0x00] + vfnmadd213ps 512(%rdx){1to16}, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps -512(%rdx){1to16}, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0x52,0x80] + vfnmadd213ps -512(%rdx){1to16}, %zmm10, %zmm26 + +// CHECK: vfnmadd213ps -516(%rdx){1to16}, %zmm10, %zmm26 +// CHECK: encoding: [0x62,0x62,0x2d,0x58,0xac,0x92,0xfc,0xfd,0xff,0xff] + vfnmadd213ps -516(%rdx){1to16}, %zmm10, %zmm26 + +// CHECK: vfnmadd213pd %zmm9, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xc2,0xfd,0x40,0xac,0xc9] + vfnmadd213pd %zmm9, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd %zmm9, %zmm16, %zmm17 {%k4} +// CHECK: encoding: [0x62,0xc2,0xfd,0x44,0xac,0xc9] + vfnmadd213pd %zmm9, %zmm16, %zmm17 {%k4} + +// CHECK: vfnmadd213pd %zmm9, %zmm16, %zmm17 {%k4} {z} +// CHECK: encoding: [0x62,0xc2,0xfd,0xc4,0xac,0xc9] + vfnmadd213pd %zmm9, %zmm16, %zmm17 {%k4} {z} + +// CHECK: vfnmadd213pd {rn-sae}, %zmm9, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xc2,0xfd,0x10,0xac,0xc9] + vfnmadd213pd {rn-sae}, %zmm9, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd {ru-sae}, %zmm9, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xc2,0xfd,0x50,0xac,0xc9] + vfnmadd213pd {ru-sae}, %zmm9, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd {rd-sae}, %zmm9, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xc2,0xfd,0x30,0xac,0xc9] + vfnmadd213pd {rd-sae}, %zmm9, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd {rz-sae}, %zmm9, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xc2,0xfd,0x70,0xac,0xc9] + vfnmadd213pd {rz-sae}, %zmm9, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd (%rcx), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xac,0x09] + vfnmadd213pd (%rcx), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd 291(%rax,%r14,8), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xa2,0xfd,0x40,0xac,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213pd 291(%rax,%r14,8), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd (%rcx){1to8}, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xac,0x09] + vfnmadd213pd (%rcx){1to8}, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd 8128(%rdx), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xac,0x4a,0x7f] + vfnmadd213pd 8128(%rdx), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd 8192(%rdx), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xac,0x8a,0x00,0x20,0x00,0x00] + vfnmadd213pd 8192(%rdx), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd -8192(%rdx), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xac,0x4a,0x80] + vfnmadd213pd -8192(%rdx), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd -8256(%rdx), %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x40,0xac,0x8a,0xc0,0xdf,0xff,0xff] + vfnmadd213pd -8256(%rdx), %zmm16, %zmm17 + +// CHECK: vfnmadd213pd 1016(%rdx){1to8}, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xac,0x4a,0x7f] + vfnmadd213pd 1016(%rdx){1to8}, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd 1024(%rdx){1to8}, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xac,0x8a,0x00,0x04,0x00,0x00] + vfnmadd213pd 1024(%rdx){1to8}, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd -1024(%rdx){1to8}, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xac,0x4a,0x80] + vfnmadd213pd -1024(%rdx){1to8}, %zmm16, %zmm17 + +// CHECK: vfnmadd213pd -1032(%rdx){1to8}, %zmm16, %zmm17 +// CHECK: encoding: [0x62,0xe2,0xfd,0x50,0xac,0x8a,0xf8,0xfb,0xff,0xff] + vfnmadd213pd -1032(%rdx){1to8}, %zmm16, %zmm17 + +// CHECK: vfnmadd231ps %zmm24, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x12,0x45,0x48,0xbc,0xf0] + vfnmadd231ps %zmm24, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps %zmm24, %zmm7, %zmm14 {%k5} +// CHECK: encoding: [0x62,0x12,0x45,0x4d,0xbc,0xf0] + vfnmadd231ps %zmm24, %zmm7, %zmm14 {%k5} + +// CHECK: vfnmadd231ps %zmm24, %zmm7, %zmm14 {%k5} {z} +// CHECK: encoding: [0x62,0x12,0x45,0xcd,0xbc,0xf0] + vfnmadd231ps %zmm24, %zmm7, %zmm14 {%k5} {z} + +// CHECK: vfnmadd231ps {rn-sae}, %zmm24, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x12,0x45,0x18,0xbc,0xf0] + vfnmadd231ps {rn-sae}, %zmm24, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps {ru-sae}, %zmm24, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x12,0x45,0x58,0xbc,0xf0] + vfnmadd231ps {ru-sae}, %zmm24, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps {rd-sae}, %zmm24, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x12,0x45,0x38,0xbc,0xf0] + vfnmadd231ps {rd-sae}, %zmm24, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps {rz-sae}, %zmm24, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x12,0x45,0x78,0xbc,0xf0] + vfnmadd231ps {rz-sae}, %zmm24, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps (%rcx), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x48,0xbc,0x31] + vfnmadd231ps (%rcx), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps 291(%rax,%r14,8), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x32,0x45,0x48,0xbc,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231ps 291(%rax,%r14,8), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps (%rcx){1to16}, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x58,0xbc,0x31] + vfnmadd231ps (%rcx){1to16}, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps 8128(%rdx), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x48,0xbc,0x72,0x7f] + vfnmadd231ps 8128(%rdx), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps 8192(%rdx), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x48,0xbc,0xb2,0x00,0x20,0x00,0x00] + vfnmadd231ps 8192(%rdx), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps -8192(%rdx), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x48,0xbc,0x72,0x80] + vfnmadd231ps -8192(%rdx), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps -8256(%rdx), %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x48,0xbc,0xb2,0xc0,0xdf,0xff,0xff] + vfnmadd231ps -8256(%rdx), %zmm7, %zmm14 + +// CHECK: vfnmadd231ps 508(%rdx){1to16}, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x58,0xbc,0x72,0x7f] + vfnmadd231ps 508(%rdx){1to16}, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps 512(%rdx){1to16}, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x58,0xbc,0xb2,0x00,0x02,0x00,0x00] + vfnmadd231ps 512(%rdx){1to16}, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps -512(%rdx){1to16}, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x58,0xbc,0x72,0x80] + vfnmadd231ps -512(%rdx){1to16}, %zmm7, %zmm14 + +// CHECK: vfnmadd231ps -516(%rdx){1to16}, %zmm7, %zmm14 +// CHECK: encoding: [0x62,0x72,0x45,0x58,0xbc,0xb2,0xfc,0xfd,0xff,0xff] + vfnmadd231ps -516(%rdx){1to16}, %zmm7, %zmm14 + +// CHECK: vfnmadd231pd %zmm16, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x48,0xbc,0xe0] + vfnmadd231pd %zmm16, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd %zmm16, %zmm11, %zmm12 {%k6} +// CHECK: encoding: [0x62,0x32,0xa5,0x4e,0xbc,0xe0] + vfnmadd231pd %zmm16, %zmm11, %zmm12 {%k6} + +// CHECK: vfnmadd231pd %zmm16, %zmm11, %zmm12 {%k6} {z} +// CHECK: encoding: [0x62,0x32,0xa5,0xce,0xbc,0xe0] + vfnmadd231pd %zmm16, %zmm11, %zmm12 {%k6} {z} + +// CHECK: vfnmadd231pd {rn-sae}, %zmm16, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x18,0xbc,0xe0] + vfnmadd231pd {rn-sae}, %zmm16, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd {ru-sae}, %zmm16, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x58,0xbc,0xe0] + vfnmadd231pd {ru-sae}, %zmm16, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd {rd-sae}, %zmm16, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x38,0xbc,0xe0] + vfnmadd231pd {rd-sae}, %zmm16, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd {rz-sae}, %zmm16, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x78,0xbc,0xe0] + vfnmadd231pd {rz-sae}, %zmm16, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd (%rcx), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x48,0xbc,0x21] + vfnmadd231pd (%rcx), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd 291(%rax,%r14,8), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x32,0xa5,0x48,0xbc,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231pd 291(%rax,%r14,8), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd (%rcx){1to8}, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x58,0xbc,0x21] + vfnmadd231pd (%rcx){1to8}, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd 8128(%rdx), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x48,0xbc,0x62,0x7f] + vfnmadd231pd 8128(%rdx), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd 8192(%rdx), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x48,0xbc,0xa2,0x00,0x20,0x00,0x00] + vfnmadd231pd 8192(%rdx), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd -8192(%rdx), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x48,0xbc,0x62,0x80] + vfnmadd231pd -8192(%rdx), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd -8256(%rdx), %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x48,0xbc,0xa2,0xc0,0xdf,0xff,0xff] + vfnmadd231pd -8256(%rdx), %zmm11, %zmm12 + +// CHECK: vfnmadd231pd 1016(%rdx){1to8}, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x58,0xbc,0x62,0x7f] + vfnmadd231pd 1016(%rdx){1to8}, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd 1024(%rdx){1to8}, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x58,0xbc,0xa2,0x00,0x04,0x00,0x00] + vfnmadd231pd 1024(%rdx){1to8}, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd -1024(%rdx){1to8}, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x58,0xbc,0x62,0x80] + vfnmadd231pd -1024(%rdx){1to8}, %zmm11, %zmm12 + +// CHECK: vfnmadd231pd -1032(%rdx){1to8}, %zmm11, %zmm12 +// CHECK: encoding: [0x62,0x72,0xa5,0x58,0xbc,0xa2,0xf8,0xfb,0xff,0xff] + vfnmadd231pd -1032(%rdx){1to8}, %zmm11, %zmm12 + +// CHECK: vfnmsub132ps %zmm6, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0xe6] + vfnmsub132ps %zmm6, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps %zmm6, %zmm18, %zmm4 {%k2} +// CHECK: encoding: [0x62,0xf2,0x6d,0x42,0x9e,0xe6] + vfnmsub132ps %zmm6, %zmm18, %zmm4 {%k2} + +// CHECK: vfnmsub132ps %zmm6, %zmm18, %zmm4 {%k2} {z} +// CHECK: encoding: [0x62,0xf2,0x6d,0xc2,0x9e,0xe6] + vfnmsub132ps %zmm6, %zmm18, %zmm4 {%k2} {z} + +// CHECK: vfnmsub132ps {rn-sae}, %zmm6, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x10,0x9e,0xe6] + vfnmsub132ps {rn-sae}, %zmm6, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps {ru-sae}, %zmm6, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0xe6] + vfnmsub132ps {ru-sae}, %zmm6, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps {rd-sae}, %zmm6, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x30,0x9e,0xe6] + vfnmsub132ps {rd-sae}, %zmm6, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps {rz-sae}, %zmm6, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x70,0x9e,0xe6] + vfnmsub132ps {rz-sae}, %zmm6, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps (%rcx), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0x21] + vfnmsub132ps (%rcx), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps 291(%rax,%r14,8), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xb2,0x6d,0x40,0x9e,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132ps 291(%rax,%r14,8), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps (%rcx){1to16}, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0x21] + vfnmsub132ps (%rcx){1to16}, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps 8128(%rdx), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0x62,0x7f] + vfnmsub132ps 8128(%rdx), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps 8192(%rdx), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0xa2,0x00,0x20,0x00,0x00] + vfnmsub132ps 8192(%rdx), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps -8192(%rdx), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0x62,0x80] + vfnmsub132ps -8192(%rdx), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps -8256(%rdx), %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x40,0x9e,0xa2,0xc0,0xdf,0xff,0xff] + vfnmsub132ps -8256(%rdx), %zmm18, %zmm4 + +// CHECK: vfnmsub132ps 508(%rdx){1to16}, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0x62,0x7f] + vfnmsub132ps 508(%rdx){1to16}, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps 512(%rdx){1to16}, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0xa2,0x00,0x02,0x00,0x00] + vfnmsub132ps 512(%rdx){1to16}, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps -512(%rdx){1to16}, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0x62,0x80] + vfnmsub132ps -512(%rdx){1to16}, %zmm18, %zmm4 + +// CHECK: vfnmsub132ps -516(%rdx){1to16}, %zmm18, %zmm4 +// CHECK: encoding: [0x62,0xf2,0x6d,0x50,0x9e,0xa2,0xfc,0xfd,0xff,0xff] + vfnmsub132ps -516(%rdx){1to16}, %zmm18, %zmm4 + +// CHECK: vfnmsub132pd %zmm6, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0xe6] + vfnmsub132pd %zmm6, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd %zmm6, %zmm5, %zmm28 {%k2} +// CHECK: encoding: [0x62,0x62,0xd5,0x4a,0x9e,0xe6] + vfnmsub132pd %zmm6, %zmm5, %zmm28 {%k2} + +// CHECK: vfnmsub132pd %zmm6, %zmm5, %zmm28 {%k2} {z} +// CHECK: encoding: [0x62,0x62,0xd5,0xca,0x9e,0xe6] + vfnmsub132pd %zmm6, %zmm5, %zmm28 {%k2} {z} + +// CHECK: vfnmsub132pd {rn-sae}, %zmm6, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x18,0x9e,0xe6] + vfnmsub132pd {rn-sae}, %zmm6, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd {ru-sae}, %zmm6, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0xe6] + vfnmsub132pd {ru-sae}, %zmm6, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd {rd-sae}, %zmm6, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x38,0x9e,0xe6] + vfnmsub132pd {rd-sae}, %zmm6, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd {rz-sae}, %zmm6, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x78,0x9e,0xe6] + vfnmsub132pd {rz-sae}, %zmm6, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd (%rcx), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0x21] + vfnmsub132pd (%rcx), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd 291(%rax,%r14,8), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x22,0xd5,0x48,0x9e,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132pd 291(%rax,%r14,8), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd (%rcx){1to8}, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0x21] + vfnmsub132pd (%rcx){1to8}, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd 8128(%rdx), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0x62,0x7f] + vfnmsub132pd 8128(%rdx), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd 8192(%rdx), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0xa2,0x00,0x20,0x00,0x00] + vfnmsub132pd 8192(%rdx), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd -8192(%rdx), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0x62,0x80] + vfnmsub132pd -8192(%rdx), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd -8256(%rdx), %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x48,0x9e,0xa2,0xc0,0xdf,0xff,0xff] + vfnmsub132pd -8256(%rdx), %zmm5, %zmm28 + +// CHECK: vfnmsub132pd 1016(%rdx){1to8}, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0x62,0x7f] + vfnmsub132pd 1016(%rdx){1to8}, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd 1024(%rdx){1to8}, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0xa2,0x00,0x04,0x00,0x00] + vfnmsub132pd 1024(%rdx){1to8}, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd -1024(%rdx){1to8}, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0x62,0x80] + vfnmsub132pd -1024(%rdx){1to8}, %zmm5, %zmm28 + +// CHECK: vfnmsub132pd -1032(%rdx){1to8}, %zmm5, %zmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x58,0x9e,0xa2,0xf8,0xfb,0xff,0xff] + vfnmsub132pd -1032(%rdx){1to8}, %zmm5, %zmm28 + +// CHECK: vfnmsub213ps %zmm2, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0xea] + vfnmsub213ps %zmm2, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps %zmm2, %zmm13, %zmm21 {%k3} +// CHECK: encoding: [0x62,0xe2,0x15,0x4b,0xae,0xea] + vfnmsub213ps %zmm2, %zmm13, %zmm21 {%k3} + +// CHECK: vfnmsub213ps %zmm2, %zmm13, %zmm21 {%k3} {z} +// CHECK: encoding: [0x62,0xe2,0x15,0xcb,0xae,0xea] + vfnmsub213ps %zmm2, %zmm13, %zmm21 {%k3} {z} + +// CHECK: vfnmsub213ps {rn-sae}, %zmm2, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x18,0xae,0xea] + vfnmsub213ps {rn-sae}, %zmm2, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps {ru-sae}, %zmm2, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0xea] + vfnmsub213ps {ru-sae}, %zmm2, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps {rd-sae}, %zmm2, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x38,0xae,0xea] + vfnmsub213ps {rd-sae}, %zmm2, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps {rz-sae}, %zmm2, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x78,0xae,0xea] + vfnmsub213ps {rz-sae}, %zmm2, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps (%rcx), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0x29] + vfnmsub213ps (%rcx), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps 291(%rax,%r14,8), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xa2,0x15,0x48,0xae,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213ps 291(%rax,%r14,8), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps (%rcx){1to16}, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0x29] + vfnmsub213ps (%rcx){1to16}, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps 8128(%rdx), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0x6a,0x7f] + vfnmsub213ps 8128(%rdx), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps 8192(%rdx), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0xaa,0x00,0x20,0x00,0x00] + vfnmsub213ps 8192(%rdx), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps -8192(%rdx), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0x6a,0x80] + vfnmsub213ps -8192(%rdx), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps -8256(%rdx), %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x48,0xae,0xaa,0xc0,0xdf,0xff,0xff] + vfnmsub213ps -8256(%rdx), %zmm13, %zmm21 + +// CHECK: vfnmsub213ps 508(%rdx){1to16}, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0x6a,0x7f] + vfnmsub213ps 508(%rdx){1to16}, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps 512(%rdx){1to16}, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0xaa,0x00,0x02,0x00,0x00] + vfnmsub213ps 512(%rdx){1to16}, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps -512(%rdx){1to16}, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0x6a,0x80] + vfnmsub213ps -512(%rdx){1to16}, %zmm13, %zmm21 + +// CHECK: vfnmsub213ps -516(%rdx){1to16}, %zmm13, %zmm21 +// CHECK: encoding: [0x62,0xe2,0x15,0x58,0xae,0xaa,0xfc,0xfd,0xff,0xff] + vfnmsub213ps -516(%rdx){1to16}, %zmm13, %zmm21 + +// CHECK: vfnmsub213pd %zmm11, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xed,0x40,0xae,0xfb] + vfnmsub213pd %zmm11, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd %zmm11, %zmm18, %zmm23 {%k2} +// CHECK: encoding: [0x62,0xc2,0xed,0x42,0xae,0xfb] + vfnmsub213pd %zmm11, %zmm18, %zmm23 {%k2} + +// CHECK: vfnmsub213pd %zmm11, %zmm18, %zmm23 {%k2} {z} +// CHECK: encoding: [0x62,0xc2,0xed,0xc2,0xae,0xfb] + vfnmsub213pd %zmm11, %zmm18, %zmm23 {%k2} {z} + +// CHECK: vfnmsub213pd {rn-sae}, %zmm11, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xed,0x10,0xae,0xfb] + vfnmsub213pd {rn-sae}, %zmm11, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd {ru-sae}, %zmm11, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xed,0x50,0xae,0xfb] + vfnmsub213pd {ru-sae}, %zmm11, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd {rd-sae}, %zmm11, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xed,0x30,0xae,0xfb] + vfnmsub213pd {rd-sae}, %zmm11, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd {rz-sae}, %zmm11, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xed,0x70,0xae,0xfb] + vfnmsub213pd {rz-sae}, %zmm11, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd (%rcx), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x40,0xae,0x39] + vfnmsub213pd (%rcx), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd 291(%rax,%r14,8), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xa2,0xed,0x40,0xae,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213pd 291(%rax,%r14,8), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd (%rcx){1to8}, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x50,0xae,0x39] + vfnmsub213pd (%rcx){1to8}, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd 8128(%rdx), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x40,0xae,0x7a,0x7f] + vfnmsub213pd 8128(%rdx), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd 8192(%rdx), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x40,0xae,0xba,0x00,0x20,0x00,0x00] + vfnmsub213pd 8192(%rdx), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd -8192(%rdx), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x40,0xae,0x7a,0x80] + vfnmsub213pd -8192(%rdx), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd -8256(%rdx), %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x40,0xae,0xba,0xc0,0xdf,0xff,0xff] + vfnmsub213pd -8256(%rdx), %zmm18, %zmm23 + +// CHECK: vfnmsub213pd 1016(%rdx){1to8}, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x50,0xae,0x7a,0x7f] + vfnmsub213pd 1016(%rdx){1to8}, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd 1024(%rdx){1to8}, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x50,0xae,0xba,0x00,0x04,0x00,0x00] + vfnmsub213pd 1024(%rdx){1to8}, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd -1024(%rdx){1to8}, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x50,0xae,0x7a,0x80] + vfnmsub213pd -1024(%rdx){1to8}, %zmm18, %zmm23 + +// CHECK: vfnmsub213pd -1032(%rdx){1to8}, %zmm18, %zmm23 +// CHECK: encoding: [0x62,0xe2,0xed,0x50,0xae,0xba,0xf8,0xfb,0xff,0xff] + vfnmsub213pd -1032(%rdx){1to8}, %zmm18, %zmm23 + +// CHECK: vfnmsub231ps %zmm13, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x52,0x4d,0x48,0xbe,0xc5] + vfnmsub231ps %zmm13, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps %zmm13, %zmm6, %zmm8 {%k2} +// CHECK: encoding: [0x62,0x52,0x4d,0x4a,0xbe,0xc5] + vfnmsub231ps %zmm13, %zmm6, %zmm8 {%k2} + +// CHECK: vfnmsub231ps %zmm13, %zmm6, %zmm8 {%k2} {z} +// CHECK: encoding: [0x62,0x52,0x4d,0xca,0xbe,0xc5] + vfnmsub231ps %zmm13, %zmm6, %zmm8 {%k2} {z} + +// CHECK: vfnmsub231ps {rn-sae}, %zmm13, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x52,0x4d,0x18,0xbe,0xc5] + vfnmsub231ps {rn-sae}, %zmm13, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps {ru-sae}, %zmm13, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x52,0x4d,0x58,0xbe,0xc5] + vfnmsub231ps {ru-sae}, %zmm13, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps {rd-sae}, %zmm13, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x52,0x4d,0x38,0xbe,0xc5] + vfnmsub231ps {rd-sae}, %zmm13, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps {rz-sae}, %zmm13, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x52,0x4d,0x78,0xbe,0xc5] + vfnmsub231ps {rz-sae}, %zmm13, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps (%rcx), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x48,0xbe,0x01] + vfnmsub231ps (%rcx), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps 291(%rax,%r14,8), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x32,0x4d,0x48,0xbe,0x84,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231ps 291(%rax,%r14,8), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps (%rcx){1to16}, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x58,0xbe,0x01] + vfnmsub231ps (%rcx){1to16}, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps 8128(%rdx), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x48,0xbe,0x42,0x7f] + vfnmsub231ps 8128(%rdx), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps 8192(%rdx), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x48,0xbe,0x82,0x00,0x20,0x00,0x00] + vfnmsub231ps 8192(%rdx), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps -8192(%rdx), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x48,0xbe,0x42,0x80] + vfnmsub231ps -8192(%rdx), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps -8256(%rdx), %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x48,0xbe,0x82,0xc0,0xdf,0xff,0xff] + vfnmsub231ps -8256(%rdx), %zmm6, %zmm8 + +// CHECK: vfnmsub231ps 508(%rdx){1to16}, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x58,0xbe,0x42,0x7f] + vfnmsub231ps 508(%rdx){1to16}, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps 512(%rdx){1to16}, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x58,0xbe,0x82,0x00,0x02,0x00,0x00] + vfnmsub231ps 512(%rdx){1to16}, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps -512(%rdx){1to16}, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x58,0xbe,0x42,0x80] + vfnmsub231ps -512(%rdx){1to16}, %zmm6, %zmm8 + +// CHECK: vfnmsub231ps -516(%rdx){1to16}, %zmm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x4d,0x58,0xbe,0x82,0xfc,0xfd,0xff,0xff] + vfnmsub231ps -516(%rdx){1to16}, %zmm6, %zmm8 + +// CHECK: vfnmsub231pd %zmm24, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x48,0xbe,0xe8] + vfnmsub231pd %zmm24, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd %zmm24, %zmm4, %zmm29 {%k7} +// CHECK: encoding: [0x62,0x02,0xdd,0x4f,0xbe,0xe8] + vfnmsub231pd %zmm24, %zmm4, %zmm29 {%k7} + +// CHECK: vfnmsub231pd %zmm24, %zmm4, %zmm29 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0xdd,0xcf,0xbe,0xe8] + vfnmsub231pd %zmm24, %zmm4, %zmm29 {%k7} {z} + +// CHECK: vfnmsub231pd {rn-sae}, %zmm24, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x18,0xbe,0xe8] + vfnmsub231pd {rn-sae}, %zmm24, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd {ru-sae}, %zmm24, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x58,0xbe,0xe8] + vfnmsub231pd {ru-sae}, %zmm24, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd {rd-sae}, %zmm24, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x38,0xbe,0xe8] + vfnmsub231pd {rd-sae}, %zmm24, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd {rz-sae}, %zmm24, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x78,0xbe,0xe8] + vfnmsub231pd {rz-sae}, %zmm24, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd (%rcx), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x48,0xbe,0x29] + vfnmsub231pd (%rcx), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd 291(%rax,%r14,8), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x22,0xdd,0x48,0xbe,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231pd 291(%rax,%r14,8), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd (%rcx){1to8}, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x58,0xbe,0x29] + vfnmsub231pd (%rcx){1to8}, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd 8128(%rdx), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x48,0xbe,0x6a,0x7f] + vfnmsub231pd 8128(%rdx), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd 8192(%rdx), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x48,0xbe,0xaa,0x00,0x20,0x00,0x00] + vfnmsub231pd 8192(%rdx), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd -8192(%rdx), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x48,0xbe,0x6a,0x80] + vfnmsub231pd -8192(%rdx), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd -8256(%rdx), %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x48,0xbe,0xaa,0xc0,0xdf,0xff,0xff] + vfnmsub231pd -8256(%rdx), %zmm4, %zmm29 + +// CHECK: vfnmsub231pd 1016(%rdx){1to8}, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x58,0xbe,0x6a,0x7f] + vfnmsub231pd 1016(%rdx){1to8}, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd 1024(%rdx){1to8}, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x58,0xbe,0xaa,0x00,0x04,0x00,0x00] + vfnmsub231pd 1024(%rdx){1to8}, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd -1024(%rdx){1to8}, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x58,0xbe,0x6a,0x80] + vfnmsub231pd -1024(%rdx){1to8}, %zmm4, %zmm29 + +// CHECK: vfnmsub231pd -1032(%rdx){1to8}, %zmm4, %zmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x58,0xbe,0xaa,0xf8,0xfb,0xff,0xff] + vfnmsub231pd -1032(%rdx){1to8}, %zmm4, %zmm29 + + +// CHECK: vfmadd231ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x1d,0xc3,0xb8,0x9a,0x00,0x20,0x00,0x00] + vfmadd231ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd231ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x1d,0x93,0xb8,0xd9] + vfmadd231ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd231ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x5d,0xd3,0xb8,0x82,0xf8,0xfb,0xff,0xff] + vfmadd231ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} + +// CHECK: vfmadd231pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x9d,0xc3,0xb8,0x9a,0x00,0x20,0x00,0x00] + vfmadd231pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd231pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x9d,0x93,0xb8,0xd9] + vfmadd231pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd231pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0xdd,0xd3,0xb8,0x82,0xf8,0xfb,0xff,0xff] + vfmadd231pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} + +// CHECK: vfmadd213ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x1d,0xc3,0xa8,0x9a,0x00,0x20,0x00,0x00] + vfmadd213ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd213ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x1d,0x93,0xa8,0xd9] + vfmadd213ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd213ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x5d,0xd3,0xa8,0x82,0xf8,0xfb,0xff,0xff] + vfmadd213ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} + +// CHECK: vfmadd213pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x9d,0xc3,0xa8,0x9a,0x00,0x20,0x00,0x00] + vfmadd213pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd213pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x9d,0x93,0xa8,0xd9] + vfmadd213pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd213pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0xdd,0xd3,0xa8,0x82,0xf8,0xfb,0xff,0xff] + vfmadd213pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} + +// CHECK: vfmadd132ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x1d,0xc3,0x98,0x9a,0x00,0x20,0x00,0x00] + vfmadd132ps 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd132ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x1d,0x93,0x98,0xd9] + vfmadd132ps {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd132ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x5d,0xd3,0x98,0x82,0xf8,0xfb,0xff,0xff] + vfmadd132ps -1032(%rdx){1to16}, %zmm20, %zmm24 {%k3} {z} + +// CHECK: vfmadd132pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0x9d,0xc3,0x98,0x9a,0x00,0x20,0x00,0x00] + vfmadd132pd 8192(%rdx), %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd132pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x9d,0x93,0x98,0xd9] + vfmadd132pd {rn-sae}, %zmm25, %zmm28, %zmm27 {%k3} {z} + +// CHECK: vfmadd132pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x62,0xdd,0xd3,0x98,0x82,0xf8,0xfb,0xff,0xff] + vfmadd132pd -1032(%rdx){1to8}, %zmm20, %zmm24 {%k3} {z} + // CHECK: vpermi2d %zmm4, %zmm28, %zmm10 // CHECK: encoding: [0x62,0x72,0x1d,0x40,0x76,0xd4] vpermi2d %zmm4, %zmm28, %zmm10 @@ -9514,3 +12179,1786 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2 // CHECK: encoding: [0x62,0xe2,0xd5,0x58,0x77,0xa2,0xf8,0xfb,0xff,0xff] vpermi2pd -1032(%rdx){1to8}, %zmm5, %zmm20 +// CHECK: vcompresspd %zmm9, (%rcx) +// CHECK: encoding: [0x62,0x72,0xfd,0x48,0x8a,0x09] + vcompresspd %zmm9, (%rcx) + +// CHECK: vcompresspd %zmm9, (%rcx) {%k4} +// CHECK: encoding: [0x62,0x72,0xfd,0x4c,0x8a,0x09] + vcompresspd %zmm9, (%rcx) {%k4} + +// CHECK: vcompresspd %zmm9, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x32,0xfd,0x48,0x8a,0x8c,0xf0,0x23,0x01,0x00,0x00] + vcompresspd %zmm9, 291(%rax,%r14,8) + +// CHECK: vcompresspd %zmm9, 1016(%rdx) +// CHECK: encoding: [0x62,0x72,0xfd,0x48,0x8a,0x4a,0x7f] + vcompresspd %zmm9, 1016(%rdx) + +// CHECK: vcompresspd %zmm9, 1024(%rdx) +// CHECK: encoding: [0x62,0x72,0xfd,0x48,0x8a,0x8a,0x00,0x04,0x00,0x00] + vcompresspd %zmm9, 1024(%rdx) + +// CHECK: vcompresspd %zmm9, -1024(%rdx) +// CHECK: encoding: [0x62,0x72,0xfd,0x48,0x8a,0x4a,0x80] + vcompresspd %zmm9, -1024(%rdx) + +// CHECK: vcompresspd %zmm9, -1032(%rdx) +// CHECK: encoding: [0x62,0x72,0xfd,0x48,0x8a,0x8a,0xf8,0xfb,0xff,0xff] + vcompresspd %zmm9, -1032(%rdx) + +// CHECK: vcompresspd %zmm4, %zmm8 +// CHECK: encoding: [0x62,0xd2,0xfd,0x48,0x8a,0xe0] + vcompresspd %zmm4, %zmm8 + +// CHECK: vcompresspd %zmm4, %zmm8 {%k6} +// CHECK: encoding: [0x62,0xd2,0xfd,0x4e,0x8a,0xe0] + vcompresspd %zmm4, %zmm8 {%k6} + +// CHECK: vcompresspd %zmm4, %zmm8 {%k6} {z} +// CHECK: encoding: [0x62,0xd2,0xfd,0xce,0x8a,0xe0] + vcompresspd %zmm4, %zmm8 {%k6} {z} + +// CHECK: vcompressps %zmm10, (%rcx) +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0x11] + vcompressps %zmm10, (%rcx) + +// CHECK: vcompressps %zmm10, (%rcx) {%k7} +// CHECK: encoding: [0x62,0x72,0x7d,0x4f,0x8a,0x11] + vcompressps %zmm10, (%rcx) {%k7} + +// CHECK: vcompressps %zmm10, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x32,0x7d,0x48,0x8a,0x94,0xf0,0x23,0x01,0x00,0x00] + vcompressps %zmm10, 291(%rax,%r14,8) + +// CHECK: vcompressps %zmm10, 508(%rdx) +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0x52,0x7f] + vcompressps %zmm10, 508(%rdx) + +// CHECK: vcompressps %zmm10, 512(%rdx) +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0x92,0x00,0x02,0x00,0x00] + vcompressps %zmm10, 512(%rdx) + +// CHECK: vcompressps %zmm10, -512(%rdx) +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0x52,0x80] + vcompressps %zmm10, -512(%rdx) + +// CHECK: vcompressps %zmm10, -516(%rdx) +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0x92,0xfc,0xfd,0xff,0xff] + vcompressps %zmm10, -516(%rdx) + +// CHECK: vcompressps %zmm14, %zmm4 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x8a,0xf4] + vcompressps %zmm14, %zmm4 + +// CHECK: vcompressps %zmm14, %zmm4 {%k2} +// CHECK: encoding: [0x62,0x72,0x7d,0x4a,0x8a,0xf4] + vcompressps %zmm14, %zmm4 {%k2} + +// CHECK: vcompressps %zmm14, %zmm4 {%k2} {z} +// CHECK: encoding: [0x62,0x72,0x7d,0xca,0x8a,0xf4] + vcompressps %zmm14, %zmm4 {%k2} {z} + +// CHECK: vexpandpd (%rcx), %zmm24 +// CHECK: encoding: [0x62,0x62,0xfd,0x48,0x88,0x01] + vexpandpd (%rcx), %zmm24 + +// CHECK: vexpandpd (%rcx), %zmm24 {%k4} +// CHECK: encoding: [0x62,0x62,0xfd,0x4c,0x88,0x01] + vexpandpd (%rcx), %zmm24 {%k4} + +// CHECK: vexpandpd (%rcx), %zmm24 {%k4} {z} +// CHECK: encoding: [0x62,0x62,0xfd,0xcc,0x88,0x01] + vexpandpd (%rcx), %zmm24 {%k4} {z} + +// CHECK: vexpandpd 291(%rax,%r14,8), %zmm24 +// CHECK: encoding: [0x62,0x22,0xfd,0x48,0x88,0x84,0xf0,0x23,0x01,0x00,0x00] + vexpandpd 291(%rax,%r14,8), %zmm24 + +// CHECK: vexpandpd 1016(%rdx), %zmm24 +// CHECK: encoding: [0x62,0x62,0xfd,0x48,0x88,0x42,0x7f] + vexpandpd 1016(%rdx), %zmm24 + +// CHECK: vexpandpd 1024(%rdx), %zmm24 +// CHECK: encoding: [0x62,0x62,0xfd,0x48,0x88,0x82,0x00,0x04,0x00,0x00] + vexpandpd 1024(%rdx), %zmm24 + +// CHECK: vexpandpd -1024(%rdx), %zmm24 +// CHECK: encoding: [0x62,0x62,0xfd,0x48,0x88,0x42,0x80] + vexpandpd -1024(%rdx), %zmm24 + +// CHECK: vexpandpd -1032(%rdx), %zmm24 +// CHECK: encoding: [0x62,0x62,0xfd,0x48,0x88,0x82,0xf8,0xfb,0xff,0xff] + vexpandpd -1032(%rdx), %zmm24 + +// CHECK: vexpandpd %zmm15, %zmm23 +// CHECK: encoding: [0x62,0xc2,0xfd,0x48,0x88,0xff] + vexpandpd %zmm15, %zmm23 + +// CHECK: vexpandpd %zmm15, %zmm23 {%k5} +// CHECK: encoding: [0x62,0xc2,0xfd,0x4d,0x88,0xff] + vexpandpd %zmm15, %zmm23 {%k5} + +// CHECK: vexpandpd %zmm15, %zmm23 {%k5} {z} +// CHECK: encoding: [0x62,0xc2,0xfd,0xcd,0x88,0xff] + vexpandpd %zmm15, %zmm23 {%k5} {z} + +// CHECK: vexpandps (%rcx), %zmm4 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x88,0x21] + vexpandps (%rcx), %zmm4 + +// CHECK: vexpandps (%rcx), %zmm4 {%k6} +// CHECK: encoding: [0x62,0xf2,0x7d,0x4e,0x88,0x21] + vexpandps (%rcx), %zmm4 {%k6} + +// CHECK: vexpandps (%rcx), %zmm4 {%k6} {z} +// CHECK: encoding: [0x62,0xf2,0x7d,0xce,0x88,0x21] + vexpandps (%rcx), %zmm4 {%k6} {z} + +// CHECK: vexpandps 291(%rax,%r14,8), %zmm4 +// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x88,0xa4,0xf0,0x23,0x01,0x00,0x00] + vexpandps 291(%rax,%r14,8), %zmm4 + +// CHECK: vexpandps 508(%rdx), %zmm4 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x88,0x62,0x7f] + vexpandps 508(%rdx), %zmm4 + +// CHECK: vexpandps 512(%rdx), %zmm4 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x88,0xa2,0x00,0x02,0x00,0x00] + vexpandps 512(%rdx), %zmm4 + +// CHECK: vexpandps -512(%rdx), %zmm4 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x88,0x62,0x80] + vexpandps -512(%rdx), %zmm4 + +// CHECK: vexpandps -516(%rdx), %zmm4 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x88,0xa2,0xfc,0xfd,0xff,0xff] + vexpandps -516(%rdx), %zmm4 + +// CHECK: vexpandps %zmm9, %zmm14 +// CHECK: encoding: [0x62,0x52,0x7d,0x48,0x88,0xf1] + vexpandps %zmm9, %zmm14 + +// CHECK: vexpandps %zmm9, %zmm14 {%k2} +// CHECK: encoding: [0x62,0x52,0x7d,0x4a,0x88,0xf1] + vexpandps %zmm9, %zmm14 {%k2} + +// CHECK: vexpandps %zmm9, %zmm14 {%k2} {z} +// CHECK: encoding: [0x62,0x52,0x7d,0xca,0x88,0xf1] + vexpandps %zmm9, %zmm14 {%k2} {z} + +// CHECK: vpabsd %zmm14, %zmm15 +// CHECK: encoding: [0x62,0x52,0x7d,0x48,0x1e,0xfe] + vpabsd %zmm14, %zmm15 + +// CHECK: vpabsd %zmm14, %zmm15 {%k6} +// CHECK: encoding: [0x62,0x52,0x7d,0x4e,0x1e,0xfe] + vpabsd %zmm14, %zmm15 {%k6} + +// CHECK: vpabsd %zmm14, %zmm15 {%k6} {z} +// CHECK: encoding: [0x62,0x52,0x7d,0xce,0x1e,0xfe] + vpabsd %zmm14, %zmm15 {%k6} {z} + +// CHECK: vpabsd (%rcx), %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x1e,0x39] + vpabsd (%rcx), %zmm15 + +// CHECK: vpabsd 291(%rax,%r14,8), %zmm15 +// CHECK: encoding: [0x62,0x32,0x7d,0x48,0x1e,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpabsd 291(%rax,%r14,8), %zmm15 + +// CHECK: vpabsd (%rcx){1to16}, %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x58,0x1e,0x39] + vpabsd (%rcx){1to16}, %zmm15 + +// CHECK: vpabsd 8128(%rdx), %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x1e,0x7a,0x7f] + vpabsd 8128(%rdx), %zmm15 + +// CHECK: vpabsd 8192(%rdx), %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x1e,0xba,0x00,0x20,0x00,0x00] + vpabsd 8192(%rdx), %zmm15 + +// CHECK: vpabsd -8192(%rdx), %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x1e,0x7a,0x80] + vpabsd -8192(%rdx), %zmm15 + +// CHECK: vpabsd -8256(%rdx), %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x1e,0xba,0xc0,0xdf,0xff,0xff] + vpabsd -8256(%rdx), %zmm15 + +// CHECK: vpabsd 508(%rdx){1to16}, %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x58,0x1e,0x7a,0x7f] + vpabsd 508(%rdx){1to16}, %zmm15 + +// CHECK: vpabsd 512(%rdx){1to16}, %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x58,0x1e,0xba,0x00,0x02,0x00,0x00] + vpabsd 512(%rdx){1to16}, %zmm15 + +// CHECK: vpabsd -512(%rdx){1to16}, %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x58,0x1e,0x7a,0x80] + vpabsd -512(%rdx){1to16}, %zmm15 + +// CHECK: vpabsd -516(%rdx){1to16}, %zmm15 +// CHECK: encoding: [0x62,0x72,0x7d,0x58,0x1e,0xba,0xfc,0xfd,0xff,0xff] + vpabsd -516(%rdx){1to16}, %zmm15 + +// CHECK: vpabsq %zmm24, %zmm5 +// CHECK: encoding: [0x62,0x92,0xfd,0x48,0x1f,0xe8] + vpabsq %zmm24, %zmm5 + +// CHECK: vpabsq %zmm24, %zmm5 {%k6} +// CHECK: encoding: [0x62,0x92,0xfd,0x4e,0x1f,0xe8] + vpabsq %zmm24, %zmm5 {%k6} + +// CHECK: vpabsq %zmm24, %zmm5 {%k6} {z} +// CHECK: encoding: [0x62,0x92,0xfd,0xce,0x1f,0xe8] + vpabsq %zmm24, %zmm5 {%k6} {z} + +// CHECK: vpabsq (%rcx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x1f,0x29] + vpabsq (%rcx), %zmm5 + +// CHECK: vpabsq 291(%rax,%r14,8), %zmm5 +// CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x1f,0xac,0xf0,0x23,0x01,0x00,0x00] + vpabsq 291(%rax,%r14,8), %zmm5 + +// CHECK: vpabsq (%rcx){1to8}, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x58,0x1f,0x29] + vpabsq (%rcx){1to8}, %zmm5 + +// CHECK: vpabsq 8128(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x1f,0x6a,0x7f] + vpabsq 8128(%rdx), %zmm5 + +// CHECK: vpabsq 8192(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xaa,0x00,0x20,0x00,0x00] + vpabsq 8192(%rdx), %zmm5 + +// CHECK: vpabsq -8192(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x1f,0x6a,0x80] + vpabsq -8192(%rdx), %zmm5 + +// CHECK: vpabsq -8256(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xaa,0xc0,0xdf,0xff,0xff] + vpabsq -8256(%rdx), %zmm5 + +// CHECK: vpabsq 1016(%rdx){1to8}, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x58,0x1f,0x6a,0x7f] + vpabsq 1016(%rdx){1to8}, %zmm5 + +// CHECK: vpabsq 1024(%rdx){1to8}, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x58,0x1f,0xaa,0x00,0x04,0x00,0x00] + vpabsq 1024(%rdx){1to8}, %zmm5 + +// CHECK: vpabsq -1024(%rdx){1to8}, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x58,0x1f,0x6a,0x80] + vpabsq -1024(%rdx){1to8}, %zmm5 + +// CHECK: vpabsq -1032(%rdx){1to8}, %zmm5 +// CHECK: encoding: [0x62,0xf2,0xfd,0x58,0x1f,0xaa,0xf8,0xfb,0xff,0xff] + vpabsq -1032(%rdx){1to8}, %zmm5 + +// CHECK: vpgatherdd 123(%r14,%zmm11,8), %zmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x49,0x90,0x8c,0xde,0x7b,0x00,0x00,0x00] + vpgatherdd 123(%r14, %zmm11,8), %zmm17 {%k1} + +// CHECK: vpgatherdd 256(%r9,%zmm11), %zmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x49,0x90,0x4c,0x19,0x40] + vpgatherdd 256(%r9,%zmm11), %zmm17 {%k1} + +// CHECK: vpgatherdd 1024(%rcx,%zmm11,4), %zmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x49,0x90,0x8c,0x99,0x00,0x04,0x00,0x00] + vpgatherdd 1024(%rcx, %zmm11,4), %zmm17 {%k1} + +// CHECK: vpgatherdq 123(%r14,%ymm14,8), %zmm8 {%k1} +// CHECK: encoding: [0x62,0x12,0xfd,0x49,0x90,0x84,0xf6,0x7b,0x00,0x00,0x00] + vpgatherdq 123(%r14, %ymm14,8), %zmm8 {%k1} + +// CHECK: vpgatherdq 256(%r9,%ymm14), %zmm8 {%k1} +// CHECK: encoding: [0x62,0x12,0xfd,0x49,0x90,0x44,0x31,0x20] + vpgatherdq 256(%r9, %ymm14), %zmm8 {%k1} + +// CHECK: vpgatherdq 1024(%rcx,%ymm14,4), %zmm8 {%k1} +// CHECK: encoding: [0x62,0x32,0xfd,0x49,0x90,0x84,0xb1,0x00,0x04,0x00,0x00] + vpgatherdq 1024(%rcx, %ymm14,4), %zmm8 {%k1} + +// CHECK: vpgatherqd 123(%r14,%zmm17,8), %ymm3 {%k1} +// CHECK: encoding: [0x62,0xd2,0x7d,0x41,0x91,0x9c,0xce,0x7b,0x00,0x00,0x00] + vpgatherqd 123(%r14, %zmm17,8), %ymm3 {%k1} + +// CHECK: vpgatherqd 256(%r9,%zmm17), %ymm3 {%k1} +// CHECK: encoding: [0x62,0xd2,0x7d,0x41,0x91,0x5c,0x09,0x40] + vpgatherqd 256(%r9,%zmm17), %ymm3 {%k1} + +// CHECK: vpgatherqd 1024(%rcx,%zmm17,4), %ymm3 {%k1} +// CHECK: encoding: [0x62,0xf2,0x7d,0x41,0x91,0x9c,0x89,0x00,0x04,0x00,0x00] + vpgatherqd 1024(%rcx, %zmm17,4), %ymm3 {%k1} + +// CHECK: vpgatherqq 123(%r14,%zmm21,8), %zmm17 {%k1} +// CHECK: encoding: [0x62,0xc2,0xfd,0x41,0x91,0x8c,0xee,0x7b,0x00,0x00,0x00] + vpgatherqq 123(%r14, %zmm21,8), %zmm17 {%k1} + +// CHECK: vpgatherqq 256(%r9,%zmm21), %zmm17 {%k1} +// CHECK: encoding: [0x62,0xc2,0xfd,0x41,0x91,0x4c,0x29,0x20] + vpgatherqq 256(%r9,%zmm21), %zmm17 {%k1} + +// CHECK: vpgatherqq 1024(%rcx,%zmm21,4), %zmm17 {%k1} +// CHECK: encoding: [0x62,0xe2,0xfd,0x41,0x91,0x8c,0xa9,0x00,0x04,0x00,0x00] + vpgatherqq 1024(%rcx, %zmm21,4), %zmm17 {%k1} + +// CHECK: vpscatterdd %zmm19, 123(%r14,%zmm16,8) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x41,0xa0,0x9c,0xc6,0x7b,0x00,0x00,0x00] + vpscatterdd %zmm19, 123(%r14,%zmm16,8) {%k1} + +// CHECK: vpscatterdd %zmm19, 123(%r14,%zmm16,8) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x41,0xa0,0x9c,0xc6,0x7b,0x00,0x00,0x00] + vpscatterdd %zmm19, 123(%r14,%zmm16,8) {%k1} + +// CHECK: vpscatterdd %zmm19, 256(%r9,%zmm16) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x41,0xa0,0x5c,0x01,0x40] + vpscatterdd %zmm19, 256(%r9,%zmm16) {%k1} + +// CHECK: vpscatterdd %zmm19, 1024(%rcx,%zmm16,4) {%k1} +// CHECK: encoding: [0x62,0xe2,0x7d,0x41,0xa0,0x9c,0x81,0x00,0x04,0x00,0x00] + vpscatterdd %zmm19, 1024(%rcx,%zmm16,4) {%k1} + +// CHECK: vpscatterdq %zmm5, 123(%r14,%ymm6,8) {%k1} +// CHECK: encoding: [0x62,0xd2,0xfd,0x49,0xa0,0xac,0xf6,0x7b,0x00,0x00,0x00] + vpscatterdq %zmm5, 123(%r14,%ymm6,8) {%k1} + +// CHECK: vpscatterdq %zmm5, 123(%r14,%ymm6,8) {%k1} +// CHECK: encoding: [0x62,0xd2,0xfd,0x49,0xa0,0xac,0xf6,0x7b,0x00,0x00,0x00] + vpscatterdq %zmm5, 123(%r14,%ymm6,8) {%k1} + +// CHECK: vpscatterdq %zmm5, 256(%r9,%ymm6) {%k1} +// CHECK: encoding: [0x62,0xd2,0xfd,0x49,0xa0,0x6c,0x31,0x20] + vpscatterdq %zmm5, 256(%r9,%ymm6) {%k1} + +// CHECK: vpscatterdq %zmm5, 1024(%rcx,%ymm6,4) {%k1} +// CHECK: encoding: [0x62,0xf2,0xfd,0x49,0xa0,0xac,0xb1,0x00,0x04,0x00,0x00] + vpscatterdq %zmm5, 1024(%rcx,%ymm6,4) {%k1} + +// CHECK: vpscatterqd %ymm20, 123(%r14,%zmm2,8) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x49,0xa1,0xa4,0xd6,0x7b,0x00,0x00,0x00] + vpscatterqd %ymm20, 123(%r14,%zmm2,8) {%k1} + +// CHECK: vpscatterqd %ymm20, 123(%r14,%zmm2,8) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x49,0xa1,0xa4,0xd6,0x7b,0x00,0x00,0x00] + vpscatterqd %ymm20, 123(%r14,%zmm2,8) {%k1} + +// CHECK: vpscatterqd %ymm20, 256(%r9,%zmm2) {%k1} +// CHECK: encoding: [0x62,0xc2,0x7d,0x49,0xa1,0x64,0x11,0x40] + vpscatterqd %ymm20, 256(%r9,%zmm2) {%k1} + +// CHECK: vpscatterqd %ymm20, 1024(%rcx,%zmm2,4) {%k1} +// CHECK: encoding: [0x62,0xe2,0x7d,0x49,0xa1,0xa4,0x91,0x00,0x04,0x00,0x00] + vpscatterqd %ymm20, 1024(%rcx,%zmm2,4) {%k1} + +// CHECK: vpscatterqq %zmm14, 123(%r14,%zmm20,8) {%k1} +// CHECK: encoding: [0x62,0x52,0xfd,0x41,0xa1,0xb4,0xe6,0x7b,0x00,0x00,0x00] + vpscatterqq %zmm14, 123(%r14,%zmm20,8) {%k1} + +// CHECK: vpscatterqq %zmm14, 123(%r14,%zmm20,8) {%k1} +// CHECK: encoding: [0x62,0x52,0xfd,0x41,0xa1,0xb4,0xe6,0x7b,0x00,0x00,0x00] + vpscatterqq %zmm14, 123(%r14,%zmm20,8) {%k1} + +// CHECK: vpscatterqq %zmm14, 256(%r9,%zmm20) {%k1} +// CHECK: encoding: [0x62,0x52,0xfd,0x41,0xa1,0x74,0x21,0x20] + vpscatterqq %zmm14, 256(%r9,%zmm20) {%k1} + +// CHECK: vpscatterqq %zmm14, 1024(%rcx,%zmm20,4) {%k1} +// CHECK: encoding: [0x62,0x72,0xfd,0x41,0xa1,0xb4,0xa1,0x00,0x04,0x00,0x00] + vpscatterqq %zmm14, 1024(%rcx,%zmm20,4) {%k1} +// CHECK: vscalefpd %zmm28, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x02,0xad,0x40,0x2c,0xd4] + vscalefpd %zmm28, %zmm26, %zmm26 + +// CHECK: vscalefpd %zmm28, %zmm26, %zmm26 {%k5} +// CHECK: encoding: [0x62,0x02,0xad,0x45,0x2c,0xd4] + vscalefpd %zmm28, %zmm26, %zmm26 {%k5} + +// CHECK: vscalefpd %zmm28, %zmm26, %zmm26 {%k5} {z} +// CHECK: encoding: [0x62,0x02,0xad,0xc5,0x2c,0xd4] + vscalefpd %zmm28, %zmm26, %zmm26 {%k5} {z} + +// CHECK: vscalefpd {rn-sae}, %zmm28, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x02,0xad,0x10,0x2c,0xd4] + vscalefpd {rn-sae}, %zmm28, %zmm26, %zmm26 + +// CHECK: vscalefpd {ru-sae}, %zmm28, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x02,0xad,0x50,0x2c,0xd4] + vscalefpd {ru-sae}, %zmm28, %zmm26, %zmm26 + +// CHECK: vscalefpd {rd-sae}, %zmm28, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x02,0xad,0x30,0x2c,0xd4] + vscalefpd {rd-sae}, %zmm28, %zmm26, %zmm26 + +// CHECK: vscalefpd {rz-sae}, %zmm28, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x02,0xad,0x70,0x2c,0xd4] + vscalefpd {rz-sae}, %zmm28, %zmm26, %zmm26 + +// CHECK: vscalefpd (%rcx), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x40,0x2c,0x11] + vscalefpd (%rcx), %zmm26, %zmm26 + +// CHECK: vscalefpd 291(%rax,%r14,8), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x22,0xad,0x40,0x2c,0x94,0xf0,0x23,0x01,0x00,0x00] + vscalefpd 291(%rax,%r14,8), %zmm26, %zmm26 + +// CHECK: vscalefpd (%rcx){1to8}, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x50,0x2c,0x11] + vscalefpd (%rcx){1to8}, %zmm26, %zmm26 + +// CHECK: vscalefpd 8128(%rdx), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x40,0x2c,0x52,0x7f] + vscalefpd 8128(%rdx), %zmm26, %zmm26 + +// CHECK: vscalefpd 8192(%rdx), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x40,0x2c,0x92,0x00,0x20,0x00,0x00] + vscalefpd 8192(%rdx), %zmm26, %zmm26 + +// CHECK: vscalefpd -8192(%rdx), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x40,0x2c,0x52,0x80] + vscalefpd -8192(%rdx), %zmm26, %zmm26 + +// CHECK: vscalefpd -8256(%rdx), %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x40,0x2c,0x92,0xc0,0xdf,0xff,0xff] + vscalefpd -8256(%rdx), %zmm26, %zmm26 + +// CHECK: vscalefpd 1016(%rdx){1to8}, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x50,0x2c,0x52,0x7f] + vscalefpd 1016(%rdx){1to8}, %zmm26, %zmm26 + +// CHECK: vscalefpd 1024(%rdx){1to8}, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x50,0x2c,0x92,0x00,0x04,0x00,0x00] + vscalefpd 1024(%rdx){1to8}, %zmm26, %zmm26 + +// CHECK: vscalefpd -1024(%rdx){1to8}, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x50,0x2c,0x52,0x80] + vscalefpd -1024(%rdx){1to8}, %zmm26, %zmm26 + +// CHECK: vscalefpd -1032(%rdx){1to8}, %zmm26, %zmm26 +// CHECK: encoding: [0x62,0x62,0xad,0x50,0x2c,0x92,0xf8,0xfb,0xff,0xff] + vscalefpd -1032(%rdx){1to8}, %zmm26, %zmm26 + +// CHECK: vscalefps %zmm18, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x48,0x2c,0xda] + vscalefps %zmm18, %zmm6, %zmm19 + +// CHECK: vscalefps %zmm18, %zmm6, %zmm19 {%k6} +// CHECK: encoding: [0x62,0xa2,0x4d,0x4e,0x2c,0xda] + vscalefps %zmm18, %zmm6, %zmm19 {%k6} + +// CHECK: vscalefps %zmm18, %zmm6, %zmm19 {%k6} {z} +// CHECK: encoding: [0x62,0xa2,0x4d,0xce,0x2c,0xda] + vscalefps %zmm18, %zmm6, %zmm19 {%k6} {z} + +// CHECK: vscalefps {rn-sae}, %zmm18, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x18,0x2c,0xda] + vscalefps {rn-sae}, %zmm18, %zmm6, %zmm19 + +// CHECK: vscalefps {ru-sae}, %zmm18, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x58,0x2c,0xda] + vscalefps {ru-sae}, %zmm18, %zmm6, %zmm19 + +// CHECK: vscalefps {rd-sae}, %zmm18, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x38,0x2c,0xda] + vscalefps {rd-sae}, %zmm18, %zmm6, %zmm19 + +// CHECK: vscalefps {rz-sae}, %zmm18, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x78,0x2c,0xda] + vscalefps {rz-sae}, %zmm18, %zmm6, %zmm19 + +// CHECK: vscalefps (%rcx), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x48,0x2c,0x19] + vscalefps (%rcx), %zmm6, %zmm19 + +// CHECK: vscalefps 291(%rax,%r14,8), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xa2,0x4d,0x48,0x2c,0x9c,0xf0,0x23,0x01,0x00,0x00] + vscalefps 291(%rax,%r14,8), %zmm6, %zmm19 + +// CHECK: vscalefps (%rcx){1to16}, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x19] + vscalefps (%rcx){1to16}, %zmm6, %zmm19 + +// CHECK: vscalefps 8128(%rdx), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x48,0x2c,0x5a,0x7f] + vscalefps 8128(%rdx), %zmm6, %zmm19 + +// CHECK: vscalefps 8192(%rdx), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x48,0x2c,0x9a,0x00,0x20,0x00,0x00] + vscalefps 8192(%rdx), %zmm6, %zmm19 + +// CHECK: vscalefps -8192(%rdx), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x48,0x2c,0x5a,0x80] + vscalefps -8192(%rdx), %zmm6, %zmm19 + +// CHECK: vscalefps -8256(%rdx), %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x48,0x2c,0x9a,0xc0,0xdf,0xff,0xff] + vscalefps -8256(%rdx), %zmm6, %zmm19 + +// CHECK: vscalefps 508(%rdx){1to16}, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x5a,0x7f] + vscalefps 508(%rdx){1to16}, %zmm6, %zmm19 + +// CHECK: vscalefps 512(%rdx){1to16}, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x9a,0x00,0x02,0x00,0x00] + vscalefps 512(%rdx){1to16}, %zmm6, %zmm19 + +// CHECK: vscalefps -512(%rdx){1to16}, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x5a,0x80] + vscalefps -512(%rdx){1to16}, %zmm6, %zmm19 + +// CHECK: vscalefps -516(%rdx){1to16}, %zmm6, %zmm19 +// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x9a,0xfc,0xfd,0xff,0xff] + vscalefps -516(%rdx){1to16}, %zmm6, %zmm19 + +// CHECK: vfmadd132ss %xmm22, %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x00,0x99,0xf6] + vfmadd132ss %xmm22, %xmm17, %xmm30 + +// CHECK: vfmadd132ss %xmm22, %xmm17, %xmm30 {%k3} +// CHECK: encoding: [0x62,0x22,0x75,0x03,0x99,0xf6] + vfmadd132ss %xmm22, %xmm17, %xmm30 {%k3} + +// CHECK: vfmadd132ss %xmm22, %xmm17, %xmm30 {%k3} {z} +// CHECK: encoding: [0x62,0x22,0x75,0x83,0x99,0xf6] + vfmadd132ss %xmm22, %xmm17, %xmm30 {%k3} {z} + +// CHECK: vfmadd132ss {rn-sae}, %xmm22, %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x10,0x99,0xf6] + vfmadd132ss {rn-sae}, %xmm22, %xmm17, %xmm30 + +// CHECK: vfmadd132ss {ru-sae}, %xmm22, %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x50,0x99,0xf6] + vfmadd132ss {ru-sae}, %xmm22, %xmm17, %xmm30 + +// CHECK: vfmadd132ss {rd-sae}, %xmm22, %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x30,0x99,0xf6] + vfmadd132ss {rd-sae}, %xmm22, %xmm17, %xmm30 + +// CHECK: vfmadd132ss {rz-sae}, %xmm22, %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x70,0x99,0xf6] + vfmadd132ss {rz-sae}, %xmm22, %xmm17, %xmm30 + +// CHECK: vfmadd132ss (%rcx), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x62,0x75,0x00,0x99,0x31] + vfmadd132ss (%rcx), %xmm17, %xmm30 + +// CHECK: vfmadd132ss 291(%rax,%r14,8), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x22,0x75,0x00,0x99,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd132ss 291(%rax,%r14,8), %xmm17, %xmm30 + +// CHECK: vfmadd132ss 508(%rdx), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x62,0x75,0x00,0x99,0x72,0x7f] + vfmadd132ss 508(%rdx), %xmm17, %xmm30 + +// CHECK: vfmadd132ss 512(%rdx), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x62,0x75,0x00,0x99,0xb2,0x00,0x02,0x00,0x00] + vfmadd132ss 512(%rdx), %xmm17, %xmm30 + +// CHECK: vfmadd132ss -512(%rdx), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x62,0x75,0x00,0x99,0x72,0x80] + vfmadd132ss -512(%rdx), %xmm17, %xmm30 + +// CHECK: vfmadd132ss -516(%rdx), %xmm17, %xmm30 +// CHECK: encoding: [0x62,0x62,0x75,0x00,0x99,0xb2,0xfc,0xfd,0xff,0xff] + vfmadd132ss -516(%rdx), %xmm17, %xmm30 + +// CHECK: vfmadd132sd %xmm3, %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0xe3] + vfmadd132sd %xmm3, %xmm17, %xmm28 + +// CHECK: vfmadd132sd %xmm3, %xmm17, %xmm28 {%k2} +// CHECK: encoding: [0x62,0x62,0xf5,0x02,0x99,0xe3] + vfmadd132sd %xmm3, %xmm17, %xmm28 {%k2} + +// CHECK: vfmadd132sd %xmm3, %xmm17, %xmm28 {%k2} {z} +// CHECK: encoding: [0x62,0x62,0xf5,0x82,0x99,0xe3] + vfmadd132sd %xmm3, %xmm17, %xmm28 {%k2} {z} + +// CHECK: vfmadd132sd {rn-sae}, %xmm3, %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x99,0xe3] + vfmadd132sd {rn-sae}, %xmm3, %xmm17, %xmm28 + +// CHECK: vfmadd132sd {ru-sae}, %xmm3, %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x50,0x99,0xe3] + vfmadd132sd {ru-sae}, %xmm3, %xmm17, %xmm28 + +// CHECK: vfmadd132sd {rd-sae}, %xmm3, %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x99,0xe3] + vfmadd132sd {rd-sae}, %xmm3, %xmm17, %xmm28 + +// CHECK: vfmadd132sd {rz-sae}, %xmm3, %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x70,0x99,0xe3] + vfmadd132sd {rz-sae}, %xmm3, %xmm17, %xmm28 + +// CHECK: vfmadd132sd (%rcx), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0x21] + vfmadd132sd (%rcx), %xmm17, %xmm28 + +// CHECK: vfmadd132sd 291(%rax,%r14,8), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x22,0xf5,0x00,0x99,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmadd132sd 291(%rax,%r14,8), %xmm17, %xmm28 + +// CHECK: vfmadd132sd 1016(%rdx), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0x62,0x7f] + vfmadd132sd 1016(%rdx), %xmm17, %xmm28 + +// CHECK: vfmadd132sd 1024(%rdx), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0xa2,0x00,0x04,0x00,0x00] + vfmadd132sd 1024(%rdx), %xmm17, %xmm28 + +// CHECK: vfmadd132sd -1024(%rdx), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0x62,0x80] + vfmadd132sd -1024(%rdx), %xmm17, %xmm28 + +// CHECK: vfmadd132sd -1032(%rdx), %xmm17, %xmm28 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x99,0xa2,0xf8,0xfb,0xff,0xff] + vfmadd132sd -1032(%rdx), %xmm17, %xmm28 + +// CHECK: vfmadd213ss %xmm16, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x00,0xa9,0xf0] + vfmadd213ss %xmm16, %xmm22, %xmm30 + +// CHECK: vfmadd213ss %xmm16, %xmm22, %xmm30 {%k1} +// CHECK: encoding: [0x62,0x22,0x4d,0x01,0xa9,0xf0] + vfmadd213ss %xmm16, %xmm22, %xmm30 {%k1} + +// CHECK: vfmadd213ss %xmm16, %xmm22, %xmm30 {%k1} {z} +// CHECK: encoding: [0x62,0x22,0x4d,0x81,0xa9,0xf0] + vfmadd213ss %xmm16, %xmm22, %xmm30 {%k1} {z} + +// CHECK: vfmadd213ss {rn-sae}, %xmm16, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x10,0xa9,0xf0] + vfmadd213ss {rn-sae}, %xmm16, %xmm22, %xmm30 + +// CHECK: vfmadd213ss {ru-sae}, %xmm16, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x50,0xa9,0xf0] + vfmadd213ss {ru-sae}, %xmm16, %xmm22, %xmm30 + +// CHECK: vfmadd213ss {rd-sae}, %xmm16, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x30,0xa9,0xf0] + vfmadd213ss {rd-sae}, %xmm16, %xmm22, %xmm30 + +// CHECK: vfmadd213ss {rz-sae}, %xmm16, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x70,0xa9,0xf0] + vfmadd213ss {rz-sae}, %xmm16, %xmm22, %xmm30 + +// CHECK: vfmadd213ss (%rcx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0xa9,0x31] + vfmadd213ss (%rcx), %xmm22, %xmm30 + +// CHECK: vfmadd213ss 291(%rax,%r14,8), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x00,0xa9,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd213ss 291(%rax,%r14,8), %xmm22, %xmm30 + +// CHECK: vfmadd213ss 508(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0xa9,0x72,0x7f] + vfmadd213ss 508(%rdx), %xmm22, %xmm30 + +// CHECK: vfmadd213ss 512(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0xa9,0xb2,0x00,0x02,0x00,0x00] + vfmadd213ss 512(%rdx), %xmm22, %xmm30 + +// CHECK: vfmadd213ss -512(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0xa9,0x72,0x80] + vfmadd213ss -512(%rdx), %xmm22, %xmm30 + +// CHECK: vfmadd213ss -516(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0xa9,0xb2,0xfc,0xfd,0xff,0xff] + vfmadd213ss -516(%rdx), %xmm22, %xmm30 + +// CHECK: vfmadd213sd %xmm13, %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x42,0xad,0x00,0xa9,0xc5] + vfmadd213sd %xmm13, %xmm26, %xmm24 + +// CHECK: vfmadd213sd %xmm13, %xmm26, %xmm24 {%k3} +// CHECK: encoding: [0x62,0x42,0xad,0x03,0xa9,0xc5] + vfmadd213sd %xmm13, %xmm26, %xmm24 {%k3} + +// CHECK: vfmadd213sd %xmm13, %xmm26, %xmm24 {%k3} {z} +// CHECK: encoding: [0x62,0x42,0xad,0x83,0xa9,0xc5] + vfmadd213sd %xmm13, %xmm26, %xmm24 {%k3} {z} + +// CHECK: vfmadd213sd {rn-sae}, %xmm13, %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x42,0xad,0x10,0xa9,0xc5] + vfmadd213sd {rn-sae}, %xmm13, %xmm26, %xmm24 + +// CHECK: vfmadd213sd {ru-sae}, %xmm13, %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x42,0xad,0x50,0xa9,0xc5] + vfmadd213sd {ru-sae}, %xmm13, %xmm26, %xmm24 + +// CHECK: vfmadd213sd {rd-sae}, %xmm13, %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x42,0xad,0x30,0xa9,0xc5] + vfmadd213sd {rd-sae}, %xmm13, %xmm26, %xmm24 + +// CHECK: vfmadd213sd {rz-sae}, %xmm13, %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x42,0xad,0x70,0xa9,0xc5] + vfmadd213sd {rz-sae}, %xmm13, %xmm26, %xmm24 + +// CHECK: vfmadd213sd (%rcx), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x62,0xad,0x00,0xa9,0x01] + vfmadd213sd (%rcx), %xmm26, %xmm24 + +// CHECK: vfmadd213sd 291(%rax,%r14,8), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x22,0xad,0x00,0xa9,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmadd213sd 291(%rax,%r14,8), %xmm26, %xmm24 + +// CHECK: vfmadd213sd 1016(%rdx), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x62,0xad,0x00,0xa9,0x42,0x7f] + vfmadd213sd 1016(%rdx), %xmm26, %xmm24 + +// CHECK: vfmadd213sd 1024(%rdx), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x62,0xad,0x00,0xa9,0x82,0x00,0x04,0x00,0x00] + vfmadd213sd 1024(%rdx), %xmm26, %xmm24 + +// CHECK: vfmadd213sd -1024(%rdx), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x62,0xad,0x00,0xa9,0x42,0x80] + vfmadd213sd -1024(%rdx), %xmm26, %xmm24 + +// CHECK: vfmadd213sd -1032(%rdx), %xmm26, %xmm24 +// CHECK: encoding: [0x62,0x62,0xad,0x00,0xa9,0x82,0xf8,0xfb,0xff,0xff] + vfmadd213sd -1032(%rdx), %xmm26, %xmm24 + +// CHECK: vfmadd231ss %xmm10, %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x42,0x05,0x08,0xb9,0xea] + vfmadd231ss %xmm10, %xmm15, %xmm29 + +// CHECK: vfmadd231ss %xmm10, %xmm15, %xmm29 {%k4} +// CHECK: encoding: [0x62,0x42,0x05,0x0c,0xb9,0xea] + vfmadd231ss %xmm10, %xmm15, %xmm29 {%k4} + +// CHECK: vfmadd231ss %xmm10, %xmm15, %xmm29 {%k4} {z} +// CHECK: encoding: [0x62,0x42,0x05,0x8c,0xb9,0xea] + vfmadd231ss %xmm10, %xmm15, %xmm29 {%k4} {z} + +// CHECK: vfmadd231ss {rn-sae}, %xmm10, %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x42,0x05,0x18,0xb9,0xea] + vfmadd231ss {rn-sae}, %xmm10, %xmm15, %xmm29 + +// CHECK: vfmadd231ss {ru-sae}, %xmm10, %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x42,0x05,0x58,0xb9,0xea] + vfmadd231ss {ru-sae}, %xmm10, %xmm15, %xmm29 + +// CHECK: vfmadd231ss {rd-sae}, %xmm10, %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x42,0x05,0x38,0xb9,0xea] + vfmadd231ss {rd-sae}, %xmm10, %xmm15, %xmm29 + +// CHECK: vfmadd231ss {rz-sae}, %xmm10, %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x42,0x05,0x78,0xb9,0xea] + vfmadd231ss {rz-sae}, %xmm10, %xmm15, %xmm29 + +// CHECK: vfmadd231ss (%rcx), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x62,0x05,0x08,0xb9,0x29] + vfmadd231ss (%rcx), %xmm15, %xmm29 + +// CHECK: vfmadd231ss 291(%rax,%r14,8), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x22,0x05,0x08,0xb9,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmadd231ss 291(%rax,%r14,8), %xmm15, %xmm29 + +// CHECK: vfmadd231ss 508(%rdx), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x62,0x05,0x08,0xb9,0x6a,0x7f] + vfmadd231ss 508(%rdx), %xmm15, %xmm29 + +// CHECK: vfmadd231ss 512(%rdx), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x62,0x05,0x08,0xb9,0xaa,0x00,0x02,0x00,0x00] + vfmadd231ss 512(%rdx), %xmm15, %xmm29 + +// CHECK: vfmadd231ss -512(%rdx), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x62,0x05,0x08,0xb9,0x6a,0x80] + vfmadd231ss -512(%rdx), %xmm15, %xmm29 + +// CHECK: vfmadd231ss -516(%rdx), %xmm15, %xmm29 +// CHECK: encoding: [0x62,0x62,0x05,0x08,0xb9,0xaa,0xfc,0xfd,0xff,0xff] + vfmadd231ss -516(%rdx), %xmm15, %xmm29 + +// CHECK: vfmadd231sd %xmm14, %xmm1, %xmm4 +// CHECK: encoding: [0xc4,0xc2,0xf1,0xb9,0xe6] + vfmadd231sd %xmm14, %xmm1, %xmm4 + +// CHECK: vfmadd231sd %xmm14, %xmm1, %xmm4 {%k1} +// CHECK: encoding: [0x62,0xd2,0xf5,0x09,0xb9,0xe6] + vfmadd231sd %xmm14, %xmm1, %xmm4 {%k1} + +// CHECK: vfmadd231sd %xmm14, %xmm1, %xmm4 {%k1} {z} +// CHECK: encoding: [0x62,0xd2,0xf5,0x89,0xb9,0xe6] + vfmadd231sd %xmm14, %xmm1, %xmm4 {%k1} {z} + +// CHECK: vfmadd231sd {rn-sae}, %xmm14, %xmm1, %xmm4 +// CHECK: encoding: [0x62,0xd2,0xf5,0x18,0xb9,0xe6] + vfmadd231sd {rn-sae}, %xmm14, %xmm1, %xmm4 + +// CHECK: vfmadd231sd {ru-sae}, %xmm14, %xmm1, %xmm4 +// CHECK: encoding: [0x62,0xd2,0xf5,0x58,0xb9,0xe6] + vfmadd231sd {ru-sae}, %xmm14, %xmm1, %xmm4 + +// CHECK: vfmadd231sd {rd-sae}, %xmm14, %xmm1, %xmm4 +// CHECK: encoding: [0x62,0xd2,0xf5,0x38,0xb9,0xe6] + vfmadd231sd {rd-sae}, %xmm14, %xmm1, %xmm4 + +// CHECK: vfmadd231sd {rz-sae}, %xmm14, %xmm1, %xmm4 +// CHECK: encoding: [0x62,0xd2,0xf5,0x78,0xb9,0xe6] + vfmadd231sd {rz-sae}, %xmm14, %xmm1, %xmm4 + +// CHECK: vfmadd231sd (%rcx), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x08,0xb9,0x01] + vfmadd231sd (%rcx), %xmm1, %xmm24 + +// CHECK: vfmadd231sd 291(%rax,%r14,8), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x22,0xf5,0x08,0xb9,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmadd231sd 291(%rax,%r14,8), %xmm1, %xmm24 + +// CHECK: vfmadd231sd 1016(%rdx), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x08,0xb9,0x42,0x7f] + vfmadd231sd 1016(%rdx), %xmm1, %xmm24 + +// CHECK: vfmadd231sd 1024(%rdx), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x08,0xb9,0x82,0x00,0x04,0x00,0x00] + vfmadd231sd 1024(%rdx), %xmm1, %xmm24 + +// CHECK: vfmadd231sd -1024(%rdx), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x08,0xb9,0x42,0x80] + vfmadd231sd -1024(%rdx), %xmm1, %xmm24 + +// CHECK: vfmadd231sd -1032(%rdx), %xmm1, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x08,0xb9,0x82,0xf8,0xfb,0xff,0xff] + vfmadd231sd -1032(%rdx), %xmm1, %xmm24 + +// CHECK: vfmsub132ss %xmm27, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x02,0x4d,0x00,0x9b,0xf3] + vfmsub132ss %xmm27, %xmm22, %xmm30 + +// CHECK: vfmsub132ss %xmm27, %xmm22, %xmm30 {%k3} +// CHECK: encoding: [0x62,0x02,0x4d,0x03,0x9b,0xf3] + vfmsub132ss %xmm27, %xmm22, %xmm30 {%k3} + +// CHECK: vfmsub132ss %xmm27, %xmm22, %xmm30 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x4d,0x83,0x9b,0xf3] + vfmsub132ss %xmm27, %xmm22, %xmm30 {%k3} {z} + +// CHECK: vfmsub132ss {rn-sae}, %xmm27, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x02,0x4d,0x10,0x9b,0xf3] + vfmsub132ss {rn-sae}, %xmm27, %xmm22, %xmm30 + +// CHECK: vfmsub132ss {ru-sae}, %xmm27, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x02,0x4d,0x50,0x9b,0xf3] + vfmsub132ss {ru-sae}, %xmm27, %xmm22, %xmm30 + +// CHECK: vfmsub132ss {rd-sae}, %xmm27, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x02,0x4d,0x30,0x9b,0xf3] + vfmsub132ss {rd-sae}, %xmm27, %xmm22, %xmm30 + +// CHECK: vfmsub132ss {rz-sae}, %xmm27, %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x02,0x4d,0x70,0x9b,0xf3] + vfmsub132ss {rz-sae}, %xmm27, %xmm22, %xmm30 + +// CHECK: vfmsub132ss (%rcx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0x9b,0x31] + vfmsub132ss (%rcx), %xmm22, %xmm30 + +// CHECK: vfmsub132ss 291(%rax,%r14,8), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x22,0x4d,0x00,0x9b,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub132ss 291(%rax,%r14,8), %xmm22, %xmm30 + +// CHECK: vfmsub132ss 508(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0x9b,0x72,0x7f] + vfmsub132ss 508(%rdx), %xmm22, %xmm30 + +// CHECK: vfmsub132ss 512(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0x9b,0xb2,0x00,0x02,0x00,0x00] + vfmsub132ss 512(%rdx), %xmm22, %xmm30 + +// CHECK: vfmsub132ss -512(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0x9b,0x72,0x80] + vfmsub132ss -512(%rdx), %xmm22, %xmm30 + +// CHECK: vfmsub132ss -516(%rdx), %xmm22, %xmm30 +// CHECK: encoding: [0x62,0x62,0x4d,0x00,0x9b,0xb2,0xfc,0xfd,0xff,0xff] + vfmsub132ss -516(%rdx), %xmm22, %xmm30 + +// CHECK: vfmsub132sd %xmm27, %xmm8, %xmm12 +// CHECK: encoding: [0x62,0x12,0xbd,0x08,0x9b,0xe3] + vfmsub132sd %xmm27, %xmm8, %xmm12 + +// CHECK: vfmsub132sd %xmm27, %xmm8, %xmm12 {%k3} +// CHECK: encoding: [0x62,0x12,0xbd,0x0b,0x9b,0xe3] + vfmsub132sd %xmm27, %xmm8, %xmm12 {%k3} + +// CHECK: vfmsub132sd %xmm27, %xmm8, %xmm12 {%k3} {z} +// CHECK: encoding: [0x62,0x12,0xbd,0x8b,0x9b,0xe3] + vfmsub132sd %xmm27, %xmm8, %xmm12 {%k3} {z} + +// CHECK: vfmsub132sd {rn-sae}, %xmm27, %xmm8, %xmm12 +// CHECK: encoding: [0x62,0x12,0xbd,0x18,0x9b,0xe3] + vfmsub132sd {rn-sae}, %xmm27, %xmm8, %xmm12 + +// CHECK: vfmsub132sd {ru-sae}, %xmm27, %xmm8, %xmm12 +// CHECK: encoding: [0x62,0x12,0xbd,0x58,0x9b,0xe3] + vfmsub132sd {ru-sae}, %xmm27, %xmm8, %xmm12 + +// CHECK: vfmsub132sd {rd-sae}, %xmm27, %xmm8, %xmm12 +// CHECK: encoding: [0x62,0x12,0xbd,0x38,0x9b,0xe3] + vfmsub132sd {rd-sae}, %xmm27, %xmm8, %xmm12 + +// CHECK: vfmsub132sd {rz-sae}, %xmm27, %xmm8, %xmm12 +// CHECK: encoding: [0x62,0x12,0xbd,0x78,0x9b,0xe3] + vfmsub132sd {rz-sae}, %xmm27, %xmm8, %xmm12 + +// CHECK: vfmsub132sd (%rcx), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x08,0x9b,0x31] + vfmsub132sd (%rcx), %xmm8, %xmm22 + +// CHECK: vfmsub132sd 291(%rax,%r14,8), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xa2,0xbd,0x08,0x9b,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub132sd 291(%rax,%r14,8), %xmm8, %xmm22 + +// CHECK: vfmsub132sd 1016(%rdx), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x08,0x9b,0x72,0x7f] + vfmsub132sd 1016(%rdx), %xmm8, %xmm22 + +// CHECK: vfmsub132sd 1024(%rdx), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x08,0x9b,0xb2,0x00,0x04,0x00,0x00] + vfmsub132sd 1024(%rdx), %xmm8, %xmm22 + +// CHECK: vfmsub132sd -1024(%rdx), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x08,0x9b,0x72,0x80] + vfmsub132sd -1024(%rdx), %xmm8, %xmm22 + +// CHECK: vfmsub132sd -1032(%rdx), %xmm8, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x08,0x9b,0xb2,0xf8,0xfb,0xff,0xff] + vfmsub132sd -1032(%rdx), %xmm8, %xmm22 + +// CHECK: vfmsub213ss %xmm26, %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x02,0x15,0x08,0xab,0xf2] + vfmsub213ss %xmm26, %xmm13, %xmm30 + +// CHECK: vfmsub213ss %xmm26, %xmm13, %xmm30 {%k1} +// CHECK: encoding: [0x62,0x02,0x15,0x09,0xab,0xf2] + vfmsub213ss %xmm26, %xmm13, %xmm30 {%k1} + +// CHECK: vfmsub213ss %xmm26, %xmm13, %xmm30 {%k1} {z} +// CHECK: encoding: [0x62,0x02,0x15,0x89,0xab,0xf2] + vfmsub213ss %xmm26, %xmm13, %xmm30 {%k1} {z} + +// CHECK: vfmsub213ss {rn-sae}, %xmm26, %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x02,0x15,0x18,0xab,0xf2] + vfmsub213ss {rn-sae}, %xmm26, %xmm13, %xmm30 + +// CHECK: vfmsub213ss {ru-sae}, %xmm26, %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x02,0x15,0x58,0xab,0xf2] + vfmsub213ss {ru-sae}, %xmm26, %xmm13, %xmm30 + +// CHECK: vfmsub213ss {rd-sae}, %xmm26, %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x02,0x15,0x38,0xab,0xf2] + vfmsub213ss {rd-sae}, %xmm26, %xmm13, %xmm30 + +// CHECK: vfmsub213ss {rz-sae}, %xmm26, %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x02,0x15,0x78,0xab,0xf2] + vfmsub213ss {rz-sae}, %xmm26, %xmm13, %xmm30 + +// CHECK: vfmsub213ss (%rcx), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xab,0x31] + vfmsub213ss (%rcx), %xmm13, %xmm30 + +// CHECK: vfmsub213ss 291(%rax,%r14,8), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x22,0x15,0x08,0xab,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub213ss 291(%rax,%r14,8), %xmm13, %xmm30 + +// CHECK: vfmsub213ss 508(%rdx), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xab,0x72,0x7f] + vfmsub213ss 508(%rdx), %xmm13, %xmm30 + +// CHECK: vfmsub213ss 512(%rdx), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xab,0xb2,0x00,0x02,0x00,0x00] + vfmsub213ss 512(%rdx), %xmm13, %xmm30 + +// CHECK: vfmsub213ss -512(%rdx), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xab,0x72,0x80] + vfmsub213ss -512(%rdx), %xmm13, %xmm30 + +// CHECK: vfmsub213ss -516(%rdx), %xmm13, %xmm30 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xab,0xb2,0xfc,0xfd,0xff,0xff] + vfmsub213ss -516(%rdx), %xmm13, %xmm30 + +// CHECK: vfmsub213sd %xmm12, %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x42,0xbd,0x08,0xab,0xd4] + vfmsub213sd %xmm12, %xmm8, %xmm26 + +// CHECK: vfmsub213sd %xmm12, %xmm8, %xmm6 {%k1} +// CHECK: encoding: [0x62,0xd2,0xbd,0x09,0xab,0xf4] + vfmsub213sd %xmm12, %xmm8, %xmm6 {%k1} + +// CHECK: vfmsub213sd %xmm12, %xmm8, %xmm6 {%k1} {z} +// CHECK: encoding: [0x62,0xd2,0xbd,0x89,0xab,0xf4] + vfmsub213sd %xmm12, %xmm8, %xmm6 {%k1} {z} + +// CHECK: vfmsub213sd {rn-sae}, %xmm12, %xmm8, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xbd,0x18,0xab,0xf4] + vfmsub213sd {rn-sae}, %xmm12, %xmm8, %xmm6 + +// CHECK: vfmsub213sd {ru-sae}, %xmm12, %xmm8, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xbd,0x58,0xab,0xf4] + vfmsub213sd {ru-sae}, %xmm12, %xmm8, %xmm6 + +// CHECK: vfmsub213sd {rd-sae}, %xmm12, %xmm8, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xbd,0x38,0xab,0xf4] + vfmsub213sd {rd-sae}, %xmm12, %xmm8, %xmm6 + +// CHECK: vfmsub213sd {rz-sae}, %xmm12, %xmm8, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xbd,0x78,0xab,0xf4] + vfmsub213sd {rz-sae}, %xmm12, %xmm8, %xmm6 + +// CHECK: vfmsub213sd (%rcx), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x62,0xbd,0x08,0xab,0x11] + vfmsub213sd (%rcx), %xmm8, %xmm26 + +// CHECK: vfmsub213sd 291(%rax,%r14,8), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x22,0xbd,0x08,0xab,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsub213sd 291(%rax,%r14,8), %xmm8, %xmm26 + +// CHECK: vfmsub213sd 1016(%rdx), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x62,0xbd,0x08,0xab,0x52,0x7f] + vfmsub213sd 1016(%rdx), %xmm8, %xmm26 + +// CHECK: vfmsub213sd 1024(%rdx), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x62,0xbd,0x08,0xab,0x92,0x00,0x04,0x00,0x00] + vfmsub213sd 1024(%rdx), %xmm8, %xmm26 + +// CHECK: vfmsub213sd -1024(%rdx), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x62,0xbd,0x08,0xab,0x52,0x80] + vfmsub213sd -1024(%rdx), %xmm8, %xmm26 + +// CHECK: vfmsub213sd -1032(%rdx), %xmm8, %xmm26 +// CHECK: encoding: [0x62,0x62,0xbd,0x08,0xab,0x92,0xf8,0xfb,0xff,0xff] + vfmsub213sd -1032(%rdx), %xmm8, %xmm26 + +// CHECK: vfmsub231ss %xmm5, %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0xed] + vfmsub231ss %xmm5, %xmm3, %xmm29 + +// CHECK: vfmsub231ss %xmm5, %xmm3, %xmm29 {%k6} +// CHECK: encoding: [0x62,0x62,0x65,0x0e,0xbb,0xed] + vfmsub231ss %xmm5, %xmm3, %xmm29 {%k6} + +// CHECK: vfmsub231ss %xmm5, %xmm3, %xmm29 {%k6} {z} +// CHECK: encoding: [0x62,0x62,0x65,0x8e,0xbb,0xed] + vfmsub231ss %xmm5, %xmm3, %xmm29 {%k6} {z} + +// CHECK: vfmsub231ss {rn-sae}, %xmm5, %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x18,0xbb,0xed] + vfmsub231ss {rn-sae}, %xmm5, %xmm3, %xmm29 + +// CHECK: vfmsub231ss {ru-sae}, %xmm5, %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x58,0xbb,0xed] + vfmsub231ss {ru-sae}, %xmm5, %xmm3, %xmm29 + +// CHECK: vfmsub231ss {rd-sae}, %xmm5, %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x38,0xbb,0xed] + vfmsub231ss {rd-sae}, %xmm5, %xmm3, %xmm29 + +// CHECK: vfmsub231ss {rz-sae}, %xmm5, %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x78,0xbb,0xed] + vfmsub231ss {rz-sae}, %xmm5, %xmm3, %xmm29 + +// CHECK: vfmsub231ss (%rcx), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0x29] + vfmsub231ss (%rcx), %xmm3, %xmm29 + +// CHECK: vfmsub231ss 291(%rax,%r14,8), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x22,0x65,0x08,0xbb,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmsub231ss 291(%rax,%r14,8), %xmm3, %xmm29 + +// CHECK: vfmsub231ss 508(%rdx), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0x6a,0x7f] + vfmsub231ss 508(%rdx), %xmm3, %xmm29 + +// CHECK: vfmsub231ss 512(%rdx), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0xaa,0x00,0x02,0x00,0x00] + vfmsub231ss 512(%rdx), %xmm3, %xmm29 + +// CHECK: vfmsub231ss -512(%rdx), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0x6a,0x80] + vfmsub231ss -512(%rdx), %xmm3, %xmm29 + +// CHECK: vfmsub231ss -516(%rdx), %xmm3, %xmm29 +// CHECK: encoding: [0x62,0x62,0x65,0x08,0xbb,0xaa,0xfc,0xfd,0xff,0xff] + vfmsub231ss -516(%rdx), %xmm3, %xmm29 + +// CHECK: vfmsub231sd %xmm6, %xmm11, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0xa1,0xbb,0xde] + vfmsub231sd %xmm6, %xmm11, %xmm3 + +// CHECK: vfmsub231sd %xmm6, %xmm11, %xmm3 {%k7} +// CHECK: encoding: [0x62,0xf2,0xa5,0x0f,0xbb,0xde] + vfmsub231sd %xmm6, %xmm11, %xmm3 {%k7} + +// CHECK: vfmsub231sd %xmm6, %xmm11, %xmm3 {%k7} {z} +// CHECK: encoding: [0x62,0xf2,0xa5,0x8f,0xbb,0xde] + vfmsub231sd %xmm6, %xmm11, %xmm3 {%k7} {z} + +// CHECK: vfmsub231sd {rn-sae}, %xmm6, %xmm11, %xmm3 +// CHECK: encoding: [0x62,0xf2,0xa5,0x18,0xbb,0xde] + vfmsub231sd {rn-sae}, %xmm6, %xmm11, %xmm3 + +// CHECK: vfmsub231sd {ru-sae}, %xmm6, %xmm11, %xmm3 +// CHECK: encoding: [0x62,0xf2,0xa5,0x58,0xbb,0xde] + vfmsub231sd {ru-sae}, %xmm6, %xmm11, %xmm3 + +// CHECK: vfmsub231sd {rd-sae}, %xmm6, %xmm11, %xmm3 +// CHECK: encoding: [0x62,0xf2,0xa5,0x38,0xbb,0xde] + vfmsub231sd {rd-sae}, %xmm6, %xmm11, %xmm3 + +// CHECK: vfmsub231sd {rz-sae}, %xmm6, %xmm11, %xmm3 +// CHECK: encoding: [0x62,0xf2,0xa5,0x78,0xbb,0xde] + vfmsub231sd {rz-sae}, %xmm6, %xmm11, %xmm3 + +// CHECK: vfmsub231sd (%rcx), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xa5,0x08,0xbb,0x39] + vfmsub231sd (%rcx), %xmm11, %xmm23 + +// CHECK: vfmsub231sd 291(%rax,%r14,8), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xa2,0xa5,0x08,0xbb,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmsub231sd 291(%rax,%r14,8), %xmm11, %xmm23 + +// CHECK: vfmsub231sd 1016(%rdx), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xa5,0x08,0xbb,0x7a,0x7f] + vfmsub231sd 1016(%rdx), %xmm11, %xmm23 + +// CHECK: vfmsub231sd 1024(%rdx), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xa5,0x08,0xbb,0xba,0x00,0x04,0x00,0x00] + vfmsub231sd 1024(%rdx), %xmm11, %xmm23 + +// CHECK: vfmsub231sd -1024(%rdx), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xa5,0x08,0xbb,0x7a,0x80] + vfmsub231sd -1024(%rdx), %xmm11, %xmm23 + +// CHECK: vfmsub231sd -1032(%rdx), %xmm11, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xa5,0x08,0xbb,0xba,0xf8,0xfb,0xff,0xff] + vfmsub231sd -1032(%rdx), %xmm11, %xmm23 + +// CHECK: vfnmadd132ss %xmm23, %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x08,0x9d,0xcf] + vfnmadd132ss %xmm23, %xmm1, %xmm25 + +// CHECK: vfnmadd132ss %xmm23, %xmm1, %xmm25 {%k3} +// CHECK: encoding: [0x62,0x22,0x75,0x0b,0x9d,0xcf] + vfnmadd132ss %xmm23, %xmm1, %xmm25 {%k3} + +// CHECK: vfnmadd132ss %xmm23, %xmm1, %xmm25 {%k3} {z} +// CHECK: encoding: [0x62,0x22,0x75,0x8b,0x9d,0xcf] + vfnmadd132ss %xmm23, %xmm1, %xmm25 {%k3} {z} + +// CHECK: vfnmadd132ss {rn-sae}, %xmm23, %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x18,0x9d,0xcf] + vfnmadd132ss {rn-sae}, %xmm23, %xmm1, %xmm25 + +// CHECK: vfnmadd132ss {ru-sae}, %xmm23, %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x58,0x9d,0xcf] + vfnmadd132ss {ru-sae}, %xmm23, %xmm1, %xmm25 + +// CHECK: vfnmadd132ss {rd-sae}, %xmm23, %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x38,0x9d,0xcf] + vfnmadd132ss {rd-sae}, %xmm23, %xmm1, %xmm25 + +// CHECK: vfnmadd132ss {rz-sae}, %xmm23, %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x78,0x9d,0xcf] + vfnmadd132ss {rz-sae}, %xmm23, %xmm1, %xmm25 + +// CHECK: vfnmadd132ss (%rcx), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x62,0x75,0x08,0x9d,0x09] + vfnmadd132ss (%rcx), %xmm1, %xmm25 + +// CHECK: vfnmadd132ss 291(%rax,%r14,8), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x22,0x75,0x08,0x9d,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132ss 291(%rax,%r14,8), %xmm1, %xmm25 + +// CHECK: vfnmadd132ss 508(%rdx), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x62,0x75,0x08,0x9d,0x4a,0x7f] + vfnmadd132ss 508(%rdx), %xmm1, %xmm25 + +// CHECK: vfnmadd132ss 512(%rdx), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x62,0x75,0x08,0x9d,0x8a,0x00,0x02,0x00,0x00] + vfnmadd132ss 512(%rdx), %xmm1, %xmm25 + +// CHECK: vfnmadd132ss -512(%rdx), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x62,0x75,0x08,0x9d,0x4a,0x80] + vfnmadd132ss -512(%rdx), %xmm1, %xmm25 + +// CHECK: vfnmadd132ss -516(%rdx), %xmm1, %xmm25 +// CHECK: encoding: [0x62,0x62,0x75,0x08,0x9d,0x8a,0xfc,0xfd,0xff,0xff] + vfnmadd132ss -516(%rdx), %xmm1, %xmm25 + +// CHECK: vfnmadd132sd %xmm11, %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xc2,0xe5,0x08,0x9d,0xdb] + vfnmadd132sd %xmm11, %xmm3, %xmm19 + +// CHECK: vfnmadd132sd %xmm11, %xmm3, %xmm19 {%k2} +// CHECK: encoding: [0x62,0xc2,0xe5,0x0a,0x9d,0xdb] + vfnmadd132sd %xmm11, %xmm3, %xmm19 {%k2} + +// CHECK: vfnmadd132sd %xmm11, %xmm3, %xmm19 {%k2} {z} +// CHECK: encoding: [0x62,0xc2,0xe5,0x8a,0x9d,0xdb] + vfnmadd132sd %xmm11, %xmm3, %xmm19 {%k2} {z} + +// CHECK: vfnmadd132sd {rn-sae}, %xmm11, %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xc2,0xe5,0x18,0x9d,0xdb] + vfnmadd132sd {rn-sae}, %xmm11, %xmm3, %xmm19 + +// CHECK: vfnmadd132sd {ru-sae}, %xmm11, %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xc2,0xe5,0x58,0x9d,0xdb] + vfnmadd132sd {ru-sae}, %xmm11, %xmm3, %xmm19 + +// CHECK: vfnmadd132sd {rd-sae}, %xmm11, %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xc2,0xe5,0x38,0x9d,0xdb] + vfnmadd132sd {rd-sae}, %xmm11, %xmm3, %xmm19 + +// CHECK: vfnmadd132sd {rz-sae}, %xmm11, %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xc2,0xe5,0x78,0x9d,0xdb] + vfnmadd132sd {rz-sae}, %xmm11, %xmm3, %xmm19 + +// CHECK: vfnmadd132sd (%rcx), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x08,0x9d,0x19] + vfnmadd132sd (%rcx), %xmm3, %xmm19 + +// CHECK: vfnmadd132sd 291(%rax,%r14,8), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xe5,0x08,0x9d,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132sd 291(%rax,%r14,8), %xmm3, %xmm19 + +// CHECK: vfnmadd132sd 1016(%rdx), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x08,0x9d,0x5a,0x7f] + vfnmadd132sd 1016(%rdx), %xmm3, %xmm19 + +// CHECK: vfnmadd132sd 1024(%rdx), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x08,0x9d,0x9a,0x00,0x04,0x00,0x00] + vfnmadd132sd 1024(%rdx), %xmm3, %xmm19 + +// CHECK: vfnmadd132sd -1024(%rdx), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x08,0x9d,0x5a,0x80] + vfnmadd132sd -1024(%rdx), %xmm3, %xmm19 + +// CHECK: vfnmadd132sd -1032(%rdx), %xmm3, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x08,0x9d,0x9a,0xf8,0xfb,0xff,0xff] + vfnmadd132sd -1032(%rdx), %xmm3, %xmm19 + +// CHECK: vfnmadd213ss %xmm28, %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x02,0x45,0x08,0xad,0xec] + vfnmadd213ss %xmm28, %xmm7, %xmm29 + +// CHECK: vfnmadd213ss %xmm28, %xmm7, %xmm29 {%k2} +// CHECK: encoding: [0x62,0x02,0x45,0x0a,0xad,0xec] + vfnmadd213ss %xmm28, %xmm7, %xmm29 {%k2} + +// CHECK: vfnmadd213ss %xmm28, %xmm7, %xmm29 {%k2} {z} +// CHECK: encoding: [0x62,0x02,0x45,0x8a,0xad,0xec] + vfnmadd213ss %xmm28, %xmm7, %xmm29 {%k2} {z} + +// CHECK: vfnmadd213ss {rn-sae}, %xmm28, %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x02,0x45,0x18,0xad,0xec] + vfnmadd213ss {rn-sae}, %xmm28, %xmm7, %xmm29 + +// CHECK: vfnmadd213ss {ru-sae}, %xmm28, %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x02,0x45,0x58,0xad,0xec] + vfnmadd213ss {ru-sae}, %xmm28, %xmm7, %xmm29 + +// CHECK: vfnmadd213ss {rd-sae}, %xmm28, %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x02,0x45,0x38,0xad,0xec] + vfnmadd213ss {rd-sae}, %xmm28, %xmm7, %xmm29 + +// CHECK: vfnmadd213ss {rz-sae}, %xmm28, %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x02,0x45,0x78,0xad,0xec] + vfnmadd213ss {rz-sae}, %xmm28, %xmm7, %xmm29 + +// CHECK: vfnmadd213ss (%rcx), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x62,0x45,0x08,0xad,0x29] + vfnmadd213ss (%rcx), %xmm7, %xmm29 + +// CHECK: vfnmadd213ss 291(%rax,%r14,8), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x22,0x45,0x08,0xad,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213ss 291(%rax,%r14,8), %xmm7, %xmm29 + +// CHECK: vfnmadd213ss 508(%rdx), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x62,0x45,0x08,0xad,0x6a,0x7f] + vfnmadd213ss 508(%rdx), %xmm7, %xmm29 + +// CHECK: vfnmadd213ss 512(%rdx), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x62,0x45,0x08,0xad,0xaa,0x00,0x02,0x00,0x00] + vfnmadd213ss 512(%rdx), %xmm7, %xmm29 + +// CHECK: vfnmadd213ss -512(%rdx), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x62,0x45,0x08,0xad,0x6a,0x80] + vfnmadd213ss -512(%rdx), %xmm7, %xmm29 + +// CHECK: vfnmadd213ss -516(%rdx), %xmm7, %xmm29 +// CHECK: encoding: [0x62,0x62,0x45,0x08,0xad,0xaa,0xfc,0xfd,0xff,0xff] + vfnmadd213ss -516(%rdx), %xmm7, %xmm29 + +// CHECK: vfnmadd213sd %xmm2, %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0xea] + vfnmadd213sd %xmm2, %xmm27, %xmm13 + +// CHECK: vfnmadd213sd %xmm2, %xmm27, %xmm13 {%k7} +// CHECK: encoding: [0x62,0x72,0xa5,0x07,0xad,0xea] + vfnmadd213sd %xmm2, %xmm27, %xmm13 {%k7} + +// CHECK: vfnmadd213sd %xmm2, %xmm27, %xmm13 {%k7} {z} +// CHECK: encoding: [0x62,0x72,0xa5,0x87,0xad,0xea] + vfnmadd213sd %xmm2, %xmm27, %xmm13 {%k7} {z} + +// CHECK: vfnmadd213sd {rn-sae}, %xmm2, %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x10,0xad,0xea] + vfnmadd213sd {rn-sae}, %xmm2, %xmm27, %xmm13 + +// CHECK: vfnmadd213sd {ru-sae}, %xmm2, %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x50,0xad,0xea] + vfnmadd213sd {ru-sae}, %xmm2, %xmm27, %xmm13 + +// CHECK: vfnmadd213sd {rd-sae}, %xmm2, %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x30,0xad,0xea] + vfnmadd213sd {rd-sae}, %xmm2, %xmm27, %xmm13 + +// CHECK: vfnmadd213sd {rz-sae}, %xmm2, %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x70,0xad,0xea] + vfnmadd213sd {rz-sae}, %xmm2, %xmm27, %xmm13 + +// CHECK: vfnmadd213sd (%rcx), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0x29] + vfnmadd213sd (%rcx), %xmm27, %xmm13 + +// CHECK: vfnmadd213sd 291(%rax,%r14,8), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x32,0xa5,0x00,0xad,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213sd 291(%rax,%r14,8), %xmm27, %xmm13 + +// CHECK: vfnmadd213sd 1016(%rdx), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0x6a,0x7f] + vfnmadd213sd 1016(%rdx), %xmm27, %xmm13 + +// CHECK: vfnmadd213sd 1024(%rdx), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0xaa,0x00,0x04,0x00,0x00] + vfnmadd213sd 1024(%rdx), %xmm27, %xmm13 + +// CHECK: vfnmadd213sd -1024(%rdx), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0x6a,0x80] + vfnmadd213sd -1024(%rdx), %xmm27, %xmm13 + +// CHECK: vfnmadd213sd -1032(%rdx), %xmm27, %xmm13 +// CHECK: encoding: [0x62,0x72,0xa5,0x00,0xad,0xaa,0xf8,0xfb,0xff,0xff] + vfnmadd213sd -1032(%rdx), %xmm27, %xmm13 + +// CHECK: vfnmadd231ss %xmm17, %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x08,0xbd,0xd9] + vfnmadd231ss %xmm17, %xmm2, %xmm27 + +// CHECK: vfnmadd231ss %xmm17, %xmm2, %xmm27 {%k1} +// CHECK: encoding: [0x62,0x22,0x6d,0x09,0xbd,0xd9] + vfnmadd231ss %xmm17, %xmm2, %xmm27 {%k1} + +// CHECK: vfnmadd231ss %xmm17, %xmm2, %xmm27 {%k1} {z} +// CHECK: encoding: [0x62,0x22,0x6d,0x89,0xbd,0xd9] + vfnmadd231ss %xmm17, %xmm2, %xmm27 {%k1} {z} + +// CHECK: vfnmadd231ss {rn-sae}, %xmm17, %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x18,0xbd,0xd9] + vfnmadd231ss {rn-sae}, %xmm17, %xmm2, %xmm27 + +// CHECK: vfnmadd231ss {ru-sae}, %xmm17, %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x58,0xbd,0xd9] + vfnmadd231ss {ru-sae}, %xmm17, %xmm2, %xmm27 + +// CHECK: vfnmadd231ss {rd-sae}, %xmm17, %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x38,0xbd,0xd9] + vfnmadd231ss {rd-sae}, %xmm17, %xmm2, %xmm27 + +// CHECK: vfnmadd231ss {rz-sae}, %xmm17, %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x78,0xbd,0xd9] + vfnmadd231ss {rz-sae}, %xmm17, %xmm2, %xmm27 + +// CHECK: vfnmadd231ss (%rcx), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x62,0x6d,0x08,0xbd,0x19] + vfnmadd231ss (%rcx), %xmm2, %xmm27 + +// CHECK: vfnmadd231ss 291(%rax,%r14,8), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x22,0x6d,0x08,0xbd,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231ss 291(%rax,%r14,8), %xmm2, %xmm27 + +// CHECK: vfnmadd231ss 508(%rdx), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x62,0x6d,0x08,0xbd,0x5a,0x7f] + vfnmadd231ss 508(%rdx), %xmm2, %xmm27 + +// CHECK: vfnmadd231ss 512(%rdx), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x62,0x6d,0x08,0xbd,0x9a,0x00,0x02,0x00,0x00] + vfnmadd231ss 512(%rdx), %xmm2, %xmm27 + +// CHECK: vfnmadd231ss -512(%rdx), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x62,0x6d,0x08,0xbd,0x5a,0x80] + vfnmadd231ss -512(%rdx), %xmm2, %xmm27 + +// CHECK: vfnmadd231ss -516(%rdx), %xmm2, %xmm27 +// CHECK: encoding: [0x62,0x62,0x6d,0x08,0xbd,0x9a,0xfc,0xfd,0xff,0xff] + vfnmadd231ss -516(%rdx), %xmm2, %xmm27 + +// CHECK: vfnmadd231sd %xmm18, %xmm11, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xa5,0x08,0xbd,0xf2] + vfnmadd231sd %xmm18, %xmm11, %xmm6 + +// CHECK: vfnmadd231sd %xmm18, %xmm11, %xmm6 {%k3} +// CHECK: encoding: [0x62,0xb2,0xa5,0x0b,0xbd,0xf2] + vfnmadd231sd %xmm18, %xmm11, %xmm6 {%k3} + +// CHECK: vfnmadd231sd %xmm18, %xmm11, %xmm6 {%k3} {z} +// CHECK: encoding: [0x62,0xb2,0xa5,0x8b,0xbd,0xf2] + vfnmadd231sd %xmm18, %xmm11, %xmm6 {%k3} {z} + +// CHECK: vfnmadd231sd {rn-sae}, %xmm18, %xmm11, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xa5,0x18,0xbd,0xf2] + vfnmadd231sd {rn-sae}, %xmm18, %xmm11, %xmm6 + +// CHECK: vfnmadd231sd {ru-sae}, %xmm18, %xmm11, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xa5,0x58,0xbd,0xf2] + vfnmadd231sd {ru-sae}, %xmm18, %xmm11, %xmm6 + +// CHECK: vfnmadd231sd {rd-sae}, %xmm18, %xmm11, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xa5,0x38,0xbd,0xf2] + vfnmadd231sd {rd-sae}, %xmm18, %xmm11, %xmm6 + +// CHECK: vfnmadd231sd {rz-sae}, %xmm18, %xmm11, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xa5,0x78,0xbd,0xf2] + vfnmadd231sd {rz-sae}, %xmm18, %xmm11, %xmm6 + +// CHECK: vfnmadd231sd (%rcx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0xbd,0x11] + vfnmadd231sd (%rcx), %xmm11, %xmm26 + +// CHECK: vfnmadd231sd 291(%rax,%r14,8), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x22,0xa5,0x08,0xbd,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231sd 291(%rax,%r14,8), %xmm11, %xmm26 + +// CHECK: vfnmadd231sd 1016(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0xbd,0x52,0x7f] + vfnmadd231sd 1016(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmadd231sd 1024(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0xbd,0x92,0x00,0x04,0x00,0x00] + vfnmadd231sd 1024(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmadd231sd -1024(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0xbd,0x52,0x80] + vfnmadd231sd -1024(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmadd231sd -1032(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0xbd,0x92,0xf8,0xfb,0xff,0xff] + vfnmadd231sd -1032(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmsub132ss %xmm24, %xmm22, %xmm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x00,0x9f,0xf8] + vfnmsub132ss %xmm24, %xmm22, %xmm23 + +// CHECK: vfnmsub132ss %xmm24, %xmm22, %xmm23 {%k6} +// CHECK: encoding: [0x62,0x82,0x4d,0x06,0x9f,0xf8] + vfnmsub132ss %xmm24, %xmm22, %xmm23 {%k6} + +// CHECK: vfnmsub132ss %xmm24, %xmm22, %xmm23 {%k6} {z} +// CHECK: encoding: [0x62,0x82,0x4d,0x86,0x9f,0xf8] + vfnmsub132ss %xmm24, %xmm22, %xmm23 {%k6} {z} + +// CHECK: vfnmsub132ss {rn-sae}, %xmm24, %xmm22, %xmm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x10,0x9f,0xf8] + vfnmsub132ss {rn-sae}, %xmm24, %xmm22, %xmm23 + +// CHECK: vfnmsub132ss {ru-sae}, %xmm24, %xmm22, %xmm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x50,0x9f,0xf8] + vfnmsub132ss {ru-sae}, %xmm24, %xmm22, %xmm23 + +// CHECK: vfnmsub132ss {rd-sae}, %xmm24, %xmm22, %xmm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x30,0x9f,0xf8] + vfnmsub132ss {rd-sae}, %xmm24, %xmm22, %xmm23 + +// CHECK: vfnmsub132ss {rz-sae}, %xmm24, %xmm22, %xmm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x70,0x9f,0xf8] + vfnmsub132ss {rz-sae}, %xmm24, %xmm22, %xmm23 + +// CHECK: vfnmsub132ss (%rcx), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x00,0x9f,0x39] + vfnmsub132ss (%rcx), %xmm22, %xmm23 + +// CHECK: vfnmsub132ss 291(%rax,%r14,8), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xa2,0x4d,0x00,0x9f,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132ss 291(%rax,%r14,8), %xmm22, %xmm23 + +// CHECK: vfnmsub132ss 508(%rdx), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x00,0x9f,0x7a,0x7f] + vfnmsub132ss 508(%rdx), %xmm22, %xmm23 + +// CHECK: vfnmsub132ss 512(%rdx), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x00,0x9f,0xba,0x00,0x02,0x00,0x00] + vfnmsub132ss 512(%rdx), %xmm22, %xmm23 + +// CHECK: vfnmsub132ss -512(%rdx), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x00,0x9f,0x7a,0x80] + vfnmsub132ss -512(%rdx), %xmm22, %xmm23 + +// CHECK: vfnmsub132ss -516(%rdx), %xmm22, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x00,0x9f,0xba,0xfc,0xfd,0xff,0xff] + vfnmsub132ss -516(%rdx), %xmm22, %xmm23 + +// CHECK: vfnmsub132sd %xmm13, %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x42,0xa5,0x08,0x9f,0xd5] + vfnmsub132sd %xmm13, %xmm11, %xmm26 + +// CHECK: vfnmsub132sd %xmm13, %xmm11, %xmm26 {%k6} +// CHECK: encoding: [0x62,0x42,0xa5,0x0e,0x9f,0xd5] + vfnmsub132sd %xmm13, %xmm11, %xmm26 {%k6} + +// CHECK: vfnmsub132sd %xmm13, %xmm11, %xmm26 {%k6} {z} +// CHECK: encoding: [0x62,0x42,0xa5,0x8e,0x9f,0xd5] + vfnmsub132sd %xmm13, %xmm11, %xmm26 {%k6} {z} + +// CHECK: vfnmsub132sd {rn-sae}, %xmm13, %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x42,0xa5,0x18,0x9f,0xd5] + vfnmsub132sd {rn-sae}, %xmm13, %xmm11, %xmm26 + +// CHECK: vfnmsub132sd {ru-sae}, %xmm13, %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x42,0xa5,0x58,0x9f,0xd5] + vfnmsub132sd {ru-sae}, %xmm13, %xmm11, %xmm26 + +// CHECK: vfnmsub132sd {rd-sae}, %xmm13, %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x42,0xa5,0x38,0x9f,0xd5] + vfnmsub132sd {rd-sae}, %xmm13, %xmm11, %xmm26 + +// CHECK: vfnmsub132sd {rz-sae}, %xmm13, %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x42,0xa5,0x78,0x9f,0xd5] + vfnmsub132sd {rz-sae}, %xmm13, %xmm11, %xmm26 + +// CHECK: vfnmsub132sd (%rcx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0x9f,0x11] + vfnmsub132sd (%rcx), %xmm11, %xmm26 + +// CHECK: vfnmsub132sd 291(%rax,%r14,8), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x22,0xa5,0x08,0x9f,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132sd 291(%rax,%r14,8), %xmm11, %xmm26 + +// CHECK: vfnmsub132sd 1016(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0x9f,0x52,0x7f] + vfnmsub132sd 1016(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmsub132sd 1024(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0x9f,0x92,0x00,0x04,0x00,0x00] + vfnmsub132sd 1024(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmsub132sd -1024(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0x9f,0x52,0x80] + vfnmsub132sd -1024(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmsub132sd -1032(%rdx), %xmm11, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x08,0x9f,0x92,0xf8,0xfb,0xff,0xff] + vfnmsub132sd -1032(%rdx), %xmm11, %xmm26 + +// CHECK: vfnmsub213ss %xmm12, %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x52,0x1d,0x00,0xaf,0xf4] + vfnmsub213ss %xmm12, %xmm28, %xmm14 + +// CHECK: vfnmsub213ss %xmm12, %xmm28, %xmm14 {%k4} +// CHECK: encoding: [0x62,0x52,0x1d,0x04,0xaf,0xf4] + vfnmsub213ss %xmm12, %xmm28, %xmm14 {%k4} + +// CHECK: vfnmsub213ss %xmm12, %xmm28, %xmm14 {%k4} {z} +// CHECK: encoding: [0x62,0x52,0x1d,0x84,0xaf,0xf4] + vfnmsub213ss %xmm12, %xmm28, %xmm14 {%k4} {z} + +// CHECK: vfnmsub213ss {rn-sae}, %xmm12, %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x52,0x1d,0x10,0xaf,0xf4] + vfnmsub213ss {rn-sae}, %xmm12, %xmm28, %xmm14 + +// CHECK: vfnmsub213ss {ru-sae}, %xmm12, %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x52,0x1d,0x50,0xaf,0xf4] + vfnmsub213ss {ru-sae}, %xmm12, %xmm28, %xmm14 + +// CHECK: vfnmsub213ss {rd-sae}, %xmm12, %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x52,0x1d,0x30,0xaf,0xf4] + vfnmsub213ss {rd-sae}, %xmm12, %xmm28, %xmm14 + +// CHECK: vfnmsub213ss {rz-sae}, %xmm12, %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x52,0x1d,0x70,0xaf,0xf4] + vfnmsub213ss {rz-sae}, %xmm12, %xmm28, %xmm14 + +// CHECK: vfnmsub213ss (%rcx), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x72,0x1d,0x00,0xaf,0x31] + vfnmsub213ss (%rcx), %xmm28, %xmm14 + +// CHECK: vfnmsub213ss 291(%rax,%r14,8), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x32,0x1d,0x00,0xaf,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213ss 291(%rax,%r14,8), %xmm28, %xmm14 + +// CHECK: vfnmsub213ss 508(%rdx), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x72,0x1d,0x00,0xaf,0x72,0x7f] + vfnmsub213ss 508(%rdx), %xmm28, %xmm14 + +// CHECK: vfnmsub213ss 512(%rdx), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x72,0x1d,0x00,0xaf,0xb2,0x00,0x02,0x00,0x00] + vfnmsub213ss 512(%rdx), %xmm28, %xmm14 + +// CHECK: vfnmsub213ss -512(%rdx), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x72,0x1d,0x00,0xaf,0x72,0x80] + vfnmsub213ss -512(%rdx), %xmm28, %xmm14 + +// CHECK: vfnmsub213ss -516(%rdx), %xmm28, %xmm14 +// CHECK: encoding: [0x62,0x72,0x1d,0x00,0xaf,0xb2,0xfc,0xfd,0xff,0xff] + vfnmsub213ss -516(%rdx), %xmm28, %xmm14 + +// CHECK: vfnmsub213sd %xmm28, %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x02,0xc5,0x00,0xaf,0xec] + vfnmsub213sd %xmm28, %xmm23, %xmm29 + +// CHECK: vfnmsub213sd %xmm28, %xmm23, %xmm29 {%k3} +// CHECK: encoding: [0x62,0x02,0xc5,0x03,0xaf,0xec] + vfnmsub213sd %xmm28, %xmm23, %xmm29 {%k3} + +// CHECK: vfnmsub213sd %xmm28, %xmm23, %xmm29 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0xc5,0x83,0xaf,0xec] + vfnmsub213sd %xmm28, %xmm23, %xmm29 {%k3} {z} + +// CHECK: vfnmsub213sd {rn-sae}, %xmm28, %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x02,0xc5,0x10,0xaf,0xec] + vfnmsub213sd {rn-sae}, %xmm28, %xmm23, %xmm29 + +// CHECK: vfnmsub213sd {ru-sae}, %xmm28, %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x02,0xc5,0x50,0xaf,0xec] + vfnmsub213sd {ru-sae}, %xmm28, %xmm23, %xmm29 + +// CHECK: vfnmsub213sd {rd-sae}, %xmm28, %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x02,0xc5,0x30,0xaf,0xec] + vfnmsub213sd {rd-sae}, %xmm28, %xmm23, %xmm29 + +// CHECK: vfnmsub213sd {rz-sae}, %xmm28, %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x02,0xc5,0x70,0xaf,0xec] + vfnmsub213sd {rz-sae}, %xmm28, %xmm23, %xmm29 + +// CHECK: vfnmsub213sd (%rcx), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x62,0xc5,0x00,0xaf,0x29] + vfnmsub213sd (%rcx), %xmm23, %xmm29 + +// CHECK: vfnmsub213sd 291(%rax,%r14,8), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x22,0xc5,0x00,0xaf,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213sd 291(%rax,%r14,8), %xmm23, %xmm29 + +// CHECK: vfnmsub213sd 1016(%rdx), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x62,0xc5,0x00,0xaf,0x6a,0x7f] + vfnmsub213sd 1016(%rdx), %xmm23, %xmm29 + +// CHECK: vfnmsub213sd 1024(%rdx), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x62,0xc5,0x00,0xaf,0xaa,0x00,0x04,0x00,0x00] + vfnmsub213sd 1024(%rdx), %xmm23, %xmm29 + +// CHECK: vfnmsub213sd -1024(%rdx), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x62,0xc5,0x00,0xaf,0x6a,0x80] + vfnmsub213sd -1024(%rdx), %xmm23, %xmm29 + +// CHECK: vfnmsub213sd -1032(%rdx), %xmm23, %xmm29 +// CHECK: encoding: [0x62,0x62,0xc5,0x00,0xaf,0xaa,0xf8,0xfb,0xff,0xff] + vfnmsub213sd -1032(%rdx), %xmm23, %xmm29 + +// CHECK: vfnmsub231ss %xmm10, %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x42,0x15,0x08,0xbf,0xd2] + vfnmsub231ss %xmm10, %xmm13, %xmm26 + +// CHECK: vfnmsub231ss %xmm10, %xmm13, %xmm26 {%k4} +// CHECK: encoding: [0x62,0x42,0x15,0x0c,0xbf,0xd2] + vfnmsub231ss %xmm10, %xmm13, %xmm26 {%k4} + +// CHECK: vfnmsub231ss %xmm10, %xmm13, %xmm26 {%k4} {z} +// CHECK: encoding: [0x62,0x42,0x15,0x8c,0xbf,0xd2] + vfnmsub231ss %xmm10, %xmm13, %xmm26 {%k4} {z} + +// CHECK: vfnmsub231ss {rn-sae}, %xmm10, %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x42,0x15,0x18,0xbf,0xd2] + vfnmsub231ss {rn-sae}, %xmm10, %xmm13, %xmm26 + +// CHECK: vfnmsub231ss {ru-sae}, %xmm10, %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x42,0x15,0x58,0xbf,0xd2] + vfnmsub231ss {ru-sae}, %xmm10, %xmm13, %xmm26 + +// CHECK: vfnmsub231ss {rd-sae}, %xmm10, %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x42,0x15,0x38,0xbf,0xd2] + vfnmsub231ss {rd-sae}, %xmm10, %xmm13, %xmm26 + +// CHECK: vfnmsub231ss {rz-sae}, %xmm10, %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x42,0x15,0x78,0xbf,0xd2] + vfnmsub231ss {rz-sae}, %xmm10, %xmm13, %xmm26 + +// CHECK: vfnmsub231ss (%rcx), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xbf,0x11] + vfnmsub231ss (%rcx), %xmm13, %xmm26 + +// CHECK: vfnmsub231ss 291(%rax,%r14,8), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x22,0x15,0x08,0xbf,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231ss 291(%rax,%r14,8), %xmm13, %xmm26 + +// CHECK: vfnmsub231ss 508(%rdx), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xbf,0x52,0x7f] + vfnmsub231ss 508(%rdx), %xmm13, %xmm26 + +// CHECK: vfnmsub231ss 512(%rdx), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xbf,0x92,0x00,0x02,0x00,0x00] + vfnmsub231ss 512(%rdx), %xmm13, %xmm26 + +// CHECK: vfnmsub231ss -512(%rdx), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xbf,0x52,0x80] + vfnmsub231ss -512(%rdx), %xmm13, %xmm26 + +// CHECK: vfnmsub231ss -516(%rdx), %xmm13, %xmm26 +// CHECK: encoding: [0x62,0x62,0x15,0x08,0xbf,0x92,0xfc,0xfd,0xff,0xff] + vfnmsub231ss -516(%rdx), %xmm13, %xmm26 + +// CHECK: vfnmsub231sd %xmm14, %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xdd,0x00,0xbf,0xf6] + vfnmsub231sd %xmm14, %xmm20, %xmm6 + +// CHECK: vfnmsub231sd %xmm14, %xmm20, %xmm6 {%k1} +// CHECK: encoding: [0x62,0xd2,0xdd,0x01,0xbf,0xf6] + vfnmsub231sd %xmm14, %xmm20, %xmm6 {%k1} + +// CHECK: vfnmsub231sd %xmm14, %xmm20, %xmm6 {%k1} {z} +// CHECK: encoding: [0x62,0xd2,0xdd,0x81,0xbf,0xf6] + vfnmsub231sd %xmm14, %xmm20, %xmm6 {%k1} {z} + +// CHECK: vfnmsub231sd {rn-sae}, %xmm14, %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xdd,0x10,0xbf,0xf6] + vfnmsub231sd {rn-sae}, %xmm14, %xmm20, %xmm6 + +// CHECK: vfnmsub231sd {ru-sae}, %xmm14, %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xdd,0x50,0xbf,0xf6] + vfnmsub231sd {ru-sae}, %xmm14, %xmm20, %xmm6 + +// CHECK: vfnmsub231sd {rd-sae}, %xmm14, %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xdd,0x30,0xbf,0xf6] + vfnmsub231sd {rd-sae}, %xmm14, %xmm20, %xmm6 + +// CHECK: vfnmsub231sd {rz-sae}, %xmm14, %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xd2,0xdd,0x70,0xbf,0xf6] + vfnmsub231sd {rz-sae}, %xmm14, %xmm20, %xmm6 + +// CHECK: vfnmsub231sd (%rcx), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xf2,0xdd,0x00,0xbf,0x31] + vfnmsub231sd (%rcx), %xmm20, %xmm6 + +// CHECK: vfnmsub231sd 291(%rax,%r14,8), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xb2,0xdd,0x00,0xbf,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231sd 291(%rax,%r14,8), %xmm20, %xmm6 + +// CHECK: vfnmsub231sd 1016(%rdx), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xf2,0xdd,0x00,0xbf,0x72,0x7f] + vfnmsub231sd 1016(%rdx), %xmm20, %xmm6 + +// CHECK: vfnmsub231sd 1024(%rdx), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xf2,0xdd,0x00,0xbf,0xb2,0x00,0x04,0x00,0x00] + vfnmsub231sd 1024(%rdx), %xmm20, %xmm6 + +// CHECK: vfnmsub231sd -1024(%rdx), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xf2,0xdd,0x00,0xbf,0x72,0x80] + vfnmsub231sd -1024(%rdx), %xmm20, %xmm6 + +// CHECK: vfnmsub231sd -1032(%rdx), %xmm20, %xmm6 +// CHECK: encoding: [0x62,0xf2,0xdd,0x00,0xbf,0xb2,0xf8,0xfb,0xff,0xff] + vfnmsub231sd -1032(%rdx), %xmm20, %xmm6 + diff --git a/test/MC/X86/avx512vl-encoding.s b/test/MC/X86/avx512vl-encoding.s index dd1ac24b04eaa..e1fc32848ccdb 100644 --- a/test/MC/X86/avx512vl-encoding.s +++ b/test/MC/X86/avx512vl-encoding.s @@ -891,3 +891,883 @@ // CHECK: vpmovm2q %k2, %ymm30 // CHECK: encoding: [0x62,0x62,0xfe,0x28,0x38,0xf2] vpmovm2q %k2, %ymm30 + +// CHECK: vcompresspd %xmm23, (%rcx) +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x8a,0x39] + vcompresspd %xmm23, (%rcx) + +// CHECK: vcompresspd %xmm23, (%rcx) {%k6} +// CHECK: encoding: [0x62,0xe2,0xfd,0x0e,0x8a,0x39] + vcompresspd %xmm23, (%rcx) {%k6} + +// CHECK: vcompresspd %xmm23, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xa2,0xfd,0x08,0x8a,0xbc,0xf0,0x23,0x01,0x00,0x00] + vcompresspd %xmm23, 291(%rax,%r14,8) + +// CHECK: vcompresspd %xmm23, 1016(%rdx) +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x8a,0x7a,0x7f] + vcompresspd %xmm23, 1016(%rdx) + +// CHECK: vcompresspd %xmm23, 1024(%rdx) +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x8a,0xba,0x00,0x04,0x00,0x00] + vcompresspd %xmm23, 1024(%rdx) + +// CHECK: vcompresspd %xmm23, -1024(%rdx) +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x8a,0x7a,0x80] + vcompresspd %xmm23, -1024(%rdx) + +// CHECK: vcompresspd %xmm23, -1032(%rdx) +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x8a,0xba,0xf8,0xfb,0xff,0xff] + vcompresspd %xmm23, -1032(%rdx) + +// CHECK: vcompresspd %ymm29, (%rcx) +// CHECK: encoding: [0x62,0x62,0xfd,0x28,0x8a,0x29] + vcompresspd %ymm29, (%rcx) + +// CHECK: vcompresspd %ymm29, (%rcx) {%k2} +// CHECK: encoding: [0x62,0x62,0xfd,0x2a,0x8a,0x29] + vcompresspd %ymm29, (%rcx) {%k2} + +// CHECK: vcompresspd %ymm29, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x22,0xfd,0x28,0x8a,0xac,0xf0,0x23,0x01,0x00,0x00] + vcompresspd %ymm29, 291(%rax,%r14,8) + +// CHECK: vcompresspd %ymm29, 1016(%rdx) +// CHECK: encoding: [0x62,0x62,0xfd,0x28,0x8a,0x6a,0x7f] + vcompresspd %ymm29, 1016(%rdx) + +// CHECK: vcompresspd %ymm29, 1024(%rdx) +// CHECK: encoding: [0x62,0x62,0xfd,0x28,0x8a,0xaa,0x00,0x04,0x00,0x00] + vcompresspd %ymm29, 1024(%rdx) + +// CHECK: vcompresspd %ymm29, -1024(%rdx) +// CHECK: encoding: [0x62,0x62,0xfd,0x28,0x8a,0x6a,0x80] + vcompresspd %ymm29, -1024(%rdx) + +// CHECK: vcompresspd %ymm29, -1032(%rdx) +// CHECK: encoding: [0x62,0x62,0xfd,0x28,0x8a,0xaa,0xf8,0xfb,0xff,0xff] + vcompresspd %ymm29, -1032(%rdx) + +// CHECK: vcompresspd %xmm27, %xmm20 +// CHECK: encoding: [0x62,0x22,0xfd,0x08,0x8a,0xdc] + vcompresspd %xmm27, %xmm20 + +// CHECK: vcompresspd %xmm27, %xmm20 {%k2} +// CHECK: encoding: [0x62,0x22,0xfd,0x0a,0x8a,0xdc] + vcompresspd %xmm27, %xmm20 {%k2} + +// CHECK: vcompresspd %xmm27, %xmm20 {%k2} {z} +// CHECK: encoding: [0x62,0x22,0xfd,0x8a,0x8a,0xdc] + vcompresspd %xmm27, %xmm20 {%k2} {z} + +// CHECK: vcompresspd %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x82,0xfd,0x28,0x8a,0xe0] + vcompresspd %ymm20, %ymm24 + +// CHECK: vcompresspd %ymm20, %ymm24 {%k3} +// CHECK: encoding: [0x62,0x82,0xfd,0x2b,0x8a,0xe0] + vcompresspd %ymm20, %ymm24 {%k3} + +// CHECK: vcompresspd %ymm20, %ymm24 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0xfd,0xab,0x8a,0xe0] + vcompresspd %ymm20, %ymm24 {%k3} {z} + +// CHECK: vcompressps %xmm21, (%rcx) +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x8a,0x29] + vcompressps %xmm21, (%rcx) + +// CHECK: vcompressps %xmm21, (%rcx) {%k7} +// CHECK: encoding: [0x62,0xe2,0x7d,0x0f,0x8a,0x29] + vcompressps %xmm21, (%rcx) {%k7} + +// CHECK: vcompressps %xmm21, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xa2,0x7d,0x08,0x8a,0xac,0xf0,0x23,0x01,0x00,0x00] + vcompressps %xmm21, 291(%rax,%r14,8) + +// CHECK: vcompressps %xmm21, 508(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x8a,0x6a,0x7f] + vcompressps %xmm21, 508(%rdx) + +// CHECK: vcompressps %xmm21, 512(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x8a,0xaa,0x00,0x02,0x00,0x00] + vcompressps %xmm21, 512(%rdx) + +// CHECK: vcompressps %xmm21, -512(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x8a,0x6a,0x80] + vcompressps %xmm21, -512(%rdx) + +// CHECK: vcompressps %xmm21, -516(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x8a,0xaa,0xfc,0xfd,0xff,0xff] + vcompressps %xmm21, -516(%rdx) + +// CHECK: vcompressps %ymm24, (%rcx) +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x8a,0x01] + vcompressps %ymm24, (%rcx) + +// CHECK: vcompressps %ymm24, (%rcx) {%k7} +// CHECK: encoding: [0x62,0x62,0x7d,0x2f,0x8a,0x01] + vcompressps %ymm24, (%rcx) {%k7} + +// CHECK: vcompressps %ymm24, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x8a,0x84,0xf0,0x23,0x01,0x00,0x00] + vcompressps %ymm24, 291(%rax,%r14,8) + +// CHECK: vcompressps %ymm24, 508(%rdx) +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x8a,0x42,0x7f] + vcompressps %ymm24, 508(%rdx) + +// CHECK: vcompressps %ymm24, 512(%rdx) +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x8a,0x82,0x00,0x02,0x00,0x00] + vcompressps %ymm24, 512(%rdx) + +// CHECK: vcompressps %ymm24, -512(%rdx) +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x8a,0x42,0x80] + vcompressps %ymm24, -512(%rdx) + +// CHECK: vcompressps %ymm24, -516(%rdx) +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x8a,0x82,0xfc,0xfd,0xff,0xff] + vcompressps %ymm24, -516(%rdx) + +// CHECK: vcompressps %xmm29, %xmm28 +// CHECK: encoding: [0x62,0x02,0x7d,0x08,0x8a,0xec] + vcompressps %xmm29, %xmm28 + +// CHECK: vcompressps %xmm29, %xmm28 {%k3} +// CHECK: encoding: [0x62,0x02,0x7d,0x0b,0x8a,0xec] + vcompressps %xmm29, %xmm28 {%k3} + +// CHECK: vcompressps %xmm29, %xmm28 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0x7d,0x8b,0x8a,0xec] + vcompressps %xmm29, %xmm28 {%k3} {z} + +// CHECK: vcompressps %ymm25, %ymm23 +// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x8a,0xcf] + vcompressps %ymm25, %ymm23 + +// CHECK: vcompressps %ymm25, %ymm23 {%k6} +// CHECK: encoding: [0x62,0x22,0x7d,0x2e,0x8a,0xcf] + vcompressps %ymm25, %ymm23 {%k6} + +// CHECK: vcompressps %ymm25, %ymm23 {%k6} {z} +// CHECK: encoding: [0x62,0x22,0x7d,0xae,0x8a,0xcf] + vcompressps %ymm25, %ymm23 {%k6} {z} + +// CHECK: vexpandpd (%rcx), %xmm23 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x88,0x39] + vexpandpd (%rcx), %xmm23 + +// CHECK: vexpandpd (%rcx), %xmm23 {%k3} +// CHECK: encoding: [0x62,0xe2,0xfd,0x0b,0x88,0x39] + vexpandpd (%rcx), %xmm23 {%k3} + +// CHECK: vexpandpd (%rcx), %xmm23 {%k3} {z} +// CHECK: encoding: [0x62,0xe2,0xfd,0x8b,0x88,0x39] + vexpandpd (%rcx), %xmm23 {%k3} {z} + +// CHECK: vexpandpd 291(%rax,%r14,8), %xmm23 +// CHECK: encoding: [0x62,0xa2,0xfd,0x08,0x88,0xbc,0xf0,0x23,0x01,0x00,0x00] + vexpandpd 291(%rax,%r14,8), %xmm23 + +// CHECK: vexpandpd 1016(%rdx), %xmm23 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x88,0x7a,0x7f] + vexpandpd 1016(%rdx), %xmm23 + +// CHECK: vexpandpd 1024(%rdx), %xmm23 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x88,0xba,0x00,0x04,0x00,0x00] + vexpandpd 1024(%rdx), %xmm23 + +// CHECK: vexpandpd -1024(%rdx), %xmm23 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x88,0x7a,0x80] + vexpandpd -1024(%rdx), %xmm23 + +// CHECK: vexpandpd -1032(%rdx), %xmm23 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x88,0xba,0xf8,0xfb,0xff,0xff] + vexpandpd -1032(%rdx), %xmm23 + +// CHECK: vexpandpd (%rcx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x88,0x31] + vexpandpd (%rcx), %ymm22 + +// CHECK: vexpandpd (%rcx), %ymm22 {%k5} +// CHECK: encoding: [0x62,0xe2,0xfd,0x2d,0x88,0x31] + vexpandpd (%rcx), %ymm22 {%k5} + +// CHECK: vexpandpd (%rcx), %ymm22 {%k5} {z} +// CHECK: encoding: [0x62,0xe2,0xfd,0xad,0x88,0x31] + vexpandpd (%rcx), %ymm22 {%k5} {z} + +// CHECK: vexpandpd 291(%rax,%r14,8), %ymm22 +// CHECK: encoding: [0x62,0xa2,0xfd,0x28,0x88,0xb4,0xf0,0x23,0x01,0x00,0x00] + vexpandpd 291(%rax,%r14,8), %ymm22 + +// CHECK: vexpandpd 1016(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x88,0x72,0x7f] + vexpandpd 1016(%rdx), %ymm22 + +// CHECK: vexpandpd 1024(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x88,0xb2,0x00,0x04,0x00,0x00] + vexpandpd 1024(%rdx), %ymm22 + +// CHECK: vexpandpd -1024(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x88,0x72,0x80] + vexpandpd -1024(%rdx), %ymm22 + +// CHECK: vexpandpd -1032(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x88,0xb2,0xf8,0xfb,0xff,0xff] + vexpandpd -1032(%rdx), %ymm22 + +// CHECK: vexpandpd %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x02,0xfd,0x08,0x88,0xe9] + vexpandpd %xmm25, %xmm29 + +// CHECK: vexpandpd %xmm25, %xmm29 {%k7} +// CHECK: encoding: [0x62,0x02,0xfd,0x0f,0x88,0xe9] + vexpandpd %xmm25, %xmm29 {%k7} + +// CHECK: vexpandpd %xmm25, %xmm29 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0xfd,0x8f,0x88,0xe9] + vexpandpd %xmm25, %xmm29 {%k7} {z} + +// CHECK: vexpandpd %ymm27, %ymm21 +// CHECK: encoding: [0x62,0x82,0xfd,0x28,0x88,0xeb] + vexpandpd %ymm27, %ymm21 + +// CHECK: vexpandpd %ymm27, %ymm21 {%k2} +// CHECK: encoding: [0x62,0x82,0xfd,0x2a,0x88,0xeb] + vexpandpd %ymm27, %ymm21 {%k2} + +// CHECK: vexpandpd %ymm27, %ymm21 {%k2} {z} +// CHECK: encoding: [0x62,0x82,0xfd,0xaa,0x88,0xeb] + vexpandpd %ymm27, %ymm21 {%k2} {z} + +// CHECK: vexpandps (%rcx), %xmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x88,0x11] + vexpandps (%rcx), %xmm18 + +// CHECK: vexpandps (%rcx), %xmm18 {%k1} +// CHECK: encoding: [0x62,0xe2,0x7d,0x09,0x88,0x11] + vexpandps (%rcx), %xmm18 {%k1} + +// CHECK: vexpandps (%rcx), %xmm18 {%k1} {z} +// CHECK: encoding: [0x62,0xe2,0x7d,0x89,0x88,0x11] + vexpandps (%rcx), %xmm18 {%k1} {z} + +// CHECK: vexpandps 291(%rax,%r14,8), %xmm18 +// CHECK: encoding: [0x62,0xa2,0x7d,0x08,0x88,0x94,0xf0,0x23,0x01,0x00,0x00] + vexpandps 291(%rax,%r14,8), %xmm18 + +// CHECK: vexpandps 508(%rdx), %xmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x88,0x52,0x7f] + vexpandps 508(%rdx), %xmm18 + +// CHECK: vexpandps 512(%rdx), %xmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x88,0x92,0x00,0x02,0x00,0x00] + vexpandps 512(%rdx), %xmm18 + +// CHECK: vexpandps -512(%rdx), %xmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x88,0x52,0x80] + vexpandps -512(%rdx), %xmm18 + +// CHECK: vexpandps -516(%rdx), %xmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x08,0x88,0x92,0xfc,0xfd,0xff,0xff] + vexpandps -516(%rdx), %xmm18 + +// CHECK: vexpandps (%rcx), %ymm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x88,0x39] + vexpandps (%rcx), %ymm23 + +// CHECK: vexpandps (%rcx), %ymm23 {%k7} +// CHECK: encoding: [0x62,0xe2,0x7d,0x2f,0x88,0x39] + vexpandps (%rcx), %ymm23 {%k7} + +// CHECK: vexpandps (%rcx), %ymm23 {%k7} {z} +// CHECK: encoding: [0x62,0xe2,0x7d,0xaf,0x88,0x39] + vexpandps (%rcx), %ymm23 {%k7} {z} + +// CHECK: vexpandps 291(%rax,%r14,8), %ymm23 +// CHECK: encoding: [0x62,0xa2,0x7d,0x28,0x88,0xbc,0xf0,0x23,0x01,0x00,0x00] + vexpandps 291(%rax,%r14,8), %ymm23 + +// CHECK: vexpandps 508(%rdx), %ymm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x88,0x7a,0x7f] + vexpandps 508(%rdx), %ymm23 + +// CHECK: vexpandps 512(%rdx), %ymm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x88,0xba,0x00,0x02,0x00,0x00] + vexpandps 512(%rdx), %ymm23 + +// CHECK: vexpandps -512(%rdx), %ymm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x88,0x7a,0x80] + vexpandps -512(%rdx), %ymm23 + +// CHECK: vexpandps -516(%rdx), %ymm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x88,0xba,0xfc,0xfd,0xff,0xff] + vexpandps -516(%rdx), %ymm23 + +// CHECK: vexpandps %xmm19, %xmm29 +// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x88,0xeb] + vexpandps %xmm19, %xmm29 + +// CHECK: vexpandps %xmm19, %xmm29 {%k5} +// CHECK: encoding: [0x62,0x22,0x7d,0x0d,0x88,0xeb] + vexpandps %xmm19, %xmm29 {%k5} + +// CHECK: vexpandps %xmm19, %xmm29 {%k5} {z} +// CHECK: encoding: [0x62,0x22,0x7d,0x8d,0x88,0xeb] + vexpandps %xmm19, %xmm29 {%k5} {z} + +// CHECK: vexpandps %ymm29, %ymm29 +// CHECK: encoding: [0x62,0x02,0x7d,0x28,0x88,0xed] + vexpandps %ymm29, %ymm29 + +// CHECK: vexpandps %ymm29, %ymm29 {%k5} +// CHECK: encoding: [0x62,0x02,0x7d,0x2d,0x88,0xed] + vexpandps %ymm29, %ymm29 {%k5} + +// CHECK: vexpandps %ymm29, %ymm29 {%k5} {z} +// CHECK: encoding: [0x62,0x02,0x7d,0xad,0x88,0xed] + vexpandps %ymm29, %ymm29 {%k5} {z} + +// CHECK: vpabsd %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x1e,0xe3] + vpabsd %xmm19, %xmm28 + +// CHECK: vpabsd %xmm19, %xmm28 {%k6} +// CHECK: encoding: [0x62,0x22,0x7d,0x0e,0x1e,0xe3] + vpabsd %xmm19, %xmm28 {%k6} + +// CHECK: vpabsd %xmm19, %xmm28 {%k6} {z} +// CHECK: encoding: [0x62,0x22,0x7d,0x8e,0x1e,0xe3] + vpabsd %xmm19, %xmm28 {%k6} {z} + +// CHECK: vpabsd (%rcx), %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x1e,0x21] + vpabsd (%rcx), %xmm28 + +// CHECK: vpabsd 291(%rax,%r14,8), %xmm28 +// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x1e,0xa4,0xf0,0x23,0x01,0x00,0x00] + vpabsd 291(%rax,%r14,8), %xmm28 + +// CHECK: vpabsd (%rcx){1to4}, %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x18,0x1e,0x21] + vpabsd (%rcx){1to4}, %xmm28 + +// CHECK: vpabsd 2032(%rdx), %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x1e,0x62,0x7f] + vpabsd 2032(%rdx), %xmm28 + +// CHECK: vpabsd 2048(%rdx), %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x1e,0xa2,0x00,0x08,0x00,0x00] + vpabsd 2048(%rdx), %xmm28 + +// CHECK: vpabsd -2048(%rdx), %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x1e,0x62,0x80] + vpabsd -2048(%rdx), %xmm28 + +// CHECK: vpabsd -2064(%rdx), %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x1e,0xa2,0xf0,0xf7,0xff,0xff] + vpabsd -2064(%rdx), %xmm28 + +// CHECK: vpabsd 508(%rdx){1to4}, %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x18,0x1e,0x62,0x7f] + vpabsd 508(%rdx){1to4}, %xmm28 + +// CHECK: vpabsd 512(%rdx){1to4}, %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x18,0x1e,0xa2,0x00,0x02,0x00,0x00] + vpabsd 512(%rdx){1to4}, %xmm28 + +// CHECK: vpabsd -512(%rdx){1to4}, %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x18,0x1e,0x62,0x80] + vpabsd -512(%rdx){1to4}, %xmm28 + +// CHECK: vpabsd -516(%rdx){1to4}, %xmm28 +// CHECK: encoding: [0x62,0x62,0x7d,0x18,0x1e,0xa2,0xfc,0xfd,0xff,0xff] + vpabsd -516(%rdx){1to4}, %xmm28 + +// CHECK: vpabsd %ymm18, %ymm25 +// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x1e,0xca] + vpabsd %ymm18, %ymm25 + +// CHECK: vpabsd %ymm18, %ymm25 {%k2} +// CHECK: encoding: [0x62,0x22,0x7d,0x2a,0x1e,0xca] + vpabsd %ymm18, %ymm25 {%k2} + +// CHECK: vpabsd %ymm18, %ymm25 {%k2} {z} +// CHECK: encoding: [0x62,0x22,0x7d,0xaa,0x1e,0xca] + vpabsd %ymm18, %ymm25 {%k2} {z} + +// CHECK: vpabsd (%rcx), %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x1e,0x09] + vpabsd (%rcx), %ymm25 + +// CHECK: vpabsd 291(%rax,%r14,8), %ymm25 +// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x1e,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpabsd 291(%rax,%r14,8), %ymm25 + +// CHECK: vpabsd (%rcx){1to8}, %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x1e,0x09] + vpabsd (%rcx){1to8}, %ymm25 + +// CHECK: vpabsd 4064(%rdx), %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x1e,0x4a,0x7f] + vpabsd 4064(%rdx), %ymm25 + +// CHECK: vpabsd 4096(%rdx), %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x1e,0x8a,0x00,0x10,0x00,0x00] + vpabsd 4096(%rdx), %ymm25 + +// CHECK: vpabsd -4096(%rdx), %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x1e,0x4a,0x80] + vpabsd -4096(%rdx), %ymm25 + +// CHECK: vpabsd -4128(%rdx), %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x1e,0x8a,0xe0,0xef,0xff,0xff] + vpabsd -4128(%rdx), %ymm25 + +// CHECK: vpabsd 508(%rdx){1to8}, %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x1e,0x4a,0x7f] + vpabsd 508(%rdx){1to8}, %ymm25 + +// CHECK: vpabsd 512(%rdx){1to8}, %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x1e,0x8a,0x00,0x02,0x00,0x00] + vpabsd 512(%rdx){1to8}, %ymm25 + +// CHECK: vpabsd -512(%rdx){1to8}, %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x1e,0x4a,0x80] + vpabsd -512(%rdx){1to8}, %ymm25 + +// CHECK: vpabsd -516(%rdx){1to8}, %ymm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x38,0x1e,0x8a,0xfc,0xfd,0xff,0xff] + vpabsd -516(%rdx){1to8}, %ymm25 + +// CHECK: vpabsq %xmm22, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xfd,0x08,0x1f,0xde] + vpabsq %xmm22, %xmm19 + +// CHECK: vpabsq %xmm22, %xmm19 {%k2} +// CHECK: encoding: [0x62,0xa2,0xfd,0x0a,0x1f,0xde] + vpabsq %xmm22, %xmm19 {%k2} + +// CHECK: vpabsq %xmm22, %xmm19 {%k2} {z} +// CHECK: encoding: [0x62,0xa2,0xfd,0x8a,0x1f,0xde] + vpabsq %xmm22, %xmm19 {%k2} {z} + +// CHECK: vpabsq (%rcx), %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x1f,0x19] + vpabsq (%rcx), %xmm19 + +// CHECK: vpabsq 291(%rax,%r14,8), %xmm19 +// CHECK: encoding: [0x62,0xa2,0xfd,0x08,0x1f,0x9c,0xf0,0x23,0x01,0x00,0x00] + vpabsq 291(%rax,%r14,8), %xmm19 + +// CHECK: vpabsq (%rcx){1to2}, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x18,0x1f,0x19] + vpabsq (%rcx){1to2}, %xmm19 + +// CHECK: vpabsq 2032(%rdx), %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x1f,0x5a,0x7f] + vpabsq 2032(%rdx), %xmm19 + +// CHECK: vpabsq 2048(%rdx), %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x1f,0x9a,0x00,0x08,0x00,0x00] + vpabsq 2048(%rdx), %xmm19 + +// CHECK: vpabsq -2048(%rdx), %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x1f,0x5a,0x80] + vpabsq -2048(%rdx), %xmm19 + +// CHECK: vpabsq -2064(%rdx), %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x08,0x1f,0x9a,0xf0,0xf7,0xff,0xff] + vpabsq -2064(%rdx), %xmm19 + +// CHECK: vpabsq 1016(%rdx){1to2}, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x18,0x1f,0x5a,0x7f] + vpabsq 1016(%rdx){1to2}, %xmm19 + +// CHECK: vpabsq 1024(%rdx){1to2}, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x18,0x1f,0x9a,0x00,0x04,0x00,0x00] + vpabsq 1024(%rdx){1to2}, %xmm19 + +// CHECK: vpabsq -1024(%rdx){1to2}, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x18,0x1f,0x5a,0x80] + vpabsq -1024(%rdx){1to2}, %xmm19 + +// CHECK: vpabsq -1032(%rdx){1to2}, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xfd,0x18,0x1f,0x9a,0xf8,0xfb,0xff,0xff] + vpabsq -1032(%rdx){1to2}, %xmm19 + +// CHECK: vpabsq %ymm17, %ymm22 +// CHECK: encoding: [0x62,0xa2,0xfd,0x28,0x1f,0xf1] + vpabsq %ymm17, %ymm22 + +// CHECK: vpabsq %ymm17, %ymm22 {%k6} +// CHECK: encoding: [0x62,0xa2,0xfd,0x2e,0x1f,0xf1] + vpabsq %ymm17, %ymm22 {%k6} + +// CHECK: vpabsq %ymm17, %ymm22 {%k6} {z} +// CHECK: encoding: [0x62,0xa2,0xfd,0xae,0x1f,0xf1] + vpabsq %ymm17, %ymm22 {%k6} {z} + +// CHECK: vpabsq (%rcx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x1f,0x31] + vpabsq (%rcx), %ymm22 + +// CHECK: vpabsq 291(%rax,%r14,8), %ymm22 +// CHECK: encoding: [0x62,0xa2,0xfd,0x28,0x1f,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpabsq 291(%rax,%r14,8), %ymm22 + +// CHECK: vpabsq (%rcx){1to4}, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x38,0x1f,0x31] + vpabsq (%rcx){1to4}, %ymm22 + +// CHECK: vpabsq 4064(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x1f,0x72,0x7f] + vpabsq 4064(%rdx), %ymm22 + +// CHECK: vpabsq 4096(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x1f,0xb2,0x00,0x10,0x00,0x00] + vpabsq 4096(%rdx), %ymm22 + +// CHECK: vpabsq -4096(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x1f,0x72,0x80] + vpabsq -4096(%rdx), %ymm22 + +// CHECK: vpabsq -4128(%rdx), %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x28,0x1f,0xb2,0xe0,0xef,0xff,0xff] + vpabsq -4128(%rdx), %ymm22 + +// CHECK: vpabsq 1016(%rdx){1to4}, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x38,0x1f,0x72,0x7f] + vpabsq 1016(%rdx){1to4}, %ymm22 + +// CHECK: vpabsq 1024(%rdx){1to4}, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x38,0x1f,0xb2,0x00,0x04,0x00,0x00] + vpabsq 1024(%rdx){1to4}, %ymm22 + +// CHECK: vpabsq -1024(%rdx){1to4}, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x38,0x1f,0x72,0x80] + vpabsq -1024(%rdx){1to4}, %ymm22 + +// CHECK: vpabsq -1032(%rdx){1to4}, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x38,0x1f,0xb2,0xf8,0xfb,0xff,0xff] + vpabsq -1032(%rdx){1to4}, %ymm22 + +// CHECK: vpgatherdd 123(%r14,%xmm31,8), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x90,0x8c,0xfe,0x7b,0x00,0x00,0x00] + vpgatherdd 123(%r14,%xmm31,8), %xmm17 {%k1} + +// CHECK: vpgatherdd 256(%r9,%xmm31), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x90,0x4c,0x39,0x40] + vpgatherdd 256(%r9,%xmm31), %xmm17 {%k1} + +// CHECK: vpgatherdd 1024(%rcx,%xmm31,4), %xmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0x90,0x8c,0xb9,0x00,0x04,0x00,0x00] + vpgatherdd 1024(%rcx,%xmm31,4), %xmm17 {%k1} + +// CHECK: vpgatherdd 123(%r14,%ymm31,8), %ymm19 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x21,0x90,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vpgatherdd 123(%r14,%ymm31,8), %ymm19 {%k1} + +// CHECK: vpgatherdd 256(%r9,%ymm31), %ymm19 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x21,0x90,0x5c,0x39,0x40] + vpgatherdd 256(%r9,%ymm31), %ymm19 {%k1} + +// CHECK: vpgatherdd 1024(%rcx,%ymm31,4), %ymm19 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x21,0x90,0x9c,0xb9,0x00,0x04,0x00,0x00] + vpgatherdd 1024(%rcx,%ymm31,4), %ymm19 {%k1} + +// CHECK: vpgatherdq 123(%r14,%xmm31,8), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x90,0x8c,0xfe,0x7b,0x00,0x00,0x00] + vpgatherdq 123(%r14,%xmm31,8), %xmm17 {%k1} + +// CHECK: vpgatherdq 256(%r9,%xmm31), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x90,0x4c,0x39,0x20] + vpgatherdq 256(%r9,%xmm31), %xmm17 {%k1} + +// CHECK: vpgatherdq 1024(%rcx,%xmm31,4), %xmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x01,0x90,0x8c,0xb9,0x00,0x04,0x00,0x00] + vpgatherdq 1024(%rcx,%xmm31,4), %xmm17 {%k1} + +// CHECK: vpgatherdq 123(%r14,%xmm31,8), %ymm26 {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0x90,0x94,0xfe,0x7b,0x00,0x00,0x00] + vpgatherdq 123(%r14,%xmm31,8), %ymm26 {%k1} + +// CHECK: vpgatherdq 256(%r9,%xmm31), %ymm26 {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0x90,0x54,0x39,0x20] + vpgatherdq 256(%r9,%xmm31), %ymm26 {%k1} + +// CHECK: vpgatherdq 1024(%rcx,%xmm31,4), %ymm26 {%k1} +// CHECK: encoding: [0x62,0x22,0xfd,0x21,0x90,0x94,0xb9,0x00,0x04,0x00,0x00] + vpgatherdq 1024(%rcx,%xmm31,4), %ymm26 {%k1} + +// CHECK: vpgatherqd 123(%r14,%xmm31,8), %xmm21 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x91,0xac,0xfe,0x7b,0x00,0x00,0x00] + vpgatherqd 123(%r14,%xmm31,8), %xmm21 {%k1} + +// CHECK: vpgatherqd 256(%r9,%xmm31), %xmm21 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x91,0x6c,0x39,0x40] + vpgatherqd 256(%r9,%xmm31), %xmm21 {%k1} + +// CHECK: vpgatherqd 1024(%rcx,%xmm31,4), %xmm21 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0x91,0xac,0xb9,0x00,0x04,0x00,0x00] + vpgatherqd 1024(%rcx,%xmm31,4), %xmm21 {%k1} + +// CHECK: vpgatherqd 123(%r14,%ymm31,8), %xmm25 {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0x91,0x8c,0xfe,0x7b,0x00,0x00,0x00] + vpgatherqd 123(%r14,%ymm31,8), %xmm25 {%k1} + +// CHECK: vpgatherqd 256(%r9,%ymm31), %xmm25 {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0x91,0x4c,0x39,0x40] + vpgatherqd 256(%r9,%ymm31), %xmm25 {%k1} + +// CHECK: vpgatherqd 1024(%rcx,%ymm31,4), %xmm25 {%k1} +// CHECK: encoding: [0x62,0x22,0x7d,0x21,0x91,0x8c,0xb9,0x00,0x04,0x00,0x00] + vpgatherqd 1024(%rcx,%ymm31,4), %xmm25 {%k1} + +// CHECK: vpgatherqq 123(%r14,%xmm31,8), %xmm18 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x91,0x94,0xfe,0x7b,0x00,0x00,0x00] + vpgatherqq 123(%r14,%xmm31,8), %xmm18 {%k1} + +// CHECK: vpgatherqq 256(%r9,%xmm31), %xmm18 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x91,0x54,0x39,0x20] + vpgatherqq 256(%r9,%xmm31), %xmm18 {%k1} + +// CHECK: vpgatherqq 1024(%rcx,%xmm31,4), %xmm18 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x01,0x91,0x94,0xb9,0x00,0x04,0x00,0x00] + vpgatherqq 1024(%rcx,%xmm31,4), %xmm18 {%k1} + +// CHECK: vpgatherqq 123(%r14,%ymm31,8), %ymm19 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0x91,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vpgatherqq 123(%r14,%ymm31,8), %ymm19 {%k1} + +// CHECK: vpgatherqq 256(%r9,%ymm31), %ymm19 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0x91,0x5c,0x39,0x20] + vpgatherqq 256(%r9,%ymm31), %ymm19 {%k1} + +// CHECK: vpgatherqq 1024(%rcx,%ymm31,4), %ymm19 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x21,0x91,0x9c,0xb9,0x00,0x04,0x00,0x00] + vpgatherqq 1024(%rcx,%ymm31,4), %ymm19 {%k1} + +// CHECK: vgatherdpd 123(%r14,%xmm31,8), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x92,0x8c,0xfe,0x7b,0x00,0x00,0x00] + vgatherdpd 123(%r14,%xmm31,8), %xmm17 {%k1} + +// CHECK: vgatherdpd 256(%r9,%xmm31), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x92,0x4c,0x39,0x20] + vgatherdpd 256(%r9,%xmm31), %xmm17 {%k1} + +// CHECK: vgatherdpd 1024(%rcx,%xmm31,4), %xmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x01,0x92,0x8c,0xb9,0x00,0x04,0x00,0x00] + vgatherdpd 1024(%rcx,%xmm31,4), %xmm17 {%k1} + +// CHECK: vgatherdpd 123(%r14,%xmm31,8), %ymm23 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0x92,0xbc,0xfe,0x7b,0x00,0x00,0x00] + vgatherdpd 123(%r14,%xmm31,8), %ymm23 {%k1} + +// CHECK: vgatherdpd 256(%r9,%xmm31), %ymm23 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0x92,0x7c,0x39,0x20] + vgatherdpd 256(%r9,%xmm31), %ymm23 {%k1} + +// CHECK: vgatherdpd 1024(%rcx,%xmm31,4), %ymm23 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x21,0x92,0xbc,0xb9,0x00,0x04,0x00,0x00] + vgatherdpd 1024(%rcx,%xmm31,4), %ymm23 {%k1} + +// CHECK: vgatherdps 123(%r14,%xmm31,8), %xmm18 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x92,0x94,0xfe,0x7b,0x00,0x00,0x00] + vgatherdps 123(%r14,%xmm31,8), %xmm18 {%k1} + +// CHECK: vgatherdps 256(%r9,%xmm31), %xmm18 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x92,0x54,0x39,0x40] + vgatherdps 256(%r9,%xmm31), %xmm18 {%k1} + +// CHECK: vgatherdps 1024(%rcx,%xmm31,4), %xmm18 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0x92,0x94,0xb9,0x00,0x04,0x00,0x00] + vgatherdps 1024(%rcx,%xmm31,4), %xmm18 {%k1} + +// CHECK: vgatherdps 123(%r14,%ymm31,8), %ymm27 {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0x92,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vgatherdps 123(%r14,%ymm31,8), %ymm27 {%k1} + +// CHECK: vgatherdps 256(%r9,%ymm31), %ymm27 {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0x92,0x5c,0x39,0x40] + vgatherdps 256(%r9,%ymm31), %ymm27 {%k1} + +// CHECK: vgatherdps 1024(%rcx,%ymm31,4), %ymm27 {%k1} +// CHECK: encoding: [0x62,0x22,0x7d,0x21,0x92,0x9c,0xb9,0x00,0x04,0x00,0x00] + vgatherdps 1024(%rcx,%ymm31,4), %ymm27 {%k1} + +// CHECK: vgatherqpd 123(%r14,%xmm31,8), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x93,0x8c,0xfe,0x7b,0x00,0x00,0x00] + vgatherqpd 123(%r14,%xmm31,8), %xmm17 {%k1} + +// CHECK: vgatherqpd 256(%r9,%xmm31), %xmm17 {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0x93,0x4c,0x39,0x20] + vgatherqpd 256(%r9,%xmm31), %xmm17 {%k1} + +// CHECK: vgatherqpd 1024(%rcx,%xmm31,4), %xmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x01,0x93,0x8c,0xb9,0x00,0x04,0x00,0x00] + vgatherqpd 1024(%rcx,%xmm31,4), %xmm17 {%k1} + +// CHECK: vgatherqpd 123(%r14,%ymm31,8), %ymm29 {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0x93,0xac,0xfe,0x7b,0x00,0x00,0x00] + vgatherqpd 123(%r14,%ymm31,8), %ymm29 {%k1} + +// CHECK: vgatherqpd 256(%r9,%ymm31), %ymm29 {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0x93,0x6c,0x39,0x20] + vgatherqpd 256(%r9,%ymm31), %ymm29 {%k1} + +// CHECK: vgatherqpd 1024(%rcx,%ymm31,4), %ymm29 {%k1} +// CHECK: encoding: [0x62,0x22,0xfd,0x21,0x93,0xac,0xb9,0x00,0x04,0x00,0x00] + vgatherqpd 1024(%rcx,%ymm31,4), %ymm29 {%k1} + +// CHECK: vgatherqps 123(%r14,%xmm31,8), %xmm21 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x93,0xac,0xfe,0x7b,0x00,0x00,0x00] + vgatherqps 123(%r14,%xmm31,8), %xmm21 {%k1} + +// CHECK: vgatherqps 256(%r9,%xmm31), %xmm21 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0x93,0x6c,0x39,0x40] + vgatherqps 256(%r9,%xmm31), %xmm21 {%k1} + +// CHECK: vgatherqps 1024(%rcx,%xmm31,4), %xmm21 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0x93,0xac,0xb9,0x00,0x04,0x00,0x00] + vgatherqps 1024(%rcx,%xmm31,4), %xmm21 {%k1} + +// CHECK: vgatherqps 123(%r14,%ymm31,8), %xmm19 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x21,0x93,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vgatherqps 123(%r14,%ymm31,8), %xmm19 {%k1} + +// CHECK: vgatherqps 256(%r9,%ymm31), %xmm19 {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x21,0x93,0x5c,0x39,0x40] + vgatherqps 256(%r9,%ymm31), %xmm19 {%k1} + +// CHECK: vgatherqps 1024(%rcx,%ymm31,4), %xmm19 {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x21,0x93,0x9c,0xb9,0x00,0x04,0x00,0x00] + vgatherqps 1024(%rcx,%ymm31,4), %xmm19 {%k1} + +// CHECK: vpscatterdd %xmm20, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdd %xmm20, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdd %xmm20, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdd %xmm20, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdd %xmm20, 256(%r9,%xmm31) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa0,0x64,0x39,0x40] + vpscatterdd %xmm20, 256(%r9,%xmm31) {%k1} + +// CHECK: vpscatterdd %xmm20, 1024(%rcx,%xmm31,4) {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0xa0,0xa4,0xb9,0x00,0x04,0x00,0x00] + vpscatterdd %xmm20, 1024(%rcx,%xmm31,4) {%k1} + +// CHECK: vpscatterdd %ymm28, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdd %ymm28, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterdd %ymm28, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdd %ymm28, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterdd %ymm28, 256(%r9,%ymm31) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa0,0x64,0x39,0x40] + vpscatterdd %ymm28, 256(%r9,%ymm31) {%k1} + +// CHECK: vpscatterdd %ymm28, 1024(%rcx,%ymm31,4) {%k1} +// CHECK: encoding: [0x62,0x22,0x7d,0x21,0xa0,0xa4,0xb9,0x00,0x04,0x00,0x00] + vpscatterdd %ymm28, 1024(%rcx,%ymm31,4) {%k1} + +// CHECK: vpscatterdq %xmm21, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0xa0,0xac,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdq %xmm21, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdq %xmm21, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0xa0,0xac,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdq %xmm21, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdq %xmm21, 256(%r9,%xmm31) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x01,0xa0,0x6c,0x39,0x20] + vpscatterdq %xmm21, 256(%r9,%xmm31) {%k1} + +// CHECK: vpscatterdq %xmm21, 1024(%rcx,%xmm31,4) {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x01,0xa0,0xac,0xb9,0x00,0x04,0x00,0x00] + vpscatterdq %xmm21, 1024(%rcx,%xmm31,4) {%k1} + +// CHECK: vpscatterdq %ymm28, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdq %ymm28, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdq %ymm28, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0xa0,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterdq %ymm28, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterdq %ymm28, 256(%r9,%xmm31) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x21,0xa0,0x64,0x39,0x20] + vpscatterdq %ymm28, 256(%r9,%xmm31) {%k1} + +// CHECK: vpscatterdq %ymm28, 1024(%rcx,%xmm31,4) {%k1} +// CHECK: encoding: [0x62,0x22,0xfd,0x21,0xa0,0xa4,0xb9,0x00,0x04,0x00,0x00] + vpscatterdq %ymm28, 1024(%rcx,%xmm31,4) {%k1} + +// CHECK: vpscatterqd %xmm22, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa1,0xb4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqd %xmm22, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterqd %xmm22, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa1,0xb4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqd %xmm22, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterqd %xmm22, 256(%r9,%xmm31) {%k1} +// CHECK: encoding: [0x62,0x82,0x7d,0x01,0xa1,0x74,0x39,0x40] + vpscatterqd %xmm22, 256(%r9,%xmm31) {%k1} + +// CHECK: vpscatterqd %xmm22, 1024(%rcx,%xmm31,4) {%k1} +// CHECK: encoding: [0x62,0xa2,0x7d,0x01,0xa1,0xb4,0xb9,0x00,0x04,0x00,0x00] + vpscatterqd %xmm22, 1024(%rcx,%xmm31,4) {%k1} + +// CHECK: vpscatterqd %xmm24, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa1,0x84,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqd %xmm24, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterqd %xmm24, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa1,0x84,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqd %xmm24, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterqd %xmm24, 256(%r9,%ymm31) {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x21,0xa1,0x44,0x39,0x40] + vpscatterqd %xmm24, 256(%r9,%ymm31) {%k1} + +// CHECK: vpscatterqd %xmm24, 1024(%rcx,%ymm31,4) {%k1} +// CHECK: encoding: [0x62,0x22,0x7d,0x21,0xa1,0x84,0xb9,0x00,0x04,0x00,0x00] + vpscatterqd %xmm24, 1024(%rcx,%ymm31,4) {%k1} + +// CHECK: vpscatterqq %xmm28, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x01,0xa1,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqq %xmm28, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterqq %xmm28, 123(%r14,%xmm31,8) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x01,0xa1,0xa4,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqq %xmm28, 123(%r14,%xmm31,8) {%k1} + +// CHECK: vpscatterqq %xmm28, 256(%r9,%xmm31) {%k1} +// CHECK: encoding: [0x62,0x02,0xfd,0x01,0xa1,0x64,0x39,0x20] + vpscatterqq %xmm28, 256(%r9,%xmm31) {%k1} + +// CHECK: vpscatterqq %xmm28, 1024(%rcx,%xmm31,4) {%k1} +// CHECK: encoding: [0x62,0x22,0xfd,0x01,0xa1,0xa4,0xb9,0x00,0x04,0x00,0x00] + vpscatterqq %xmm28, 1024(%rcx,%xmm31,4) {%k1} + +// CHECK: vpscatterqq %ymm19, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0xa1,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqq %ymm19, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterqq %ymm19, 123(%r14,%ymm31,8) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0xa1,0x9c,0xfe,0x7b,0x00,0x00,0x00] + vpscatterqq %ymm19, 123(%r14,%ymm31,8) {%k1} + +// CHECK: vpscatterqq %ymm19, 256(%r9,%ymm31) {%k1} +// CHECK: encoding: [0x62,0x82,0xfd,0x21,0xa1,0x5c,0x39,0x20] + vpscatterqq %ymm19, 256(%r9,%ymm31) {%k1} + +// CHECK: vpscatterqq %ymm19, 1024(%rcx,%ymm31,4) {%k1} +// CHECK: encoding: [0x62,0xa2,0xfd,0x21,0xa1,0x9c,0xb9,0x00,0x04,0x00,0x00] + vpscatterqq %ymm19, 1024(%rcx,%ymm31,4) {%k1} diff --git a/test/MC/X86/faultmap-section-parsing.s b/test/MC/X86/faultmap-section-parsing.s new file mode 100644 index 0000000000000..758e70fe685cf --- /dev/null +++ b/test/MC/X86/faultmap-section-parsing.s @@ -0,0 +1,29 @@ +// RUN: llvm-mc < %s -triple=x86_64-apple-macosx -filetype=obj -o - | llvm-objdump -fault-map-section - | FileCheck %s + + .section __LLVM_FAULTMAPS,__llvm_faultmaps +__LLVM_FaultMaps: + .byte 1 + .byte 0 + .short 0 + .long 2 + .quad 0xFFDEAD + .long 1 + .long 0 + .long 1 + .long 100 + .long 200 + + .quad 0xFFDAED + .long 1 + .long 0 + .long 1 + .long 400 + .long 500 + +// CHECK: FaultMap table: +// CHECK-NEXT: Version: 0x1 +// CHECK-NEXT: NumFunctions: 2 +// CHECK-NEXT: FunctionAddress: 0xffdead, NumFaultingPCs: 1 +// CHECK-NEXT: Fault kind: FaultingLoad, faulting PC offset: 100, handling PC offset: 200 +// CHECK-NEXT: FunctionAddress: 0xffdaed, NumFaultingPCs: 1 +// CHECK-NEXT: Fault kind: FaultingLoad, faulting PC offset: 400, handling PC offset: 500 diff --git a/test/MC/X86/inline-asm-obj.ll b/test/MC/X86/inline-asm-obj.ll new file mode 100644 index 0000000000000..2ee998dbc45df --- /dev/null +++ b/test/MC/X86/inline-asm-obj.ll @@ -0,0 +1,13 @@ +; RUN: llc %s -o - | llvm-mc -triple=x86_64-pc-linux -o %t1 -filetype=obj +; RUN: llc %s -o %t2 -filetype=obj +; RUN: cmp %t1 %t2 + +; Test that we can handle inline assembly referring to a temporary label. +; We crashed when using direct object emission in the past. + +target triple = "x86_64-unknown-linux-gnu" + +define void @fj() { + call void asm "bsr $0,%eax", "o"(i32 1) + ret void +} diff --git a/test/MC/X86/x86-64-avx512bw.s b/test/MC/X86/x86-64-avx512bw.s index 45e746308cbe8..fc6df8c2d40b5 100644 --- a/test/MC/X86/x86-64-avx512bw.s +++ b/test/MC/X86/x86-64-avx512bw.s @@ -3560,3 +3560,110 @@ // CHECK: encoding: [0x62,0x61,0x15,0x40,0xe3,0xaa,0xc0,0xdf,0xff,0xff] vpavgw -8256(%rdx), %zmm29, %zmm29 +// CHECK: vpshufb %zmm20, %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xa2,0x2d,0x40,0x00,0xf4] + vpshufb %zmm20, %zmm26, %zmm22 + +// CHECK: vpshufb %zmm20, %zmm26, %zmm22 {%k7} +// CHECK: encoding: [0x62,0xa2,0x2d,0x47,0x00,0xf4] + vpshufb %zmm20, %zmm26, %zmm22 {%k7} + +// CHECK: vpshufb %zmm20, %zmm26, %zmm22 {%k7} {z} +// CHECK: encoding: [0x62,0xa2,0x2d,0xc7,0x00,0xf4] + vpshufb %zmm20, %zmm26, %zmm22 {%k7} {z} + +// CHECK: vpshufb (%rcx), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x40,0x00,0x31] + vpshufb (%rcx), %zmm26, %zmm22 + +// CHECK: vpshufb 291(%rax,%r14,8), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xa2,0x2d,0x40,0x00,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpshufb 291(%rax,%r14,8), %zmm26, %zmm22 + +// CHECK: vpshufb 8128(%rdx), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x40,0x00,0x72,0x7f] + vpshufb 8128(%rdx), %zmm26, %zmm22 + +// CHECK: vpshufb 8192(%rdx), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x40,0x00,0xb2,0x00,0x20,0x00,0x00] + vpshufb 8192(%rdx), %zmm26, %zmm22 + +// CHECK: vpshufb -8192(%rdx), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x40,0x00,0x72,0x80] + vpshufb -8192(%rdx), %zmm26, %zmm22 + +// CHECK: vpshufb -8256(%rdx), %zmm26, %zmm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x40,0x00,0xb2,0xc0,0xdf,0xff,0xff] + vpshufb -8256(%rdx), %zmm26, %zmm22 + +// CHECK: vpabsb %zmm27, %zmm17 +// CHECK: encoding: [0x62,0x82,0x7d,0x48,0x1c,0xcb] + vpabsb %zmm27, %zmm17 + +// CHECK: vpabsb %zmm27, %zmm17 {%k7} +// CHECK: encoding: [0x62,0x82,0x7d,0x4f,0x1c,0xcb] + vpabsb %zmm27, %zmm17 {%k7} + +// CHECK: vpabsb %zmm27, %zmm17 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0x7d,0xcf,0x1c,0xcb] + vpabsb %zmm27, %zmm17 {%k7} {z} + +// CHECK: vpabsb (%rcx), %zmm17 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x1c,0x09] + vpabsb (%rcx), %zmm17 + +// CHECK: vpabsb 291(%rax,%r14,8), %zmm17 +// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x1c,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpabsb 291(%rax,%r14,8), %zmm17 + +// CHECK: vpabsb 8128(%rdx), %zmm17 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x1c,0x4a,0x7f] + vpabsb 8128(%rdx), %zmm17 + +// CHECK: vpabsb 8192(%rdx), %zmm17 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x1c,0x8a,0x00,0x20,0x00,0x00] + vpabsb 8192(%rdx), %zmm17 + +// CHECK: vpabsb -8192(%rdx), %zmm17 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x1c,0x4a,0x80] + vpabsb -8192(%rdx), %zmm17 + +// CHECK: vpabsb -8256(%rdx), %zmm17 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x1c,0x8a,0xc0,0xdf,0xff,0xff] + vpabsb -8256(%rdx), %zmm17 + +// CHECK: vpabsw %zmm24, %zmm30 +// CHECK: encoding: [0x62,0x02,0x7d,0x48,0x1d,0xf0] + vpabsw %zmm24, %zmm30 + +// CHECK: vpabsw %zmm24, %zmm30 {%k6} +// CHECK: encoding: [0x62,0x02,0x7d,0x4e,0x1d,0xf0] + vpabsw %zmm24, %zmm30 {%k6} + +// CHECK: vpabsw %zmm24, %zmm30 {%k6} {z} +// CHECK: encoding: [0x62,0x02,0x7d,0xce,0x1d,0xf0] + vpabsw %zmm24, %zmm30 {%k6} {z} + +// CHECK: vpabsw (%rcx), %zmm30 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0x31] + vpabsw (%rcx), %zmm30 + +// CHECK: vpabsw 291(%rax,%r14,8), %zmm30 +// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x1d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpabsw 291(%rax,%r14,8), %zmm30 + +// CHECK: vpabsw 8128(%rdx), %zmm30 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0x72,0x7f] + vpabsw 8128(%rdx), %zmm30 + +// CHECK: vpabsw 8192(%rdx), %zmm30 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0xb2,0x00,0x20,0x00,0x00] + vpabsw 8192(%rdx), %zmm30 + +// CHECK: vpabsw -8192(%rdx), %zmm30 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0x72,0x80] + vpabsw -8192(%rdx), %zmm30 + +// CHECK: vpabsw -8256(%rdx), %zmm30 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x1d,0xb2,0xc0,0xdf,0xff,0xff] + vpabsw -8256(%rdx), %zmm30 diff --git a/test/MC/X86/x86-64-avx512bw_vl.s b/test/MC/X86/x86-64-avx512bw_vl.s index 991c6102ebdfe..14a87df1ea835 100644 --- a/test/MC/X86/x86-64-avx512bw_vl.s +++ b/test/MC/X86/x86-64-avx512bw_vl.s @@ -6510,3 +6510,76 @@ // CHECK: vpavgw -4128(%rdx), %ymm23, %ymm21 // CHECK: encoding: [0x62,0xe1,0x45,0x20,0xe3,0xaa,0xe0,0xef,0xff,0xff] vpavgw -4128(%rdx), %ymm23, %ymm21 + +// CHECK: vpshufb %xmm27, %xmm24, %xmm23 +// CHECK: encoding: [0x62,0x82,0x3d,0x00,0x00,0xfb] + vpshufb %xmm27, %xmm24, %xmm23 + +// CHECK: vpshufb %xmm27, %xmm24, %xmm23 {%k4} +// CHECK: encoding: [0x62,0x82,0x3d,0x04,0x00,0xfb] + vpshufb %xmm27, %xmm24, %xmm23 {%k4} + +// CHECK: vpshufb %xmm27, %xmm24, %xmm23 {%k4} {z} +// CHECK: encoding: [0x62,0x82,0x3d,0x84,0x00,0xfb] + vpshufb %xmm27, %xmm24, %xmm23 {%k4} {z} + +// CHECK: vpshufb (%rcx), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x3d,0x00,0x00,0x39] + vpshufb (%rcx), %xmm24, %xmm23 + +// CHECK: vpshufb 291(%rax,%r14,8), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xa2,0x3d,0x00,0x00,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpshufb 291(%rax,%r14,8), %xmm24, %xmm23 + +// CHECK: vpshufb 2032(%rdx), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x3d,0x00,0x00,0x7a,0x7f] + vpshufb 2032(%rdx), %xmm24, %xmm23 + +// CHECK: vpshufb 2048(%rdx), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x3d,0x00,0x00,0xba,0x00,0x08,0x00,0x00] + vpshufb 2048(%rdx), %xmm24, %xmm23 + +// CHECK: vpshufb -2048(%rdx), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x3d,0x00,0x00,0x7a,0x80] + vpshufb -2048(%rdx), %xmm24, %xmm23 + +// CHECK: vpshufb -2064(%rdx), %xmm24, %xmm23 +// CHECK: encoding: [0x62,0xe2,0x3d,0x00,0x00,0xba,0xf0,0xf7,0xff,0xff] + vpshufb -2064(%rdx), %xmm24, %xmm23 + +// CHECK: vpshufb %ymm17, %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xa2,0x6d,0x20,0x00,0xd9] + vpshufb %ymm17, %ymm18, %ymm19 + +// CHECK: vpshufb %ymm17, %ymm18, %ymm19 {%k4} +// CHECK: encoding: [0x62,0xa2,0x6d,0x24,0x00,0xd9] + vpshufb %ymm17, %ymm18, %ymm19 {%k4} + +// CHECK: vpshufb %ymm17, %ymm18, %ymm19 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0x6d,0xa4,0x00,0xd9] + vpshufb %ymm17, %ymm18, %ymm19 {%k4} {z} + +// CHECK: vpshufb (%rcx), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x19] + vpshufb (%rcx), %ymm18, %ymm19 + +// CHECK: vpshufb 291(%rax,%r14,8), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xa2,0x6d,0x20,0x00,0x9c,0xf0,0x23,0x01,0x00,0x00] + vpshufb 291(%rax,%r14,8), %ymm18, %ymm19 + +// CHECK: vpshufb 4064(%rdx), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x5a,0x7f] + vpshufb 4064(%rdx), %ymm18, %ymm19 + +// CHECK: vpshufb 4096(%rdx), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x9a,0x00,0x10,0x00,0x00] + vpshufb 4096(%rdx), %ymm18, %ymm19 + +// CHECK: vpshufb -4096(%rdx), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x5a,0x80] + vpshufb -4096(%rdx), %ymm18, %ymm19 + +// CHECK: vpshufb -4128(%rdx), %ymm18, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x6d,0x20,0x00,0x9a,0xe0,0xef,0xff,0xff] + vpshufb -4128(%rdx), %ymm18, %ymm19 + diff --git a/test/MC/X86/x86-64-avx512f_vl.s b/test/MC/X86/x86-64-avx512f_vl.s index 1381b2e76e180..c587f8a75aaa7 100644 --- a/test/MC/X86/x86-64-avx512f_vl.s +++ b/test/MC/X86/x86-64-avx512f_vl.s @@ -11133,6 +11133,4038 @@ vaddpd {rz-sae}, %zmm2, %zmm1, %zmm1 // CHECK: encoding: [0x62,0x63,0xbd,0x30,0x03,0x8a,0xf8,0xfb,0xff,0xff,0x7b] valignq $0x7b, -1032(%rdx){1to4}, %ymm24, %ymm25 +// CHECK: vfmadd132ps %xmm19, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x22,0x35,0x00,0x98,0xeb] + vfmadd132ps %xmm19, %xmm25, %xmm29 + +// CHECK: vfmadd132ps %xmm19, %xmm25, %xmm29 {%k4} +// CHECK: encoding: [0x62,0x22,0x35,0x04,0x98,0xeb] + vfmadd132ps %xmm19, %xmm25, %xmm29 {%k4} + +// CHECK: vfmadd132ps %xmm19, %xmm25, %xmm29 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0x35,0x84,0x98,0xeb] + vfmadd132ps %xmm19, %xmm25, %xmm29 {%k4} {z} + +// CHECK: vfmadd132ps (%rcx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x00,0x98,0x29] + vfmadd132ps (%rcx), %xmm25, %xmm29 + +// CHECK: vfmadd132ps 291(%rax,%r14,8), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x22,0x35,0x00,0x98,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmadd132ps 291(%rax,%r14,8), %xmm25, %xmm29 + +// CHECK: vfmadd132ps (%rcx){1to4}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x10,0x98,0x29] + vfmadd132ps (%rcx){1to4}, %xmm25, %xmm29 + +// CHECK: vfmadd132ps 2032(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x00,0x98,0x6a,0x7f] + vfmadd132ps 2032(%rdx), %xmm25, %xmm29 + +// CHECK: vfmadd132ps 2048(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x00,0x98,0xaa,0x00,0x08,0x00,0x00] + vfmadd132ps 2048(%rdx), %xmm25, %xmm29 + +// CHECK: vfmadd132ps -2048(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x00,0x98,0x6a,0x80] + vfmadd132ps -2048(%rdx), %xmm25, %xmm29 + +// CHECK: vfmadd132ps -2064(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x00,0x98,0xaa,0xf0,0xf7,0xff,0xff] + vfmadd132ps -2064(%rdx), %xmm25, %xmm29 + +// CHECK: vfmadd132ps 508(%rdx){1to4}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x10,0x98,0x6a,0x7f] + vfmadd132ps 508(%rdx){1to4}, %xmm25, %xmm29 + +// CHECK: vfmadd132ps 512(%rdx){1to4}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x10,0x98,0xaa,0x00,0x02,0x00,0x00] + vfmadd132ps 512(%rdx){1to4}, %xmm25, %xmm29 + +// CHECK: vfmadd132ps -512(%rdx){1to4}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x10,0x98,0x6a,0x80] + vfmadd132ps -512(%rdx){1to4}, %xmm25, %xmm29 + +// CHECK: vfmadd132ps -516(%rdx){1to4}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0x35,0x10,0x98,0xaa,0xfc,0xfd,0xff,0xff] + vfmadd132ps -516(%rdx){1to4}, %xmm25, %xmm29 + +// CHECK: vfmadd132ps %ymm26, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0x82,0x4d,0x20,0x98,0xfa] + vfmadd132ps %ymm26, %ymm22, %ymm23 + +// CHECK: vfmadd132ps %ymm26, %ymm22, %ymm23 {%k5} +// CHECK: encoding: [0x62,0x82,0x4d,0x25,0x98,0xfa] + vfmadd132ps %ymm26, %ymm22, %ymm23 {%k5} + +// CHECK: vfmadd132ps %ymm26, %ymm22, %ymm23 {%k5} {z} +// CHECK: encoding: [0x62,0x82,0x4d,0xa5,0x98,0xfa] + vfmadd132ps %ymm26, %ymm22, %ymm23 {%k5} {z} + +// CHECK: vfmadd132ps (%rcx), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x20,0x98,0x39] + vfmadd132ps (%rcx), %ymm22, %ymm23 + +// CHECK: vfmadd132ps 291(%rax,%r14,8), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xa2,0x4d,0x20,0x98,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmadd132ps 291(%rax,%r14,8), %ymm22, %ymm23 + +// CHECK: vfmadd132ps (%rcx){1to8}, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x30,0x98,0x39] + vfmadd132ps (%rcx){1to8}, %ymm22, %ymm23 + +// CHECK: vfmadd132ps 4064(%rdx), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x20,0x98,0x7a,0x7f] + vfmadd132ps 4064(%rdx), %ymm22, %ymm23 + +// CHECK: vfmadd132ps 4096(%rdx), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x20,0x98,0xba,0x00,0x10,0x00,0x00] + vfmadd132ps 4096(%rdx), %ymm22, %ymm23 + +// CHECK: vfmadd132ps -4096(%rdx), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x20,0x98,0x7a,0x80] + vfmadd132ps -4096(%rdx), %ymm22, %ymm23 + +// CHECK: vfmadd132ps -4128(%rdx), %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x20,0x98,0xba,0xe0,0xef,0xff,0xff] + vfmadd132ps -4128(%rdx), %ymm22, %ymm23 + +// CHECK: vfmadd132ps 508(%rdx){1to8}, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x30,0x98,0x7a,0x7f] + vfmadd132ps 508(%rdx){1to8}, %ymm22, %ymm23 + +// CHECK: vfmadd132ps 512(%rdx){1to8}, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x30,0x98,0xba,0x00,0x02,0x00,0x00] + vfmadd132ps 512(%rdx){1to8}, %ymm22, %ymm23 + +// CHECK: vfmadd132ps -512(%rdx){1to8}, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x30,0x98,0x7a,0x80] + vfmadd132ps -512(%rdx){1to8}, %ymm22, %ymm23 + +// CHECK: vfmadd132ps -516(%rdx){1to8}, %ymm22, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x4d,0x30,0x98,0xba,0xfc,0xfd,0xff,0xff] + vfmadd132ps -516(%rdx){1to8}, %ymm22, %ymm23 + +// CHECK: vfmadd132pd %xmm27, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x02,0xd5,0x00,0x98,0xe3] + vfmadd132pd %xmm27, %xmm21, %xmm28 + +// CHECK: vfmadd132pd %xmm27, %xmm21, %xmm28 {%k1} +// CHECK: encoding: [0x62,0x02,0xd5,0x01,0x98,0xe3] + vfmadd132pd %xmm27, %xmm21, %xmm28 {%k1} + +// CHECK: vfmadd132pd %xmm27, %xmm21, %xmm28 {%k1} {z} +// CHECK: encoding: [0x62,0x02,0xd5,0x81,0x98,0xe3] + vfmadd132pd %xmm27, %xmm21, %xmm28 {%k1} {z} + +// CHECK: vfmadd132pd (%rcx), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x98,0x21] + vfmadd132pd (%rcx), %xmm21, %xmm28 + +// CHECK: vfmadd132pd 291(%rax,%r14,8), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x22,0xd5,0x00,0x98,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmadd132pd 291(%rax,%r14,8), %xmm21, %xmm28 + +// CHECK: vfmadd132pd (%rcx){1to2}, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x98,0x21] + vfmadd132pd (%rcx){1to2}, %xmm21, %xmm28 + +// CHECK: vfmadd132pd 2032(%rdx), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x98,0x62,0x7f] + vfmadd132pd 2032(%rdx), %xmm21, %xmm28 + +// CHECK: vfmadd132pd 2048(%rdx), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x98,0xa2,0x00,0x08,0x00,0x00] + vfmadd132pd 2048(%rdx), %xmm21, %xmm28 + +// CHECK: vfmadd132pd -2048(%rdx), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x98,0x62,0x80] + vfmadd132pd -2048(%rdx), %xmm21, %xmm28 + +// CHECK: vfmadd132pd -2064(%rdx), %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x98,0xa2,0xf0,0xf7,0xff,0xff] + vfmadd132pd -2064(%rdx), %xmm21, %xmm28 + +// CHECK: vfmadd132pd 1016(%rdx){1to2}, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x98,0x62,0x7f] + vfmadd132pd 1016(%rdx){1to2}, %xmm21, %xmm28 + +// CHECK: vfmadd132pd 1024(%rdx){1to2}, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x98,0xa2,0x00,0x04,0x00,0x00] + vfmadd132pd 1024(%rdx){1to2}, %xmm21, %xmm28 + +// CHECK: vfmadd132pd -1024(%rdx){1to2}, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x98,0x62,0x80] + vfmadd132pd -1024(%rdx){1to2}, %xmm21, %xmm28 + +// CHECK: vfmadd132pd -1032(%rdx){1to2}, %xmm21, %xmm28 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x98,0xa2,0xf8,0xfb,0xff,0xff] + vfmadd132pd -1032(%rdx){1to2}, %xmm21, %xmm28 + +// CHECK: vfmadd132pd %ymm27, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0x82,0xbd,0x20,0x98,0xf3] + vfmadd132pd %ymm27, %ymm24, %ymm22 + +// CHECK: vfmadd132pd %ymm27, %ymm24, %ymm22 {%k7} +// CHECK: encoding: [0x62,0x82,0xbd,0x27,0x98,0xf3] + vfmadd132pd %ymm27, %ymm24, %ymm22 {%k7} + +// CHECK: vfmadd132pd %ymm27, %ymm24, %ymm22 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0xbd,0xa7,0x98,0xf3] + vfmadd132pd %ymm27, %ymm24, %ymm22 {%k7} {z} + +// CHECK: vfmadd132pd (%rcx), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x20,0x98,0x31] + vfmadd132pd (%rcx), %ymm24, %ymm22 + +// CHECK: vfmadd132pd 291(%rax,%r14,8), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xa2,0xbd,0x20,0x98,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd132pd 291(%rax,%r14,8), %ymm24, %ymm22 + +// CHECK: vfmadd132pd (%rcx){1to4}, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x30,0x98,0x31] + vfmadd132pd (%rcx){1to4}, %ymm24, %ymm22 + +// CHECK: vfmadd132pd 4064(%rdx), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x20,0x98,0x72,0x7f] + vfmadd132pd 4064(%rdx), %ymm24, %ymm22 + +// CHECK: vfmadd132pd 4096(%rdx), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x20,0x98,0xb2,0x00,0x10,0x00,0x00] + vfmadd132pd 4096(%rdx), %ymm24, %ymm22 + +// CHECK: vfmadd132pd -4096(%rdx), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x20,0x98,0x72,0x80] + vfmadd132pd -4096(%rdx), %ymm24, %ymm22 + +// CHECK: vfmadd132pd -4128(%rdx), %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x20,0x98,0xb2,0xe0,0xef,0xff,0xff] + vfmadd132pd -4128(%rdx), %ymm24, %ymm22 + +// CHECK: vfmadd132pd 1016(%rdx){1to4}, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x30,0x98,0x72,0x7f] + vfmadd132pd 1016(%rdx){1to4}, %ymm24, %ymm22 + +// CHECK: vfmadd132pd 1024(%rdx){1to4}, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x30,0x98,0xb2,0x00,0x04,0x00,0x00] + vfmadd132pd 1024(%rdx){1to4}, %ymm24, %ymm22 + +// CHECK: vfmadd132pd -1024(%rdx){1to4}, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x30,0x98,0x72,0x80] + vfmadd132pd -1024(%rdx){1to4}, %ymm24, %ymm22 + +// CHECK: vfmadd132pd -1032(%rdx){1to4}, %ymm24, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xbd,0x30,0x98,0xb2,0xf8,0xfb,0xff,0xff] + vfmadd132pd -1032(%rdx){1to4}, %ymm24, %ymm22 + +// CHECK: vfmadd213ps %xmm28, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x02,0x1d,0x00,0xa8,0xc4] + vfmadd213ps %xmm28, %xmm28, %xmm24 + +// CHECK: vfmadd213ps %xmm28, %xmm28, %xmm24 {%k1} +// CHECK: encoding: [0x62,0x02,0x1d,0x01,0xa8,0xc4] + vfmadd213ps %xmm28, %xmm28, %xmm24 {%k1} + +// CHECK: vfmadd213ps %xmm28, %xmm28, %xmm24 {%k1} {z} +// CHECK: encoding: [0x62,0x02,0x1d,0x81,0xa8,0xc4] + vfmadd213ps %xmm28, %xmm28, %xmm24 {%k1} {z} + +// CHECK: vfmadd213ps (%rcx), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xa8,0x01] + vfmadd213ps (%rcx), %xmm28, %xmm24 + +// CHECK: vfmadd213ps 291(%rax,%r14,8), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x22,0x1d,0x00,0xa8,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmadd213ps 291(%rax,%r14,8), %xmm28, %xmm24 + +// CHECK: vfmadd213ps (%rcx){1to4}, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xa8,0x01] + vfmadd213ps (%rcx){1to4}, %xmm28, %xmm24 + +// CHECK: vfmadd213ps 2032(%rdx), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xa8,0x42,0x7f] + vfmadd213ps 2032(%rdx), %xmm28, %xmm24 + +// CHECK: vfmadd213ps 2048(%rdx), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xa8,0x82,0x00,0x08,0x00,0x00] + vfmadd213ps 2048(%rdx), %xmm28, %xmm24 + +// CHECK: vfmadd213ps -2048(%rdx), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xa8,0x42,0x80] + vfmadd213ps -2048(%rdx), %xmm28, %xmm24 + +// CHECK: vfmadd213ps -2064(%rdx), %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xa8,0x82,0xf0,0xf7,0xff,0xff] + vfmadd213ps -2064(%rdx), %xmm28, %xmm24 + +// CHECK: vfmadd213ps 508(%rdx){1to4}, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xa8,0x42,0x7f] + vfmadd213ps 508(%rdx){1to4}, %xmm28, %xmm24 + +// CHECK: vfmadd213ps 512(%rdx){1to4}, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xa8,0x82,0x00,0x02,0x00,0x00] + vfmadd213ps 512(%rdx){1to4}, %xmm28, %xmm24 + +// CHECK: vfmadd213ps -512(%rdx){1to4}, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xa8,0x42,0x80] + vfmadd213ps -512(%rdx){1to4}, %xmm28, %xmm24 + +// CHECK: vfmadd213ps -516(%rdx){1to4}, %xmm28, %xmm24 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xa8,0x82,0xfc,0xfd,0xff,0xff] + vfmadd213ps -516(%rdx){1to4}, %xmm28, %xmm24 + +// CHECK: vfmadd213ps %ymm17, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x22,0x4d,0x20,0xa8,0xd1] + vfmadd213ps %ymm17, %ymm22, %ymm26 + +// CHECK: vfmadd213ps %ymm17, %ymm22, %ymm26 {%k3} +// CHECK: encoding: [0x62,0x22,0x4d,0x23,0xa8,0xd1] + vfmadd213ps %ymm17, %ymm22, %ymm26 {%k3} + +// CHECK: vfmadd213ps %ymm17, %ymm22, %ymm26 {%k3} {z} +// CHECK: encoding: [0x62,0x22,0x4d,0xa3,0xa8,0xd1] + vfmadd213ps %ymm17, %ymm22, %ymm26 {%k3} {z} + +// CHECK: vfmadd213ps (%rcx), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0xa8,0x11] + vfmadd213ps (%rcx), %ymm22, %ymm26 + +// CHECK: vfmadd213ps 291(%rax,%r14,8), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x22,0x4d,0x20,0xa8,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmadd213ps 291(%rax,%r14,8), %ymm22, %ymm26 + +// CHECK: vfmadd213ps (%rcx){1to8}, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0xa8,0x11] + vfmadd213ps (%rcx){1to8}, %ymm22, %ymm26 + +// CHECK: vfmadd213ps 4064(%rdx), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0xa8,0x52,0x7f] + vfmadd213ps 4064(%rdx), %ymm22, %ymm26 + +// CHECK: vfmadd213ps 4096(%rdx), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0xa8,0x92,0x00,0x10,0x00,0x00] + vfmadd213ps 4096(%rdx), %ymm22, %ymm26 + +// CHECK: vfmadd213ps -4096(%rdx), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0xa8,0x52,0x80] + vfmadd213ps -4096(%rdx), %ymm22, %ymm26 + +// CHECK: vfmadd213ps -4128(%rdx), %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0xa8,0x92,0xe0,0xef,0xff,0xff] + vfmadd213ps -4128(%rdx), %ymm22, %ymm26 + +// CHECK: vfmadd213ps 508(%rdx){1to8}, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0xa8,0x52,0x7f] + vfmadd213ps 508(%rdx){1to8}, %ymm22, %ymm26 + +// CHECK: vfmadd213ps 512(%rdx){1to8}, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0xa8,0x92,0x00,0x02,0x00,0x00] + vfmadd213ps 512(%rdx){1to8}, %ymm22, %ymm26 + +// CHECK: vfmadd213ps -512(%rdx){1to8}, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0xa8,0x52,0x80] + vfmadd213ps -512(%rdx){1to8}, %ymm22, %ymm26 + +// CHECK: vfmadd213ps -516(%rdx){1to8}, %ymm22, %ymm26 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0xa8,0x92,0xfc,0xfd,0xff,0xff] + vfmadd213ps -516(%rdx){1to8}, %ymm22, %ymm26 + +// CHECK: vfmadd213pd %xmm23, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xa2,0xd5,0x00,0xa8,0xf7] + vfmadd213pd %xmm23, %xmm21, %xmm22 + +// CHECK: vfmadd213pd %xmm23, %xmm21, %xmm22 {%k4} +// CHECK: encoding: [0x62,0xa2,0xd5,0x04,0xa8,0xf7] + vfmadd213pd %xmm23, %xmm21, %xmm22 {%k4} + +// CHECK: vfmadd213pd %xmm23, %xmm21, %xmm22 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0xd5,0x84,0xa8,0xf7] + vfmadd213pd %xmm23, %xmm21, %xmm22 {%k4} {z} + +// CHECK: vfmadd213pd (%rcx), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa8,0x31] + vfmadd213pd (%rcx), %xmm21, %xmm22 + +// CHECK: vfmadd213pd 291(%rax,%r14,8), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xa2,0xd5,0x00,0xa8,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd213pd 291(%rax,%r14,8), %xmm21, %xmm22 + +// CHECK: vfmadd213pd (%rcx){1to2}, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa8,0x31] + vfmadd213pd (%rcx){1to2}, %xmm21, %xmm22 + +// CHECK: vfmadd213pd 2032(%rdx), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa8,0x72,0x7f] + vfmadd213pd 2032(%rdx), %xmm21, %xmm22 + +// CHECK: vfmadd213pd 2048(%rdx), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa8,0xb2,0x00,0x08,0x00,0x00] + vfmadd213pd 2048(%rdx), %xmm21, %xmm22 + +// CHECK: vfmadd213pd -2048(%rdx), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa8,0x72,0x80] + vfmadd213pd -2048(%rdx), %xmm21, %xmm22 + +// CHECK: vfmadd213pd -2064(%rdx), %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa8,0xb2,0xf0,0xf7,0xff,0xff] + vfmadd213pd -2064(%rdx), %xmm21, %xmm22 + +// CHECK: vfmadd213pd 1016(%rdx){1to2}, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa8,0x72,0x7f] + vfmadd213pd 1016(%rdx){1to2}, %xmm21, %xmm22 + +// CHECK: vfmadd213pd 1024(%rdx){1to2}, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa8,0xb2,0x00,0x04,0x00,0x00] + vfmadd213pd 1024(%rdx){1to2}, %xmm21, %xmm22 + +// CHECK: vfmadd213pd -1024(%rdx){1to2}, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa8,0x72,0x80] + vfmadd213pd -1024(%rdx){1to2}, %xmm21, %xmm22 + +// CHECK: vfmadd213pd -1032(%rdx){1to2}, %xmm21, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa8,0xb2,0xf8,0xfb,0xff,0xff] + vfmadd213pd -1032(%rdx){1to2}, %xmm21, %xmm22 + +// CHECK: vfmadd213pd %ymm17, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xa2,0xe5,0x20,0xa8,0xd1] + vfmadd213pd %ymm17, %ymm19, %ymm18 + +// CHECK: vfmadd213pd %ymm17, %ymm19, %ymm18 {%k1} +// CHECK: encoding: [0x62,0xa2,0xe5,0x21,0xa8,0xd1] + vfmadd213pd %ymm17, %ymm19, %ymm18 {%k1} + +// CHECK: vfmadd213pd %ymm17, %ymm19, %ymm18 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0xe5,0xa1,0xa8,0xd1] + vfmadd213pd %ymm17, %ymm19, %ymm18 {%k1} {z} + +// CHECK: vfmadd213pd (%rcx), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x20,0xa8,0x11] + vfmadd213pd (%rcx), %ymm19, %ymm18 + +// CHECK: vfmadd213pd 291(%rax,%r14,8), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xa2,0xe5,0x20,0xa8,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmadd213pd 291(%rax,%r14,8), %ymm19, %ymm18 + +// CHECK: vfmadd213pd (%rcx){1to4}, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x30,0xa8,0x11] + vfmadd213pd (%rcx){1to4}, %ymm19, %ymm18 + +// CHECK: vfmadd213pd 4064(%rdx), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x20,0xa8,0x52,0x7f] + vfmadd213pd 4064(%rdx), %ymm19, %ymm18 + +// CHECK: vfmadd213pd 4096(%rdx), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x20,0xa8,0x92,0x00,0x10,0x00,0x00] + vfmadd213pd 4096(%rdx), %ymm19, %ymm18 + +// CHECK: vfmadd213pd -4096(%rdx), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x20,0xa8,0x52,0x80] + vfmadd213pd -4096(%rdx), %ymm19, %ymm18 + +// CHECK: vfmadd213pd -4128(%rdx), %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x20,0xa8,0x92,0xe0,0xef,0xff,0xff] + vfmadd213pd -4128(%rdx), %ymm19, %ymm18 + +// CHECK: vfmadd213pd 1016(%rdx){1to4}, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x30,0xa8,0x52,0x7f] + vfmadd213pd 1016(%rdx){1to4}, %ymm19, %ymm18 + +// CHECK: vfmadd213pd 1024(%rdx){1to4}, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x30,0xa8,0x92,0x00,0x04,0x00,0x00] + vfmadd213pd 1024(%rdx){1to4}, %ymm19, %ymm18 + +// CHECK: vfmadd213pd -1024(%rdx){1to4}, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x30,0xa8,0x52,0x80] + vfmadd213pd -1024(%rdx){1to4}, %ymm19, %ymm18 + +// CHECK: vfmadd213pd -1032(%rdx){1to4}, %ymm19, %ymm18 +// CHECK: encoding: [0x62,0xe2,0xe5,0x30,0xa8,0x92,0xf8,0xfb,0xff,0xff] + vfmadd213pd -1032(%rdx){1to4}, %ymm19, %ymm18 + +// CHECK: vfmadd231ps %xmm27, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x02,0x5d,0x00,0xb8,0xf3] + vfmadd231ps %xmm27, %xmm20, %xmm30 + +// CHECK: vfmadd231ps %xmm27, %xmm20, %xmm30 {%k7} +// CHECK: encoding: [0x62,0x02,0x5d,0x07,0xb8,0xf3] + vfmadd231ps %xmm27, %xmm20, %xmm30 {%k7} + +// CHECK: vfmadd231ps %xmm27, %xmm20, %xmm30 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0x5d,0x87,0xb8,0xf3] + vfmadd231ps %xmm27, %xmm20, %xmm30 {%k7} {z} + +// CHECK: vfmadd231ps (%rcx), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x00,0xb8,0x31] + vfmadd231ps (%rcx), %xmm20, %xmm30 + +// CHECK: vfmadd231ps 291(%rax,%r14,8), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x22,0x5d,0x00,0xb8,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd231ps 291(%rax,%r14,8), %xmm20, %xmm30 + +// CHECK: vfmadd231ps (%rcx){1to4}, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x10,0xb8,0x31] + vfmadd231ps (%rcx){1to4}, %xmm20, %xmm30 + +// CHECK: vfmadd231ps 2032(%rdx), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x00,0xb8,0x72,0x7f] + vfmadd231ps 2032(%rdx), %xmm20, %xmm30 + +// CHECK: vfmadd231ps 2048(%rdx), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x00,0xb8,0xb2,0x00,0x08,0x00,0x00] + vfmadd231ps 2048(%rdx), %xmm20, %xmm30 + +// CHECK: vfmadd231ps -2048(%rdx), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x00,0xb8,0x72,0x80] + vfmadd231ps -2048(%rdx), %xmm20, %xmm30 + +// CHECK: vfmadd231ps -2064(%rdx), %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x00,0xb8,0xb2,0xf0,0xf7,0xff,0xff] + vfmadd231ps -2064(%rdx), %xmm20, %xmm30 + +// CHECK: vfmadd231ps 508(%rdx){1to4}, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x10,0xb8,0x72,0x7f] + vfmadd231ps 508(%rdx){1to4}, %xmm20, %xmm30 + +// CHECK: vfmadd231ps 512(%rdx){1to4}, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x10,0xb8,0xb2,0x00,0x02,0x00,0x00] + vfmadd231ps 512(%rdx){1to4}, %xmm20, %xmm30 + +// CHECK: vfmadd231ps -512(%rdx){1to4}, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x10,0xb8,0x72,0x80] + vfmadd231ps -512(%rdx){1to4}, %xmm20, %xmm30 + +// CHECK: vfmadd231ps -516(%rdx){1to4}, %xmm20, %xmm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x10,0xb8,0xb2,0xfc,0xfd,0xff,0xff] + vfmadd231ps -516(%rdx){1to4}, %xmm20, %xmm30 + +// CHECK: vfmadd231ps %ymm25, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0x82,0x2d,0x20,0xb8,0xf1] + vfmadd231ps %ymm25, %ymm26, %ymm22 + +// CHECK: vfmadd231ps %ymm25, %ymm26, %ymm22 {%k7} +// CHECK: encoding: [0x62,0x82,0x2d,0x27,0xb8,0xf1] + vfmadd231ps %ymm25, %ymm26, %ymm22 {%k7} + +// CHECK: vfmadd231ps %ymm25, %ymm26, %ymm22 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0x2d,0xa7,0xb8,0xf1] + vfmadd231ps %ymm25, %ymm26, %ymm22 {%k7} {z} + +// CHECK: vfmadd231ps (%rcx), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xb8,0x31] + vfmadd231ps (%rcx), %ymm26, %ymm22 + +// CHECK: vfmadd231ps 291(%rax,%r14,8), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xa2,0x2d,0x20,0xb8,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmadd231ps 291(%rax,%r14,8), %ymm26, %ymm22 + +// CHECK: vfmadd231ps (%rcx){1to8}, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xb8,0x31] + vfmadd231ps (%rcx){1to8}, %ymm26, %ymm22 + +// CHECK: vfmadd231ps 4064(%rdx), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xb8,0x72,0x7f] + vfmadd231ps 4064(%rdx), %ymm26, %ymm22 + +// CHECK: vfmadd231ps 4096(%rdx), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xb8,0xb2,0x00,0x10,0x00,0x00] + vfmadd231ps 4096(%rdx), %ymm26, %ymm22 + +// CHECK: vfmadd231ps -4096(%rdx), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xb8,0x72,0x80] + vfmadd231ps -4096(%rdx), %ymm26, %ymm22 + +// CHECK: vfmadd231ps -4128(%rdx), %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xb8,0xb2,0xe0,0xef,0xff,0xff] + vfmadd231ps -4128(%rdx), %ymm26, %ymm22 + +// CHECK: vfmadd231ps 508(%rdx){1to8}, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xb8,0x72,0x7f] + vfmadd231ps 508(%rdx){1to8}, %ymm26, %ymm22 + +// CHECK: vfmadd231ps 512(%rdx){1to8}, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xb8,0xb2,0x00,0x02,0x00,0x00] + vfmadd231ps 512(%rdx){1to8}, %ymm26, %ymm22 + +// CHECK: vfmadd231ps -512(%rdx){1to8}, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xb8,0x72,0x80] + vfmadd231ps -512(%rdx){1to8}, %ymm26, %ymm22 + +// CHECK: vfmadd231ps -516(%rdx){1to8}, %ymm26, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xb8,0xb2,0xfc,0xfd,0xff,0xff] + vfmadd231ps -516(%rdx){1to8}, %ymm26, %ymm22 + +// CHECK: vfmadd231pd %xmm24, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x00,0xb8,0xe8] + vfmadd231pd %xmm24, %xmm20, %xmm29 + +// CHECK: vfmadd231pd %xmm24, %xmm20, %xmm29 {%k7} +// CHECK: encoding: [0x62,0x02,0xdd,0x07,0xb8,0xe8] + vfmadd231pd %xmm24, %xmm20, %xmm29 {%k7} + +// CHECK: vfmadd231pd %xmm24, %xmm20, %xmm29 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0xdd,0x87,0xb8,0xe8] + vfmadd231pd %xmm24, %xmm20, %xmm29 {%k7} {z} + +// CHECK: vfmadd231pd (%rcx), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xb8,0x29] + vfmadd231pd (%rcx), %xmm20, %xmm29 + +// CHECK: vfmadd231pd 291(%rax,%r14,8), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x22,0xdd,0x00,0xb8,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmadd231pd 291(%rax,%r14,8), %xmm20, %xmm29 + +// CHECK: vfmadd231pd (%rcx){1to2}, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xb8,0x29] + vfmadd231pd (%rcx){1to2}, %xmm20, %xmm29 + +// CHECK: vfmadd231pd 2032(%rdx), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xb8,0x6a,0x7f] + vfmadd231pd 2032(%rdx), %xmm20, %xmm29 + +// CHECK: vfmadd231pd 2048(%rdx), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xb8,0xaa,0x00,0x08,0x00,0x00] + vfmadd231pd 2048(%rdx), %xmm20, %xmm29 + +// CHECK: vfmadd231pd -2048(%rdx), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xb8,0x6a,0x80] + vfmadd231pd -2048(%rdx), %xmm20, %xmm29 + +// CHECK: vfmadd231pd -2064(%rdx), %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xb8,0xaa,0xf0,0xf7,0xff,0xff] + vfmadd231pd -2064(%rdx), %xmm20, %xmm29 + +// CHECK: vfmadd231pd 1016(%rdx){1to2}, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xb8,0x6a,0x7f] + vfmadd231pd 1016(%rdx){1to2}, %xmm20, %xmm29 + +// CHECK: vfmadd231pd 1024(%rdx){1to2}, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xb8,0xaa,0x00,0x04,0x00,0x00] + vfmadd231pd 1024(%rdx){1to2}, %xmm20, %xmm29 + +// CHECK: vfmadd231pd -1024(%rdx){1to2}, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xb8,0x6a,0x80] + vfmadd231pd -1024(%rdx){1to2}, %xmm20, %xmm29 + +// CHECK: vfmadd231pd -1032(%rdx){1to2}, %xmm20, %xmm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xb8,0xaa,0xf8,0xfb,0xff,0xff] + vfmadd231pd -1032(%rdx){1to2}, %xmm20, %xmm29 + +// CHECK: vfmadd231pd %ymm26, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x02,0xdd,0x20,0xb8,0xc2] + vfmadd231pd %ymm26, %ymm20, %ymm24 + +// CHECK: vfmadd231pd %ymm26, %ymm20, %ymm24 {%k6} +// CHECK: encoding: [0x62,0x02,0xdd,0x26,0xb8,0xc2] + vfmadd231pd %ymm26, %ymm20, %ymm24 {%k6} + +// CHECK: vfmadd231pd %ymm26, %ymm20, %ymm24 {%k6} {z} +// CHECK: encoding: [0x62,0x02,0xdd,0xa6,0xb8,0xc2] + vfmadd231pd %ymm26, %ymm20, %ymm24 {%k6} {z} + +// CHECK: vfmadd231pd (%rcx), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xb8,0x01] + vfmadd231pd (%rcx), %ymm20, %ymm24 + +// CHECK: vfmadd231pd 291(%rax,%r14,8), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x22,0xdd,0x20,0xb8,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmadd231pd 291(%rax,%r14,8), %ymm20, %ymm24 + +// CHECK: vfmadd231pd (%rcx){1to4}, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xb8,0x01] + vfmadd231pd (%rcx){1to4}, %ymm20, %ymm24 + +// CHECK: vfmadd231pd 4064(%rdx), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xb8,0x42,0x7f] + vfmadd231pd 4064(%rdx), %ymm20, %ymm24 + +// CHECK: vfmadd231pd 4096(%rdx), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xb8,0x82,0x00,0x10,0x00,0x00] + vfmadd231pd 4096(%rdx), %ymm20, %ymm24 + +// CHECK: vfmadd231pd -4096(%rdx), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xb8,0x42,0x80] + vfmadd231pd -4096(%rdx), %ymm20, %ymm24 + +// CHECK: vfmadd231pd -4128(%rdx), %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xb8,0x82,0xe0,0xef,0xff,0xff] + vfmadd231pd -4128(%rdx), %ymm20, %ymm24 + +// CHECK: vfmadd231pd 1016(%rdx){1to4}, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xb8,0x42,0x7f] + vfmadd231pd 1016(%rdx){1to4}, %ymm20, %ymm24 + +// CHECK: vfmadd231pd 1024(%rdx){1to4}, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xb8,0x82,0x00,0x04,0x00,0x00] + vfmadd231pd 1024(%rdx){1to4}, %ymm20, %ymm24 + +// CHECK: vfmadd231pd -1024(%rdx){1to4}, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xb8,0x42,0x80] + vfmadd231pd -1024(%rdx){1to4}, %ymm20, %ymm24 + +// CHECK: vfmadd231pd -1032(%rdx){1to4}, %ymm20, %ymm24 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xb8,0x82,0xf8,0xfb,0xff,0xff] + vfmadd231pd -1032(%rdx){1to4}, %ymm20, %ymm24 + +// CHECK: vfmsub132ps %xmm21, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xa2,0x6d,0x00,0x9a,0xcd] + vfmsub132ps %xmm21, %xmm18, %xmm17 + +// CHECK: vfmsub132ps %xmm21, %xmm18, %xmm17 {%k1} +// CHECK: encoding: [0x62,0xa2,0x6d,0x01,0x9a,0xcd] + vfmsub132ps %xmm21, %xmm18, %xmm17 {%k1} + +// CHECK: vfmsub132ps %xmm21, %xmm18, %xmm17 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x6d,0x81,0x9a,0xcd] + vfmsub132ps %xmm21, %xmm18, %xmm17 {%k1} {z} + +// CHECK: vfmsub132ps (%rcx), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x00,0x9a,0x09] + vfmsub132ps (%rcx), %xmm18, %xmm17 + +// CHECK: vfmsub132ps 291(%rax,%r14,8), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xa2,0x6d,0x00,0x9a,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmsub132ps 291(%rax,%r14,8), %xmm18, %xmm17 + +// CHECK: vfmsub132ps (%rcx){1to4}, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x10,0x9a,0x09] + vfmsub132ps (%rcx){1to4}, %xmm18, %xmm17 + +// CHECK: vfmsub132ps 2032(%rdx), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x00,0x9a,0x4a,0x7f] + vfmsub132ps 2032(%rdx), %xmm18, %xmm17 + +// CHECK: vfmsub132ps 2048(%rdx), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x00,0x9a,0x8a,0x00,0x08,0x00,0x00] + vfmsub132ps 2048(%rdx), %xmm18, %xmm17 + +// CHECK: vfmsub132ps -2048(%rdx), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x00,0x9a,0x4a,0x80] + vfmsub132ps -2048(%rdx), %xmm18, %xmm17 + +// CHECK: vfmsub132ps -2064(%rdx), %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x00,0x9a,0x8a,0xf0,0xf7,0xff,0xff] + vfmsub132ps -2064(%rdx), %xmm18, %xmm17 + +// CHECK: vfmsub132ps 508(%rdx){1to4}, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x10,0x9a,0x4a,0x7f] + vfmsub132ps 508(%rdx){1to4}, %xmm18, %xmm17 + +// CHECK: vfmsub132ps 512(%rdx){1to4}, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x10,0x9a,0x8a,0x00,0x02,0x00,0x00] + vfmsub132ps 512(%rdx){1to4}, %xmm18, %xmm17 + +// CHECK: vfmsub132ps -512(%rdx){1to4}, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x10,0x9a,0x4a,0x80] + vfmsub132ps -512(%rdx){1to4}, %xmm18, %xmm17 + +// CHECK: vfmsub132ps -516(%rdx){1to4}, %xmm18, %xmm17 +// CHECK: encoding: [0x62,0xe2,0x6d,0x10,0x9a,0x8a,0xfc,0xfd,0xff,0xff] + vfmsub132ps -516(%rdx){1to4}, %xmm18, %xmm17 + +// CHECK: vfmsub132ps %ymm23, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x22,0x1d,0x20,0x9a,0xcf] + vfmsub132ps %ymm23, %ymm28, %ymm25 + +// CHECK: vfmsub132ps %ymm23, %ymm28, %ymm25 {%k5} +// CHECK: encoding: [0x62,0x22,0x1d,0x25,0x9a,0xcf] + vfmsub132ps %ymm23, %ymm28, %ymm25 {%k5} + +// CHECK: vfmsub132ps %ymm23, %ymm28, %ymm25 {%k5} {z} +// CHECK: encoding: [0x62,0x22,0x1d,0xa5,0x9a,0xcf] + vfmsub132ps %ymm23, %ymm28, %ymm25 {%k5} {z} + +// CHECK: vfmsub132ps (%rcx), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x20,0x9a,0x09] + vfmsub132ps (%rcx), %ymm28, %ymm25 + +// CHECK: vfmsub132ps 291(%rax,%r14,8), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x22,0x1d,0x20,0x9a,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmsub132ps 291(%rax,%r14,8), %ymm28, %ymm25 + +// CHECK: vfmsub132ps (%rcx){1to8}, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x30,0x9a,0x09] + vfmsub132ps (%rcx){1to8}, %ymm28, %ymm25 + +// CHECK: vfmsub132ps 4064(%rdx), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x20,0x9a,0x4a,0x7f] + vfmsub132ps 4064(%rdx), %ymm28, %ymm25 + +// CHECK: vfmsub132ps 4096(%rdx), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x20,0x9a,0x8a,0x00,0x10,0x00,0x00] + vfmsub132ps 4096(%rdx), %ymm28, %ymm25 + +// CHECK: vfmsub132ps -4096(%rdx), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x20,0x9a,0x4a,0x80] + vfmsub132ps -4096(%rdx), %ymm28, %ymm25 + +// CHECK: vfmsub132ps -4128(%rdx), %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x20,0x9a,0x8a,0xe0,0xef,0xff,0xff] + vfmsub132ps -4128(%rdx), %ymm28, %ymm25 + +// CHECK: vfmsub132ps 508(%rdx){1to8}, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x30,0x9a,0x4a,0x7f] + vfmsub132ps 508(%rdx){1to8}, %ymm28, %ymm25 + +// CHECK: vfmsub132ps 512(%rdx){1to8}, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x30,0x9a,0x8a,0x00,0x02,0x00,0x00] + vfmsub132ps 512(%rdx){1to8}, %ymm28, %ymm25 + +// CHECK: vfmsub132ps -512(%rdx){1to8}, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x30,0x9a,0x4a,0x80] + vfmsub132ps -512(%rdx){1to8}, %ymm28, %ymm25 + +// CHECK: vfmsub132ps -516(%rdx){1to8}, %ymm28, %ymm25 +// CHECK: encoding: [0x62,0x62,0x1d,0x30,0x9a,0x8a,0xfc,0xfd,0xff,0xff] + vfmsub132ps -516(%rdx){1to8}, %ymm28, %ymm25 + +// CHECK: vfmsub132pd %xmm20, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xa2,0xd5,0x00,0x9a,0xd4] + vfmsub132pd %xmm20, %xmm21, %xmm18 + +// CHECK: vfmsub132pd %xmm20, %xmm21, %xmm18 {%k1} +// CHECK: encoding: [0x62,0xa2,0xd5,0x01,0x9a,0xd4] + vfmsub132pd %xmm20, %xmm21, %xmm18 {%k1} + +// CHECK: vfmsub132pd %xmm20, %xmm21, %xmm18 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0xd5,0x81,0x9a,0xd4] + vfmsub132pd %xmm20, %xmm21, %xmm18 {%k1} {z} + +// CHECK: vfmsub132pd (%rcx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0x9a,0x11] + vfmsub132pd (%rcx), %xmm21, %xmm18 + +// CHECK: vfmsub132pd 291(%rax,%r14,8), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xa2,0xd5,0x00,0x9a,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsub132pd 291(%rax,%r14,8), %xmm21, %xmm18 + +// CHECK: vfmsub132pd (%rcx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0x9a,0x11] + vfmsub132pd (%rcx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsub132pd 2032(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0x9a,0x52,0x7f] + vfmsub132pd 2032(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsub132pd 2048(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0x9a,0x92,0x00,0x08,0x00,0x00] + vfmsub132pd 2048(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsub132pd -2048(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0x9a,0x52,0x80] + vfmsub132pd -2048(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsub132pd -2064(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0x9a,0x92,0xf0,0xf7,0xff,0xff] + vfmsub132pd -2064(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsub132pd 1016(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0x9a,0x52,0x7f] + vfmsub132pd 1016(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsub132pd 1024(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0x9a,0x92,0x00,0x04,0x00,0x00] + vfmsub132pd 1024(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsub132pd -1024(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0x9a,0x52,0x80] + vfmsub132pd -1024(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsub132pd -1032(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0x9a,0x92,0xf8,0xfb,0xff,0xff] + vfmsub132pd -1032(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsub132pd %ymm17, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x9a,0xf1] + vfmsub132pd %ymm17, %ymm28, %ymm22 + +// CHECK: vfmsub132pd %ymm17, %ymm28, %ymm22 {%k5} +// CHECK: encoding: [0x62,0xa2,0x9d,0x25,0x9a,0xf1] + vfmsub132pd %ymm17, %ymm28, %ymm22 {%k5} + +// CHECK: vfmsub132pd %ymm17, %ymm28, %ymm22 {%k5} {z} +// CHECK: encoding: [0x62,0xa2,0x9d,0xa5,0x9a,0xf1] + vfmsub132pd %ymm17, %ymm28, %ymm22 {%k5} {z} + +// CHECK: vfmsub132pd (%rcx), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9a,0x31] + vfmsub132pd (%rcx), %ymm28, %ymm22 + +// CHECK: vfmsub132pd 291(%rax,%r14,8), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x9a,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub132pd 291(%rax,%r14,8), %ymm28, %ymm22 + +// CHECK: vfmsub132pd (%rcx){1to4}, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9a,0x31] + vfmsub132pd (%rcx){1to4}, %ymm28, %ymm22 + +// CHECK: vfmsub132pd 4064(%rdx), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9a,0x72,0x7f] + vfmsub132pd 4064(%rdx), %ymm28, %ymm22 + +// CHECK: vfmsub132pd 4096(%rdx), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9a,0xb2,0x00,0x10,0x00,0x00] + vfmsub132pd 4096(%rdx), %ymm28, %ymm22 + +// CHECK: vfmsub132pd -4096(%rdx), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9a,0x72,0x80] + vfmsub132pd -4096(%rdx), %ymm28, %ymm22 + +// CHECK: vfmsub132pd -4128(%rdx), %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9a,0xb2,0xe0,0xef,0xff,0xff] + vfmsub132pd -4128(%rdx), %ymm28, %ymm22 + +// CHECK: vfmsub132pd 1016(%rdx){1to4}, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9a,0x72,0x7f] + vfmsub132pd 1016(%rdx){1to4}, %ymm28, %ymm22 + +// CHECK: vfmsub132pd 1024(%rdx){1to4}, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9a,0xb2,0x00,0x04,0x00,0x00] + vfmsub132pd 1024(%rdx){1to4}, %ymm28, %ymm22 + +// CHECK: vfmsub132pd -1024(%rdx){1to4}, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9a,0x72,0x80] + vfmsub132pd -1024(%rdx){1to4}, %ymm28, %ymm22 + +// CHECK: vfmsub132pd -1032(%rdx){1to4}, %ymm28, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9a,0xb2,0xf8,0xfb,0xff,0xff] + vfmsub132pd -1032(%rdx){1to4}, %ymm28, %ymm22 + +// CHECK: vfmsub213ps %xmm28, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0x82,0x25,0x00,0xaa,0xf4] + vfmsub213ps %xmm28, %xmm27, %xmm22 + +// CHECK: vfmsub213ps %xmm28, %xmm27, %xmm22 {%k2} +// CHECK: encoding: [0x62,0x82,0x25,0x02,0xaa,0xf4] + vfmsub213ps %xmm28, %xmm27, %xmm22 {%k2} + +// CHECK: vfmsub213ps %xmm28, %xmm27, %xmm22 {%k2} {z} +// CHECK: encoding: [0x62,0x82,0x25,0x82,0xaa,0xf4] + vfmsub213ps %xmm28, %xmm27, %xmm22 {%k2} {z} + +// CHECK: vfmsub213ps (%rcx), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xaa,0x31] + vfmsub213ps (%rcx), %xmm27, %xmm22 + +// CHECK: vfmsub213ps 291(%rax,%r14,8), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xa2,0x25,0x00,0xaa,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsub213ps 291(%rax,%r14,8), %xmm27, %xmm22 + +// CHECK: vfmsub213ps (%rcx){1to4}, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xaa,0x31] + vfmsub213ps (%rcx){1to4}, %xmm27, %xmm22 + +// CHECK: vfmsub213ps 2032(%rdx), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xaa,0x72,0x7f] + vfmsub213ps 2032(%rdx), %xmm27, %xmm22 + +// CHECK: vfmsub213ps 2048(%rdx), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xaa,0xb2,0x00,0x08,0x00,0x00] + vfmsub213ps 2048(%rdx), %xmm27, %xmm22 + +// CHECK: vfmsub213ps -2048(%rdx), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xaa,0x72,0x80] + vfmsub213ps -2048(%rdx), %xmm27, %xmm22 + +// CHECK: vfmsub213ps -2064(%rdx), %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xaa,0xb2,0xf0,0xf7,0xff,0xff] + vfmsub213ps -2064(%rdx), %xmm27, %xmm22 + +// CHECK: vfmsub213ps 508(%rdx){1to4}, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xaa,0x72,0x7f] + vfmsub213ps 508(%rdx){1to4}, %xmm27, %xmm22 + +// CHECK: vfmsub213ps 512(%rdx){1to4}, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xaa,0xb2,0x00,0x02,0x00,0x00] + vfmsub213ps 512(%rdx){1to4}, %xmm27, %xmm22 + +// CHECK: vfmsub213ps -512(%rdx){1to4}, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xaa,0x72,0x80] + vfmsub213ps -512(%rdx){1to4}, %xmm27, %xmm22 + +// CHECK: vfmsub213ps -516(%rdx){1to4}, %xmm27, %xmm22 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xaa,0xb2,0xfc,0xfd,0xff,0xff] + vfmsub213ps -516(%rdx){1to4}, %xmm27, %xmm22 + +// CHECK: vfmsub213ps %ymm22, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x22,0x15,0x20,0xaa,0xe6] + vfmsub213ps %ymm22, %ymm29, %ymm28 + +// CHECK: vfmsub213ps %ymm22, %ymm29, %ymm28 {%k1} +// CHECK: encoding: [0x62,0x22,0x15,0x21,0xaa,0xe6] + vfmsub213ps %ymm22, %ymm29, %ymm28 {%k1} + +// CHECK: vfmsub213ps %ymm22, %ymm29, %ymm28 {%k1} {z} +// CHECK: encoding: [0x62,0x22,0x15,0xa1,0xaa,0xe6] + vfmsub213ps %ymm22, %ymm29, %ymm28 {%k1} {z} + +// CHECK: vfmsub213ps (%rcx), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x20,0xaa,0x21] + vfmsub213ps (%rcx), %ymm29, %ymm28 + +// CHECK: vfmsub213ps 291(%rax,%r14,8), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x22,0x15,0x20,0xaa,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmsub213ps 291(%rax,%r14,8), %ymm29, %ymm28 + +// CHECK: vfmsub213ps (%rcx){1to8}, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x30,0xaa,0x21] + vfmsub213ps (%rcx){1to8}, %ymm29, %ymm28 + +// CHECK: vfmsub213ps 4064(%rdx), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x20,0xaa,0x62,0x7f] + vfmsub213ps 4064(%rdx), %ymm29, %ymm28 + +// CHECK: vfmsub213ps 4096(%rdx), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x20,0xaa,0xa2,0x00,0x10,0x00,0x00] + vfmsub213ps 4096(%rdx), %ymm29, %ymm28 + +// CHECK: vfmsub213ps -4096(%rdx), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x20,0xaa,0x62,0x80] + vfmsub213ps -4096(%rdx), %ymm29, %ymm28 + +// CHECK: vfmsub213ps -4128(%rdx), %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x20,0xaa,0xa2,0xe0,0xef,0xff,0xff] + vfmsub213ps -4128(%rdx), %ymm29, %ymm28 + +// CHECK: vfmsub213ps 508(%rdx){1to8}, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x30,0xaa,0x62,0x7f] + vfmsub213ps 508(%rdx){1to8}, %ymm29, %ymm28 + +// CHECK: vfmsub213ps 512(%rdx){1to8}, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x30,0xaa,0xa2,0x00,0x02,0x00,0x00] + vfmsub213ps 512(%rdx){1to8}, %ymm29, %ymm28 + +// CHECK: vfmsub213ps -512(%rdx){1to8}, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x30,0xaa,0x62,0x80] + vfmsub213ps -512(%rdx){1to8}, %ymm29, %ymm28 + +// CHECK: vfmsub213ps -516(%rdx){1to8}, %ymm29, %ymm28 +// CHECK: encoding: [0x62,0x62,0x15,0x30,0xaa,0xa2,0xfc,0xfd,0xff,0xff] + vfmsub213ps -516(%rdx){1to8}, %ymm29, %ymm28 + +// CHECK: vfmsub213pd %xmm20, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xe5,0x00,0xaa,0xdc] + vfmsub213pd %xmm20, %xmm19, %xmm19 + +// CHECK: vfmsub213pd %xmm20, %xmm19, %xmm19 {%k1} +// CHECK: encoding: [0x62,0xa2,0xe5,0x01,0xaa,0xdc] + vfmsub213pd %xmm20, %xmm19, %xmm19 {%k1} + +// CHECK: vfmsub213pd %xmm20, %xmm19, %xmm19 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0xe5,0x81,0xaa,0xdc] + vfmsub213pd %xmm20, %xmm19, %xmm19 {%k1} {z} + +// CHECK: vfmsub213pd (%rcx), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xaa,0x19] + vfmsub213pd (%rcx), %xmm19, %xmm19 + +// CHECK: vfmsub213pd 291(%rax,%r14,8), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xe5,0x00,0xaa,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmsub213pd 291(%rax,%r14,8), %xmm19, %xmm19 + +// CHECK: vfmsub213pd (%rcx){1to2}, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xaa,0x19] + vfmsub213pd (%rcx){1to2}, %xmm19, %xmm19 + +// CHECK: vfmsub213pd 2032(%rdx), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xaa,0x5a,0x7f] + vfmsub213pd 2032(%rdx), %xmm19, %xmm19 + +// CHECK: vfmsub213pd 2048(%rdx), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xaa,0x9a,0x00,0x08,0x00,0x00] + vfmsub213pd 2048(%rdx), %xmm19, %xmm19 + +// CHECK: vfmsub213pd -2048(%rdx), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xaa,0x5a,0x80] + vfmsub213pd -2048(%rdx), %xmm19, %xmm19 + +// CHECK: vfmsub213pd -2064(%rdx), %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xaa,0x9a,0xf0,0xf7,0xff,0xff] + vfmsub213pd -2064(%rdx), %xmm19, %xmm19 + +// CHECK: vfmsub213pd 1016(%rdx){1to2}, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xaa,0x5a,0x7f] + vfmsub213pd 1016(%rdx){1to2}, %xmm19, %xmm19 + +// CHECK: vfmsub213pd 1024(%rdx){1to2}, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xaa,0x9a,0x00,0x04,0x00,0x00] + vfmsub213pd 1024(%rdx){1to2}, %xmm19, %xmm19 + +// CHECK: vfmsub213pd -1024(%rdx){1to2}, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xaa,0x5a,0x80] + vfmsub213pd -1024(%rdx){1to2}, %xmm19, %xmm19 + +// CHECK: vfmsub213pd -1032(%rdx){1to2}, %xmm19, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xaa,0x9a,0xf8,0xfb,0xff,0xff] + vfmsub213pd -1032(%rdx){1to2}, %xmm19, %xmm19 + +// CHECK: vfmsub213pd %ymm28, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x02,0xb5,0x20,0xaa,0xdc] + vfmsub213pd %ymm28, %ymm25, %ymm27 + +// CHECK: vfmsub213pd %ymm28, %ymm25, %ymm27 {%k4} +// CHECK: encoding: [0x62,0x02,0xb5,0x24,0xaa,0xdc] + vfmsub213pd %ymm28, %ymm25, %ymm27 {%k4} + +// CHECK: vfmsub213pd %ymm28, %ymm25, %ymm27 {%k4} {z} +// CHECK: encoding: [0x62,0x02,0xb5,0xa4,0xaa,0xdc] + vfmsub213pd %ymm28, %ymm25, %ymm27 {%k4} {z} + +// CHECK: vfmsub213pd (%rcx), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xaa,0x19] + vfmsub213pd (%rcx), %ymm25, %ymm27 + +// CHECK: vfmsub213pd 291(%rax,%r14,8), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x22,0xb5,0x20,0xaa,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmsub213pd 291(%rax,%r14,8), %ymm25, %ymm27 + +// CHECK: vfmsub213pd (%rcx){1to4}, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xaa,0x19] + vfmsub213pd (%rcx){1to4}, %ymm25, %ymm27 + +// CHECK: vfmsub213pd 4064(%rdx), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xaa,0x5a,0x7f] + vfmsub213pd 4064(%rdx), %ymm25, %ymm27 + +// CHECK: vfmsub213pd 4096(%rdx), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xaa,0x9a,0x00,0x10,0x00,0x00] + vfmsub213pd 4096(%rdx), %ymm25, %ymm27 + +// CHECK: vfmsub213pd -4096(%rdx), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xaa,0x5a,0x80] + vfmsub213pd -4096(%rdx), %ymm25, %ymm27 + +// CHECK: vfmsub213pd -4128(%rdx), %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xaa,0x9a,0xe0,0xef,0xff,0xff] + vfmsub213pd -4128(%rdx), %ymm25, %ymm27 + +// CHECK: vfmsub213pd 1016(%rdx){1to4}, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xaa,0x5a,0x7f] + vfmsub213pd 1016(%rdx){1to4}, %ymm25, %ymm27 + +// CHECK: vfmsub213pd 1024(%rdx){1to4}, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xaa,0x9a,0x00,0x04,0x00,0x00] + vfmsub213pd 1024(%rdx){1to4}, %ymm25, %ymm27 + +// CHECK: vfmsub213pd -1024(%rdx){1to4}, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xaa,0x5a,0x80] + vfmsub213pd -1024(%rdx){1to4}, %ymm25, %ymm27 + +// CHECK: vfmsub213pd -1032(%rdx){1to4}, %ymm25, %ymm27 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xaa,0x9a,0xf8,0xfb,0xff,0xff] + vfmsub213pd -1032(%rdx){1to4}, %ymm25, %ymm27 + +// CHECK: vfmsub231ps %xmm25, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x02,0x65,0x00,0xba,0xe1] + vfmsub231ps %xmm25, %xmm19, %xmm28 + +// CHECK: vfmsub231ps %xmm25, %xmm19, %xmm28 {%k1} +// CHECK: encoding: [0x62,0x02,0x65,0x01,0xba,0xe1] + vfmsub231ps %xmm25, %xmm19, %xmm28 {%k1} + +// CHECK: vfmsub231ps %xmm25, %xmm19, %xmm28 {%k1} {z} +// CHECK: encoding: [0x62,0x02,0x65,0x81,0xba,0xe1] + vfmsub231ps %xmm25, %xmm19, %xmm28 {%k1} {z} + +// CHECK: vfmsub231ps (%rcx), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x00,0xba,0x21] + vfmsub231ps (%rcx), %xmm19, %xmm28 + +// CHECK: vfmsub231ps 291(%rax,%r14,8), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x22,0x65,0x00,0xba,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmsub231ps 291(%rax,%r14,8), %xmm19, %xmm28 + +// CHECK: vfmsub231ps (%rcx){1to4}, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x10,0xba,0x21] + vfmsub231ps (%rcx){1to4}, %xmm19, %xmm28 + +// CHECK: vfmsub231ps 2032(%rdx), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x00,0xba,0x62,0x7f] + vfmsub231ps 2032(%rdx), %xmm19, %xmm28 + +// CHECK: vfmsub231ps 2048(%rdx), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x00,0xba,0xa2,0x00,0x08,0x00,0x00] + vfmsub231ps 2048(%rdx), %xmm19, %xmm28 + +// CHECK: vfmsub231ps -2048(%rdx), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x00,0xba,0x62,0x80] + vfmsub231ps -2048(%rdx), %xmm19, %xmm28 + +// CHECK: vfmsub231ps -2064(%rdx), %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x00,0xba,0xa2,0xf0,0xf7,0xff,0xff] + vfmsub231ps -2064(%rdx), %xmm19, %xmm28 + +// CHECK: vfmsub231ps 508(%rdx){1to4}, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x10,0xba,0x62,0x7f] + vfmsub231ps 508(%rdx){1to4}, %xmm19, %xmm28 + +// CHECK: vfmsub231ps 512(%rdx){1to4}, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x10,0xba,0xa2,0x00,0x02,0x00,0x00] + vfmsub231ps 512(%rdx){1to4}, %xmm19, %xmm28 + +// CHECK: vfmsub231ps -512(%rdx){1to4}, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x10,0xba,0x62,0x80] + vfmsub231ps -512(%rdx){1to4}, %xmm19, %xmm28 + +// CHECK: vfmsub231ps -516(%rdx){1to4}, %xmm19, %xmm28 +// CHECK: encoding: [0x62,0x62,0x65,0x10,0xba,0xa2,0xfc,0xfd,0xff,0xff] + vfmsub231ps -516(%rdx){1to4}, %xmm19, %xmm28 + +// CHECK: vfmsub231ps %ymm26, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0x82,0x2d,0x20,0xba,0xfa] + vfmsub231ps %ymm26, %ymm26, %ymm23 + +// CHECK: vfmsub231ps %ymm26, %ymm26, %ymm23 {%k1} +// CHECK: encoding: [0x62,0x82,0x2d,0x21,0xba,0xfa] + vfmsub231ps %ymm26, %ymm26, %ymm23 {%k1} + +// CHECK: vfmsub231ps %ymm26, %ymm26, %ymm23 {%k1} {z} +// CHECK: encoding: [0x62,0x82,0x2d,0xa1,0xba,0xfa] + vfmsub231ps %ymm26, %ymm26, %ymm23 {%k1} {z} + +// CHECK: vfmsub231ps (%rcx), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xba,0x39] + vfmsub231ps (%rcx), %ymm26, %ymm23 + +// CHECK: vfmsub231ps 291(%rax,%r14,8), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xa2,0x2d,0x20,0xba,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmsub231ps 291(%rax,%r14,8), %ymm26, %ymm23 + +// CHECK: vfmsub231ps (%rcx){1to8}, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xba,0x39] + vfmsub231ps (%rcx){1to8}, %ymm26, %ymm23 + +// CHECK: vfmsub231ps 4064(%rdx), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xba,0x7a,0x7f] + vfmsub231ps 4064(%rdx), %ymm26, %ymm23 + +// CHECK: vfmsub231ps 4096(%rdx), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xba,0xba,0x00,0x10,0x00,0x00] + vfmsub231ps 4096(%rdx), %ymm26, %ymm23 + +// CHECK: vfmsub231ps -4096(%rdx), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xba,0x7a,0x80] + vfmsub231ps -4096(%rdx), %ymm26, %ymm23 + +// CHECK: vfmsub231ps -4128(%rdx), %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x20,0xba,0xba,0xe0,0xef,0xff,0xff] + vfmsub231ps -4128(%rdx), %ymm26, %ymm23 + +// CHECK: vfmsub231ps 508(%rdx){1to8}, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xba,0x7a,0x7f] + vfmsub231ps 508(%rdx){1to8}, %ymm26, %ymm23 + +// CHECK: vfmsub231ps 512(%rdx){1to8}, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xba,0xba,0x00,0x02,0x00,0x00] + vfmsub231ps 512(%rdx){1to8}, %ymm26, %ymm23 + +// CHECK: vfmsub231ps -512(%rdx){1to8}, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xba,0x7a,0x80] + vfmsub231ps -512(%rdx){1to8}, %ymm26, %ymm23 + +// CHECK: vfmsub231ps -516(%rdx){1to8}, %ymm26, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x2d,0x30,0xba,0xba,0xfc,0xfd,0xff,0xff] + vfmsub231ps -516(%rdx){1to8}, %ymm26, %ymm23 + +// CHECK: vfmsub231pd %xmm23, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x22,0xdd,0x00,0xba,0xe7] + vfmsub231pd %xmm23, %xmm20, %xmm28 + +// CHECK: vfmsub231pd %xmm23, %xmm20, %xmm28 {%k4} +// CHECK: encoding: [0x62,0x22,0xdd,0x04,0xba,0xe7] + vfmsub231pd %xmm23, %xmm20, %xmm28 {%k4} + +// CHECK: vfmsub231pd %xmm23, %xmm20, %xmm28 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0xdd,0x84,0xba,0xe7] + vfmsub231pd %xmm23, %xmm20, %xmm28 {%k4} {z} + +// CHECK: vfmsub231pd (%rcx), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xba,0x21] + vfmsub231pd (%rcx), %xmm20, %xmm28 + +// CHECK: vfmsub231pd 291(%rax,%r14,8), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x22,0xdd,0x00,0xba,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmsub231pd 291(%rax,%r14,8), %xmm20, %xmm28 + +// CHECK: vfmsub231pd (%rcx){1to2}, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xba,0x21] + vfmsub231pd (%rcx){1to2}, %xmm20, %xmm28 + +// CHECK: vfmsub231pd 2032(%rdx), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xba,0x62,0x7f] + vfmsub231pd 2032(%rdx), %xmm20, %xmm28 + +// CHECK: vfmsub231pd 2048(%rdx), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xba,0xa2,0x00,0x08,0x00,0x00] + vfmsub231pd 2048(%rdx), %xmm20, %xmm28 + +// CHECK: vfmsub231pd -2048(%rdx), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xba,0x62,0x80] + vfmsub231pd -2048(%rdx), %xmm20, %xmm28 + +// CHECK: vfmsub231pd -2064(%rdx), %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x00,0xba,0xa2,0xf0,0xf7,0xff,0xff] + vfmsub231pd -2064(%rdx), %xmm20, %xmm28 + +// CHECK: vfmsub231pd 1016(%rdx){1to2}, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xba,0x62,0x7f] + vfmsub231pd 1016(%rdx){1to2}, %xmm20, %xmm28 + +// CHECK: vfmsub231pd 1024(%rdx){1to2}, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xba,0xa2,0x00,0x04,0x00,0x00] + vfmsub231pd 1024(%rdx){1to2}, %xmm20, %xmm28 + +// CHECK: vfmsub231pd -1024(%rdx){1to2}, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xba,0x62,0x80] + vfmsub231pd -1024(%rdx){1to2}, %xmm20, %xmm28 + +// CHECK: vfmsub231pd -1032(%rdx){1to2}, %xmm20, %xmm28 +// CHECK: encoding: [0x62,0x62,0xdd,0x10,0xba,0xa2,0xf8,0xfb,0xff,0xff] + vfmsub231pd -1032(%rdx){1to2}, %xmm20, %xmm28 + +// CHECK: vfmsub231pd %ymm22, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xa2,0xed,0x20,0xba,0xce] + vfmsub231pd %ymm22, %ymm18, %ymm17 + +// CHECK: vfmsub231pd %ymm22, %ymm18, %ymm17 {%k2} +// CHECK: encoding: [0x62,0xa2,0xed,0x22,0xba,0xce] + vfmsub231pd %ymm22, %ymm18, %ymm17 {%k2} + +// CHECK: vfmsub231pd %ymm22, %ymm18, %ymm17 {%k2} {z} +// CHECK: encoding: [0x62,0xa2,0xed,0xa2,0xba,0xce] + vfmsub231pd %ymm22, %ymm18, %ymm17 {%k2} {z} + +// CHECK: vfmsub231pd (%rcx), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xba,0x09] + vfmsub231pd (%rcx), %ymm18, %ymm17 + +// CHECK: vfmsub231pd 291(%rax,%r14,8), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xa2,0xed,0x20,0xba,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmsub231pd 291(%rax,%r14,8), %ymm18, %ymm17 + +// CHECK: vfmsub231pd (%rcx){1to4}, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xba,0x09] + vfmsub231pd (%rcx){1to4}, %ymm18, %ymm17 + +// CHECK: vfmsub231pd 4064(%rdx), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xba,0x4a,0x7f] + vfmsub231pd 4064(%rdx), %ymm18, %ymm17 + +// CHECK: vfmsub231pd 4096(%rdx), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xba,0x8a,0x00,0x10,0x00,0x00] + vfmsub231pd 4096(%rdx), %ymm18, %ymm17 + +// CHECK: vfmsub231pd -4096(%rdx), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xba,0x4a,0x80] + vfmsub231pd -4096(%rdx), %ymm18, %ymm17 + +// CHECK: vfmsub231pd -4128(%rdx), %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xba,0x8a,0xe0,0xef,0xff,0xff] + vfmsub231pd -4128(%rdx), %ymm18, %ymm17 + +// CHECK: vfmsub231pd 1016(%rdx){1to4}, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xba,0x4a,0x7f] + vfmsub231pd 1016(%rdx){1to4}, %ymm18, %ymm17 + +// CHECK: vfmsub231pd 1024(%rdx){1to4}, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xba,0x8a,0x00,0x04,0x00,0x00] + vfmsub231pd 1024(%rdx){1to4}, %ymm18, %ymm17 + +// CHECK: vfmsub231pd -1024(%rdx){1to4}, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xba,0x4a,0x80] + vfmsub231pd -1024(%rdx){1to4}, %ymm18, %ymm17 + +// CHECK: vfmsub231pd -1032(%rdx){1to4}, %ymm18, %ymm17 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xba,0x8a,0xf8,0xfb,0xff,0xff] + vfmsub231pd -1032(%rdx){1to4}, %ymm18, %ymm17 + +// CHECK: vfmaddsub132ps %xmm18, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x22,0x25,0x00,0x96,0xc2] + vfmaddsub132ps %xmm18, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps %xmm18, %xmm27, %xmm24 {%k2} +// CHECK: encoding: [0x62,0x22,0x25,0x02,0x96,0xc2] + vfmaddsub132ps %xmm18, %xmm27, %xmm24 {%k2} + +// CHECK: vfmaddsub132ps %xmm18, %xmm27, %xmm24 {%k2} {z} +// CHECK: encoding: [0x62,0x22,0x25,0x82,0x96,0xc2] + vfmaddsub132ps %xmm18, %xmm27, %xmm24 {%k2} {z} + +// CHECK: vfmaddsub132ps (%rcx), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x00,0x96,0x01] + vfmaddsub132ps (%rcx), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps 291(%rax,%r14,8), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x22,0x25,0x00,0x96,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132ps 291(%rax,%r14,8), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps (%rcx){1to4}, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x10,0x96,0x01] + vfmaddsub132ps (%rcx){1to4}, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps 2032(%rdx), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x00,0x96,0x42,0x7f] + vfmaddsub132ps 2032(%rdx), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps 2048(%rdx), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x00,0x96,0x82,0x00,0x08,0x00,0x00] + vfmaddsub132ps 2048(%rdx), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps -2048(%rdx), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x00,0x96,0x42,0x80] + vfmaddsub132ps -2048(%rdx), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps -2064(%rdx), %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x00,0x96,0x82,0xf0,0xf7,0xff,0xff] + vfmaddsub132ps -2064(%rdx), %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps 508(%rdx){1to4}, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x10,0x96,0x42,0x7f] + vfmaddsub132ps 508(%rdx){1to4}, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps 512(%rdx){1to4}, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x10,0x96,0x82,0x00,0x02,0x00,0x00] + vfmaddsub132ps 512(%rdx){1to4}, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps -512(%rdx){1to4}, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x10,0x96,0x42,0x80] + vfmaddsub132ps -512(%rdx){1to4}, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps -516(%rdx){1to4}, %xmm27, %xmm24 +// CHECK: encoding: [0x62,0x62,0x25,0x10,0x96,0x82,0xfc,0xfd,0xff,0xff] + vfmaddsub132ps -516(%rdx){1to4}, %xmm27, %xmm24 + +// CHECK: vfmaddsub132ps %ymm24, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0x82,0x5d,0x20,0x96,0xe8] + vfmaddsub132ps %ymm24, %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps %ymm24, %ymm20, %ymm21 {%k5} +// CHECK: encoding: [0x62,0x82,0x5d,0x25,0x96,0xe8] + vfmaddsub132ps %ymm24, %ymm20, %ymm21 {%k5} + +// CHECK: vfmaddsub132ps %ymm24, %ymm20, %ymm21 {%k5} {z} +// CHECK: encoding: [0x62,0x82,0x5d,0xa5,0x96,0xe8] + vfmaddsub132ps %ymm24, %ymm20, %ymm21 {%k5} {z} + +// CHECK: vfmaddsub132ps (%rcx), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0x96,0x29] + vfmaddsub132ps (%rcx), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps 291(%rax,%r14,8), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xa2,0x5d,0x20,0x96,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132ps 291(%rax,%r14,8), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps (%rcx){1to8}, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0x96,0x29] + vfmaddsub132ps (%rcx){1to8}, %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps 4064(%rdx), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0x96,0x6a,0x7f] + vfmaddsub132ps 4064(%rdx), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps 4096(%rdx), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0x96,0xaa,0x00,0x10,0x00,0x00] + vfmaddsub132ps 4096(%rdx), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps -4096(%rdx), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0x96,0x6a,0x80] + vfmaddsub132ps -4096(%rdx), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps -4128(%rdx), %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0x96,0xaa,0xe0,0xef,0xff,0xff] + vfmaddsub132ps -4128(%rdx), %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps 508(%rdx){1to8}, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0x96,0x6a,0x7f] + vfmaddsub132ps 508(%rdx){1to8}, %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps 512(%rdx){1to8}, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0x96,0xaa,0x00,0x02,0x00,0x00] + vfmaddsub132ps 512(%rdx){1to8}, %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps -512(%rdx){1to8}, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0x96,0x6a,0x80] + vfmaddsub132ps -512(%rdx){1to8}, %ymm20, %ymm21 + +// CHECK: vfmaddsub132ps -516(%rdx){1to8}, %ymm20, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0x96,0xaa,0xfc,0xfd,0xff,0xff] + vfmaddsub132ps -516(%rdx){1to8}, %ymm20, %ymm21 + +// CHECK: vfmaddsub132pd %xmm20, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x22,0xa5,0x00,0x96,0xd4] + vfmaddsub132pd %xmm20, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd %xmm20, %xmm27, %xmm26 {%k6} +// CHECK: encoding: [0x62,0x22,0xa5,0x06,0x96,0xd4] + vfmaddsub132pd %xmm20, %xmm27, %xmm26 {%k6} + +// CHECK: vfmaddsub132pd %xmm20, %xmm27, %xmm26 {%k6} {z} +// CHECK: encoding: [0x62,0x22,0xa5,0x86,0x96,0xd4] + vfmaddsub132pd %xmm20, %xmm27, %xmm26 {%k6} {z} + +// CHECK: vfmaddsub132pd (%rcx), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x00,0x96,0x11] + vfmaddsub132pd (%rcx), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd 291(%rax,%r14,8), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x22,0xa5,0x00,0x96,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132pd 291(%rax,%r14,8), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd (%rcx){1to2}, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x10,0x96,0x11] + vfmaddsub132pd (%rcx){1to2}, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd 2032(%rdx), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x00,0x96,0x52,0x7f] + vfmaddsub132pd 2032(%rdx), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd 2048(%rdx), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x00,0x96,0x92,0x00,0x08,0x00,0x00] + vfmaddsub132pd 2048(%rdx), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd -2048(%rdx), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x00,0x96,0x52,0x80] + vfmaddsub132pd -2048(%rdx), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd -2064(%rdx), %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x00,0x96,0x92,0xf0,0xf7,0xff,0xff] + vfmaddsub132pd -2064(%rdx), %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd 1016(%rdx){1to2}, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x10,0x96,0x52,0x7f] + vfmaddsub132pd 1016(%rdx){1to2}, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd 1024(%rdx){1to2}, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x10,0x96,0x92,0x00,0x04,0x00,0x00] + vfmaddsub132pd 1024(%rdx){1to2}, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd -1024(%rdx){1to2}, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x10,0x96,0x52,0x80] + vfmaddsub132pd -1024(%rdx){1to2}, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd -1032(%rdx){1to2}, %xmm27, %xmm26 +// CHECK: encoding: [0x62,0x62,0xa5,0x10,0x96,0x92,0xf8,0xfb,0xff,0xff] + vfmaddsub132pd -1032(%rdx){1to2}, %xmm27, %xmm26 + +// CHECK: vfmaddsub132pd %ymm28, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x02,0xed,0x20,0x96,0xf4] + vfmaddsub132pd %ymm28, %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd %ymm28, %ymm18, %ymm30 {%k2} +// CHECK: encoding: [0x62,0x02,0xed,0x22,0x96,0xf4] + vfmaddsub132pd %ymm28, %ymm18, %ymm30 {%k2} + +// CHECK: vfmaddsub132pd %ymm28, %ymm18, %ymm30 {%k2} {z} +// CHECK: encoding: [0x62,0x02,0xed,0xa2,0x96,0xf4] + vfmaddsub132pd %ymm28, %ymm18, %ymm30 {%k2} {z} + +// CHECK: vfmaddsub132pd (%rcx), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x20,0x96,0x31] + vfmaddsub132pd (%rcx), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd 291(%rax,%r14,8), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x22,0xed,0x20,0x96,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub132pd 291(%rax,%r14,8), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd (%rcx){1to4}, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x30,0x96,0x31] + vfmaddsub132pd (%rcx){1to4}, %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd 4064(%rdx), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x20,0x96,0x72,0x7f] + vfmaddsub132pd 4064(%rdx), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd 4096(%rdx), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x20,0x96,0xb2,0x00,0x10,0x00,0x00] + vfmaddsub132pd 4096(%rdx), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd -4096(%rdx), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x20,0x96,0x72,0x80] + vfmaddsub132pd -4096(%rdx), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd -4128(%rdx), %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x20,0x96,0xb2,0xe0,0xef,0xff,0xff] + vfmaddsub132pd -4128(%rdx), %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd 1016(%rdx){1to4}, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x30,0x96,0x72,0x7f] + vfmaddsub132pd 1016(%rdx){1to4}, %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd 1024(%rdx){1to4}, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x30,0x96,0xb2,0x00,0x04,0x00,0x00] + vfmaddsub132pd 1024(%rdx){1to4}, %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd -1024(%rdx){1to4}, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x30,0x96,0x72,0x80] + vfmaddsub132pd -1024(%rdx){1to4}, %ymm18, %ymm30 + +// CHECK: vfmaddsub132pd -1032(%rdx){1to4}, %ymm18, %ymm30 +// CHECK: encoding: [0x62,0x62,0xed,0x30,0x96,0xb2,0xf8,0xfb,0xff,0xff] + vfmaddsub132pd -1032(%rdx){1to4}, %ymm18, %ymm30 + +// CHECK: vfmaddsub213ps %xmm17, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xa2,0x15,0x00,0xa6,0xe1] + vfmaddsub213ps %xmm17, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps %xmm17, %xmm29, %xmm20 {%k1} +// CHECK: encoding: [0x62,0xa2,0x15,0x01,0xa6,0xe1] + vfmaddsub213ps %xmm17, %xmm29, %xmm20 {%k1} + +// CHECK: vfmaddsub213ps %xmm17, %xmm29, %xmm20 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x15,0x81,0xa6,0xe1] + vfmaddsub213ps %xmm17, %xmm29, %xmm20 {%k1} {z} + +// CHECK: vfmaddsub213ps (%rcx), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xa6,0x21] + vfmaddsub213ps (%rcx), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps 291(%rax,%r14,8), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xa2,0x15,0x00,0xa6,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213ps 291(%rax,%r14,8), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps (%rcx){1to4}, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xa6,0x21] + vfmaddsub213ps (%rcx){1to4}, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps 2032(%rdx), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xa6,0x62,0x7f] + vfmaddsub213ps 2032(%rdx), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps 2048(%rdx), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xa6,0xa2,0x00,0x08,0x00,0x00] + vfmaddsub213ps 2048(%rdx), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps -2048(%rdx), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xa6,0x62,0x80] + vfmaddsub213ps -2048(%rdx), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps -2064(%rdx), %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xa6,0xa2,0xf0,0xf7,0xff,0xff] + vfmaddsub213ps -2064(%rdx), %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps 508(%rdx){1to4}, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xa6,0x62,0x7f] + vfmaddsub213ps 508(%rdx){1to4}, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps 512(%rdx){1to4}, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xa6,0xa2,0x00,0x02,0x00,0x00] + vfmaddsub213ps 512(%rdx){1to4}, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps -512(%rdx){1to4}, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xa6,0x62,0x80] + vfmaddsub213ps -512(%rdx){1to4}, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps -516(%rdx){1to4}, %xmm29, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xa6,0xa2,0xfc,0xfd,0xff,0xff] + vfmaddsub213ps -516(%rdx){1to4}, %xmm29, %xmm20 + +// CHECK: vfmaddsub213ps %ymm23, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x22,0x25,0x20,0xa6,0xcf] + vfmaddsub213ps %ymm23, %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps %ymm23, %ymm27, %ymm25 {%k4} +// CHECK: encoding: [0x62,0x22,0x25,0x24,0xa6,0xcf] + vfmaddsub213ps %ymm23, %ymm27, %ymm25 {%k4} + +// CHECK: vfmaddsub213ps %ymm23, %ymm27, %ymm25 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0x25,0xa4,0xa6,0xcf] + vfmaddsub213ps %ymm23, %ymm27, %ymm25 {%k4} {z} + +// CHECK: vfmaddsub213ps (%rcx), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x20,0xa6,0x09] + vfmaddsub213ps (%rcx), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps 291(%rax,%r14,8), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x22,0x25,0x20,0xa6,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213ps 291(%rax,%r14,8), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps (%rcx){1to8}, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x30,0xa6,0x09] + vfmaddsub213ps (%rcx){1to8}, %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps 4064(%rdx), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x20,0xa6,0x4a,0x7f] + vfmaddsub213ps 4064(%rdx), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps 4096(%rdx), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x20,0xa6,0x8a,0x00,0x10,0x00,0x00] + vfmaddsub213ps 4096(%rdx), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps -4096(%rdx), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x20,0xa6,0x4a,0x80] + vfmaddsub213ps -4096(%rdx), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps -4128(%rdx), %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x20,0xa6,0x8a,0xe0,0xef,0xff,0xff] + vfmaddsub213ps -4128(%rdx), %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps 508(%rdx){1to8}, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x30,0xa6,0x4a,0x7f] + vfmaddsub213ps 508(%rdx){1to8}, %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps 512(%rdx){1to8}, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x30,0xa6,0x8a,0x00,0x02,0x00,0x00] + vfmaddsub213ps 512(%rdx){1to8}, %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps -512(%rdx){1to8}, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x30,0xa6,0x4a,0x80] + vfmaddsub213ps -512(%rdx){1to8}, %ymm27, %ymm25 + +// CHECK: vfmaddsub213ps -516(%rdx){1to8}, %ymm27, %ymm25 +// CHECK: encoding: [0x62,0x62,0x25,0x30,0xa6,0x8a,0xfc,0xfd,0xff,0xff] + vfmaddsub213ps -516(%rdx){1to8}, %ymm27, %ymm25 + +// CHECK: vfmaddsub213pd %xmm19, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x22,0x95,0x00,0xa6,0xcb] + vfmaddsub213pd %xmm19, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd %xmm19, %xmm29, %xmm25 {%k7} +// CHECK: encoding: [0x62,0x22,0x95,0x07,0xa6,0xcb] + vfmaddsub213pd %xmm19, %xmm29, %xmm25 {%k7} + +// CHECK: vfmaddsub213pd %xmm19, %xmm29, %xmm25 {%k7} {z} +// CHECK: encoding: [0x62,0x22,0x95,0x87,0xa6,0xcb] + vfmaddsub213pd %xmm19, %xmm29, %xmm25 {%k7} {z} + +// CHECK: vfmaddsub213pd (%rcx), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x00,0xa6,0x09] + vfmaddsub213pd (%rcx), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd 291(%rax,%r14,8), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x22,0x95,0x00,0xa6,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213pd 291(%rax,%r14,8), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd (%rcx){1to2}, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x10,0xa6,0x09] + vfmaddsub213pd (%rcx){1to2}, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd 2032(%rdx), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x00,0xa6,0x4a,0x7f] + vfmaddsub213pd 2032(%rdx), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd 2048(%rdx), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x00,0xa6,0x8a,0x00,0x08,0x00,0x00] + vfmaddsub213pd 2048(%rdx), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd -2048(%rdx), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x00,0xa6,0x4a,0x80] + vfmaddsub213pd -2048(%rdx), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd -2064(%rdx), %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x00,0xa6,0x8a,0xf0,0xf7,0xff,0xff] + vfmaddsub213pd -2064(%rdx), %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd 1016(%rdx){1to2}, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x10,0xa6,0x4a,0x7f] + vfmaddsub213pd 1016(%rdx){1to2}, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd 1024(%rdx){1to2}, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x10,0xa6,0x8a,0x00,0x04,0x00,0x00] + vfmaddsub213pd 1024(%rdx){1to2}, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd -1024(%rdx){1to2}, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x10,0xa6,0x4a,0x80] + vfmaddsub213pd -1024(%rdx){1to2}, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd -1032(%rdx){1to2}, %xmm29, %xmm25 +// CHECK: encoding: [0x62,0x62,0x95,0x10,0xa6,0x8a,0xf8,0xfb,0xff,0xff] + vfmaddsub213pd -1032(%rdx){1to2}, %xmm29, %xmm25 + +// CHECK: vfmaddsub213pd %ymm20, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xa2,0xf5,0x20,0xa6,0xec] + vfmaddsub213pd %ymm20, %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd %ymm20, %ymm17, %ymm21 {%k4} +// CHECK: encoding: [0x62,0xa2,0xf5,0x24,0xa6,0xec] + vfmaddsub213pd %ymm20, %ymm17, %ymm21 {%k4} + +// CHECK: vfmaddsub213pd %ymm20, %ymm17, %ymm21 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0xf5,0xa4,0xa6,0xec] + vfmaddsub213pd %ymm20, %ymm17, %ymm21 {%k4} {z} + +// CHECK: vfmaddsub213pd (%rcx), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x20,0xa6,0x29] + vfmaddsub213pd (%rcx), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd 291(%rax,%r14,8), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xa2,0xf5,0x20,0xa6,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub213pd 291(%rax,%r14,8), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd (%rcx){1to4}, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x30,0xa6,0x29] + vfmaddsub213pd (%rcx){1to4}, %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd 4064(%rdx), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x20,0xa6,0x6a,0x7f] + vfmaddsub213pd 4064(%rdx), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd 4096(%rdx), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x20,0xa6,0xaa,0x00,0x10,0x00,0x00] + vfmaddsub213pd 4096(%rdx), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd -4096(%rdx), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x20,0xa6,0x6a,0x80] + vfmaddsub213pd -4096(%rdx), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd -4128(%rdx), %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x20,0xa6,0xaa,0xe0,0xef,0xff,0xff] + vfmaddsub213pd -4128(%rdx), %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd 1016(%rdx){1to4}, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x30,0xa6,0x6a,0x7f] + vfmaddsub213pd 1016(%rdx){1to4}, %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd 1024(%rdx){1to4}, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x30,0xa6,0xaa,0x00,0x04,0x00,0x00] + vfmaddsub213pd 1024(%rdx){1to4}, %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd -1024(%rdx){1to4}, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x30,0xa6,0x6a,0x80] + vfmaddsub213pd -1024(%rdx){1to4}, %ymm17, %ymm21 + +// CHECK: vfmaddsub213pd -1032(%rdx){1to4}, %ymm17, %ymm21 +// CHECK: encoding: [0x62,0xe2,0xf5,0x30,0xa6,0xaa,0xf8,0xfb,0xff,0xff] + vfmaddsub213pd -1032(%rdx){1to4}, %ymm17, %ymm21 + +// CHECK: vfmaddsub231ps %xmm20, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x15,0x00,0xb6,0xdc] + vfmaddsub231ps %xmm20, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps %xmm20, %xmm29, %xmm19 {%k6} +// CHECK: encoding: [0x62,0xa2,0x15,0x06,0xb6,0xdc] + vfmaddsub231ps %xmm20, %xmm29, %xmm19 {%k6} + +// CHECK: vfmaddsub231ps %xmm20, %xmm29, %xmm19 {%k6} {z} +// CHECK: encoding: [0x62,0xa2,0x15,0x86,0xb6,0xdc] + vfmaddsub231ps %xmm20, %xmm29, %xmm19 {%k6} {z} + +// CHECK: vfmaddsub231ps (%rcx), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xb6,0x19] + vfmaddsub231ps (%rcx), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps 291(%rax,%r14,8), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x15,0x00,0xb6,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231ps 291(%rax,%r14,8), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps (%rcx){1to4}, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xb6,0x19] + vfmaddsub231ps (%rcx){1to4}, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps 2032(%rdx), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xb6,0x5a,0x7f] + vfmaddsub231ps 2032(%rdx), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps 2048(%rdx), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xb6,0x9a,0x00,0x08,0x00,0x00] + vfmaddsub231ps 2048(%rdx), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps -2048(%rdx), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xb6,0x5a,0x80] + vfmaddsub231ps -2048(%rdx), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps -2064(%rdx), %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x00,0xb6,0x9a,0xf0,0xf7,0xff,0xff] + vfmaddsub231ps -2064(%rdx), %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps 508(%rdx){1to4}, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xb6,0x5a,0x7f] + vfmaddsub231ps 508(%rdx){1to4}, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps 512(%rdx){1to4}, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xb6,0x9a,0x00,0x02,0x00,0x00] + vfmaddsub231ps 512(%rdx){1to4}, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps -512(%rdx){1to4}, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xb6,0x5a,0x80] + vfmaddsub231ps -512(%rdx){1to4}, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps -516(%rdx){1to4}, %xmm29, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x15,0x10,0xb6,0x9a,0xfc,0xfd,0xff,0xff] + vfmaddsub231ps -516(%rdx){1to4}, %xmm29, %xmm19 + +// CHECK: vfmaddsub231ps %ymm17, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xa2,0x3d,0x20,0xb6,0xd9] + vfmaddsub231ps %ymm17, %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps %ymm17, %ymm24, %ymm19 {%k1} +// CHECK: encoding: [0x62,0xa2,0x3d,0x21,0xb6,0xd9] + vfmaddsub231ps %ymm17, %ymm24, %ymm19 {%k1} + +// CHECK: vfmaddsub231ps %ymm17, %ymm24, %ymm19 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x3d,0xa1,0xb6,0xd9] + vfmaddsub231ps %ymm17, %ymm24, %ymm19 {%k1} {z} + +// CHECK: vfmaddsub231ps (%rcx), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0xb6,0x19] + vfmaddsub231ps (%rcx), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps 291(%rax,%r14,8), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xa2,0x3d,0x20,0xb6,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231ps 291(%rax,%r14,8), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps (%rcx){1to8}, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0xb6,0x19] + vfmaddsub231ps (%rcx){1to8}, %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps 4064(%rdx), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0xb6,0x5a,0x7f] + vfmaddsub231ps 4064(%rdx), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps 4096(%rdx), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0xb6,0x9a,0x00,0x10,0x00,0x00] + vfmaddsub231ps 4096(%rdx), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps -4096(%rdx), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0xb6,0x5a,0x80] + vfmaddsub231ps -4096(%rdx), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps -4128(%rdx), %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0xb6,0x9a,0xe0,0xef,0xff,0xff] + vfmaddsub231ps -4128(%rdx), %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps 508(%rdx){1to8}, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0xb6,0x5a,0x7f] + vfmaddsub231ps 508(%rdx){1to8}, %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps 512(%rdx){1to8}, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0xb6,0x9a,0x00,0x02,0x00,0x00] + vfmaddsub231ps 512(%rdx){1to8}, %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps -512(%rdx){1to8}, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0xb6,0x5a,0x80] + vfmaddsub231ps -512(%rdx){1to8}, %ymm24, %ymm19 + +// CHECK: vfmaddsub231ps -516(%rdx){1to8}, %ymm24, %ymm19 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0xb6,0x9a,0xfc,0xfd,0xff,0xff] + vfmaddsub231ps -516(%rdx){1to8}, %ymm24, %ymm19 + +// CHECK: vfmaddsub231pd %xmm28, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0x82,0xad,0x00,0xb6,0xfc] + vfmaddsub231pd %xmm28, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd %xmm28, %xmm26, %xmm23 {%k7} +// CHECK: encoding: [0x62,0x82,0xad,0x07,0xb6,0xfc] + vfmaddsub231pd %xmm28, %xmm26, %xmm23 {%k7} + +// CHECK: vfmaddsub231pd %xmm28, %xmm26, %xmm23 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0xad,0x87,0xb6,0xfc] + vfmaddsub231pd %xmm28, %xmm26, %xmm23 {%k7} {z} + +// CHECK: vfmaddsub231pd (%rcx), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0xb6,0x39] + vfmaddsub231pd (%rcx), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd 291(%rax,%r14,8), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xa2,0xad,0x00,0xb6,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231pd 291(%rax,%r14,8), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd (%rcx){1to2}, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0xb6,0x39] + vfmaddsub231pd (%rcx){1to2}, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd 2032(%rdx), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0xb6,0x7a,0x7f] + vfmaddsub231pd 2032(%rdx), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd 2048(%rdx), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0xb6,0xba,0x00,0x08,0x00,0x00] + vfmaddsub231pd 2048(%rdx), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd -2048(%rdx), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0xb6,0x7a,0x80] + vfmaddsub231pd -2048(%rdx), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd -2064(%rdx), %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0xb6,0xba,0xf0,0xf7,0xff,0xff] + vfmaddsub231pd -2064(%rdx), %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd 1016(%rdx){1to2}, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0xb6,0x7a,0x7f] + vfmaddsub231pd 1016(%rdx){1to2}, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd 1024(%rdx){1to2}, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0xb6,0xba,0x00,0x04,0x00,0x00] + vfmaddsub231pd 1024(%rdx){1to2}, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd -1024(%rdx){1to2}, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0xb6,0x7a,0x80] + vfmaddsub231pd -1024(%rdx){1to2}, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd -1032(%rdx){1to2}, %xmm26, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0xb6,0xba,0xf8,0xfb,0xff,0xff] + vfmaddsub231pd -1032(%rdx){1to2}, %xmm26, %xmm23 + +// CHECK: vfmaddsub231pd %ymm27, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x02,0xb5,0x20,0xb6,0xf3] + vfmaddsub231pd %ymm27, %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd %ymm27, %ymm25, %ymm30 {%k5} +// CHECK: encoding: [0x62,0x02,0xb5,0x25,0xb6,0xf3] + vfmaddsub231pd %ymm27, %ymm25, %ymm30 {%k5} + +// CHECK: vfmaddsub231pd %ymm27, %ymm25, %ymm30 {%k5} {z} +// CHECK: encoding: [0x62,0x02,0xb5,0xa5,0xb6,0xf3] + vfmaddsub231pd %ymm27, %ymm25, %ymm30 {%k5} {z} + +// CHECK: vfmaddsub231pd (%rcx), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xb6,0x31] + vfmaddsub231pd (%rcx), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd 291(%rax,%r14,8), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x22,0xb5,0x20,0xb6,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmaddsub231pd 291(%rax,%r14,8), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd (%rcx){1to4}, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xb6,0x31] + vfmaddsub231pd (%rcx){1to4}, %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd 4064(%rdx), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xb6,0x72,0x7f] + vfmaddsub231pd 4064(%rdx), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd 4096(%rdx), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xb6,0xb2,0x00,0x10,0x00,0x00] + vfmaddsub231pd 4096(%rdx), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd -4096(%rdx), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xb6,0x72,0x80] + vfmaddsub231pd -4096(%rdx), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd -4128(%rdx), %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x20,0xb6,0xb2,0xe0,0xef,0xff,0xff] + vfmaddsub231pd -4128(%rdx), %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd 1016(%rdx){1to4}, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xb6,0x72,0x7f] + vfmaddsub231pd 1016(%rdx){1to4}, %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd 1024(%rdx){1to4}, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xb6,0xb2,0x00,0x04,0x00,0x00] + vfmaddsub231pd 1024(%rdx){1to4}, %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd -1024(%rdx){1to4}, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xb6,0x72,0x80] + vfmaddsub231pd -1024(%rdx){1to4}, %ymm25, %ymm30 + +// CHECK: vfmaddsub231pd -1032(%rdx){1to4}, %ymm25, %ymm30 +// CHECK: encoding: [0x62,0x62,0xb5,0x30,0xb6,0xb2,0xf8,0xfb,0xff,0xff] + vfmaddsub231pd -1032(%rdx){1to4}, %ymm25, %ymm30 + +// CHECK: vfmsubadd132ps %xmm20, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x22,0x45,0x00,0x97,0xc4] + vfmsubadd132ps %xmm20, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps %xmm20, %xmm23, %xmm24 {%k5} +// CHECK: encoding: [0x62,0x22,0x45,0x05,0x97,0xc4] + vfmsubadd132ps %xmm20, %xmm23, %xmm24 {%k5} + +// CHECK: vfmsubadd132ps %xmm20, %xmm23, %xmm24 {%k5} {z} +// CHECK: encoding: [0x62,0x22,0x45,0x85,0x97,0xc4] + vfmsubadd132ps %xmm20, %xmm23, %xmm24 {%k5} {z} + +// CHECK: vfmsubadd132ps (%rcx), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x00,0x97,0x01] + vfmsubadd132ps (%rcx), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps 291(%rax,%r14,8), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x22,0x45,0x00,0x97,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132ps 291(%rax,%r14,8), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps (%rcx){1to4}, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x10,0x97,0x01] + vfmsubadd132ps (%rcx){1to4}, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps 2032(%rdx), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x00,0x97,0x42,0x7f] + vfmsubadd132ps 2032(%rdx), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps 2048(%rdx), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x00,0x97,0x82,0x00,0x08,0x00,0x00] + vfmsubadd132ps 2048(%rdx), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps -2048(%rdx), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x00,0x97,0x42,0x80] + vfmsubadd132ps -2048(%rdx), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps -2064(%rdx), %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x00,0x97,0x82,0xf0,0xf7,0xff,0xff] + vfmsubadd132ps -2064(%rdx), %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps 508(%rdx){1to4}, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x10,0x97,0x42,0x7f] + vfmsubadd132ps 508(%rdx){1to4}, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps 512(%rdx){1to4}, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x10,0x97,0x82,0x00,0x02,0x00,0x00] + vfmsubadd132ps 512(%rdx){1to4}, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps -512(%rdx){1to4}, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x10,0x97,0x42,0x80] + vfmsubadd132ps -512(%rdx){1to4}, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps -516(%rdx){1to4}, %xmm23, %xmm24 +// CHECK: encoding: [0x62,0x62,0x45,0x10,0x97,0x82,0xfc,0xfd,0xff,0xff] + vfmsubadd132ps -516(%rdx){1to4}, %xmm23, %xmm24 + +// CHECK: vfmsubadd132ps %ymm23, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xa2,0x1d,0x20,0x97,0xff] + vfmsubadd132ps %ymm23, %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps %ymm23, %ymm28, %ymm23 {%k1} +// CHECK: encoding: [0x62,0xa2,0x1d,0x21,0x97,0xff] + vfmsubadd132ps %ymm23, %ymm28, %ymm23 {%k1} + +// CHECK: vfmsubadd132ps %ymm23, %ymm28, %ymm23 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x1d,0xa1,0x97,0xff] + vfmsubadd132ps %ymm23, %ymm28, %ymm23 {%k1} {z} + +// CHECK: vfmsubadd132ps (%rcx), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x20,0x97,0x39] + vfmsubadd132ps (%rcx), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps 291(%rax,%r14,8), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xa2,0x1d,0x20,0x97,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132ps 291(%rax,%r14,8), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps (%rcx){1to8}, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x30,0x97,0x39] + vfmsubadd132ps (%rcx){1to8}, %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps 4064(%rdx), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x20,0x97,0x7a,0x7f] + vfmsubadd132ps 4064(%rdx), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps 4096(%rdx), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x20,0x97,0xba,0x00,0x10,0x00,0x00] + vfmsubadd132ps 4096(%rdx), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps -4096(%rdx), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x20,0x97,0x7a,0x80] + vfmsubadd132ps -4096(%rdx), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps -4128(%rdx), %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x20,0x97,0xba,0xe0,0xef,0xff,0xff] + vfmsubadd132ps -4128(%rdx), %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps 508(%rdx){1to8}, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x30,0x97,0x7a,0x7f] + vfmsubadd132ps 508(%rdx){1to8}, %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps 512(%rdx){1to8}, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x30,0x97,0xba,0x00,0x02,0x00,0x00] + vfmsubadd132ps 512(%rdx){1to8}, %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps -512(%rdx){1to8}, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x30,0x97,0x7a,0x80] + vfmsubadd132ps -512(%rdx){1to8}, %ymm28, %ymm23 + +// CHECK: vfmsubadd132ps -516(%rdx){1to8}, %ymm28, %ymm23 +// CHECK: encoding: [0x62,0xe2,0x1d,0x30,0x97,0xba,0xfc,0xfd,0xff,0xff] + vfmsubadd132ps -516(%rdx){1to8}, %ymm28, %ymm23 + +// CHECK: vfmsubadd132pd %xmm24, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0x82,0xad,0x00,0x97,0xf0] + vfmsubadd132pd %xmm24, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd %xmm24, %xmm26, %xmm22 {%k3} +// CHECK: encoding: [0x62,0x82,0xad,0x03,0x97,0xf0] + vfmsubadd132pd %xmm24, %xmm26, %xmm22 {%k3} + +// CHECK: vfmsubadd132pd %xmm24, %xmm26, %xmm22 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0xad,0x83,0x97,0xf0] + vfmsubadd132pd %xmm24, %xmm26, %xmm22 {%k3} {z} + +// CHECK: vfmsubadd132pd (%rcx), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0x97,0x31] + vfmsubadd132pd (%rcx), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd 291(%rax,%r14,8), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xa2,0xad,0x00,0x97,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132pd 291(%rax,%r14,8), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd (%rcx){1to2}, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0x97,0x31] + vfmsubadd132pd (%rcx){1to2}, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd 2032(%rdx), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0x97,0x72,0x7f] + vfmsubadd132pd 2032(%rdx), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd 2048(%rdx), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0x97,0xb2,0x00,0x08,0x00,0x00] + vfmsubadd132pd 2048(%rdx), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd -2048(%rdx), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0x97,0x72,0x80] + vfmsubadd132pd -2048(%rdx), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd -2064(%rdx), %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x00,0x97,0xb2,0xf0,0xf7,0xff,0xff] + vfmsubadd132pd -2064(%rdx), %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd 1016(%rdx){1to2}, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0x97,0x72,0x7f] + vfmsubadd132pd 1016(%rdx){1to2}, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd 1024(%rdx){1to2}, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0x97,0xb2,0x00,0x04,0x00,0x00] + vfmsubadd132pd 1024(%rdx){1to2}, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd -1024(%rdx){1to2}, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0x97,0x72,0x80] + vfmsubadd132pd -1024(%rdx){1to2}, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd -1032(%rdx){1to2}, %xmm26, %xmm22 +// CHECK: encoding: [0x62,0xe2,0xad,0x10,0x97,0xb2,0xf8,0xfb,0xff,0xff] + vfmsubadd132pd -1032(%rdx){1to2}, %xmm26, %xmm22 + +// CHECK: vfmsubadd132pd %ymm21, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x22,0xf5,0x20,0x97,0xc5] + vfmsubadd132pd %ymm21, %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd %ymm21, %ymm17, %ymm24 {%k7} +// CHECK: encoding: [0x62,0x22,0xf5,0x27,0x97,0xc5] + vfmsubadd132pd %ymm21, %ymm17, %ymm24 {%k7} + +// CHECK: vfmsubadd132pd %ymm21, %ymm17, %ymm24 {%k7} {z} +// CHECK: encoding: [0x62,0x22,0xf5,0xa7,0x97,0xc5] + vfmsubadd132pd %ymm21, %ymm17, %ymm24 {%k7} {z} + +// CHECK: vfmsubadd132pd (%rcx), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x20,0x97,0x01] + vfmsubadd132pd (%rcx), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd 291(%rax,%r14,8), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x22,0xf5,0x20,0x97,0x84,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd132pd 291(%rax,%r14,8), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd (%rcx){1to4}, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x97,0x01] + vfmsubadd132pd (%rcx){1to4}, %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd 4064(%rdx), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x20,0x97,0x42,0x7f] + vfmsubadd132pd 4064(%rdx), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd 4096(%rdx), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x20,0x97,0x82,0x00,0x10,0x00,0x00] + vfmsubadd132pd 4096(%rdx), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd -4096(%rdx), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x20,0x97,0x42,0x80] + vfmsubadd132pd -4096(%rdx), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd -4128(%rdx), %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x20,0x97,0x82,0xe0,0xef,0xff,0xff] + vfmsubadd132pd -4128(%rdx), %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd 1016(%rdx){1to4}, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x97,0x42,0x7f] + vfmsubadd132pd 1016(%rdx){1to4}, %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd 1024(%rdx){1to4}, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x97,0x82,0x00,0x04,0x00,0x00] + vfmsubadd132pd 1024(%rdx){1to4}, %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd -1024(%rdx){1to4}, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x97,0x42,0x80] + vfmsubadd132pd -1024(%rdx){1to4}, %ymm17, %ymm24 + +// CHECK: vfmsubadd132pd -1032(%rdx){1to4}, %ymm17, %ymm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x30,0x97,0x82,0xf8,0xfb,0xff,0xff] + vfmsubadd132pd -1032(%rdx){1to4}, %ymm17, %ymm24 + +// CHECK: vfmsubadd213ps %xmm17, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x5d,0x00,0xa7,0xd9] + vfmsubadd213ps %xmm17, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps %xmm17, %xmm20, %xmm19 {%k5} +// CHECK: encoding: [0x62,0xa2,0x5d,0x05,0xa7,0xd9] + vfmsubadd213ps %xmm17, %xmm20, %xmm19 {%k5} + +// CHECK: vfmsubadd213ps %xmm17, %xmm20, %xmm19 {%k5} {z} +// CHECK: encoding: [0x62,0xa2,0x5d,0x85,0xa7,0xd9] + vfmsubadd213ps %xmm17, %xmm20, %xmm19 {%k5} {z} + +// CHECK: vfmsubadd213ps (%rcx), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x00,0xa7,0x19] + vfmsubadd213ps (%rcx), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps 291(%rax,%r14,8), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x5d,0x00,0xa7,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213ps 291(%rax,%r14,8), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps (%rcx){1to4}, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x10,0xa7,0x19] + vfmsubadd213ps (%rcx){1to4}, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps 2032(%rdx), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x00,0xa7,0x5a,0x7f] + vfmsubadd213ps 2032(%rdx), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps 2048(%rdx), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x00,0xa7,0x9a,0x00,0x08,0x00,0x00] + vfmsubadd213ps 2048(%rdx), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps -2048(%rdx), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x00,0xa7,0x5a,0x80] + vfmsubadd213ps -2048(%rdx), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps -2064(%rdx), %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x00,0xa7,0x9a,0xf0,0xf7,0xff,0xff] + vfmsubadd213ps -2064(%rdx), %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps 508(%rdx){1to4}, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x10,0xa7,0x5a,0x7f] + vfmsubadd213ps 508(%rdx){1to4}, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps 512(%rdx){1to4}, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x10,0xa7,0x9a,0x00,0x02,0x00,0x00] + vfmsubadd213ps 512(%rdx){1to4}, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps -512(%rdx){1to4}, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x10,0xa7,0x5a,0x80] + vfmsubadd213ps -512(%rdx){1to4}, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps -516(%rdx){1to4}, %xmm20, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x5d,0x10,0xa7,0x9a,0xfc,0xfd,0xff,0xff] + vfmsubadd213ps -516(%rdx){1to4}, %xmm20, %xmm19 + +// CHECK: vfmsubadd213ps %ymm23, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x22,0x75,0x20,0xa7,0xd7] + vfmsubadd213ps %ymm23, %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps %ymm23, %ymm17, %ymm26 {%k7} +// CHECK: encoding: [0x62,0x22,0x75,0x27,0xa7,0xd7] + vfmsubadd213ps %ymm23, %ymm17, %ymm26 {%k7} + +// CHECK: vfmsubadd213ps %ymm23, %ymm17, %ymm26 {%k7} {z} +// CHECK: encoding: [0x62,0x22,0x75,0xa7,0xa7,0xd7] + vfmsubadd213ps %ymm23, %ymm17, %ymm26 {%k7} {z} + +// CHECK: vfmsubadd213ps (%rcx), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x20,0xa7,0x11] + vfmsubadd213ps (%rcx), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps 291(%rax,%r14,8), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x22,0x75,0x20,0xa7,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213ps 291(%rax,%r14,8), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps (%rcx){1to8}, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x30,0xa7,0x11] + vfmsubadd213ps (%rcx){1to8}, %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps 4064(%rdx), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x20,0xa7,0x52,0x7f] + vfmsubadd213ps 4064(%rdx), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps 4096(%rdx), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x20,0xa7,0x92,0x00,0x10,0x00,0x00] + vfmsubadd213ps 4096(%rdx), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps -4096(%rdx), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x20,0xa7,0x52,0x80] + vfmsubadd213ps -4096(%rdx), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps -4128(%rdx), %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x20,0xa7,0x92,0xe0,0xef,0xff,0xff] + vfmsubadd213ps -4128(%rdx), %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps 508(%rdx){1to8}, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x30,0xa7,0x52,0x7f] + vfmsubadd213ps 508(%rdx){1to8}, %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps 512(%rdx){1to8}, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x30,0xa7,0x92,0x00,0x02,0x00,0x00] + vfmsubadd213ps 512(%rdx){1to8}, %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps -512(%rdx){1to8}, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x30,0xa7,0x52,0x80] + vfmsubadd213ps -512(%rdx){1to8}, %ymm17, %ymm26 + +// CHECK: vfmsubadd213ps -516(%rdx){1to8}, %ymm17, %ymm26 +// CHECK: encoding: [0x62,0x62,0x75,0x30,0xa7,0x92,0xfc,0xfd,0xff,0xff] + vfmsubadd213ps -516(%rdx){1to8}, %ymm17, %ymm26 + +// CHECK: vfmsubadd213pd %xmm28, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0x82,0xd5,0x00,0xa7,0xd4] + vfmsubadd213pd %xmm28, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd %xmm28, %xmm21, %xmm18 {%k4} +// CHECK: encoding: [0x62,0x82,0xd5,0x04,0xa7,0xd4] + vfmsubadd213pd %xmm28, %xmm21, %xmm18 {%k4} + +// CHECK: vfmsubadd213pd %xmm28, %xmm21, %xmm18 {%k4} {z} +// CHECK: encoding: [0x62,0x82,0xd5,0x84,0xa7,0xd4] + vfmsubadd213pd %xmm28, %xmm21, %xmm18 {%k4} {z} + +// CHECK: vfmsubadd213pd (%rcx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa7,0x11] + vfmsubadd213pd (%rcx), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd 291(%rax,%r14,8), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xa2,0xd5,0x00,0xa7,0x94,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213pd 291(%rax,%r14,8), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd (%rcx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa7,0x11] + vfmsubadd213pd (%rcx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd 2032(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa7,0x52,0x7f] + vfmsubadd213pd 2032(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd 2048(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa7,0x92,0x00,0x08,0x00,0x00] + vfmsubadd213pd 2048(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd -2048(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa7,0x52,0x80] + vfmsubadd213pd -2048(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd -2064(%rdx), %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x00,0xa7,0x92,0xf0,0xf7,0xff,0xff] + vfmsubadd213pd -2064(%rdx), %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd 1016(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa7,0x52,0x7f] + vfmsubadd213pd 1016(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd 1024(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa7,0x92,0x00,0x04,0x00,0x00] + vfmsubadd213pd 1024(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd -1024(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa7,0x52,0x80] + vfmsubadd213pd -1024(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd -1032(%rdx){1to2}, %xmm21, %xmm18 +// CHECK: encoding: [0x62,0xe2,0xd5,0x10,0xa7,0x92,0xf8,0xfb,0xff,0xff] + vfmsubadd213pd -1032(%rdx){1to2}, %xmm21, %xmm18 + +// CHECK: vfmsubadd213pd %ymm25, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x02,0xdd,0x20,0xa7,0xd9] + vfmsubadd213pd %ymm25, %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd %ymm25, %ymm20, %ymm27 {%k7} +// CHECK: encoding: [0x62,0x02,0xdd,0x27,0xa7,0xd9] + vfmsubadd213pd %ymm25, %ymm20, %ymm27 {%k7} + +// CHECK: vfmsubadd213pd %ymm25, %ymm20, %ymm27 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0xdd,0xa7,0xa7,0xd9] + vfmsubadd213pd %ymm25, %ymm20, %ymm27 {%k7} {z} + +// CHECK: vfmsubadd213pd (%rcx), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xa7,0x19] + vfmsubadd213pd (%rcx), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd 291(%rax,%r14,8), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x22,0xdd,0x20,0xa7,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd213pd 291(%rax,%r14,8), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd (%rcx){1to4}, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xa7,0x19] + vfmsubadd213pd (%rcx){1to4}, %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd 4064(%rdx), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xa7,0x5a,0x7f] + vfmsubadd213pd 4064(%rdx), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd 4096(%rdx), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xa7,0x9a,0x00,0x10,0x00,0x00] + vfmsubadd213pd 4096(%rdx), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd -4096(%rdx), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xa7,0x5a,0x80] + vfmsubadd213pd -4096(%rdx), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd -4128(%rdx), %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0xa7,0x9a,0xe0,0xef,0xff,0xff] + vfmsubadd213pd -4128(%rdx), %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd 1016(%rdx){1to4}, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xa7,0x5a,0x7f] + vfmsubadd213pd 1016(%rdx){1to4}, %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd 1024(%rdx){1to4}, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xa7,0x9a,0x00,0x04,0x00,0x00] + vfmsubadd213pd 1024(%rdx){1to4}, %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd -1024(%rdx){1to4}, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xa7,0x5a,0x80] + vfmsubadd213pd -1024(%rdx){1to4}, %ymm20, %ymm27 + +// CHECK: vfmsubadd213pd -1032(%rdx){1to4}, %ymm20, %ymm27 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0xa7,0x9a,0xf8,0xfb,0xff,0xff] + vfmsubadd213pd -1032(%rdx){1to4}, %ymm20, %ymm27 + +// CHECK: vfmsubadd231ps %xmm23, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xa2,0x35,0x00,0xb7,0xef] + vfmsubadd231ps %xmm23, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps %xmm23, %xmm25, %xmm21 {%k4} +// CHECK: encoding: [0x62,0xa2,0x35,0x04,0xb7,0xef] + vfmsubadd231ps %xmm23, %xmm25, %xmm21 {%k4} + +// CHECK: vfmsubadd231ps %xmm23, %xmm25, %xmm21 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0x35,0x84,0xb7,0xef] + vfmsubadd231ps %xmm23, %xmm25, %xmm21 {%k4} {z} + +// CHECK: vfmsubadd231ps (%rcx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0xb7,0x29] + vfmsubadd231ps (%rcx), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps 291(%rax,%r14,8), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xa2,0x35,0x00,0xb7,0xac,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231ps 291(%rax,%r14,8), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps (%rcx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0xb7,0x29] + vfmsubadd231ps (%rcx){1to4}, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps 2032(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0xb7,0x6a,0x7f] + vfmsubadd231ps 2032(%rdx), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps 2048(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0xb7,0xaa,0x00,0x08,0x00,0x00] + vfmsubadd231ps 2048(%rdx), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps -2048(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0xb7,0x6a,0x80] + vfmsubadd231ps -2048(%rdx), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps -2064(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0xb7,0xaa,0xf0,0xf7,0xff,0xff] + vfmsubadd231ps -2064(%rdx), %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps 508(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0xb7,0x6a,0x7f] + vfmsubadd231ps 508(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps 512(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0xb7,0xaa,0x00,0x02,0x00,0x00] + vfmsubadd231ps 512(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps -512(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0xb7,0x6a,0x80] + vfmsubadd231ps -512(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps -516(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0xb7,0xaa,0xfc,0xfd,0xff,0xff] + vfmsubadd231ps -516(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfmsubadd231ps %ymm20, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x22,0x45,0x20,0xb7,0xdc] + vfmsubadd231ps %ymm20, %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps %ymm20, %ymm23, %ymm27 {%k3} +// CHECK: encoding: [0x62,0x22,0x45,0x23,0xb7,0xdc] + vfmsubadd231ps %ymm20, %ymm23, %ymm27 {%k3} + +// CHECK: vfmsubadd231ps %ymm20, %ymm23, %ymm27 {%k3} {z} +// CHECK: encoding: [0x62,0x22,0x45,0xa3,0xb7,0xdc] + vfmsubadd231ps %ymm20, %ymm23, %ymm27 {%k3} {z} + +// CHECK: vfmsubadd231ps (%rcx), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x20,0xb7,0x19] + vfmsubadd231ps (%rcx), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps 291(%rax,%r14,8), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x22,0x45,0x20,0xb7,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231ps 291(%rax,%r14,8), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps (%rcx){1to8}, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x30,0xb7,0x19] + vfmsubadd231ps (%rcx){1to8}, %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps 4064(%rdx), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x20,0xb7,0x5a,0x7f] + vfmsubadd231ps 4064(%rdx), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps 4096(%rdx), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x20,0xb7,0x9a,0x00,0x10,0x00,0x00] + vfmsubadd231ps 4096(%rdx), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps -4096(%rdx), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x20,0xb7,0x5a,0x80] + vfmsubadd231ps -4096(%rdx), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps -4128(%rdx), %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x20,0xb7,0x9a,0xe0,0xef,0xff,0xff] + vfmsubadd231ps -4128(%rdx), %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps 508(%rdx){1to8}, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x30,0xb7,0x5a,0x7f] + vfmsubadd231ps 508(%rdx){1to8}, %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps 512(%rdx){1to8}, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x30,0xb7,0x9a,0x00,0x02,0x00,0x00] + vfmsubadd231ps 512(%rdx){1to8}, %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps -512(%rdx){1to8}, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x30,0xb7,0x5a,0x80] + vfmsubadd231ps -512(%rdx){1to8}, %ymm23, %ymm27 + +// CHECK: vfmsubadd231ps -516(%rdx){1to8}, %ymm23, %ymm27 +// CHECK: encoding: [0x62,0x62,0x45,0x30,0xb7,0x9a,0xfc,0xfd,0xff,0xff] + vfmsubadd231ps -516(%rdx){1to8}, %ymm23, %ymm27 + +// CHECK: vfmsubadd231pd %xmm28, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0x82,0xbd,0x00,0xb7,0xe4] + vfmsubadd231pd %xmm28, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd %xmm28, %xmm24, %xmm20 {%k3} +// CHECK: encoding: [0x62,0x82,0xbd,0x03,0xb7,0xe4] + vfmsubadd231pd %xmm28, %xmm24, %xmm20 {%k3} + +// CHECK: vfmsubadd231pd %xmm28, %xmm24, %xmm20 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0xbd,0x83,0xb7,0xe4] + vfmsubadd231pd %xmm28, %xmm24, %xmm20 {%k3} {z} + +// CHECK: vfmsubadd231pd (%rcx), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x00,0xb7,0x21] + vfmsubadd231pd (%rcx), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd 291(%rax,%r14,8), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xa2,0xbd,0x00,0xb7,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231pd 291(%rax,%r14,8), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd (%rcx){1to2}, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x10,0xb7,0x21] + vfmsubadd231pd (%rcx){1to2}, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd 2032(%rdx), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x00,0xb7,0x62,0x7f] + vfmsubadd231pd 2032(%rdx), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd 2048(%rdx), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x00,0xb7,0xa2,0x00,0x08,0x00,0x00] + vfmsubadd231pd 2048(%rdx), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd -2048(%rdx), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x00,0xb7,0x62,0x80] + vfmsubadd231pd -2048(%rdx), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd -2064(%rdx), %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x00,0xb7,0xa2,0xf0,0xf7,0xff,0xff] + vfmsubadd231pd -2064(%rdx), %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd 1016(%rdx){1to2}, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x10,0xb7,0x62,0x7f] + vfmsubadd231pd 1016(%rdx){1to2}, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd 1024(%rdx){1to2}, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x10,0xb7,0xa2,0x00,0x04,0x00,0x00] + vfmsubadd231pd 1024(%rdx){1to2}, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd -1024(%rdx){1to2}, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x10,0xb7,0x62,0x80] + vfmsubadd231pd -1024(%rdx){1to2}, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd -1032(%rdx){1to2}, %xmm24, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xbd,0x10,0xb7,0xa2,0xf8,0xfb,0xff,0xff] + vfmsubadd231pd -1032(%rdx){1to2}, %xmm24, %xmm20 + +// CHECK: vfmsubadd231pd %ymm21, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x22,0x95,0x20,0xb7,0xf5] + vfmsubadd231pd %ymm21, %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd %ymm21, %ymm29, %ymm30 {%k7} +// CHECK: encoding: [0x62,0x22,0x95,0x27,0xb7,0xf5] + vfmsubadd231pd %ymm21, %ymm29, %ymm30 {%k7} + +// CHECK: vfmsubadd231pd %ymm21, %ymm29, %ymm30 {%k7} {z} +// CHECK: encoding: [0x62,0x22,0x95,0xa7,0xb7,0xf5] + vfmsubadd231pd %ymm21, %ymm29, %ymm30 {%k7} {z} + +// CHECK: vfmsubadd231pd (%rcx), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x20,0xb7,0x31] + vfmsubadd231pd (%rcx), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd 291(%rax,%r14,8), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x22,0x95,0x20,0xb7,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfmsubadd231pd 291(%rax,%r14,8), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd (%rcx){1to4}, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x30,0xb7,0x31] + vfmsubadd231pd (%rcx){1to4}, %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd 4064(%rdx), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x20,0xb7,0x72,0x7f] + vfmsubadd231pd 4064(%rdx), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd 4096(%rdx), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x20,0xb7,0xb2,0x00,0x10,0x00,0x00] + vfmsubadd231pd 4096(%rdx), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd -4096(%rdx), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x20,0xb7,0x72,0x80] + vfmsubadd231pd -4096(%rdx), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd -4128(%rdx), %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x20,0xb7,0xb2,0xe0,0xef,0xff,0xff] + vfmsubadd231pd -4128(%rdx), %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd 1016(%rdx){1to4}, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x30,0xb7,0x72,0x7f] + vfmsubadd231pd 1016(%rdx){1to4}, %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd 1024(%rdx){1to4}, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x30,0xb7,0xb2,0x00,0x04,0x00,0x00] + vfmsubadd231pd 1024(%rdx){1to4}, %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd -1024(%rdx){1to4}, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x30,0xb7,0x72,0x80] + vfmsubadd231pd -1024(%rdx){1to4}, %ymm29, %ymm30 + +// CHECK: vfmsubadd231pd -1032(%rdx){1to4}, %ymm29, %ymm30 +// CHECK: encoding: [0x62,0x62,0x95,0x30,0xb7,0xb2,0xf8,0xfb,0xff,0xff] + vfmsubadd231pd -1032(%rdx){1to4}, %ymm29, %ymm30 + +// CHECK: vfnmadd132ps %xmm18, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xa2,0x2d,0x00,0x9c,0xe2] + vfnmadd132ps %xmm18, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps %xmm18, %xmm26, %xmm20 {%k7} +// CHECK: encoding: [0x62,0xa2,0x2d,0x07,0x9c,0xe2] + vfnmadd132ps %xmm18, %xmm26, %xmm20 {%k7} + +// CHECK: vfnmadd132ps %xmm18, %xmm26, %xmm20 {%k7} {z} +// CHECK: encoding: [0x62,0xa2,0x2d,0x87,0x9c,0xe2] + vfnmadd132ps %xmm18, %xmm26, %xmm20 {%k7} {z} + +// CHECK: vfnmadd132ps (%rcx), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0x9c,0x21] + vfnmadd132ps (%rcx), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps 291(%rax,%r14,8), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xa2,0x2d,0x00,0x9c,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132ps 291(%rax,%r14,8), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps (%rcx){1to4}, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0x9c,0x21] + vfnmadd132ps (%rcx){1to4}, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps 2032(%rdx), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0x9c,0x62,0x7f] + vfnmadd132ps 2032(%rdx), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps 2048(%rdx), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0x9c,0xa2,0x00,0x08,0x00,0x00] + vfnmadd132ps 2048(%rdx), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps -2048(%rdx), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0x9c,0x62,0x80] + vfnmadd132ps -2048(%rdx), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps -2064(%rdx), %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0x9c,0xa2,0xf0,0xf7,0xff,0xff] + vfnmadd132ps -2064(%rdx), %xmm26, %xmm20 + +// CHECK: vfnmadd132ps 508(%rdx){1to4}, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0x9c,0x62,0x7f] + vfnmadd132ps 508(%rdx){1to4}, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps 512(%rdx){1to4}, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0x9c,0xa2,0x00,0x02,0x00,0x00] + vfnmadd132ps 512(%rdx){1to4}, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps -512(%rdx){1to4}, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0x9c,0x62,0x80] + vfnmadd132ps -512(%rdx){1to4}, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps -516(%rdx){1to4}, %xmm26, %xmm20 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0x9c,0xa2,0xfc,0xfd,0xff,0xff] + vfnmadd132ps -516(%rdx){1to4}, %xmm26, %xmm20 + +// CHECK: vfnmadd132ps %ymm18, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x55,0x20,0x9c,0xe2] + vfnmadd132ps %ymm18, %ymm21, %ymm20 + +// CHECK: vfnmadd132ps %ymm18, %ymm21, %ymm20 {%k7} +// CHECK: encoding: [0x62,0xa2,0x55,0x27,0x9c,0xe2] + vfnmadd132ps %ymm18, %ymm21, %ymm20 {%k7} + +// CHECK: vfnmadd132ps %ymm18, %ymm21, %ymm20 {%k7} {z} +// CHECK: encoding: [0x62,0xa2,0x55,0xa7,0x9c,0xe2] + vfnmadd132ps %ymm18, %ymm21, %ymm20 {%k7} {z} + +// CHECK: vfnmadd132ps (%rcx), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x20,0x9c,0x21] + vfnmadd132ps (%rcx), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps 291(%rax,%r14,8), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x55,0x20,0x9c,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132ps 291(%rax,%r14,8), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps (%rcx){1to8}, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x30,0x9c,0x21] + vfnmadd132ps (%rcx){1to8}, %ymm21, %ymm20 + +// CHECK: vfnmadd132ps 4064(%rdx), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x20,0x9c,0x62,0x7f] + vfnmadd132ps 4064(%rdx), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps 4096(%rdx), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x20,0x9c,0xa2,0x00,0x10,0x00,0x00] + vfnmadd132ps 4096(%rdx), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps -4096(%rdx), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x20,0x9c,0x62,0x80] + vfnmadd132ps -4096(%rdx), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps -4128(%rdx), %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x20,0x9c,0xa2,0xe0,0xef,0xff,0xff] + vfnmadd132ps -4128(%rdx), %ymm21, %ymm20 + +// CHECK: vfnmadd132ps 508(%rdx){1to8}, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x30,0x9c,0x62,0x7f] + vfnmadd132ps 508(%rdx){1to8}, %ymm21, %ymm20 + +// CHECK: vfnmadd132ps 512(%rdx){1to8}, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x30,0x9c,0xa2,0x00,0x02,0x00,0x00] + vfnmadd132ps 512(%rdx){1to8}, %ymm21, %ymm20 + +// CHECK: vfnmadd132ps -512(%rdx){1to8}, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x30,0x9c,0x62,0x80] + vfnmadd132ps -512(%rdx){1to8}, %ymm21, %ymm20 + +// CHECK: vfnmadd132ps -516(%rdx){1to8}, %ymm21, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x55,0x30,0x9c,0xa2,0xfc,0xfd,0xff,0xff] + vfnmadd132ps -516(%rdx){1to8}, %ymm21, %ymm20 + +// CHECK: vfnmadd132pd %xmm18, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x22,0xd5,0x00,0x9c,0xd2] + vfnmadd132pd %xmm18, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd %xmm18, %xmm21, %xmm26 {%k6} +// CHECK: encoding: [0x62,0x22,0xd5,0x06,0x9c,0xd2] + vfnmadd132pd %xmm18, %xmm21, %xmm26 {%k6} + +// CHECK: vfnmadd132pd %xmm18, %xmm21, %xmm26 {%k6} {z} +// CHECK: encoding: [0x62,0x22,0xd5,0x86,0x9c,0xd2] + vfnmadd132pd %xmm18, %xmm21, %xmm26 {%k6} {z} + +// CHECK: vfnmadd132pd (%rcx), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x9c,0x11] + vfnmadd132pd (%rcx), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd 291(%rax,%r14,8), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x22,0xd5,0x00,0x9c,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132pd 291(%rax,%r14,8), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd (%rcx){1to2}, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x9c,0x11] + vfnmadd132pd (%rcx){1to2}, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd 2032(%rdx), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x9c,0x52,0x7f] + vfnmadd132pd 2032(%rdx), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd 2048(%rdx), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x9c,0x92,0x00,0x08,0x00,0x00] + vfnmadd132pd 2048(%rdx), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd -2048(%rdx), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x9c,0x52,0x80] + vfnmadd132pd -2048(%rdx), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd -2064(%rdx), %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x00,0x9c,0x92,0xf0,0xf7,0xff,0xff] + vfnmadd132pd -2064(%rdx), %xmm21, %xmm26 + +// CHECK: vfnmadd132pd 1016(%rdx){1to2}, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x9c,0x52,0x7f] + vfnmadd132pd 1016(%rdx){1to2}, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd 1024(%rdx){1to2}, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x9c,0x92,0x00,0x04,0x00,0x00] + vfnmadd132pd 1024(%rdx){1to2}, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd -1024(%rdx){1to2}, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x9c,0x52,0x80] + vfnmadd132pd -1024(%rdx){1to2}, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd -1032(%rdx){1to2}, %xmm21, %xmm26 +// CHECK: encoding: [0x62,0x62,0xd5,0x10,0x9c,0x92,0xf8,0xfb,0xff,0xff] + vfnmadd132pd -1032(%rdx){1to2}, %xmm21, %xmm26 + +// CHECK: vfnmadd132pd %ymm18, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x22,0xcd,0x20,0x9c,0xca] + vfnmadd132pd %ymm18, %ymm22, %ymm25 + +// CHECK: vfnmadd132pd %ymm18, %ymm22, %ymm25 {%k4} +// CHECK: encoding: [0x62,0x22,0xcd,0x24,0x9c,0xca] + vfnmadd132pd %ymm18, %ymm22, %ymm25 {%k4} + +// CHECK: vfnmadd132pd %ymm18, %ymm22, %ymm25 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0xcd,0xa4,0x9c,0xca] + vfnmadd132pd %ymm18, %ymm22, %ymm25 {%k4} {z} + +// CHECK: vfnmadd132pd (%rcx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x20,0x9c,0x09] + vfnmadd132pd (%rcx), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd 291(%rax,%r14,8), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x22,0xcd,0x20,0x9c,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfnmadd132pd 291(%rax,%r14,8), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd (%rcx){1to4}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x30,0x9c,0x09] + vfnmadd132pd (%rcx){1to4}, %ymm22, %ymm25 + +// CHECK: vfnmadd132pd 4064(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x20,0x9c,0x4a,0x7f] + vfnmadd132pd 4064(%rdx), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd 4096(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x20,0x9c,0x8a,0x00,0x10,0x00,0x00] + vfnmadd132pd 4096(%rdx), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd -4096(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x20,0x9c,0x4a,0x80] + vfnmadd132pd -4096(%rdx), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd -4128(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x20,0x9c,0x8a,0xe0,0xef,0xff,0xff] + vfnmadd132pd -4128(%rdx), %ymm22, %ymm25 + +// CHECK: vfnmadd132pd 1016(%rdx){1to4}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x30,0x9c,0x4a,0x7f] + vfnmadd132pd 1016(%rdx){1to4}, %ymm22, %ymm25 + +// CHECK: vfnmadd132pd 1024(%rdx){1to4}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x30,0x9c,0x8a,0x00,0x04,0x00,0x00] + vfnmadd132pd 1024(%rdx){1to4}, %ymm22, %ymm25 + +// CHECK: vfnmadd132pd -1024(%rdx){1to4}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x30,0x9c,0x4a,0x80] + vfnmadd132pd -1024(%rdx){1to4}, %ymm22, %ymm25 + +// CHECK: vfnmadd132pd -1032(%rdx){1to4}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0xcd,0x30,0x9c,0x8a,0xf8,0xfb,0xff,0xff] + vfnmadd132pd -1032(%rdx){1to4}, %ymm22, %ymm25 + +// CHECK: vfnmadd213ps %xmm20, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x22,0x3d,0x00,0xac,0xc4] + vfnmadd213ps %xmm20, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps %xmm20, %xmm24, %xmm24 {%k4} +// CHECK: encoding: [0x62,0x22,0x3d,0x04,0xac,0xc4] + vfnmadd213ps %xmm20, %xmm24, %xmm24 {%k4} + +// CHECK: vfnmadd213ps %xmm20, %xmm24, %xmm24 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0x3d,0x84,0xac,0xc4] + vfnmadd213ps %xmm20, %xmm24, %xmm24 {%k4} {z} + +// CHECK: vfnmadd213ps (%rcx), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x00,0xac,0x01] + vfnmadd213ps (%rcx), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps 291(%rax,%r14,8), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x22,0x3d,0x00,0xac,0x84,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213ps 291(%rax,%r14,8), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps (%rcx){1to4}, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x10,0xac,0x01] + vfnmadd213ps (%rcx){1to4}, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps 2032(%rdx), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x00,0xac,0x42,0x7f] + vfnmadd213ps 2032(%rdx), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps 2048(%rdx), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x00,0xac,0x82,0x00,0x08,0x00,0x00] + vfnmadd213ps 2048(%rdx), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps -2048(%rdx), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x00,0xac,0x42,0x80] + vfnmadd213ps -2048(%rdx), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps -2064(%rdx), %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x00,0xac,0x82,0xf0,0xf7,0xff,0xff] + vfnmadd213ps -2064(%rdx), %xmm24, %xmm24 + +// CHECK: vfnmadd213ps 508(%rdx){1to4}, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x10,0xac,0x42,0x7f] + vfnmadd213ps 508(%rdx){1to4}, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps 512(%rdx){1to4}, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x10,0xac,0x82,0x00,0x02,0x00,0x00] + vfnmadd213ps 512(%rdx){1to4}, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps -512(%rdx){1to4}, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x10,0xac,0x42,0x80] + vfnmadd213ps -512(%rdx){1to4}, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps -516(%rdx){1to4}, %xmm24, %xmm24 +// CHECK: encoding: [0x62,0x62,0x3d,0x10,0xac,0x82,0xfc,0xfd,0xff,0xff] + vfnmadd213ps -516(%rdx){1to4}, %xmm24, %xmm24 + +// CHECK: vfnmadd213ps %ymm22, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xa2,0x65,0x20,0xac,0xee] + vfnmadd213ps %ymm22, %ymm19, %ymm21 + +// CHECK: vfnmadd213ps %ymm22, %ymm19, %ymm21 {%k2} +// CHECK: encoding: [0x62,0xa2,0x65,0x22,0xac,0xee] + vfnmadd213ps %ymm22, %ymm19, %ymm21 {%k2} + +// CHECK: vfnmadd213ps %ymm22, %ymm19, %ymm21 {%k2} {z} +// CHECK: encoding: [0x62,0xa2,0x65,0xa2,0xac,0xee] + vfnmadd213ps %ymm22, %ymm19, %ymm21 {%k2} {z} + +// CHECK: vfnmadd213ps (%rcx), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x20,0xac,0x29] + vfnmadd213ps (%rcx), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps 291(%rax,%r14,8), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xa2,0x65,0x20,0xac,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213ps 291(%rax,%r14,8), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps (%rcx){1to8}, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x30,0xac,0x29] + vfnmadd213ps (%rcx){1to8}, %ymm19, %ymm21 + +// CHECK: vfnmadd213ps 4064(%rdx), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x20,0xac,0x6a,0x7f] + vfnmadd213ps 4064(%rdx), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps 4096(%rdx), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x20,0xac,0xaa,0x00,0x10,0x00,0x00] + vfnmadd213ps 4096(%rdx), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps -4096(%rdx), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x20,0xac,0x6a,0x80] + vfnmadd213ps -4096(%rdx), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps -4128(%rdx), %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x20,0xac,0xaa,0xe0,0xef,0xff,0xff] + vfnmadd213ps -4128(%rdx), %ymm19, %ymm21 + +// CHECK: vfnmadd213ps 508(%rdx){1to8}, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x30,0xac,0x6a,0x7f] + vfnmadd213ps 508(%rdx){1to8}, %ymm19, %ymm21 + +// CHECK: vfnmadd213ps 512(%rdx){1to8}, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x30,0xac,0xaa,0x00,0x02,0x00,0x00] + vfnmadd213ps 512(%rdx){1to8}, %ymm19, %ymm21 + +// CHECK: vfnmadd213ps -512(%rdx){1to8}, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x30,0xac,0x6a,0x80] + vfnmadd213ps -512(%rdx){1to8}, %ymm19, %ymm21 + +// CHECK: vfnmadd213ps -516(%rdx){1to8}, %ymm19, %ymm21 +// CHECK: encoding: [0x62,0xe2,0x65,0x30,0xac,0xaa,0xfc,0xfd,0xff,0xff] + vfnmadd213ps -516(%rdx){1to8}, %ymm19, %ymm21 + +// CHECK: vfnmadd213pd %xmm24, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x02,0xb5,0x00,0xac,0xc0] + vfnmadd213pd %xmm24, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd %xmm24, %xmm25, %xmm24 {%k4} +// CHECK: encoding: [0x62,0x02,0xb5,0x04,0xac,0xc0] + vfnmadd213pd %xmm24, %xmm25, %xmm24 {%k4} + +// CHECK: vfnmadd213pd %xmm24, %xmm25, %xmm24 {%k4} {z} +// CHECK: encoding: [0x62,0x02,0xb5,0x84,0xac,0xc0] + vfnmadd213pd %xmm24, %xmm25, %xmm24 {%k4} {z} + +// CHECK: vfnmadd213pd (%rcx), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xac,0x01] + vfnmadd213pd (%rcx), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd 291(%rax,%r14,8), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x22,0xb5,0x00,0xac,0x84,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213pd 291(%rax,%r14,8), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd (%rcx){1to2}, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xac,0x01] + vfnmadd213pd (%rcx){1to2}, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd 2032(%rdx), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xac,0x42,0x7f] + vfnmadd213pd 2032(%rdx), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd 2048(%rdx), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xac,0x82,0x00,0x08,0x00,0x00] + vfnmadd213pd 2048(%rdx), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd -2048(%rdx), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xac,0x42,0x80] + vfnmadd213pd -2048(%rdx), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd -2064(%rdx), %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xac,0x82,0xf0,0xf7,0xff,0xff] + vfnmadd213pd -2064(%rdx), %xmm25, %xmm24 + +// CHECK: vfnmadd213pd 1016(%rdx){1to2}, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xac,0x42,0x7f] + vfnmadd213pd 1016(%rdx){1to2}, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd 1024(%rdx){1to2}, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xac,0x82,0x00,0x04,0x00,0x00] + vfnmadd213pd 1024(%rdx){1to2}, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd -1024(%rdx){1to2}, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xac,0x42,0x80] + vfnmadd213pd -1024(%rdx){1to2}, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd -1032(%rdx){1to2}, %xmm25, %xmm24 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xac,0x82,0xf8,0xfb,0xff,0xff] + vfnmadd213pd -1032(%rdx){1to2}, %xmm25, %xmm24 + +// CHECK: vfnmadd213pd %ymm24, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0x82,0xa5,0x20,0xac,0xe0] + vfnmadd213pd %ymm24, %ymm27, %ymm20 + +// CHECK: vfnmadd213pd %ymm24, %ymm27, %ymm20 {%k4} +// CHECK: encoding: [0x62,0x82,0xa5,0x24,0xac,0xe0] + vfnmadd213pd %ymm24, %ymm27, %ymm20 {%k4} + +// CHECK: vfnmadd213pd %ymm24, %ymm27, %ymm20 {%k4} {z} +// CHECK: encoding: [0x62,0x82,0xa5,0xa4,0xac,0xe0] + vfnmadd213pd %ymm24, %ymm27, %ymm20 {%k4} {z} + +// CHECK: vfnmadd213pd (%rcx), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x20,0xac,0x21] + vfnmadd213pd (%rcx), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd 291(%rax,%r14,8), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xa2,0xa5,0x20,0xac,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd213pd 291(%rax,%r14,8), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd (%rcx){1to4}, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x30,0xac,0x21] + vfnmadd213pd (%rcx){1to4}, %ymm27, %ymm20 + +// CHECK: vfnmadd213pd 4064(%rdx), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x20,0xac,0x62,0x7f] + vfnmadd213pd 4064(%rdx), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd 4096(%rdx), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x20,0xac,0xa2,0x00,0x10,0x00,0x00] + vfnmadd213pd 4096(%rdx), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd -4096(%rdx), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x20,0xac,0x62,0x80] + vfnmadd213pd -4096(%rdx), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd -4128(%rdx), %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x20,0xac,0xa2,0xe0,0xef,0xff,0xff] + vfnmadd213pd -4128(%rdx), %ymm27, %ymm20 + +// CHECK: vfnmadd213pd 1016(%rdx){1to4}, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x30,0xac,0x62,0x7f] + vfnmadd213pd 1016(%rdx){1to4}, %ymm27, %ymm20 + +// CHECK: vfnmadd213pd 1024(%rdx){1to4}, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x30,0xac,0xa2,0x00,0x04,0x00,0x00] + vfnmadd213pd 1024(%rdx){1to4}, %ymm27, %ymm20 + +// CHECK: vfnmadd213pd -1024(%rdx){1to4}, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x30,0xac,0x62,0x80] + vfnmadd213pd -1024(%rdx){1to4}, %ymm27, %ymm20 + +// CHECK: vfnmadd213pd -1032(%rdx){1to4}, %ymm27, %ymm20 +// CHECK: encoding: [0x62,0xe2,0xa5,0x30,0xac,0xa2,0xf8,0xfb,0xff,0xff] + vfnmadd213pd -1032(%rdx){1to4}, %ymm27, %ymm20 + +// CHECK: vfnmadd231ps %xmm24, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0x82,0x2d,0x00,0xbc,0xd0] + vfnmadd231ps %xmm24, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps %xmm24, %xmm26, %xmm18 {%k1} +// CHECK: encoding: [0x62,0x82,0x2d,0x01,0xbc,0xd0] + vfnmadd231ps %xmm24, %xmm26, %xmm18 {%k1} + +// CHECK: vfnmadd231ps %xmm24, %xmm26, %xmm18 {%k1} {z} +// CHECK: encoding: [0x62,0x82,0x2d,0x81,0xbc,0xd0] + vfnmadd231ps %xmm24, %xmm26, %xmm18 {%k1} {z} + +// CHECK: vfnmadd231ps (%rcx), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0xbc,0x11] + vfnmadd231ps (%rcx), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps 291(%rax,%r14,8), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xa2,0x2d,0x00,0xbc,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231ps 291(%rax,%r14,8), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps (%rcx){1to4}, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0xbc,0x11] + vfnmadd231ps (%rcx){1to4}, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps 2032(%rdx), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0xbc,0x52,0x7f] + vfnmadd231ps 2032(%rdx), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps 2048(%rdx), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0xbc,0x92,0x00,0x08,0x00,0x00] + vfnmadd231ps 2048(%rdx), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps -2048(%rdx), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0xbc,0x52,0x80] + vfnmadd231ps -2048(%rdx), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps -2064(%rdx), %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x00,0xbc,0x92,0xf0,0xf7,0xff,0xff] + vfnmadd231ps -2064(%rdx), %xmm26, %xmm18 + +// CHECK: vfnmadd231ps 508(%rdx){1to4}, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0xbc,0x52,0x7f] + vfnmadd231ps 508(%rdx){1to4}, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps 512(%rdx){1to4}, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0xbc,0x92,0x00,0x02,0x00,0x00] + vfnmadd231ps 512(%rdx){1to4}, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps -512(%rdx){1to4}, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0xbc,0x52,0x80] + vfnmadd231ps -512(%rdx){1to4}, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps -516(%rdx){1to4}, %xmm26, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x2d,0x10,0xbc,0x92,0xfc,0xfd,0xff,0xff] + vfnmadd231ps -516(%rdx){1to4}, %xmm26, %xmm18 + +// CHECK: vfnmadd231ps %ymm21, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x5d,0x20,0xbc,0xe5] + vfnmadd231ps %ymm21, %ymm20, %ymm20 + +// CHECK: vfnmadd231ps %ymm21, %ymm20, %ymm20 {%k4} +// CHECK: encoding: [0x62,0xa2,0x5d,0x24,0xbc,0xe5] + vfnmadd231ps %ymm21, %ymm20, %ymm20 {%k4} + +// CHECK: vfnmadd231ps %ymm21, %ymm20, %ymm20 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0x5d,0xa4,0xbc,0xe5] + vfnmadd231ps %ymm21, %ymm20, %ymm20 {%k4} {z} + +// CHECK: vfnmadd231ps (%rcx), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0xbc,0x21] + vfnmadd231ps (%rcx), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps 291(%rax,%r14,8), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x5d,0x20,0xbc,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231ps 291(%rax,%r14,8), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps (%rcx){1to8}, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0xbc,0x21] + vfnmadd231ps (%rcx){1to8}, %ymm20, %ymm20 + +// CHECK: vfnmadd231ps 4064(%rdx), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0xbc,0x62,0x7f] + vfnmadd231ps 4064(%rdx), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps 4096(%rdx), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0xbc,0xa2,0x00,0x10,0x00,0x00] + vfnmadd231ps 4096(%rdx), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps -4096(%rdx), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0xbc,0x62,0x80] + vfnmadd231ps -4096(%rdx), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps -4128(%rdx), %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x20,0xbc,0xa2,0xe0,0xef,0xff,0xff] + vfnmadd231ps -4128(%rdx), %ymm20, %ymm20 + +// CHECK: vfnmadd231ps 508(%rdx){1to8}, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0xbc,0x62,0x7f] + vfnmadd231ps 508(%rdx){1to8}, %ymm20, %ymm20 + +// CHECK: vfnmadd231ps 512(%rdx){1to8}, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0xbc,0xa2,0x00,0x02,0x00,0x00] + vfnmadd231ps 512(%rdx){1to8}, %ymm20, %ymm20 + +// CHECK: vfnmadd231ps -512(%rdx){1to8}, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0xbc,0x62,0x80] + vfnmadd231ps -512(%rdx){1to8}, %ymm20, %ymm20 + +// CHECK: vfnmadd231ps -516(%rdx){1to8}, %ymm20, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x5d,0x30,0xbc,0xa2,0xfc,0xfd,0xff,0xff] + vfnmadd231ps -516(%rdx){1to8}, %ymm20, %ymm20 + +// CHECK: vfnmadd231pd %xmm26, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x02,0xb5,0x00,0xbc,0xea] + vfnmadd231pd %xmm26, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd %xmm26, %xmm25, %xmm29 {%k3} +// CHECK: encoding: [0x62,0x02,0xb5,0x03,0xbc,0xea] + vfnmadd231pd %xmm26, %xmm25, %xmm29 {%k3} + +// CHECK: vfnmadd231pd %xmm26, %xmm25, %xmm29 {%k3} {z} +// CHECK: encoding: [0x62,0x02,0xb5,0x83,0xbc,0xea] + vfnmadd231pd %xmm26, %xmm25, %xmm29 {%k3} {z} + +// CHECK: vfnmadd231pd (%rcx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xbc,0x29] + vfnmadd231pd (%rcx), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd 291(%rax,%r14,8), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x22,0xb5,0x00,0xbc,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231pd 291(%rax,%r14,8), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd (%rcx){1to2}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xbc,0x29] + vfnmadd231pd (%rcx){1to2}, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd 2032(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xbc,0x6a,0x7f] + vfnmadd231pd 2032(%rdx), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd 2048(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xbc,0xaa,0x00,0x08,0x00,0x00] + vfnmadd231pd 2048(%rdx), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd -2048(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xbc,0x6a,0x80] + vfnmadd231pd -2048(%rdx), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd -2064(%rdx), %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x00,0xbc,0xaa,0xf0,0xf7,0xff,0xff] + vfnmadd231pd -2064(%rdx), %xmm25, %xmm29 + +// CHECK: vfnmadd231pd 1016(%rdx){1to2}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xbc,0x6a,0x7f] + vfnmadd231pd 1016(%rdx){1to2}, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd 1024(%rdx){1to2}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xbc,0xaa,0x00,0x04,0x00,0x00] + vfnmadd231pd 1024(%rdx){1to2}, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd -1024(%rdx){1to2}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xbc,0x6a,0x80] + vfnmadd231pd -1024(%rdx){1to2}, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd -1032(%rdx){1to2}, %xmm25, %xmm29 +// CHECK: encoding: [0x62,0x62,0xb5,0x10,0xbc,0xaa,0xf8,0xfb,0xff,0xff] + vfnmadd231pd -1032(%rdx){1to2}, %xmm25, %xmm29 + +// CHECK: vfnmadd231pd %ymm23, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xa2,0x95,0x20,0xbc,0xf7] + vfnmadd231pd %ymm23, %ymm29, %ymm22 + +// CHECK: vfnmadd231pd %ymm23, %ymm29, %ymm22 {%k1} +// CHECK: encoding: [0x62,0xa2,0x95,0x21,0xbc,0xf7] + vfnmadd231pd %ymm23, %ymm29, %ymm22 {%k1} + +// CHECK: vfnmadd231pd %ymm23, %ymm29, %ymm22 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x95,0xa1,0xbc,0xf7] + vfnmadd231pd %ymm23, %ymm29, %ymm22 {%k1} {z} + +// CHECK: vfnmadd231pd (%rcx), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x20,0xbc,0x31] + vfnmadd231pd (%rcx), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd 291(%rax,%r14,8), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xa2,0x95,0x20,0xbc,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmadd231pd 291(%rax,%r14,8), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd (%rcx){1to4}, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x30,0xbc,0x31] + vfnmadd231pd (%rcx){1to4}, %ymm29, %ymm22 + +// CHECK: vfnmadd231pd 4064(%rdx), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x20,0xbc,0x72,0x7f] + vfnmadd231pd 4064(%rdx), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd 4096(%rdx), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x20,0xbc,0xb2,0x00,0x10,0x00,0x00] + vfnmadd231pd 4096(%rdx), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd -4096(%rdx), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x20,0xbc,0x72,0x80] + vfnmadd231pd -4096(%rdx), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd -4128(%rdx), %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x20,0xbc,0xb2,0xe0,0xef,0xff,0xff] + vfnmadd231pd -4128(%rdx), %ymm29, %ymm22 + +// CHECK: vfnmadd231pd 1016(%rdx){1to4}, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x30,0xbc,0x72,0x7f] + vfnmadd231pd 1016(%rdx){1to4}, %ymm29, %ymm22 + +// CHECK: vfnmadd231pd 1024(%rdx){1to4}, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x30,0xbc,0xb2,0x00,0x04,0x00,0x00] + vfnmadd231pd 1024(%rdx){1to4}, %ymm29, %ymm22 + +// CHECK: vfnmadd231pd -1024(%rdx){1to4}, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x30,0xbc,0x72,0x80] + vfnmadd231pd -1024(%rdx){1to4}, %ymm29, %ymm22 + +// CHECK: vfnmadd231pd -1032(%rdx){1to4}, %ymm29, %ymm22 +// CHECK: encoding: [0x62,0xe2,0x95,0x30,0xbc,0xb2,0xf8,0xfb,0xff,0xff] + vfnmadd231pd -1032(%rdx){1to4}, %ymm29, %ymm22 + +// CHECK: vfnmsub132ps %xmm26, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0x82,0x35,0x00,0x9e,0xea] + vfnmsub132ps %xmm26, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps %xmm26, %xmm25, %xmm21 {%k3} +// CHECK: encoding: [0x62,0x82,0x35,0x03,0x9e,0xea] + vfnmsub132ps %xmm26, %xmm25, %xmm21 {%k3} + +// CHECK: vfnmsub132ps %xmm26, %xmm25, %xmm21 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0x35,0x83,0x9e,0xea] + vfnmsub132ps %xmm26, %xmm25, %xmm21 {%k3} {z} + +// CHECK: vfnmsub132ps (%rcx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0x9e,0x29] + vfnmsub132ps (%rcx), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps 291(%rax,%r14,8), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xa2,0x35,0x00,0x9e,0xac,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132ps 291(%rax,%r14,8), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps (%rcx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0x9e,0x29] + vfnmsub132ps (%rcx){1to4}, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps 2032(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0x9e,0x6a,0x7f] + vfnmsub132ps 2032(%rdx), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps 2048(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0x9e,0xaa,0x00,0x08,0x00,0x00] + vfnmsub132ps 2048(%rdx), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps -2048(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0x9e,0x6a,0x80] + vfnmsub132ps -2048(%rdx), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps -2064(%rdx), %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x00,0x9e,0xaa,0xf0,0xf7,0xff,0xff] + vfnmsub132ps -2064(%rdx), %xmm25, %xmm21 + +// CHECK: vfnmsub132ps 508(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0x9e,0x6a,0x7f] + vfnmsub132ps 508(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps 512(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0x9e,0xaa,0x00,0x02,0x00,0x00] + vfnmsub132ps 512(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps -512(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0x9e,0x6a,0x80] + vfnmsub132ps -512(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps -516(%rdx){1to4}, %xmm25, %xmm21 +// CHECK: encoding: [0x62,0xe2,0x35,0x10,0x9e,0xaa,0xfc,0xfd,0xff,0xff] + vfnmsub132ps -516(%rdx){1to4}, %xmm25, %xmm21 + +// CHECK: vfnmsub132ps %ymm22, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xa2,0x3d,0x20,0x9e,0xd6] + vfnmsub132ps %ymm22, %ymm24, %ymm18 + +// CHECK: vfnmsub132ps %ymm22, %ymm24, %ymm18 {%k5} +// CHECK: encoding: [0x62,0xa2,0x3d,0x25,0x9e,0xd6] + vfnmsub132ps %ymm22, %ymm24, %ymm18 {%k5} + +// CHECK: vfnmsub132ps %ymm22, %ymm24, %ymm18 {%k5} {z} +// CHECK: encoding: [0x62,0xa2,0x3d,0xa5,0x9e,0xd6] + vfnmsub132ps %ymm22, %ymm24, %ymm18 {%k5} {z} + +// CHECK: vfnmsub132ps (%rcx), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0x9e,0x11] + vfnmsub132ps (%rcx), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps 291(%rax,%r14,8), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xa2,0x3d,0x20,0x9e,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132ps 291(%rax,%r14,8), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps (%rcx){1to8}, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0x9e,0x11] + vfnmsub132ps (%rcx){1to8}, %ymm24, %ymm18 + +// CHECK: vfnmsub132ps 4064(%rdx), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0x9e,0x52,0x7f] + vfnmsub132ps 4064(%rdx), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps 4096(%rdx), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0x9e,0x92,0x00,0x10,0x00,0x00] + vfnmsub132ps 4096(%rdx), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps -4096(%rdx), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0x9e,0x52,0x80] + vfnmsub132ps -4096(%rdx), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps -4128(%rdx), %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x20,0x9e,0x92,0xe0,0xef,0xff,0xff] + vfnmsub132ps -4128(%rdx), %ymm24, %ymm18 + +// CHECK: vfnmsub132ps 508(%rdx){1to8}, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0x9e,0x52,0x7f] + vfnmsub132ps 508(%rdx){1to8}, %ymm24, %ymm18 + +// CHECK: vfnmsub132ps 512(%rdx){1to8}, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0x9e,0x92,0x00,0x02,0x00,0x00] + vfnmsub132ps 512(%rdx){1to8}, %ymm24, %ymm18 + +// CHECK: vfnmsub132ps -512(%rdx){1to8}, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0x9e,0x52,0x80] + vfnmsub132ps -512(%rdx){1to8}, %ymm24, %ymm18 + +// CHECK: vfnmsub132ps -516(%rdx){1to8}, %ymm24, %ymm18 +// CHECK: encoding: [0x62,0xe2,0x3d,0x30,0x9e,0x92,0xfc,0xfd,0xff,0xff] + vfnmsub132ps -516(%rdx){1to8}, %ymm24, %ymm18 + +// CHECK: vfnmsub132pd %xmm17, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xb5,0x00,0x9e,0xd9] + vfnmsub132pd %xmm17, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd %xmm17, %xmm25, %xmm19 {%k4} +// CHECK: encoding: [0x62,0xa2,0xb5,0x04,0x9e,0xd9] + vfnmsub132pd %xmm17, %xmm25, %xmm19 {%k4} + +// CHECK: vfnmsub132pd %xmm17, %xmm25, %xmm19 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0xb5,0x84,0x9e,0xd9] + vfnmsub132pd %xmm17, %xmm25, %xmm19 {%k4} {z} + +// CHECK: vfnmsub132pd (%rcx), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x00,0x9e,0x19] + vfnmsub132pd (%rcx), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd 291(%rax,%r14,8), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xa2,0xb5,0x00,0x9e,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132pd 291(%rax,%r14,8), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd (%rcx){1to2}, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x10,0x9e,0x19] + vfnmsub132pd (%rcx){1to2}, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd 2032(%rdx), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x00,0x9e,0x5a,0x7f] + vfnmsub132pd 2032(%rdx), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd 2048(%rdx), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x00,0x9e,0x9a,0x00,0x08,0x00,0x00] + vfnmsub132pd 2048(%rdx), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd -2048(%rdx), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x00,0x9e,0x5a,0x80] + vfnmsub132pd -2048(%rdx), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd -2064(%rdx), %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x00,0x9e,0x9a,0xf0,0xf7,0xff,0xff] + vfnmsub132pd -2064(%rdx), %xmm25, %xmm19 + +// CHECK: vfnmsub132pd 1016(%rdx){1to2}, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x10,0x9e,0x5a,0x7f] + vfnmsub132pd 1016(%rdx){1to2}, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd 1024(%rdx){1to2}, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x10,0x9e,0x9a,0x00,0x04,0x00,0x00] + vfnmsub132pd 1024(%rdx){1to2}, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd -1024(%rdx){1to2}, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x10,0x9e,0x5a,0x80] + vfnmsub132pd -1024(%rdx){1to2}, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd -1032(%rdx){1to2}, %xmm25, %xmm19 +// CHECK: encoding: [0x62,0xe2,0xb5,0x10,0x9e,0x9a,0xf8,0xfb,0xff,0xff] + vfnmsub132pd -1032(%rdx){1to2}, %xmm25, %xmm19 + +// CHECK: vfnmsub132pd %ymm22, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x9e,0xce] + vfnmsub132pd %ymm22, %ymm28, %ymm17 + +// CHECK: vfnmsub132pd %ymm22, %ymm28, %ymm17 {%k5} +// CHECK: encoding: [0x62,0xa2,0x9d,0x25,0x9e,0xce] + vfnmsub132pd %ymm22, %ymm28, %ymm17 {%k5} + +// CHECK: vfnmsub132pd %ymm22, %ymm28, %ymm17 {%k5} {z} +// CHECK: encoding: [0x62,0xa2,0x9d,0xa5,0x9e,0xce] + vfnmsub132pd %ymm22, %ymm28, %ymm17 {%k5} {z} + +// CHECK: vfnmsub132pd (%rcx), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9e,0x09] + vfnmsub132pd (%rcx), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd 291(%rax,%r14,8), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x9e,0x8c,0xf0,0x23,0x01,0x00,0x00] + vfnmsub132pd 291(%rax,%r14,8), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd (%rcx){1to4}, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9e,0x09] + vfnmsub132pd (%rcx){1to4}, %ymm28, %ymm17 + +// CHECK: vfnmsub132pd 4064(%rdx), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9e,0x4a,0x7f] + vfnmsub132pd 4064(%rdx), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd 4096(%rdx), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9e,0x8a,0x00,0x10,0x00,0x00] + vfnmsub132pd 4096(%rdx), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd -4096(%rdx), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9e,0x4a,0x80] + vfnmsub132pd -4096(%rdx), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd -4128(%rdx), %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x9e,0x8a,0xe0,0xef,0xff,0xff] + vfnmsub132pd -4128(%rdx), %ymm28, %ymm17 + +// CHECK: vfnmsub132pd 1016(%rdx){1to4}, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9e,0x4a,0x7f] + vfnmsub132pd 1016(%rdx){1to4}, %ymm28, %ymm17 + +// CHECK: vfnmsub132pd 1024(%rdx){1to4}, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9e,0x8a,0x00,0x04,0x00,0x00] + vfnmsub132pd 1024(%rdx){1to4}, %ymm28, %ymm17 + +// CHECK: vfnmsub132pd -1024(%rdx){1to4}, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9e,0x4a,0x80] + vfnmsub132pd -1024(%rdx){1to4}, %ymm28, %ymm17 + +// CHECK: vfnmsub132pd -1032(%rdx){1to4}, %ymm28, %ymm17 +// CHECK: encoding: [0x62,0xe2,0x9d,0x30,0x9e,0x8a,0xf8,0xfb,0xff,0xff] + vfnmsub132pd -1032(%rdx){1to4}, %ymm28, %ymm17 + +// CHECK: vfnmsub213ps %xmm18, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x22,0x1d,0x00,0xae,0xe2] + vfnmsub213ps %xmm18, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps %xmm18, %xmm28, %xmm28 {%k4} +// CHECK: encoding: [0x62,0x22,0x1d,0x04,0xae,0xe2] + vfnmsub213ps %xmm18, %xmm28, %xmm28 {%k4} + +// CHECK: vfnmsub213ps %xmm18, %xmm28, %xmm28 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0x1d,0x84,0xae,0xe2] + vfnmsub213ps %xmm18, %xmm28, %xmm28 {%k4} {z} + +// CHECK: vfnmsub213ps (%rcx), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xae,0x21] + vfnmsub213ps (%rcx), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps 291(%rax,%r14,8), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x22,0x1d,0x00,0xae,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213ps 291(%rax,%r14,8), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps (%rcx){1to4}, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xae,0x21] + vfnmsub213ps (%rcx){1to4}, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps 2032(%rdx), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xae,0x62,0x7f] + vfnmsub213ps 2032(%rdx), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps 2048(%rdx), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xae,0xa2,0x00,0x08,0x00,0x00] + vfnmsub213ps 2048(%rdx), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps -2048(%rdx), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xae,0x62,0x80] + vfnmsub213ps -2048(%rdx), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps -2064(%rdx), %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x00,0xae,0xa2,0xf0,0xf7,0xff,0xff] + vfnmsub213ps -2064(%rdx), %xmm28, %xmm28 + +// CHECK: vfnmsub213ps 508(%rdx){1to4}, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xae,0x62,0x7f] + vfnmsub213ps 508(%rdx){1to4}, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps 512(%rdx){1to4}, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xae,0xa2,0x00,0x02,0x00,0x00] + vfnmsub213ps 512(%rdx){1to4}, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps -512(%rdx){1to4}, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xae,0x62,0x80] + vfnmsub213ps -512(%rdx){1to4}, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps -516(%rdx){1to4}, %xmm28, %xmm28 +// CHECK: encoding: [0x62,0x62,0x1d,0x10,0xae,0xa2,0xfc,0xfd,0xff,0xff] + vfnmsub213ps -516(%rdx){1to4}, %xmm28, %xmm28 + +// CHECK: vfnmsub213ps %ymm23, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x35,0x20,0xae,0xe7] + vfnmsub213ps %ymm23, %ymm25, %ymm20 + +// CHECK: vfnmsub213ps %ymm23, %ymm25, %ymm20 {%k1} +// CHECK: encoding: [0x62,0xa2,0x35,0x21,0xae,0xe7] + vfnmsub213ps %ymm23, %ymm25, %ymm20 {%k1} + +// CHECK: vfnmsub213ps %ymm23, %ymm25, %ymm20 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0x35,0xa1,0xae,0xe7] + vfnmsub213ps %ymm23, %ymm25, %ymm20 {%k1} {z} + +// CHECK: vfnmsub213ps (%rcx), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x20,0xae,0x21] + vfnmsub213ps (%rcx), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps 291(%rax,%r14,8), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xa2,0x35,0x20,0xae,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213ps 291(%rax,%r14,8), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps (%rcx){1to8}, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x30,0xae,0x21] + vfnmsub213ps (%rcx){1to8}, %ymm25, %ymm20 + +// CHECK: vfnmsub213ps 4064(%rdx), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x20,0xae,0x62,0x7f] + vfnmsub213ps 4064(%rdx), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps 4096(%rdx), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x20,0xae,0xa2,0x00,0x10,0x00,0x00] + vfnmsub213ps 4096(%rdx), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps -4096(%rdx), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x20,0xae,0x62,0x80] + vfnmsub213ps -4096(%rdx), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps -4128(%rdx), %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x20,0xae,0xa2,0xe0,0xef,0xff,0xff] + vfnmsub213ps -4128(%rdx), %ymm25, %ymm20 + +// CHECK: vfnmsub213ps 508(%rdx){1to8}, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x30,0xae,0x62,0x7f] + vfnmsub213ps 508(%rdx){1to8}, %ymm25, %ymm20 + +// CHECK: vfnmsub213ps 512(%rdx){1to8}, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x30,0xae,0xa2,0x00,0x02,0x00,0x00] + vfnmsub213ps 512(%rdx){1to8}, %ymm25, %ymm20 + +// CHECK: vfnmsub213ps -512(%rdx){1to8}, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x30,0xae,0x62,0x80] + vfnmsub213ps -512(%rdx){1to8}, %ymm25, %ymm20 + +// CHECK: vfnmsub213ps -516(%rdx){1to8}, %ymm25, %ymm20 +// CHECK: encoding: [0x62,0xe2,0x35,0x30,0xae,0xa2,0xfc,0xfd,0xff,0xff] + vfnmsub213ps -516(%rdx){1to8}, %ymm25, %ymm20 + +// CHECK: vfnmsub213pd %xmm25, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0x82,0xf5,0x00,0xae,0xe1] + vfnmsub213pd %xmm25, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd %xmm25, %xmm17, %xmm20 {%k1} +// CHECK: encoding: [0x62,0x82,0xf5,0x01,0xae,0xe1] + vfnmsub213pd %xmm25, %xmm17, %xmm20 {%k1} + +// CHECK: vfnmsub213pd %xmm25, %xmm17, %xmm20 {%k1} {z} +// CHECK: encoding: [0x62,0x82,0xf5,0x81,0xae,0xe1] + vfnmsub213pd %xmm25, %xmm17, %xmm20 {%k1} {z} + +// CHECK: vfnmsub213pd (%rcx), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x00,0xae,0x21] + vfnmsub213pd (%rcx), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd 291(%rax,%r14,8), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xa2,0xf5,0x00,0xae,0xa4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213pd 291(%rax,%r14,8), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd (%rcx){1to2}, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x10,0xae,0x21] + vfnmsub213pd (%rcx){1to2}, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd 2032(%rdx), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x00,0xae,0x62,0x7f] + vfnmsub213pd 2032(%rdx), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd 2048(%rdx), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x00,0xae,0xa2,0x00,0x08,0x00,0x00] + vfnmsub213pd 2048(%rdx), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd -2048(%rdx), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x00,0xae,0x62,0x80] + vfnmsub213pd -2048(%rdx), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd -2064(%rdx), %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x00,0xae,0xa2,0xf0,0xf7,0xff,0xff] + vfnmsub213pd -2064(%rdx), %xmm17, %xmm20 + +// CHECK: vfnmsub213pd 1016(%rdx){1to2}, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x10,0xae,0x62,0x7f] + vfnmsub213pd 1016(%rdx){1to2}, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd 1024(%rdx){1to2}, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x10,0xae,0xa2,0x00,0x04,0x00,0x00] + vfnmsub213pd 1024(%rdx){1to2}, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd -1024(%rdx){1to2}, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x10,0xae,0x62,0x80] + vfnmsub213pd -1024(%rdx){1to2}, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd -1032(%rdx){1to2}, %xmm17, %xmm20 +// CHECK: encoding: [0x62,0xe2,0xf5,0x10,0xae,0xa2,0xf8,0xfb,0xff,0xff] + vfnmsub213pd -1032(%rdx){1to2}, %xmm17, %xmm20 + +// CHECK: vfnmsub213pd %ymm28, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0x82,0xdd,0x20,0xae,0xdc] + vfnmsub213pd %ymm28, %ymm20, %ymm19 + +// CHECK: vfnmsub213pd %ymm28, %ymm20, %ymm19 {%k7} +// CHECK: encoding: [0x62,0x82,0xdd,0x27,0xae,0xdc] + vfnmsub213pd %ymm28, %ymm20, %ymm19 {%k7} + +// CHECK: vfnmsub213pd %ymm28, %ymm20, %ymm19 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0xdd,0xa7,0xae,0xdc] + vfnmsub213pd %ymm28, %ymm20, %ymm19 {%k7} {z} + +// CHECK: vfnmsub213pd (%rcx), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x20,0xae,0x19] + vfnmsub213pd (%rcx), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd 291(%rax,%r14,8), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xa2,0xdd,0x20,0xae,0x9c,0xf0,0x23,0x01,0x00,0x00] + vfnmsub213pd 291(%rax,%r14,8), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd (%rcx){1to4}, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x30,0xae,0x19] + vfnmsub213pd (%rcx){1to4}, %ymm20, %ymm19 + +// CHECK: vfnmsub213pd 4064(%rdx), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x20,0xae,0x5a,0x7f] + vfnmsub213pd 4064(%rdx), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd 4096(%rdx), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x20,0xae,0x9a,0x00,0x10,0x00,0x00] + vfnmsub213pd 4096(%rdx), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd -4096(%rdx), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x20,0xae,0x5a,0x80] + vfnmsub213pd -4096(%rdx), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd -4128(%rdx), %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x20,0xae,0x9a,0xe0,0xef,0xff,0xff] + vfnmsub213pd -4128(%rdx), %ymm20, %ymm19 + +// CHECK: vfnmsub213pd 1016(%rdx){1to4}, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x30,0xae,0x5a,0x7f] + vfnmsub213pd 1016(%rdx){1to4}, %ymm20, %ymm19 + +// CHECK: vfnmsub213pd 1024(%rdx){1to4}, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x30,0xae,0x9a,0x00,0x04,0x00,0x00] + vfnmsub213pd 1024(%rdx){1to4}, %ymm20, %ymm19 + +// CHECK: vfnmsub213pd -1024(%rdx){1to4}, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x30,0xae,0x5a,0x80] + vfnmsub213pd -1024(%rdx){1to4}, %ymm20, %ymm19 + +// CHECK: vfnmsub213pd -1032(%rdx){1to4}, %ymm20, %ymm19 +// CHECK: encoding: [0x62,0xe2,0xdd,0x30,0xae,0x9a,0xf8,0xfb,0xff,0xff] + vfnmsub213pd -1032(%rdx){1to4}, %ymm20, %ymm19 + +// CHECK: vfnmsub231ps %xmm26, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0x82,0x25,0x00,0xbe,0xd2] + vfnmsub231ps %xmm26, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps %xmm26, %xmm27, %xmm18 {%k2} +// CHECK: encoding: [0x62,0x82,0x25,0x02,0xbe,0xd2] + vfnmsub231ps %xmm26, %xmm27, %xmm18 {%k2} + +// CHECK: vfnmsub231ps %xmm26, %xmm27, %xmm18 {%k2} {z} +// CHECK: encoding: [0x62,0x82,0x25,0x82,0xbe,0xd2] + vfnmsub231ps %xmm26, %xmm27, %xmm18 {%k2} {z} + +// CHECK: vfnmsub231ps (%rcx), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xbe,0x11] + vfnmsub231ps (%rcx), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps 291(%rax,%r14,8), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xa2,0x25,0x00,0xbe,0x94,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231ps 291(%rax,%r14,8), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps (%rcx){1to4}, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xbe,0x11] + vfnmsub231ps (%rcx){1to4}, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps 2032(%rdx), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xbe,0x52,0x7f] + vfnmsub231ps 2032(%rdx), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps 2048(%rdx), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xbe,0x92,0x00,0x08,0x00,0x00] + vfnmsub231ps 2048(%rdx), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps -2048(%rdx), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xbe,0x52,0x80] + vfnmsub231ps -2048(%rdx), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps -2064(%rdx), %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0xbe,0x92,0xf0,0xf7,0xff,0xff] + vfnmsub231ps -2064(%rdx), %xmm27, %xmm18 + +// CHECK: vfnmsub231ps 508(%rdx){1to4}, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xbe,0x52,0x7f] + vfnmsub231ps 508(%rdx){1to4}, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps 512(%rdx){1to4}, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xbe,0x92,0x00,0x02,0x00,0x00] + vfnmsub231ps 512(%rdx){1to4}, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps -512(%rdx){1to4}, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xbe,0x52,0x80] + vfnmsub231ps -512(%rdx){1to4}, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps -516(%rdx){1to4}, %xmm27, %xmm18 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0xbe,0x92,0xfc,0xfd,0xff,0xff] + vfnmsub231ps -516(%rdx){1to4}, %xmm27, %xmm18 + +// CHECK: vfnmsub231ps %ymm18, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x22,0x5d,0x20,0xbe,0xf2] + vfnmsub231ps %ymm18, %ymm20, %ymm30 + +// CHECK: vfnmsub231ps %ymm18, %ymm20, %ymm30 {%k1} +// CHECK: encoding: [0x62,0x22,0x5d,0x21,0xbe,0xf2] + vfnmsub231ps %ymm18, %ymm20, %ymm30 {%k1} + +// CHECK: vfnmsub231ps %ymm18, %ymm20, %ymm30 {%k1} {z} +// CHECK: encoding: [0x62,0x22,0x5d,0xa1,0xbe,0xf2] + vfnmsub231ps %ymm18, %ymm20, %ymm30 {%k1} {z} + +// CHECK: vfnmsub231ps (%rcx), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x20,0xbe,0x31] + vfnmsub231ps (%rcx), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps 291(%rax,%r14,8), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x22,0x5d,0x20,0xbe,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231ps 291(%rax,%r14,8), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps (%rcx){1to8}, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x30,0xbe,0x31] + vfnmsub231ps (%rcx){1to8}, %ymm20, %ymm30 + +// CHECK: vfnmsub231ps 4064(%rdx), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x20,0xbe,0x72,0x7f] + vfnmsub231ps 4064(%rdx), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps 4096(%rdx), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x20,0xbe,0xb2,0x00,0x10,0x00,0x00] + vfnmsub231ps 4096(%rdx), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps -4096(%rdx), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x20,0xbe,0x72,0x80] + vfnmsub231ps -4096(%rdx), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps -4128(%rdx), %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x20,0xbe,0xb2,0xe0,0xef,0xff,0xff] + vfnmsub231ps -4128(%rdx), %ymm20, %ymm30 + +// CHECK: vfnmsub231ps 508(%rdx){1to8}, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x30,0xbe,0x72,0x7f] + vfnmsub231ps 508(%rdx){1to8}, %ymm20, %ymm30 + +// CHECK: vfnmsub231ps 512(%rdx){1to8}, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x30,0xbe,0xb2,0x00,0x02,0x00,0x00] + vfnmsub231ps 512(%rdx){1to8}, %ymm20, %ymm30 + +// CHECK: vfnmsub231ps -512(%rdx){1to8}, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x30,0xbe,0x72,0x80] + vfnmsub231ps -512(%rdx){1to8}, %ymm20, %ymm30 + +// CHECK: vfnmsub231ps -516(%rdx){1to8}, %ymm20, %ymm30 +// CHECK: encoding: [0x62,0x62,0x5d,0x30,0xbe,0xb2,0xfc,0xfd,0xff,0xff] + vfnmsub231ps -516(%rdx){1to8}, %ymm20, %ymm30 + +// CHECK: vfnmsub231pd %xmm25, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0x82,0xe5,0x00,0xbe,0xf9] + vfnmsub231pd %xmm25, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd %xmm25, %xmm19, %xmm23 {%k3} +// CHECK: encoding: [0x62,0x82,0xe5,0x03,0xbe,0xf9] + vfnmsub231pd %xmm25, %xmm19, %xmm23 {%k3} + +// CHECK: vfnmsub231pd %xmm25, %xmm19, %xmm23 {%k3} {z} +// CHECK: encoding: [0x62,0x82,0xe5,0x83,0xbe,0xf9] + vfnmsub231pd %xmm25, %xmm19, %xmm23 {%k3} {z} + +// CHECK: vfnmsub231pd (%rcx), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xbe,0x39] + vfnmsub231pd (%rcx), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd 291(%rax,%r14,8), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xa2,0xe5,0x00,0xbe,0xbc,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231pd 291(%rax,%r14,8), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd (%rcx){1to2}, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xbe,0x39] + vfnmsub231pd (%rcx){1to2}, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd 2032(%rdx), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xbe,0x7a,0x7f] + vfnmsub231pd 2032(%rdx), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd 2048(%rdx), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xbe,0xba,0x00,0x08,0x00,0x00] + vfnmsub231pd 2048(%rdx), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd -2048(%rdx), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xbe,0x7a,0x80] + vfnmsub231pd -2048(%rdx), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd -2064(%rdx), %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x00,0xbe,0xba,0xf0,0xf7,0xff,0xff] + vfnmsub231pd -2064(%rdx), %xmm19, %xmm23 + +// CHECK: vfnmsub231pd 1016(%rdx){1to2}, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xbe,0x7a,0x7f] + vfnmsub231pd 1016(%rdx){1to2}, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd 1024(%rdx){1to2}, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xbe,0xba,0x00,0x04,0x00,0x00] + vfnmsub231pd 1024(%rdx){1to2}, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd -1024(%rdx){1to2}, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xbe,0x7a,0x80] + vfnmsub231pd -1024(%rdx){1to2}, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd -1032(%rdx){1to2}, %xmm19, %xmm23 +// CHECK: encoding: [0x62,0xe2,0xe5,0x10,0xbe,0xba,0xf8,0xfb,0xff,0xff] + vfnmsub231pd -1032(%rdx){1to2}, %xmm19, %xmm23 + +// CHECK: vfnmsub231pd %ymm20, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xa2,0xed,0x20,0xbe,0xf4] + vfnmsub231pd %ymm20, %ymm18, %ymm22 + +// CHECK: vfnmsub231pd %ymm20, %ymm18, %ymm22 {%k1} +// CHECK: encoding: [0x62,0xa2,0xed,0x21,0xbe,0xf4] + vfnmsub231pd %ymm20, %ymm18, %ymm22 {%k1} + +// CHECK: vfnmsub231pd %ymm20, %ymm18, %ymm22 {%k1} {z} +// CHECK: encoding: [0x62,0xa2,0xed,0xa1,0xbe,0xf4] + vfnmsub231pd %ymm20, %ymm18, %ymm22 {%k1} {z} + +// CHECK: vfnmsub231pd (%rcx), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xbe,0x31] + vfnmsub231pd (%rcx), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd 291(%rax,%r14,8), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xa2,0xed,0x20,0xbe,0xb4,0xf0,0x23,0x01,0x00,0x00] + vfnmsub231pd 291(%rax,%r14,8), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd (%rcx){1to4}, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xbe,0x31] + vfnmsub231pd (%rcx){1to4}, %ymm18, %ymm22 + +// CHECK: vfnmsub231pd 4064(%rdx), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xbe,0x72,0x7f] + vfnmsub231pd 4064(%rdx), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd 4096(%rdx), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xbe,0xb2,0x00,0x10,0x00,0x00] + vfnmsub231pd 4096(%rdx), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd -4096(%rdx), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xbe,0x72,0x80] + vfnmsub231pd -4096(%rdx), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd -4128(%rdx), %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x20,0xbe,0xb2,0xe0,0xef,0xff,0xff] + vfnmsub231pd -4128(%rdx), %ymm18, %ymm22 + +// CHECK: vfnmsub231pd 1016(%rdx){1to4}, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xbe,0x72,0x7f] + vfnmsub231pd 1016(%rdx){1to4}, %ymm18, %ymm22 + +// CHECK: vfnmsub231pd 1024(%rdx){1to4}, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xbe,0xb2,0x00,0x04,0x00,0x00] + vfnmsub231pd 1024(%rdx){1to4}, %ymm18, %ymm22 + +// CHECK: vfnmsub231pd -1024(%rdx){1to4}, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xbe,0x72,0x80] + vfnmsub231pd -1024(%rdx){1to4}, %ymm18, %ymm22 + +// CHECK: vfnmsub231pd -1032(%rdx){1to4}, %ymm18, %ymm22 +// CHECK: encoding: [0x62,0xe2,0xed,0x30,0xbe,0xb2,0xf8,0xfb,0xff,0xff] + vfnmsub231pd -1032(%rdx){1to4}, %ymm18, %ymm22 + // CHECK: vpermi2d %xmm25, %xmm23, %xmm21 // CHECK: encoding: [0x62,0x82,0x45,0x00,0x76,0xe9] vpermi2d %xmm25, %xmm23, %xmm21 @@ -12028,3 +16060,227 @@ vaddpd {rz-sae}, %zmm2, %zmm1, %zmm1 // CHECK: vpermt2pd -1032(%rdx){1to4}, %ymm23, %ymm17 // CHECK: encoding: [0x62,0xe2,0xc5,0x30,0x7f,0x8a,0xf8,0xfb,0xff,0xff] vpermt2pd -1032(%rdx){1to4}, %ymm23, %ymm17 + +// CHECK: vscalefpd %xmm17, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x22,0xf5,0x00,0x2c,0xc1] + vscalefpd %xmm17, %xmm17, %xmm24 + +// CHECK: vscalefpd %xmm17, %xmm17, %xmm24 {%k2} +// CHECK: encoding: [0x62,0x22,0xf5,0x02,0x2c,0xc1] + vscalefpd %xmm17, %xmm17, %xmm24 {%k2} + +// CHECK: vscalefpd %xmm17, %xmm17, %xmm24 {%k2} {z} +// CHECK: encoding: [0x62,0x22,0xf5,0x82,0x2c,0xc1] + vscalefpd %xmm17, %xmm17, %xmm24 {%k2} {z} + +// CHECK: vscalefpd (%rcx), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x2c,0x01] + vscalefpd (%rcx), %xmm17, %xmm24 + +// CHECK: vscalefpd 291(%rax,%r14,8), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x22,0xf5,0x00,0x2c,0x84,0xf0,0x23,0x01,0x00,0x00] + vscalefpd 291(%rax,%r14,8), %xmm17, %xmm24 + +// CHECK: vscalefpd (%rcx){1to2}, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x2c,0x01] + vscalefpd (%rcx){1to2}, %xmm17, %xmm24 + +// CHECK: vscalefpd 2032(%rdx), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x2c,0x42,0x7f] + vscalefpd 2032(%rdx), %xmm17, %xmm24 + +// CHECK: vscalefpd 2048(%rdx), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x2c,0x82,0x00,0x08,0x00,0x00] + vscalefpd 2048(%rdx), %xmm17, %xmm24 + +// CHECK: vscalefpd -2048(%rdx), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x2c,0x42,0x80] + vscalefpd -2048(%rdx), %xmm17, %xmm24 + +// CHECK: vscalefpd -2064(%rdx), %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x00,0x2c,0x82,0xf0,0xf7,0xff,0xff] + vscalefpd -2064(%rdx), %xmm17, %xmm24 + +// CHECK: vscalefpd 1016(%rdx){1to2}, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x2c,0x42,0x7f] + vscalefpd 1016(%rdx){1to2}, %xmm17, %xmm24 + +// CHECK: vscalefpd 1024(%rdx){1to2}, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x2c,0x82,0x00,0x04,0x00,0x00] + vscalefpd 1024(%rdx){1to2}, %xmm17, %xmm24 + +// CHECK: vscalefpd -1024(%rdx){1to2}, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x2c,0x42,0x80] + vscalefpd -1024(%rdx){1to2}, %xmm17, %xmm24 + +// CHECK: vscalefpd -1032(%rdx){1to2}, %xmm17, %xmm24 +// CHECK: encoding: [0x62,0x62,0xf5,0x10,0x2c,0x82,0xf8,0xfb,0xff,0xff] + vscalefpd -1032(%rdx){1to2}, %xmm17, %xmm24 + +// CHECK: vscalefpd %ymm26, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x02,0xdd,0x20,0x2c,0xea] + vscalefpd %ymm26, %ymm20, %ymm29 + +// CHECK: vscalefpd %ymm26, %ymm20, %ymm29 {%k2} +// CHECK: encoding: [0x62,0x02,0xdd,0x22,0x2c,0xea] + vscalefpd %ymm26, %ymm20, %ymm29 {%k2} + +// CHECK: vscalefpd %ymm26, %ymm20, %ymm29 {%k2} {z} +// CHECK: encoding: [0x62,0x02,0xdd,0xa2,0x2c,0xea] + vscalefpd %ymm26, %ymm20, %ymm29 {%k2} {z} + +// CHECK: vscalefpd (%rcx), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0x2c,0x29] + vscalefpd (%rcx), %ymm20, %ymm29 + +// CHECK: vscalefpd 291(%rax,%r14,8), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x22,0xdd,0x20,0x2c,0xac,0xf0,0x23,0x01,0x00,0x00] + vscalefpd 291(%rax,%r14,8), %ymm20, %ymm29 + +// CHECK: vscalefpd (%rcx){1to4}, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0x2c,0x29] + vscalefpd (%rcx){1to4}, %ymm20, %ymm29 + +// CHECK: vscalefpd 4064(%rdx), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0x2c,0x6a,0x7f] + vscalefpd 4064(%rdx), %ymm20, %ymm29 + +// CHECK: vscalefpd 4096(%rdx), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0x2c,0xaa,0x00,0x10,0x00,0x00] + vscalefpd 4096(%rdx), %ymm20, %ymm29 + +// CHECK: vscalefpd -4096(%rdx), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0x2c,0x6a,0x80] + vscalefpd -4096(%rdx), %ymm20, %ymm29 + +// CHECK: vscalefpd -4128(%rdx), %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x20,0x2c,0xaa,0xe0,0xef,0xff,0xff] + vscalefpd -4128(%rdx), %ymm20, %ymm29 + +// CHECK: vscalefpd 1016(%rdx){1to4}, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0x2c,0x6a,0x7f] + vscalefpd 1016(%rdx){1to4}, %ymm20, %ymm29 + +// CHECK: vscalefpd 1024(%rdx){1to4}, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0x2c,0xaa,0x00,0x04,0x00,0x00] + vscalefpd 1024(%rdx){1to4}, %ymm20, %ymm29 + +// CHECK: vscalefpd -1024(%rdx){1to4}, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0x2c,0x6a,0x80] + vscalefpd -1024(%rdx){1to4}, %ymm20, %ymm29 + +// CHECK: vscalefpd -1032(%rdx){1to4}, %ymm20, %ymm29 +// CHECK: encoding: [0x62,0x62,0xdd,0x30,0x2c,0xaa,0xf8,0xfb,0xff,0xff] + vscalefpd -1032(%rdx){1to4}, %ymm20, %ymm29 + +// CHECK: vscalefps %xmm22, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x25,0x00,0x2c,0xde] + vscalefps %xmm22, %xmm27, %xmm19 + +// CHECK: vscalefps %xmm22, %xmm27, %xmm19 {%k4} +// CHECK: encoding: [0x62,0xa2,0x25,0x04,0x2c,0xde] + vscalefps %xmm22, %xmm27, %xmm19 {%k4} + +// CHECK: vscalefps %xmm22, %xmm27, %xmm19 {%k4} {z} +// CHECK: encoding: [0x62,0xa2,0x25,0x84,0x2c,0xde] + vscalefps %xmm22, %xmm27, %xmm19 {%k4} {z} + +// CHECK: vscalefps (%rcx), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0x2c,0x19] + vscalefps (%rcx), %xmm27, %xmm19 + +// CHECK: vscalefps 291(%rax,%r14,8), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xa2,0x25,0x00,0x2c,0x9c,0xf0,0x23,0x01,0x00,0x00] + vscalefps 291(%rax,%r14,8), %xmm27, %xmm19 + +// CHECK: vscalefps (%rcx){1to4}, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0x2c,0x19] + vscalefps (%rcx){1to4}, %xmm27, %xmm19 + +// CHECK: vscalefps 2032(%rdx), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0x2c,0x5a,0x7f] + vscalefps 2032(%rdx), %xmm27, %xmm19 + +// CHECK: vscalefps 2048(%rdx), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0x2c,0x9a,0x00,0x08,0x00,0x00] + vscalefps 2048(%rdx), %xmm27, %xmm19 + +// CHECK: vscalefps -2048(%rdx), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0x2c,0x5a,0x80] + vscalefps -2048(%rdx), %xmm27, %xmm19 + +// CHECK: vscalefps -2064(%rdx), %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x00,0x2c,0x9a,0xf0,0xf7,0xff,0xff] + vscalefps -2064(%rdx), %xmm27, %xmm19 + +// CHECK: vscalefps 508(%rdx){1to4}, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0x2c,0x5a,0x7f] + vscalefps 508(%rdx){1to4}, %xmm27, %xmm19 + +// CHECK: vscalefps 512(%rdx){1to4}, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0x2c,0x9a,0x00,0x02,0x00,0x00] + vscalefps 512(%rdx){1to4}, %xmm27, %xmm19 + +// CHECK: vscalefps -512(%rdx){1to4}, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0x2c,0x5a,0x80] + vscalefps -512(%rdx){1to4}, %xmm27, %xmm19 + +// CHECK: vscalefps -516(%rdx){1to4}, %xmm27, %xmm19 +// CHECK: encoding: [0x62,0xe2,0x25,0x10,0x2c,0x9a,0xfc,0xfd,0xff,0xff] + vscalefps -516(%rdx){1to4}, %xmm27, %xmm19 + +// CHECK: vscalefps %ymm23, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x22,0x4d,0x20,0x2c,0xcf] + vscalefps %ymm23, %ymm22, %ymm25 + +// CHECK: vscalefps %ymm23, %ymm22, %ymm25 {%k4} +// CHECK: encoding: [0x62,0x22,0x4d,0x24,0x2c,0xcf] + vscalefps %ymm23, %ymm22, %ymm25 {%k4} + +// CHECK: vscalefps %ymm23, %ymm22, %ymm25 {%k4} {z} +// CHECK: encoding: [0x62,0x22,0x4d,0xa4,0x2c,0xcf] + vscalefps %ymm23, %ymm22, %ymm25 {%k4} {z} + +// CHECK: vscalefps (%rcx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0x2c,0x09] + vscalefps (%rcx), %ymm22, %ymm25 + +// CHECK: vscalefps 291(%rax,%r14,8), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x22,0x4d,0x20,0x2c,0x8c,0xf0,0x23,0x01,0x00,0x00] + vscalefps 291(%rax,%r14,8), %ymm22, %ymm25 + +// CHECK: vscalefps (%rcx){1to8}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0x2c,0x09] + vscalefps (%rcx){1to8}, %ymm22, %ymm25 + +// CHECK: vscalefps 4064(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0x2c,0x4a,0x7f] + vscalefps 4064(%rdx), %ymm22, %ymm25 + +// CHECK: vscalefps 4096(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0x2c,0x8a,0x00,0x10,0x00,0x00] + vscalefps 4096(%rdx), %ymm22, %ymm25 + +// CHECK: vscalefps -4096(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0x2c,0x4a,0x80] + vscalefps -4096(%rdx), %ymm22, %ymm25 + +// CHECK: vscalefps -4128(%rdx), %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x20,0x2c,0x8a,0xe0,0xef,0xff,0xff] + vscalefps -4128(%rdx), %ymm22, %ymm25 + +// CHECK: vscalefps 508(%rdx){1to8}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0x2c,0x4a,0x7f] + vscalefps 508(%rdx){1to8}, %ymm22, %ymm25 + +// CHECK: vscalefps 512(%rdx){1to8}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0x2c,0x8a,0x00,0x02,0x00,0x00] + vscalefps 512(%rdx){1to8}, %ymm22, %ymm25 + +// CHECK: vscalefps -512(%rdx){1to8}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0x2c,0x4a,0x80] + vscalefps -512(%rdx){1to8}, %ymm22, %ymm25 + +// CHECK: vscalefps -516(%rdx){1to8}, %ymm22, %ymm25 +// CHECK: encoding: [0x62,0x62,0x4d,0x30,0x2c,0x8a,0xfc,0xfd,0xff,0xff] + vscalefps -516(%rdx){1to8}, %ymm22, %ymm25 diff --git a/test/Object/ARM/nm-mapping-symbol.s b/test/Object/ARM/nm-mapping-symbol.s new file mode 100644 index 0000000000000..485c1cc39d722 --- /dev/null +++ b/test/Object/ARM/nm-mapping-symbol.s @@ -0,0 +1,11 @@ +// RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7-pc-linux +// RUN: llvm-readobj -t %t.o | FileCheck %s +// RUN: llvm-nm %t.o | FileCheck -allow-empty --check-prefix=NM %s + +// Test that nm doesn't print the mapping symbols + +// CHECK: Name: $d.0 +// NM-NOT: $d.0 + + .section .foobar,"",%progbits + .asciz "foo" diff --git a/test/Object/Inputs/invalid-section-index.elf b/test/Object/Inputs/invalid-section-index.elf Binary files differnew file mode 100644 index 0000000000000..a019d8a5479ef --- /dev/null +++ b/test/Object/Inputs/invalid-section-index.elf diff --git a/test/Object/Inputs/invalid-section-size.elf b/test/Object/Inputs/invalid-section-size.elf Binary files differnew file mode 100644 index 0000000000000..c111a4c626226 --- /dev/null +++ b/test/Object/Inputs/invalid-section-size.elf diff --git a/test/Object/Inputs/invalid-sh_entsize.elf b/test/Object/Inputs/invalid-sh_entsize.elf Binary files differnew file mode 100755 index 0000000000000..9ea80731491c1 --- /dev/null +++ b/test/Object/Inputs/invalid-sh_entsize.elf diff --git a/test/Object/Inputs/invalid-strtab-non-null.elf b/test/Object/Inputs/invalid-strtab-non-null.elf Binary files differnew file mode 100644 index 0000000000000..f52c0a1401313 --- /dev/null +++ b/test/Object/Inputs/invalid-strtab-non-null.elf diff --git a/test/Object/Inputs/invalid-strtab-size.elf b/test/Object/Inputs/invalid-strtab-size.elf Binary files differnew file mode 100644 index 0000000000000..fb1974613ab29 --- /dev/null +++ b/test/Object/Inputs/invalid-strtab-size.elf diff --git a/test/Object/Inputs/invalid-strtab-type.elf b/test/Object/Inputs/invalid-strtab-type.elf Binary files differnew file mode 100644 index 0000000000000..2a072ebe51d47 --- /dev/null +++ b/test/Object/Inputs/invalid-strtab-type.elf diff --git a/test/Object/Inputs/stackmap-test.macho-x86-64 b/test/Object/Inputs/stackmap-test.macho-x86-64 Binary files differnew file mode 100644 index 0000000000000..588c5aa6685b9 --- /dev/null +++ b/test/Object/Inputs/stackmap-test.macho-x86-64 diff --git a/test/Object/X86/nm-print-size.s b/test/Object/X86/nm-print-size.s new file mode 100644 index 0000000000000..b833601969c2f --- /dev/null +++ b/test/Object/X86/nm-print-size.s @@ -0,0 +1,12 @@ +// RUN: llvm-mc %s -o %t -filetype=obj -triple=x86_64-pc-linux +// RUN: llvm-nm --print-size %t | FileCheck %s + +// CHECK: 0000000000000000 ffffffffffffffff n a +// CHECK: 0000000000000000 0000000000000000 N b + + .section foo +a: + .size a, 0xffffffffffffffff + + .global b +b: diff --git a/test/Object/dllimport-globalref.ll b/test/Object/dllimport-globalref.ll new file mode 100644 index 0000000000000..dd518bc2266ca --- /dev/null +++ b/test/Object/dllimport-globalref.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as %s -o - | llvm-nm - | FileCheck %s + +; We should technically emit an unmangled reference to f here, +; but no existing linker needs this. + +; XFAIL: * + +target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-pc-windows-msvc" + +; CHECK: U f + +declare dllimport void @f() +@fp = constant void ()* @f diff --git a/test/Object/invalid.test b/test/Object/invalid.test index 73bf62a1ed4ed..1d5a70b3487d1 100644 --- a/test/Object/invalid.test +++ b/test/Object/invalid.test @@ -1,2 +1,46 @@ RUN: not llvm-dwarfdump %p/Inputs/invalid-bad-rel-type.elf 2>&1 | FileCheck %s +RUN: not llvm-objdump -s %p/Inputs/invalid-strtab-type.elf 2>&1 | FileCheck %s +RUN: not llvm-objdump -s %p/Inputs/invalid-strtab-size.elf 2>&1 | FileCheck %s CHECK: Invalid data was encountered while parsing the file + +RUN: not llvm-objdump -s %p/Inputs/invalid-strtab-non-null.elf 2>&1 | FileCheck --check-prefix=NON-NULL %s +NON-NULL: String table must end with a null terminator + +Test the sh_entsize are invalid +RUN: llvm-readobj -s %p/Inputs/invalid-sh_entsize.elf | FileCheck --check-prefix=SECTION %s + +SECTION: Name: .dynsym +SECTION-NEXT: Type: SHT_DYNSYM +SECTION-NEXT: Flags [ +SECTION-NEXT: SHF_ALLOC +SECTION-NEXT: ] +SECTION-NEXT: Address: +SECTION-NEXT: Offset: +SECTION-NEXT: Size: +SECTION-NEXT: Link: +SECTION-NEXT: Info: +SECTION-NEXT: AddressAlignment: +SECTION-NEXT: EntrySize: 32 + +SECTION: Name: .symtab +SECTION-NEXT: Type: SHT_SYMTAB +SECTION-NEXT: Flags [ +SECTION-NEXT: ] +SECTION-NEXT: Address: +SECTION-NEXT: Offset: +SECTION-NEXT: Size: +SECTION-NEXT: Link: +SECTION-NEXT: Info: +SECTION-NEXT: AddressAlignment: +SECTION-NEXT: EntrySize: 32 + +RUN: not llvm-readobj -t %p/Inputs/invalid-sh_entsize.elf 2>&1 | FileCheck --check-prefix=INVALID-SYM-SIZE %s +RUN: not llvm-readobj --dyn-symbols %p/Inputs/invalid-sh_entsize.elf 2>&1 | FileCheck --check-prefix=INVALID-SYM-SIZE %s +INVALID-SYM-SIZE: Invalid symbol size + +RUN: not llvm-readobj -t %p/Inputs/invalid-section-index.elf 2>&1 | FileCheck --check-prefix=INVALID-SECTION-INDEX %s + +INVALID-SECTION-INDEX: Invalid section index + +RUN: not llvm-readobj -s %p/Inputs/invalid-section-size.elf 2>&1 | FileCheck --check-prefix=INVALID-SECTION-SIZE %s +INVALID-SECTION-SIZE: Invalid section header entry size (e_shentsize) in ELF header diff --git a/test/Object/lit.local.cfg b/test/Object/lit.local.cfg index d74d039d684b0..ec8ad451d2da0 100644 --- a/test/Object/lit.local.cfg +++ b/test/Object/lit.local.cfg @@ -1 +1 @@ -config.suffixes = ['.test', '.ll', '.yaml'] +config.suffixes = ['.test', '.ll', '.s', '.yaml'] diff --git a/test/Object/objdump-symbol-table.test b/test/Object/objdump-symbol-table.test index 3d09e1a45f39c..e66faecf4cc64 100644 --- a/test/Object/objdump-symbol-table.test +++ b/test/Object/objdump-symbol-table.test @@ -30,9 +30,9 @@ ELF-i386: 00000000 *UND* 00000000 puts macho-i386: trivial-object-test.macho-i386: file format Mach-O 32-bit i386 macho-i386: SYMBOL TABLE: -macho-i386: 00000000 g F __TEXT,__text 00000000 _main -macho-i386: 00000000 *UND* 00000000 _SomeOtherFunction -macho-i386: 00000000 *UND* 00000000 _puts +macho-i386: 00000000 g F __TEXT,__text _main +macho-i386: 00000000 *UND* _SomeOtherFunction +macho-i386: 00000000 *UND* _puts ELF-shared: shared-object-test.elf-i386: file format ELF-shared: SYMBOL TABLE: diff --git a/test/Object/relocation-executable.test b/test/Object/relocation-executable.test index 1236035d9f683..38ad5968af8d8 100644 --- a/test/Object/relocation-executable.test +++ b/test/Object/relocation-executable.test @@ -1,5 +1,7 @@ RUN: llvm-readobj -r -expand-relocs %p/Inputs/hello-world.elf-x86-64 \ RUN: | FileCheck %s +RUN: llvm-readobj -dyn-relocations -expand-relocs \ +RUN: %p/Inputs/hello-world.elf-x86-64 | FileCheck %s --check-prefix=DYN // CHECK: Relocations [ // CHECK-NEXT: Section (8) .rela.dyn { @@ -24,3 +26,12 @@ RUN: | FileCheck %s // CHECK-NEXT: Addend: 0x0 // CHECK-NEXT: } // CHECK-NEXT: } + +// DYN: Dynamic Relocations { +// DYN-NEXT: Relocation { +// DYN-NEXT: Offset: 0x4018D8 +// DYN-NEXT: Type: R_X86_64_GLOB_DAT (6) +// DYN-NEXT: Symbol: __gmon_start__ +// DYN-NEXT: Addend: 0x0 +// DYN-NEXT: } +// DYN-NEXT: } diff --git a/test/Object/stackmap-dump.test b/test/Object/stackmap-dump.test new file mode 100644 index 0000000000000..71710fb6194db --- /dev/null +++ b/test/Object/stackmap-dump.test @@ -0,0 +1,16 @@ +RUN: llvm-readobj -stackmap %p/Inputs/stackmap-test.macho-x86-64 | FileCheck %s + +CHECK: LLVM StackMap Version: 1 +CHECK-NEXT: Num Functions: 1 +CHECK-NEXT: Function address: 0, stack size: 16 +CHECK-NEXT: Num Constants: 1 +CHECK-NEXT: #1: 10000000000 +CHECK-NEXT: Num Records: 1 +CHECK-NEXT: Record ID: 2, instruction offset: 1 +CHECK-NEXT: 5 locations: +CHECK-NEXT: #1: Register R#5 +CHECK-NEXT: #2: Constant 10 +CHECK-NEXT: #3: ConstantIndex #0 (10000000000) +CHECK-NEXT: #4: Direct R#4 + -8 +CHECK-NEXT: #5: Indirect [R#6 + -16] +CHECK-NEXT: 1 live-outs: [ R#7 (8-bytes) ] diff --git a/test/Transforms/GVN/br-identical.ll b/test/Transforms/GVN/br-identical.ll new file mode 100644 index 0000000000000..dfb7abe9a5dc3 --- /dev/null +++ b/test/Transforms/GVN/br-identical.ll @@ -0,0 +1,38 @@ +; RUN: opt -gvn -S -o - %s | FileCheck %s + +; If a branch has two identical successors, we cannot declare either dead. + +define void @widget(i1 %p) { +entry: + br label %bb2 + +bb2: + %t1 = phi i64 [ 0, %entry ], [ %t5, %bb7 ] + %t2 = add i64 %t1, 1 + %t3 = icmp ult i64 0, %t2 + br i1 %t3, label %bb3, label %bb4 + +bb3: + %t4 = call i64 @f() + br label %bb4 + +bb4: + ; CHECK-NOT: phi {{.*}} undef + %foo = phi i64 [ %t4, %bb3 ], [ 0, %bb2 ] + br i1 %p, label %bb5, label %bb6 + +bb5: + br i1 true, label %bb7, label %bb7 + +bb6: + br i1 true, label %bb7, label %bb7 + +bb7: + %t5 = add i64 %t1, 1 + br i1 %p, label %bb2, label %bb8 + +bb8: + ret void +} + +declare i64 @f() diff --git a/test/Transforms/GVN/pr12979.ll b/test/Transforms/GVN/pr12979.ll index 0198a56513ea9..919c22de02acc 100644 --- a/test/Transforms/GVN/pr12979.ll +++ b/test/Transforms/GVN/pr12979.ll @@ -77,3 +77,17 @@ define i32 @test7(i32 %x, i32 %y) { %foo = add i32 %add1, %add2 ret i32 %foo } + +declare void @mumble(i2, i2) + +define void @test8(i2 %x) { +; CHECK-LABEL: @test8( +; CHECK: %[[ashr:.*]] = ashr i2 %x, 1 +; CHECK-NEXT: call void @mumble(i2 %[[ashr]], i2 %[[ashr]]) +; CHECK-NEXT: ret void + + %ashr0 = ashr exact i2 %x, 1 + %ashr1 = ashr i2 %x, 1 + call void @mumble(i2 %ashr0, i2 %ashr1) + ret void +} diff --git a/test/Transforms/Inline/X86/inline-target-attr.ll b/test/Transforms/Inline/X86/inline-target-attr.ll new file mode 100644 index 0000000000000..c59f4b4594b86 --- /dev/null +++ b/test/Transforms/Inline/X86/inline-target-attr.ll @@ -0,0 +1,35 @@ +; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -S -inline | FileCheck %s +; Check that we only inline when we have compatible target attributes. +; X86 has implemented a target attribute that will verify that the attribute +; sets are compatible. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @foo() #0 { +entry: + %call = call i32 (...) @baz() + ret i32 %call +; CHECK-LABEL: foo +; CHECK: call i32 (...) @baz() +} +declare i32 @baz(...) #0 + +define i32 @bar() #1 { +entry: + %call = call i32 @foo() + ret i32 %call +; CHECK-LABEL: bar +; CHECK: call i32 (...) @baz() +} + +define i32 @qux() #0 { +entry: + %call = call i32 @bar() + ret i32 %call +; CHECK-LABEL: qux +; CHECK: call i32 @bar() +} + +attributes #0 = { "target-cpu"="x86-64" "target-features"="+sse,+sse2" } +attributes #1 = { "target-cpu"="x86-64" "target-features"="+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3" } diff --git a/test/Transforms/Inline/X86/lit.local.cfg b/test/Transforms/Inline/X86/lit.local.cfg new file mode 100644 index 0000000000000..e71f3cc4c41e7 --- /dev/null +++ b/test/Transforms/Inline/X86/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'X86' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/Inline/nonnull.ll b/test/Transforms/Inline/nonnull.ll new file mode 100644 index 0000000000000..4aa0c28bfc722 --- /dev/null +++ b/test/Transforms/Inline/nonnull.ll @@ -0,0 +1,45 @@ +; RUN: opt -S -inline %s | FileCheck %s + +declare void @foo() +declare void @bar() + +define void @callee(i8* %arg) { + %cmp = icmp eq i8* %arg, null + br i1 %cmp, label %expensive, label %done + +; This block is designed to be too expensive to inline. We can only inline +; callee if this block is known to be dead. +expensive: + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + call void @foo() + ret void + +done: + call void @bar() + ret void +} + +; Positive test - arg is known non null +define void @caller(i8* nonnull %arg) { +; CHECK-LABEL: @caller +; CHECK: call void @bar() + call void @callee(i8* nonnull %arg) + ret void +} + +; Negative test - arg is not known to be non null +define void @caller2(i8* %arg) { +; CHECK-LABEL: @caller2 +; CHECK: call void @callee( + call void @callee(i8* %arg) + ret void +} + diff --git a/test/Transforms/InstCombine/pr23809.ll b/test/Transforms/InstCombine/pr23809.ll new file mode 100644 index 0000000000000..06c7ce20ba807 --- /dev/null +++ b/test/Transforms/InstCombine/pr23809.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +; InstCombine should preserve the call to @llvm.assume. +define i32 @icmp(i32 %a, i32 %b) { +; CHECK-LABEL: @icmp( + %sum = add i32 %a, %b + %1 = icmp sge i32 %sum, 0 + call void @llvm.assume(i1 %1) +; CHECK: call void @llvm.assume + ret i32 %sum +} + +define float @fcmp(float %a, float %b) { +; CHECK-LABEL: @fcmp( + %sum = fadd float %a, %b + %1 = fcmp oge float %sum, 0.0 + call void @llvm.assume(i1 %1) +; CHECK: call void @llvm.assume + ret float %sum +} + +declare void @llvm.assume(i1) diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index 8be247228b8ef..fdf1199a66fbf 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -1296,6 +1296,23 @@ entry: ret i32 %v } +define i32 @test78_neg(i1 %flag, i32* %x, i32* %y, i32* %z) { +; The same as @test78 but we can't speculate the load because it can trap +; if under-aligned. +; CHECK-LABEL: @test78_neg( +; CHECK: %p = select i1 %flag, i32* %x, i32* %y +; CHECK-NEXT: %v = load i32, i32* %p, align 16 +; CHECK-NEXT: ret i32 %v +entry: + store i32 0, i32* %x + store i32 0, i32* %y + ; Block forwarding by storing to %z which could alias either %x or %y. + store i32 42, i32* %z + %p = select i1 %flag, i32* %x, i32* %y + %v = load i32, i32* %p, align 16 + ret i32 %v +} + define float @test79(i1 %flag, float* %x, i32* %y, i32* %z) { ; Test that we can speculate the loads around the select even when we can't ; fold the load completely away. diff --git a/test/Transforms/InstCombine/sub.ll b/test/Transforms/InstCombine/sub.ll index c76d8d0e2205d..b1c7b7245cf34 100644 --- a/test/Transforms/InstCombine/sub.ll +++ b/test/Transforms/InstCombine/sub.ll @@ -550,3 +550,25 @@ define i32 @test46(i32 %x, i32 %y) { ; CHECK-NEXT: %sub = and i32 %y, %x.not ; CHECK: ret i32 %sub } + +define i32 @test47(i1 %A, i32 %B, i32 %C, i32 %D) { + %sel0 = select i1 %A, i32 %D, i32 %B + %sel1 = select i1 %A, i32 %C, i32 %B + %sub = sub i32 %sel0, %sel1 + ret i32 %sub +; CHECK-LABEL: @test47( +; CHECK-NEXT: %[[sub:.*]] = sub i32 %D, %C +; CHECK-NEXT: %[[sel:.*]] = select i1 %A, i32 %[[sub]], i32 0 +; CHECK-NEXT: ret i32 %[[sel]] +} + +define i32 @test48(i1 %A, i32 %B, i32 %C, i32 %D) { + %sel0 = select i1 %A, i32 %B, i32 %D + %sel1 = select i1 %A, i32 %B, i32 %C + %sub = sub i32 %sel0, %sel1 + ret i32 %sub +; CHECK-LABEL: @test48( +; CHECK-NEXT: %[[sub:.*]] = sub i32 %D, %C +; CHECK-NEXT: %[[sel:.*]] = select i1 %A, i32 0, i32 %[[sub]] +; CHECK-NEXT: ret i32 %[[sel]] +} diff --git a/test/Transforms/LoopDistribute/basic-with-memchecks.ll b/test/Transforms/LoopDistribute/basic-with-memchecks.ll index 4c1c1b822964a..fde06d33c5a5c 100644 --- a/test/Transforms/LoopDistribute/basic-with-memchecks.ll +++ b/test/Transforms/LoopDistribute/basic-with-memchecks.ll @@ -35,7 +35,7 @@ entry: ; We have two compares for each array overlap check which is a total of 10 ; compares. ; -; CHECK: for.body.ldist.memcheck: +; CHECK: for.body.lver.memcheck: ; CHECK: = icmp ; CHECK: = icmp @@ -52,14 +52,14 @@ entry: ; CHECK: = icmp ; CHECK-NOT: = icmp -; CHECK: br i1 %memcheck.conflict, label %for.body.ph.ldist.nondist, label %for.body.ph.ldist1 +; CHECK: br i1 %memcheck.conflict, label %for.body.ph.lver.orig, label %for.body.ph.ldist1 ; The non-distributed loop that the memchecks fall back on. -; CHECK: for.body.ph.ldist.nondist: -; CHECK: br label %for.body.ldist.nondist -; CHECK: for.body.ldist.nondist: -; CHECK: br i1 %exitcond.ldist.nondist, label %for.end, label %for.body.ldist.nondist +; CHECK: for.body.ph.lver.orig: +; CHECK: br label %for.body.lver.orig +; CHECK: for.body.lver.orig: +; CHECK: br i1 %exitcond.lver.orig, label %for.end, label %for.body.lver.orig ; Verify the two distributed loops. diff --git a/test/Transforms/LoopDistribute/outside-use.ll b/test/Transforms/LoopDistribute/outside-use.ll index 546050d5b0463..7a3fe1be0670d 100644 --- a/test/Transforms/LoopDistribute/outside-use.ll +++ b/test/Transforms/LoopDistribute/outside-use.ll @@ -37,7 +37,7 @@ entry: ; CHECK: for.body: ; CHECK: %sum_add = add nuw nsw i32 %sum, %loadC ; CHECK: for.end: -; CHECK: %sum_add.ldist = phi i32 [ %sum_add, %for.body ], [ %sum_add.ldist.nondist, %for.body.ldist.nondist ] +; CHECK: %sum_add.lver = phi i32 [ %sum_add, %for.body ], [ %sum_add.lver.orig, %for.body.lver.orig ] for.body: ; preds = %for.body, %entry %ind = phi i64 [ 0, %entry ], [ %add, %for.body ] diff --git a/test/Transforms/LoopIdiom/basic.ll b/test/Transforms/LoopIdiom/basic.ll index a8a2c8efa3864..c633ae95d16fc 100644 --- a/test/Transforms/LoopIdiom/basic.ll +++ b/test/Transforms/LoopIdiom/basic.ll @@ -69,7 +69,7 @@ for.end: ; preds = %for.body, %entry ret void ; CHECK-LABEL: @test2( ; CHECK: br i1 %cmp10, -; CHECK: %0 = mul i64 %Size, 4 +; CHECK: %0 = shl i64 %Size, 2 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %0, i32 4, i1 false) ; CHECK-NOT: store } diff --git a/test/Transforms/LoopReroll/nonconst_lb.ll b/test/Transforms/LoopReroll/nonconst_lb.ll index 5effa42d07c4f..96090e8dc0be0 100644 --- a/test/Transforms/LoopReroll/nonconst_lb.ll +++ b/test/Transforms/LoopReroll/nonconst_lb.ll @@ -52,7 +52,7 @@ for.end: ; preds = %for.body, %entry ; CHECK: %0 = add i32 %n, -1 ; CHECK: %1 = sub i32 %0, %m ; CHECK: %2 = lshr i32 %1, 2 -; CHECK: %3 = mul i32 %2, 4 +; CHECK: %3 = shl i32 %2, 2 ; CHECK: %4 = add i32 %m, %3 ; CHECK: %5 = add i32 %4, 3 ; CHECK: br label %for.body @@ -132,7 +132,7 @@ for.end: ; preds = %for.body, %entry ; CHECK: %0 = add i32 %n, -1 ; CHECK: %1 = sub i32 %0, %rem ; CHECK: %2 = lshr i32 %1, 2 -; CHECK: %3 = mul i32 %2, 4 +; CHECK: %3 = shl i32 %2, 2 ; CHECK: %4 = add i32 %rem, %3 ; CHECK: %5 = add i32 %4, 3 ; CHECK: br label %for.body diff --git a/test/Transforms/LoopSimplify/single-backedge.ll b/test/Transforms/LoopSimplify/single-backedge.ll index aedd6f23091c9..92fbdca8a6d22 100644 --- a/test/Transforms/LoopSimplify/single-backedge.ll +++ b/test/Transforms/LoopSimplify/single-backedge.ll @@ -5,19 +5,35 @@ ; RUN: opt < %s -indvars -S | FileCheck %s ; CHECK: Loop.backedge: ; CHECK-NOT: br -; CHECK: br label %Loop +; CHECK: br label %Loop, !dbg [[BACKEDGE_LOC:![0-9]+]] + +; CHECK: [[BACKEDGE_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}}) define i32 @test(i1 %C) { ; <label>:0 - br label %Loop -Loop: ; preds = %BE2, %BE1, %0 - %IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ] ; <i32> [#uses=2] - store i32 %IV, i32* null - %IV2 = add i32 %IV, 2 ; <i32> [#uses=2] - br i1 %C, label %BE1, label %BE2 -BE1: ; preds = %Loop - br label %Loop -BE2: ; preds = %Loop - br label %Loop + br label %Loop, !dbg !6 +Loop: ; preds = %BE2, %BE1, %0 + %IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ] ; <i32> [#uses=2] + store i32 %IV, i32* null, !dbg !7 + %IV2 = add i32 %IV, 2, !dbg !8 ; <i32> [#uses=2] + br i1 %C, label %BE1, label %BE2, !dbg !9 +BE1: ; preds = %Loop + br label %Loop, !dbg !10 +BE2: ; preds = %n br label %Loop + br label %Loop, !dbg !11 } +!llvm.module.flags = !{!0, !1} +!0 = !{i32 2, !"Dwarf Version", i32 4} +!1 = !{i32 2, !"Debug Info Version", i32 3} + +!2 = !{} +!3 = !DISubroutineType(types: !2) +!4 = !DIFile(filename: "atomic.cpp", directory: "/tmp") +!5 = !DISubprogram(name: "test", scope: !4, file: !4, line: 99, type: !3, isLocal: false, isDefinition: true, scopeLine: 100, flags: DIFlagPrototyped, isOptimized: false, variables: !2) +!6 = !DILocation(line: 100, column: 1, scope: !5) +!7 = !DILocation(line: 101, column: 1, scope: !5) +!8 = !DILocation(line: 102, column: 1, scope: !5) +!9 = !DILocation(line: 103, column: 1, scope: !5) +!10 = !DILocation(line: 104, column: 1, scope: !5) +!11 = !DILocation(line: 105, column: 1, scope: !5) diff --git a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll index cc8226e125892..5923a42fa6506 100644 --- a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll +++ b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll @@ -12,8 +12,8 @@ target datalayout = "n8:16:32:64" ; CHECK-LABEL: @test( ; multiplies are hoisted out of the loop ; CHECK: while.body.lr.ph: -; CHECK: mul i64 -; CHECK: mul i64 +; CHECK: shl i64 +; CHECK: shl i64 ; GEPs are ugly ; CHECK: while.body: ; CHECK: phi diff --git a/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll b/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll index 7925bf01020e8..24be0dc42d6d4 100644 --- a/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll +++ b/test/Transforms/LoopStrengthReduce/X86/ivchain-stress-X86.ll @@ -23,7 +23,7 @@ ; X32: add ; X32: add ; X32: add -; X32: add +; X32: leal ; X32: %for.body.3 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp { entry: diff --git a/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll b/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll index 092b274bfc032..466566ed8a0d5 100644 --- a/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll +++ b/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll @@ -6,7 +6,7 @@ ; CHECK: [[r1:%[a-z0-9]+]] = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast ; CHECK: [[r2:%[a-z0-9]+]] = lshr i64 [[r1]], 1 -; CHECK: [[r3:%[a-z0-9]+]] = mul i64 [[r2]], 2 +; CHECK: [[r3:%[a-z0-9]+]] = shl i64 [[r2]], 1 ; CHECK: br label %for.body ; CHECK: for.body: ; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ [[r3]], %for.body.lr.ph ] diff --git a/test/Transforms/LoopStrengthReduce/shl.ll b/test/Transforms/LoopStrengthReduce/shl.ll new file mode 100644 index 0000000000000..bb9cb39f437cd --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/shl.ll @@ -0,0 +1,38 @@ +; RUN: opt < %s -loop-reduce -gvn -S | FileCheck %s + +target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" + +define void @_Z3fooPfll(float* nocapture readonly %input, i64 %n, i64 %s) { +; CHECK-LABEL: @_Z3fooPfll( +entry: + %mul = shl nsw i64 %s, 2 +; CHECK: %mul = shl i64 %s, 2 + tail call void @_Z3bazl(i64 %mul) #2 +; CHECK-NEXT: call void @_Z3bazl(i64 %mul) + %cmp.5 = icmp sgt i64 %n, 0 + br i1 %cmp.5, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + ret void + +for.body: ; preds = %for.body.preheader, %for.body + %i.06 = phi i64 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds float, float* %input, i64 %i.06 +; LoopStrengthReduce should reuse %mul as the stride. +; CHECK: getelementptr i1, i1* {{[^,]+}}, i64 %mul + %0 = load float, float* %arrayidx, align 4 + tail call void @_Z3barf(float %0) #2 + %add = add nsw i64 %i.06, %s + %cmp = icmp slt i64 %add, %n + br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit +} + +declare void @_Z3bazl(i64) + +declare void @_Z3barf(float) diff --git a/test/Transforms/LoopUnroll/X86/mmx.ll b/test/Transforms/LoopUnroll/X86/mmx.ll new file mode 100644 index 0000000000000..2c4aa086e83cc --- /dev/null +++ b/test/Transforms/LoopUnroll/X86/mmx.ll @@ -0,0 +1,24 @@ +; RUN: opt < %s -S -loop-unroll | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define x86_mmx @f() #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %phi = phi i32 [ 1, %entry ], [ %add, %for.body ] + %add = add i32 %phi, 1 + %cmp = icmp eq i32 %phi, 0 + br i1 %cmp, label %exit, label %for.body + +exit: ; preds = %for.body + %ret = phi x86_mmx [ undef, %for.body ] + ; CHECK: %[[ret_unr:.*]] = phi x86_mmx [ undef, + ; CHECK: %[[ret_ph:.*]] = phi x86_mmx [ undef, + ; CHECK: %[[ret:.*]] = phi x86_mmx [ %[[ret_unr]], {{.*}} ], [ %[[ret_ph]] + ; CHECK: ret x86_mmx %[[ret]] + ret x86_mmx %ret +} + +attributes #0 = { "target-cpu"="x86-64" } diff --git a/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll b/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll new file mode 100644 index 0000000000000..d536da1e8b600 --- /dev/null +++ b/test/Transforms/LoopUnswitch/2015-06-17-Metadata.ll @@ -0,0 +1,77 @@ +;RUN: opt -loop-unswitch -simplifycfg -S < %s | FileCheck %s + +define i32 @foo(i32 %a, i32 %b) { +;CHECK-LABEL: foo +entry: + br label %for.body.lr.ph + +for.body.lr.ph: ; preds = %entry + %cmp0 = icmp sgt i32 %b, 0 + br i1 %cmp0, label %for.body, label %for.cond.cleanup + +for.body: ; preds = %for.inc, %for.body.lr.ph + %inc.i = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ] + %mul.i = phi i32 [ 3, %for.body.lr.ph ], [ %mul.p, %for.inc ] + %add.i = phi i32 [ %a, %for.body.lr.ph ], [ %add.p, %for.inc ] + %cmp1 = icmp eq i32 %a, 12345 + br i1 %cmp1, label %if.then, label %if.else, !prof !0 +; CHECK: %cmp1 = icmp eq i32 %a, 12345 +; CHECK-NEXT: br i1 %cmp1, label %if.then.us, label %if.else, !prof !0 +if.then: ; preds = %for.body +; CHECK: if.then.us: +; CHECK: add nsw i32 %{{.*}}, 123 +; CHECK: %exitcond.us = icmp eq i32 %inc.us, %b +; CHECK: br i1 %exitcond.us, label %for.cond.cleanup, label %if.then.us + %add = add nsw i32 %add.i, 123 + br label %for.inc + +if.else: ; preds = %for.body + %mul = mul nsw i32 %mul.i, %b + br label %for.inc +; CHECK: if.else: +; CHECK: %mul = mul nsw i32 %mul.i, %b +; CHECK: %inc = add nuw nsw i32 %inc.i, 1 +; CHECK: %exitcond = icmp eq i32 %inc, %b +; CHECK: br i1 %exitcond, label %for.cond.cleanup, label %if.else +for.inc: ; preds = %if.then, %if.else + %mul.p = phi i32 [ %b, %if.then ], [ %mul, %if.else ] + %add.p = phi i32 [ %add, %if.then ], [ %a, %if.else ] + %inc = add nuw nsw i32 %inc.i, 1 + %exitcond = icmp eq i32 %inc, %b + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: ; preds = %for.inc, %for.body.lr.ph + %t2 = phi i32 [ %b, %for.body.lr.ph ], [ %mul.p, %for.inc ] + %t1 = phi i32 [ %a, %for.body.lr.ph ], [ %add.p, %for.inc ] + %add3 = add nsw i32 %t2, %t1 + ret i32 %add3 +} + +define void @foo_swapped(i32 %a, i32 %b) { +;CHECK-LABEL: foo_swapped +entry: + br label %for.body +;CHECK: entry: +;CHECK-NEXT: %cmp1 = icmp eq i32 1, 2 +;CHECK-NEXT: br i1 %cmp1, label %for.body, label %for.cond.cleanup.split, !prof !1 +;CHECK: for.body: +for.body: ; preds = %for.inc, %entry + %inc.i = phi i32 [ 0, %entry ], [ %inc, %if.then ] + %add.i = phi i32 [ 100, %entry ], [ %add, %if.then ] + %inc = add nuw nsw i32 %inc.i, 1 + %cmp1 = icmp eq i32 1, 2 + br i1 %cmp1, label %if.then, label %for.cond.cleanup, !prof !0 + +if.then: ; preds = %for.body + %add = add nsw i32 %a, %add.i + + %exitcond = icmp eq i32 %inc, %b + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: ; preds = %for.inc, %for.body.lr.ph, %for.body + ret void +} +!0 = !{!"branch_weights", i32 64, i32 4} + +;CHECK: !0 = !{!"branch_weights", i32 64, i32 4} +;CHECK: !1 = !{!"branch_weights", i32 4, i32 64} diff --git a/test/Transforms/LoopVectorize/X86/ptr-indvar-crash.ll b/test/Transforms/LoopVectorize/X86/ptr-indvar-crash.ll new file mode 100644 index 0000000000000..13ceaef4dbbc6 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/ptr-indvar-crash.ll @@ -0,0 +1,20 @@ +; RUN: opt -loop-vectorize -S %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @f(i128 %p1) { +entry: + br label %while.body + +while.body: + %p.05 = phi i8* [ %add.ptr, %while.body ], [ null, %entry ] + %p1.addr.04 = phi i128 [ %sub, %while.body ], [ %p1, %entry ] + %add.ptr = getelementptr inbounds i8, i8* %p.05, i32 2 + %sub = add nsw i128 %p1.addr.04, -2 + %tobool = icmp eq i128 %sub, 0 + br i1 %tobool, label %while.end, label %while.body + +while.end: + ret void +} diff --git a/test/Transforms/LoopVectorize/optsize.ll b/test/Transforms/LoopVectorize/optsize.ll new file mode 100644 index 0000000000000..e183fda099a25 --- /dev/null +++ b/test/Transforms/LoopVectorize/optsize.ll @@ -0,0 +1,34 @@ +; This test verifies that the loop vectorizer will NOT produce a tail +; loop with Optimize for size attibute. +; REQUIRES: asserts +; RUN: opt < %s -loop-vectorize -Os -debug -debug-only=loop-vectorize -S 2>&1 | FileCheck %s + +;CHECK-NOT: <2 x i8> +;CHECK-NOT: <4 x i8> +;CHECK: Aborting. A tail loop is required in Os. + +target datalayout = "E-m:e-p:32:32-i64:32-f64:32:64-a:0:32-n32-S128" + +@tab = common global [32 x i8] zeroinitializer, align 1 + +; Function Attrs: nounwind optsize +define i32 @foo() #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds [32 x i8], [32 x i8]* @tab, i32 0, i32 %i.08 + %0 = load i8, i8* %arrayidx, align 1 + %cmp1 = icmp eq i8 %0, 0 + %. = select i1 %cmp1, i8 2, i8 1 + store i8 %., i8* %arrayidx, align 1 + %inc = add nsw i32 %i.08, 1 + %exitcond = icmp eq i32 %i.08, 202 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 0 +} + +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/Transforms/LoopVectorize/runtime-check.ll b/test/Transforms/LoopVectorize/runtime-check.ll index b1c5d402c4589..1f07d3f69594b 100644 --- a/test/Transforms/LoopVectorize/runtime-check.ll +++ b/test/Transforms/LoopVectorize/runtime-check.ll @@ -9,30 +9,31 @@ target triple = "x86_64-apple-macosx10.9.0" ; a[i] = b[i] * 3; ; } +;CHECK-LABEL: define i32 @foo ;CHECK: for.body.preheader: -;CHECK: br i1 %cmp.zero, label %middle.block, label %vector.memcheck +;CHECK: br i1 %cmp.zero, label %middle.block, label %vector.memcheck, !dbg [[BODY_LOC:![0-9]+]] ;CHECK: vector.memcheck: -;CHECK: br i1 %memcheck.conflict, label %middle.block, label %vector.ph +;CHECK: br i1 %memcheck.conflict, label %middle.block, label %vector.ph, !dbg [[BODY_LOC]] ;CHECK: load <4 x float> define i32 @foo(float* nocapture %a, float* nocapture %b, i32 %n) nounwind uwtable ssp { entry: - %cmp6 = icmp sgt i32 %n, 0 - br i1 %cmp6, label %for.body, label %for.end + %cmp6 = icmp sgt i32 %n, 0, !dbg !6 + br i1 %cmp6, label %for.body, label %for.end, !dbg !6 for.body: ; preds = %entry, %for.body - %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv - %0 = load float, float* %arrayidx, align 4 - %mul = fmul float %0, 3.000000e+00 - %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx2, align 4 - %indvars.iv.next = add i64 %indvars.iv, 1 - %lftr.wideiv = trunc i64 %indvars.iv.next to i32 - %exitcond = icmp eq i32 %lftr.wideiv, %n - br i1 %exitcond, label %for.end, label %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ], !dbg !7 + %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv, !dbg !7 + %0 = load float, float* %arrayidx, align 4, !dbg !7 + %mul = fmul float %0, 3.000000e+00, !dbg !7 + %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv, !dbg !7 + store float %mul, float* %arrayidx2, align 4, !dbg !7 + %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !7 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !7 + %exitcond = icmp eq i32 %lftr.wideiv, %n, !dbg !7 + br i1 %exitcond, label %for.end, label %for.body, !dbg !7 for.end: ; preds = %for.body, %entry - ret i32 undef + ret i32 undef, !dbg !8 } ; Make sure that we try to vectorize loops with a runtime check if the @@ -62,3 +63,17 @@ for.body: loopexit: ret void } + +; CHECK: [[BODY_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}}) + +!llvm.module.flags = !{!0, !1} +!0 = !{i32 2, !"Dwarf Version", i32 4} +!1 = !{i32 2, !"Debug Info Version", i32 3} + +!2 = !{} +!3 = !DISubroutineType(types: !2) +!4 = !DIFile(filename: "test.cpp", directory: "/tmp") +!5 = !DISubprogram(name: "foo", scope: !4, file: !4, line: 99, type: !3, isLocal: false, isDefinition: true, scopeLine: 100, flags: DIFlagPrototyped, isOptimized: false, variables: !2) +!6 = !DILocation(line: 100, column: 1, scope: !5) +!7 = !DILocation(line: 101, column: 1, scope: !5) +!8 = !DILocation(line: 102, column: 1, scope: !5) diff --git a/test/Transforms/LowerBitSets/nonglobal.ll b/test/Transforms/LowerBitSets/nonglobal.ll new file mode 100644 index 0000000000000..7591e31e3524c --- /dev/null +++ b/test/Transforms/LowerBitSets/nonglobal.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -lowerbitsets < %s | FileCheck %s + +target datalayout = "e-p:32:32" + +; CHECK-NOT: @b = alias +@a = constant i32 1 +@b = constant [2 x i32] [i32 2, i32 3] + +!0 = !{!"bitset1", i32* @a, i32 0} +!1 = !{!"bitset1", i32* bitcast ([2 x i32]* @b to i32*), i32 0} + +!llvm.bitsets = !{ !0, !1 } + +declare i1 @llvm.bitset.test(i8* %ptr, metadata %bitset) nounwind readnone + +define i1 @foo(i8* %p) { + %x = call i1 @llvm.bitset.test(i8* %p, metadata !"bitset1") + ret i1 %x +} diff --git a/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll b/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll index d08c6f60c041a..92fbd20d29827 100644 --- a/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll +++ b/test/Transforms/NaryReassociate/NVPTX/nary-gep.ll @@ -61,6 +61,40 @@ define void @reassociate_gep_nsw(float* %a, i32 %i, i32 %j) { ret void } +; assume(j >= 0); +; foo(&a[zext(j)]); +; assume(i + j >= 0); +; foo(&a[zext(i + j)]); +; => +; t1 = &a[zext(j)]; +; foo(t1); +; t2 = t1 + sext(i); +; foo(t2); +define void @reassociate_gep_assume(float* %a, i32 %i, i32 %j) { +; CHECK-LABEL: @reassociate_gep_assume( + ; assume(j >= 0) + %cmp = icmp sgt i32 %j, -1 + call void @llvm.assume(i1 %cmp) + %1 = add i32 %i, %j + %cmp2 = icmp sgt i32 %1, -1 + call void @llvm.assume(i1 %cmp2) + + %idxprom.j = zext i32 %j to i64 + %2 = getelementptr float, float* %a, i64 %idxprom.j +; CHECK: [[t1:[^ ]+]] = getelementptr float, float* %a, i64 %idxprom.j + call void @foo(float* %2) +; CHECK: call void @foo(float* [[t1]]) + + %idxprom.1 = zext i32 %1 to i64 + %3 = getelementptr float, float* %a, i64 %idxprom.1 +; CHECK: [[sexti:[^ ]+]] = sext i32 %i to i64 +; CHECK: [[t2:[^ ]+]] = getelementptr float, float* [[t1]], i64 [[sexti]] + call void @foo(float* %3) +; CHECK: call void @foo(float* [[t2]]) + + ret void +} + ; Do not split the second GEP because sext(i + j) != sext(i) + sext(j). define void @reassociate_gep_no_nsw(float* %a, i32 %i, i32 %j) { ; CHECK-LABEL: @reassociate_gep_no_nsw( @@ -88,3 +122,5 @@ define void @reassociate_gep_128(float* %a, i128 %i, i128 %j) { ; CHECK: call void @foo(float* [[t2]]) ret void } + +declare void @llvm.assume(i1) diff --git a/test/Transforms/PruneEH/pr23971.ll b/test/Transforms/PruneEH/pr23971.ll new file mode 100644 index 0000000000000..8a8a591fff0dd --- /dev/null +++ b/test/Transforms/PruneEH/pr23971.ll @@ -0,0 +1,21 @@ +; RUN: opt -S -prune-eh < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @f() #0 { +entry: + call void asm sideeffect "ret\0A\09", "~{dirflag},~{fpsr},~{flags}"() + unreachable +} + +define i32 @g() { +entry: + call void @f() + ret i32 42 +} + +; CHECK-LABEL: define i32 @g() +; CHECK: ret i32 42 + +attributes #0 = { naked noinline } diff --git a/test/Transforms/Reassociate/basictest.ll b/test/Transforms/Reassociate/basictest.ll index caaf7726514de..c557017b4c6be 100644 --- a/test/Transforms/Reassociate/basictest.ll +++ b/test/Transforms/Reassociate/basictest.ll @@ -169,7 +169,11 @@ define i32 @test11(i32 %W) { ; CHECK-NEXT: ret i32 } +declare void @mumble(i32) + define i32 @test12(i32 %X) { + %X.neg = sub nsw nuw i32 0, %X + call void @mumble(i32 %X.neg) %A = sub i32 1, %X %B = sub i32 2, %X %C = sub i32 3, %X @@ -177,8 +181,8 @@ define i32 @test12(i32 %X) { %Z = add i32 %Y, %C ret i32 %Z ; CHECK-LABEL: @test12 -; CHECK-NEXT: mul i32 %X, -3 -; CHECK-NEXT: add i32{{.*}}, 6 +; CHECK: %[[mul:.*]] = mul i32 %X, -3 +; CHECK-NEXT: add i32 %[[mul]], 6 ; CHECK-NEXT: ret i32 } diff --git a/test/Transforms/Reassociate/wrap-flags.ll b/test/Transforms/Reassociate/wrap-flags.ll index e3304b6a7bb24..f56719d32c2d4 100644 --- a/test/Transforms/Reassociate/wrap-flags.ll +++ b/test/Transforms/Reassociate/wrap-flags.ll @@ -32,3 +32,14 @@ entry: %mul2 = add i32 %mul, 1 ret i32 %mul2 } + +; CHECK-LABEL: @pr23926( +; CHECK: %[[X1_neg:.*]] = sub i2 0, %X1 +; CHECK-NEXT: %[[sub_one:.*]] = add i2 %[[X1_neg]], -1 +; CHECK-NEXT: %[[add:.*]] = add i2 %[[sub_one]], %X2 +; CHECK-NEXT: ret i2 %[[add]] +define i2 @pr23926(i2 %X1, i2 %X2) { + %add = add nuw i2 %X1, 1 + %sub = sub nuw nsw i2 %X2, %add + ret i2 %sub +} diff --git a/test/Transforms/RewriteStatepointsForGC/live-vector.ll b/test/Transforms/RewriteStatepointsForGC/live-vector.ll index 0a4456a68353a..26ad73737adc6 100644 --- a/test/Transforms/RewriteStatepointsForGC/live-vector.ll +++ b/test/Transforms/RewriteStatepointsForGC/live-vector.ll @@ -105,8 +105,6 @@ define <2 x i64 addrspace(1)*> @test5(i64 addrspace(1)* %p) ; CHECK-NEXT: bitcast ; CHECK-NEXT: gc.relocate ; CHECK-NEXT: bitcast -; CHECK-NEXT: gc.relocate -; CHECK-NEXT: bitcast ; CHECK-NEXT: insertelement ; CHECK-NEXT: insertelement ; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %7 @@ -116,6 +114,48 @@ entry: ret <2 x i64 addrspace(1)*> %vec } + +; A base vector from a load +define <2 x i64 addrspace(1)*> @test6(i1 %cnd, <2 x i64 addrspace(1)*>* %ptr) + gc "statepoint-example" { +; CHECK-LABEL: test6 +; CHECK-LABEL: merge: +; CHECK-NEXT: = phi +; CHECK-NEXT: = phi +; CHECK-NEXT: extractelement +; CHECK-NEXT: extractelement +; CHECK-NEXT: extractelement +; CHECK-NEXT: extractelement +; CHECK-NEXT: gc.statepoint +; CHECK-NEXT: gc.relocate +; CHECK-NEXT: bitcast +; CHECK-NEXT: gc.relocate +; CHECK-NEXT: bitcast +; CHECK-NEXT: gc.relocate +; CHECK-NEXT: bitcast +; CHECK-NEXT: gc.relocate +; CHECK-NEXT: bitcast +; CHECK-NEXT: insertelement +; CHECK-NEXT: insertelement +; CHECK-NEXT: insertelement +; CHECK-NEXT: insertelement +; CHECK-NEXT: ret <2 x i64 addrspace(1)*> +entry: + br i1 %cnd, label %taken, label %untaken +taken: + %obja = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr + br label %merge +untaken: + %objb = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr + br label %merge + +merge: + %obj = phi <2 x i64 addrspace(1)*> [%obja, %taken], [%objb, %untaken] + %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0) + ret <2 x i64 addrspace(1)*> %obj +} + + declare void @do_safepoint() declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) diff --git a/test/Transforms/SCCP/crash.ll b/test/Transforms/SCCP/crash.ll index 88528902d7210..3ec1fd21745e3 100644 --- a/test/Transforms/SCCP/crash.ll +++ b/test/Transforms/SCCP/crash.ll @@ -27,3 +27,8 @@ define i32 @test2([4 x i32] %A) { %B = extractvalue [4 x i32] %A, 1 ret i32 %B } + +define x86_mmx @test3() { + %load = load x86_mmx, x86_mmx* null + ret x86_mmx %load +} diff --git a/test/Transforms/SafeStack/no-attr.ll b/test/Transforms/SafeStack/no-attr.ll index ca3c21ab01bb5..d9bcefd3c8492 100644 --- a/test/Transforms/SafeStack/no-attr.ll +++ b/test/Transforms/SafeStack/no-attr.ll @@ -6,6 +6,8 @@ ; no safestack attribute ; Requires no protector. +; CHECK-NOT: __safestack_unsafe_stack_ptr + ; CHECK: @foo define void @foo(i8* %a) nounwind uwtable { entry: diff --git a/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll b/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll new file mode 100644 index 0000000000000..f587a93bf1ed0 --- /dev/null +++ b/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll @@ -0,0 +1,20 @@ +; RUN: opt < %s -slsr -S | FileCheck %s + +target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" +target triple = "amdgcn--" + +%struct.Matrix4x4 = type { [4 x [4 x float]] } + +; Function Attrs: nounwind +define fastcc void @Accelerator_Intersect(%struct.Matrix4x4 addrspace(1)* nocapture readonly %leafTransformations) #0 { +; CHECK-LABEL: @Accelerator_Intersect( +entry: + %tmp = sext i32 undef to i64 + %arrayidx114 = getelementptr inbounds %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp + %tmp1 = getelementptr %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp, i32 0, i64 0, i64 0 +; CHECK: %tmp1 = getelementptr %struct.Matrix4x4, %struct.Matrix4x4 addrspace(1)* %leafTransformations, i64 %tmp, i32 0, i64 0, i64 0 + %tmp2 = load <4 x float>, <4 x float> addrspace(1)* undef, align 4 + ret void +} + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-cpu"="tahiti" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/tools/gold/slp-vectorize.ll b/test/tools/gold/slp-vectorize.ll index a75f0b38cc1fd..30950b2d2de87 100644 --- a/test/tools/gold/slp-vectorize.ll +++ b/test/tools/gold/slp-vectorize.ll @@ -1,6 +1,6 @@ ; RUN: llvm-as %s -o %t.o -; RUN: %gold -plugin %llvmshlibdir/LLVMgold.so \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold.so \ ; RUN: --plugin-opt=save-temps \ ; RUN: -shared %t.o -o %t2.o ; RUN: llvm-dis %t2.o.opt.bc -o - | FileCheck %s @@ -8,7 +8,7 @@ ; test that the vectorizer is run. ; CHECK: fadd <4 x float> -target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" define void @f(float* nocapture %x) { %tmp = load float, float* %x, align 4 diff --git a/test/tools/llvm-cxxdump/X86/lit.local.cfg b/test/tools/llvm-cxxdump/X86/lit.local.cfg new file mode 100644 index 0000000000000..c8625f4d9d248 --- /dev/null +++ b/test/tools/llvm-cxxdump/X86/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'X86' in config.root.targets: + config.unsupported = True diff --git a/test/tools/llvm-cxxdump/X86/sym-size.s b/test/tools/llvm-cxxdump/X86/sym-size.s new file mode 100644 index 0000000000000..c2527523385c3 --- /dev/null +++ b/test/tools/llvm-cxxdump/X86/sym-size.s @@ -0,0 +1,47 @@ +// RUN: llvm-mc %s -o %t -filetype=obj -triple=x86_64-pc-win32 +// RUN: llvm-cxxdump %t | FileCheck %s + +// CHECK: ??_8B@@7B@[0]: 8 +// CHECK-NEXT: ??_8B@@7B@[4]: 9 +// CHECK-NEXT: ??_8C@@7B@[0]: 10 +// CHECK-NEXT: ??_8C@@7B@[4]: 11 +// CHECK-NEXT: ??_8D@@7B0@@[0]: 0 +// CHECK-NEXT: ??_8D@@7B0@@[4]: 1 +// CHECK-NEXT: ??_8D@@7B0@@[8]: 2 +// CHECK-NEXT: ??_8D@@7B0@@[12]: 3 +// CHECK-NEXT: ??_8D@@7BB@@@[0]: 4 +// CHECK-NEXT: ??_8D@@7BB@@@[4]: 5 +// CHECK-NEXT: ??_8D@@7BC@@@[0]: 6 +// CHECK-NEXT: ??_8D@@7BC@@@[4]: 7 +// CHECK-NEXT: ??_8XYZ[0]: 10 +// CHECK-NEXT: ??_8XYZ[4]: 11 + + .section .rdata,"dr" + .globl "??_8D@@7B0@@" +"??_8D@@7B0@@": + .long 0 + .long 1 + .long 2 + .long 3 + + .globl "??_8D@@7BB@@@" +"??_8D@@7BB@@@": + .long 4 + .long 5 + + .globl "??_8D@@7BC@@@" +"??_8D@@7BC@@@": + .long 6 + .long 7 + + .globl "??_8B@@7B@" +"??_8B@@7B@": + .long 8 + .long 9 + + .globl "??_8C@@7B@" +"??_8C@@7B@": + .long 10 + .long 11 + +"??_8XYZ" = "??_8C@@7B@" diff --git a/test/tools/llvm-objdump/X86/macho-symbol-table.test b/test/tools/llvm-objdump/X86/macho-symbol-table.test index 3fe5aea6c3775..826d78af68b1c 100644 --- a/test/tools/llvm-objdump/X86/macho-symbol-table.test +++ b/test/tools/llvm-objdump/X86/macho-symbol-table.test @@ -1,8 +1,8 @@ RUN: llvm-objdump -macho -t %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s CHECK: SYMBOL TABLE: -CHECK: 000000000000003b l F __TEXT,__cstring 00000000 L_.str -CHECK: 0000000000000068 l F __TEXT,__eh_frame 00000000 EH_frame0 -CHECK: 0000000000000000 g F __TEXT,__text 00000000 _main -CHECK: 0000000000000080 g F __TEXT,__eh_frame 00000000 _main.eh -CHECK: 0000000000000000 *UND* 00000000 _printf +CHECK: 000000000000003b l F __TEXT,__cstring L_.str +CHECK: 0000000000000068 l F __TEXT,__eh_frame EH_frame0 +CHECK: 0000000000000000 g F __TEXT,__text _main +CHECK: 0000000000000080 g F __TEXT,__eh_frame _main.eh +CHECK: 0000000000000000 *UND* _printf diff --git a/test/tools/llvm-symbolizer/Inputs/fat.c b/test/tools/llvm-symbolizer/Inputs/fat.c new file mode 100644 index 0000000000000..0331c09fe5f9a --- /dev/null +++ b/test/tools/llvm-symbolizer/Inputs/fat.c @@ -0,0 +1,15 @@ +/* Compile with: + clang -arch armv7 -arch armv7m -arch armv7em -arch x86_64 -arch x86_64h -c +*/ + +#ifdef __x86_64h__ +void x86_64h_function() {} +#elif defined(__x86_64__) +void x86_64_function() {} +#elif defined(__ARM_ARCH_7EM__) +void armv7em_function() {} +#elif defined(__ARM_ARCH_7M__) +void armv7m_function() {} +#elif defined(__ARM_ARCH_7A__) +void armv7_function() {} +#endif diff --git a/test/tools/llvm-symbolizer/Inputs/fat.o b/test/tools/llvm-symbolizer/Inputs/fat.o Binary files differnew file mode 100644 index 0000000000000..947cfc2d8cd78 --- /dev/null +++ b/test/tools/llvm-symbolizer/Inputs/fat.o diff --git a/test/tools/llvm-symbolizer/fat.test b/test/tools/llvm-symbolizer/fat.test new file mode 100644 index 0000000000000..1ecd1abb356f4 --- /dev/null +++ b/test/tools/llvm-symbolizer/fat.test @@ -0,0 +1,11 @@ +RUN: echo 0 | llvm-symbolizer -obj=%p/Inputs/fat.o -default-arch=x86_64 | FileCheck --check-prefix=X86_64 %s +RUN: echo 0 | llvm-symbolizer -obj=%p/Inputs/fat.o -default-arch=x86_64h | FileCheck --check-prefix=X86_64H %s +RUN: echo 0 | llvm-symbolizer -obj=%p/Inputs/fat.o -default-arch=armv7 | FileCheck --check-prefix=ARMV7 %s +RUN: echo 0 | llvm-symbolizer -obj=%p/Inputs/fat.o -default-arch=armv7em | FileCheck --check-prefix=ARMV7EM %s +RUN: echo 0 | llvm-symbolizer -obj=%p/Inputs/fat.o -default-arch=armv7m | FileCheck --check-prefix=ARMV7M %s + +X86_64: x86_64_function +X86_64H: x86_64h_function +ARMV7: armv7_function +ARMV7EM: armv7em_function +ARMV7M: armv7m_function |