vendor/lldb/lldb-trunk-r300422

14 files changed, 851 insertions, 1498 deletions

diff --git a/tools/debugserver/debugserver.xcodeproj/project.pbxproj b/tools/debugserver/debugserver.xcodeproj/project.pbxproj
index a4c3de58113e4..e0d1b68db7025 100644
--- a/tools/debugserver/debugserver.xcodeproj/project.pbxproj
+++ b/tools/debugserver/debugserver.xcodeproj/project.pbxproj
@@ -94,12 +94,12 @@
 		456F67641AD46CE9002850C2 /* CFBundle.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 2695DD910D3EBFF6007E4CA2 /* CFBundle.cpp */; };
 		456F67651AD46CE9002850C2 /* PseudoTerminal.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AF67ABFF0D34604D0022D128 /* PseudoTerminal.cpp */; };
 		456F67671AD46CE9002850C2 /* DNBArch.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 264D5D571293835600ED4C01 /* DNBArch.cpp */; };
-		456F67681AD46CE9002850C2 /* HasAVX.s in Sources */ = {isa = PBXBuildFile; fileRef = 4971AE7113D10F4F00649E37 /* HasAVX.s */; };
 		456F67691AD46CE9002850C2 /* DNBArchImplARM64.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 266B5ECF1460A68200E43F0A /* DNBArchImplARM64.cpp */; };
 		456F676B1AD46CE9002850C2 /* CoreFoundation.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 26ACA3340D3E956300A2120B /* CoreFoundation.framework */; settings = {ATTRIBUTES = (Required, ); }; };
-		4971AE7213D10F4F00649E37 /* HasAVX.s in Sources */ = {isa = PBXBuildFile; fileRef = 4971AE7113D10F4F00649E37 /* HasAVX.s */; };
+		49D404621E39260F00570CDC /* Foundation.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 49D404611E39260F00570CDC /* Foundation.framework */; };
 		AF48558C1D75126800D19C07 /* StdStringExtractor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AF48558B1D75126800D19C07 /* StdStringExtractor.cpp */; };
 		AF48558D1D75127500D19C07 /* StdStringExtractor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AF48558B1D75126800D19C07 /* StdStringExtractor.cpp */; };
+		AFA3FCA11E39984900218D5E /* Foundation.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = 49D404611E39260F00570CDC /* Foundation.framework */; };
 		AFEC3364194A8B0B00FF05C6 /* Genealogy.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AFEC3363194A8B0B00FF05C6 /* Genealogy.cpp */; };
 /* End PBXBuildFile section */
 
@@ -208,8 +208,7 @@
 		26CF99A31142EB7400011AAB /* DNBArchImplX86_64.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = DNBArchImplX86_64.h; sourceTree = "<group>"; };
 		26E6B9DA0D1329010037ECDD /* RNBDefs.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = RNBDefs.h; sourceTree = "<group>"; };
 		456F67721AD46CE9002850C2 /* debugserver-nonui */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = "debugserver-nonui"; sourceTree = BUILT_PRODUCTS_DIR; };
-		4971AE7013D10F4F00649E37 /* HasAVX.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = HasAVX.h; sourceTree = "<group>"; };
-		4971AE7113D10F4F00649E37 /* HasAVX.s */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.asm; path = HasAVX.s; sourceTree = "<group>"; };
+		49D404611E39260F00570CDC /* Foundation.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Foundation.framework; path = System/Library/Frameworks/Foundation.framework; sourceTree = SDKROOT; };
 		49F530111331519C008956F6 /* MachRegisterStatesI386.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MachRegisterStatesI386.h; sourceTree = "<group>"; };
 		49F5301213316D7F008956F6 /* MachRegisterStatesX86_64.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = MachRegisterStatesX86_64.h; sourceTree = "<group>"; };
 		9457ECF61419864100DFE7D8 /* stack_logging.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = stack_logging.h; sourceTree = "<group>"; };
@@ -232,6 +231,7 @@
 			isa = PBXFrameworksBuildPhase;
 			buildActionMask = 2147483647;
 			files = (
+				49D404621E39260F00570CDC /* Foundation.framework in Frameworks */,
 				26CE05CF115C36F70022F371 /* CoreFoundation.framework in Frameworks */,
 			);
 			runOnlyForDeploymentPostprocessing = 0;
@@ -241,6 +241,7 @@
 			buildActionMask = 2147483647;
 			files = (
 				456F676B1AD46CE9002850C2 /* CoreFoundation.framework in Frameworks */,
+				AFA3FCA11E39984900218D5E /* Foundation.framework in Frameworks */,
 			);
 			runOnlyForDeploymentPostprocessing = 0;
 		};
@@ -253,6 +254,7 @@
 				26ACA3330D3E94F200A2120B /* Framework */,
 				26C637D50C71334A0024798E /* source */,
 				1AB674ADFE9D54B511CA2CBB /* Products */,
+				49D404601E39260F00570CDC /* Frameworks */,
 			);
 			name = dbgnub;
 			sourceTree = "<group>";
@@ -407,8 +409,6 @@
 				26C637E90C71334A0024798E /* i386 */,
 				26C637FA0C71334A0024798E /* ppc */,
 				26CF99A11142EB7400011AAB /* x86_64 */,
-				4971AE7013D10F4F00649E37 /* HasAVX.h */,
-				4971AE7113D10F4F00649E37 /* HasAVX.s */,
 				26C637E80C71334A0024798E /* dbgnub-mig.defs */,
 				AFEC3363194A8B0B00FF05C6 /* Genealogy.cpp */,
 				AF0934BA18E12B92005A11FD /* Genealogy.h */,
@@ -483,6 +483,14 @@
 			sourceTree = "<group>";
 			usesTabs = 0;
 		};
+		49D404601E39260F00570CDC /* Frameworks */ = {
+			isa = PBXGroup;
+			children = (
+				49D404611E39260F00570CDC /* Foundation.framework */,
+			);
+			name = Frameworks;
+			sourceTree = "<group>";
+		};
 /* End PBXGroup section */
 
 /* Begin PBXNativeTarget section */
@@ -612,7 +620,6 @@
 				23562ED91D342B0000AB2BD4 /* LogMessage.cpp in Sources */,
 				26CE05F1115C387C0022F371 /* PseudoTerminal.cpp in Sources */,
 				264D5D581293835600ED4C01 /* DNBArch.cpp in Sources */,
-				4971AE7213D10F4F00649E37 /* HasAVX.s in Sources */,
 				237821B01D4917D20028B7A1 /* LogFilterExactMatch.cpp in Sources */,
 				266B5ED11460A68200E43F0A /* DNBArchImplARM64.cpp in Sources */,
 			);
@@ -665,7 +672,6 @@
 				456F67641AD46CE9002850C2 /* CFBundle.cpp in Sources */,
 				456F67651AD46CE9002850C2 /* PseudoTerminal.cpp in Sources */,
 				456F67671AD46CE9002850C2 /* DNBArch.cpp in Sources */,
-				456F67681AD46CE9002850C2 /* HasAVX.s in Sources */,
 				23AC04D01D2F58AF0072351D /* LogFilterRegex.cpp in Sources */,
 				456F67691AD46CE9002850C2 /* DNBArchImplARM64.cpp in Sources */,
 			);
@@ -874,8 +880,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -976,8 +980,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -1077,8 +1079,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -1519,8 +1519,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -1661,8 +1659,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -1877,8 +1873,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
@@ -2010,8 +2004,6 @@
 					SpringBoardServices,
 					"-framework",
 					BackBoardServices,
-					"-framework",
-					Foundation,
 					"-llockdown",
 					"-framework",
 					FrontBoardServices,
diff --git a/tools/debugserver/source/CMakeLists.txt b/tools/debugserver/source/CMakeLists.txt
index 43479bd36435b..782c946f702fe 100644
--- a/tools/debugserver/source/CMakeLists.txt
+++ b/tools/debugserver/source/CMakeLists.txt
@@ -2,12 +2,10 @@ include_directories(${CMAKE_CURRENT_BINARY_DIR}/..)
 include_directories(${LLDB_SOURCE_DIR}/source)
 include_directories(MacOSX/DarwinLog)
 
-if (CMAKE_SYSTEM_NAME MATCHES "Darwin")
-  include_directories(MacOSX)
-  #include_directories(${CMAKE_CURRENT_BINARY_DIR}/MacOSX)
+include_directories(MacOSX)
+#include_directories(${CMAKE_CURRENT_BINARY_DIR}/MacOSX)
 
-  set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -stdlib=libc++ -Wl,-sectcreate,__TEXT,__info_plist,${CMAKE_CURRENT_SOURCE_DIR}/../resources/lldb-debugserver-Info.plist")
-endif()
+set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -stdlib=libc++ -Wl,-sectcreate,__TEXT,__info_plist,${CMAKE_CURRENT_SOURCE_DIR}/../resources/lldb-debugserver-Info.plist")
 
 check_cxx_compiler_flag("-Wno-gnu-zero-variadic-macro-arguments"
                         CXX_SUPPORTS_NO_GNU_ZERO_VARIADIC_MACRO_ARGUMENTS)
@@ -27,14 +25,31 @@ if (CXX_SUPPORTS_NO_EXTENDED_OFFSETOF)
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-extended-offsetof")
 endif ()
 
-if (NOT CMAKE_SYSTEM_NAME MATCHES "Darwin")
-  add_definitions(
-    -DDEBUGSERVER_VERSION_STR="${LLDB_VERSION}"
-    )
-endif ()
+find_library(COCOA_LIBRARY Cocoa)
+add_subdirectory(MacOSX)
 
-add_library(lldbDebugserverCommon
-  debugserver.cpp
+set(generated_mach_interfaces
+  ${CMAKE_CURRENT_BINARY_DIR}/mach_exc.h
+  ${CMAKE_CURRENT_BINARY_DIR}/mach_excServer.c
+  ${CMAKE_CURRENT_BINARY_DIR}/mach_excUser.c
+  )
+add_custom_command(OUTPUT ${generated_mach_interfaces}
+  COMMAND mig ${CMAKE_CURRENT_SOURCE_DIR}/MacOSX/dbgnub-mig.defs
+  DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/MacOSX/dbgnub-mig.defs
+  )
+
+set(DEBUGSERVER_VERS_GENERATED_FILE ${CMAKE_CURRENT_BINARY_DIR}/debugserver_vers.c)
+set_source_files_properties(${DEBUGSERVER_VERS_GENERATED_FILE} PROPERTIES GENERATED 1)
+
+add_custom_command(OUTPUT ${DEBUGSERVER_VERS_GENERATED_FILE}
+  COMMAND ${LLDB_SOURCE_DIR}/scripts/generate-vers.pl
+          ${LLDB_SOURCE_DIR}/lldb.xcodeproj/project.pbxproj debugserver
+          > ${DEBUGSERVER_VERS_GENERATED_FILE}
+  DEPENDS ${LLDB_SOURCE_DIR}/scripts/generate-vers.pl
+          ${LLDB_SOURCE_DIR}/lldb.xcodeproj/project.pbxproj
+  )
+
+set(lldbDebugserverCommonSources
   DNBArch.cpp
   DNBBreakpoint.cpp
   DNB.cpp
@@ -58,11 +73,54 @@ add_library(lldbDebugserverCommon
   RNBSocket.cpp
   SysSignal.cpp
   TTYState.cpp
+  
+  MacOSX/CFBundle.cpp
+  MacOSX/CFString.cpp
+  MacOSX/Genealogy.cpp
+  MacOSX/MachException.cpp
+  MacOSX/MachProcess.mm
+  MacOSX/MachTask.mm
+  MacOSX/MachThread.cpp
+  MacOSX/MachThreadList.cpp
+  MacOSX/MachVMMemory.cpp
+  MacOSX/MachVMRegion.cpp
+  MacOSX/OsLogger.cpp
+  ${generated_mach_interfaces}
+  ${DEBUGSERVER_VERS_GENERATED_FILE})
+
+add_library(lldbDebugserverCommon ${lldbDebugserverCommonSources})
+
+target_link_libraries(lldbDebugserverCommon
+                      INTERFACE ${COCOA_LIBRARY}
+                      lldbDebugserverMacOSX_I386
+                      lldbDebugserverMacOSX_X86_64
+                      lldbDebugserverMacOSX_DarwinLog)
+
+set(LLVM_OPTIONAL_SOURCES ${lldbDebugserverCommonSources})
+add_lldb_tool(debugserver INCLUDE_IN_FRAMEWORK
+  debugserver.cpp
+
+  LINK_LIBS
+    lldbDebugserverCommon
   )
 
-if (CMAKE_SYSTEM_NAME MATCHES "Darwin")
-  find_library(COCOA_LIBRARY Cocoa)
-  target_link_libraries(lldbDebugserverCommon ${COCOA_LIBRARY})
-  add_subdirectory(MacOSX)
+set(LLDB_CODESIGN_IDENTITY "lldb_codesign"
+  CACHE STRING "Identity used for code signing. Set to empty string to skip the signing step.")
+if (NOT ("${LLDB_CODESIGN_IDENTITY}" STREQUAL ""))
+  execute_process(
+    COMMAND xcrun -f codesign_allocate
+    OUTPUT_STRIP_TRAILING_WHITESPACE
+    OUTPUT_VARIABLE CODESIGN_ALLOCATE
+    )
+  add_custom_command(TARGET debugserver
+    POST_BUILD
+    COMMAND ${CMAKE_COMMAND} -E env CODESIGN_ALLOCATE=${CODESIGN_ALLOCATE}
+            codesign --force --sign ${LLDB_CODESIGN_IDENTITY}
+            $<TARGET_FILE:debugserver>
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/bin
+  )
 endif()
 
+
+
+
diff --git a/tools/debugserver/source/MacOSX/CMakeLists.txt b/tools/debugserver/source/MacOSX/CMakeLists.txt
index 7b77eb25d5542..59b39a1bff639 100644
--- a/tools/debugserver/source/MacOSX/CMakeLists.txt
+++ b/tools/debugserver/source/MacOSX/CMakeLists.txt
@@ -6,75 +6,3 @@ add_subdirectory(x86_64)
 add_subdirectory(DarwinLog)
 
 include_directories(..)
-
-set(generated_mach_interfaces
-  ${CMAKE_CURRENT_BINARY_DIR}/mach_exc.h
-  ${CMAKE_CURRENT_BINARY_DIR}/mach_excServer.c
-  ${CMAKE_CURRENT_BINARY_DIR}/mach_excUser.c
-  )
-add_custom_command(OUTPUT ${generated_mach_interfaces}
-  COMMAND mig ${CMAKE_CURRENT_SOURCE_DIR}/dbgnub-mig.defs
-  DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/dbgnub-mig.defs
-  )
-
-set(DEBUGSERVER_VERS_GENERATED_FILE ${CMAKE_CURRENT_BINARY_DIR}/debugserver_vers.c)
-set_source_files_properties(${DEBUGSERVER_VERS_GENERATED_FILE} PROPERTIES GENERATED 1)
-
-add_custom_command(OUTPUT ${DEBUGSERVER_VERS_GENERATED_FILE}
-  COMMAND ${LLDB_SOURCE_DIR}/scripts/generate-vers.pl
-          ${LLDB_SOURCE_DIR}/lldb.xcodeproj/project.pbxproj debugserver
-          > ${DEBUGSERVER_VERS_GENERATED_FILE}
-  DEPENDS ${LLDB_SOURCE_DIR}/scripts/generate-vers.pl
-          ${LLDB_SOURCE_DIR}/lldb.xcodeproj/project.pbxproj
-  )
-
-set(DEBUGSERVER_USED_LIBS
-  lldbDebugserverCommon
-  lldbUtility
-  lldbDebugserverMacOSX_I386
-  lldbDebugserverMacOSX_X86_64
-  lldbDebugserverMacOSX_DarwinLog
-  )
-
-add_lldb_tool(debugserver INCLUDE_IN_FRAMEWORK
-  HasAVX.s
-  CFBundle.cpp
-  CFString.cpp
-  Genealogy.cpp
-  MachException.cpp
-  MachProcess.mm
-  MachTask.mm
-  MachThread.cpp
-  MachThreadList.cpp
-  MachVMMemory.cpp
-  MachVMRegion.cpp
-  OsLogger.cpp
-  ${generated_mach_interfaces}
-  ${DEBUGSERVER_VERS_GENERATED_FILE}
-  )
-
-set_source_files_properties(
-  HasAVX.s
-  # Necessary since compilation will fail with stand-alone assembler
-  PROPERTIES LANGUAGE C COMPILE_FLAGS "-x assembler-with-cpp"
-  )
-
-target_link_libraries(debugserver ${DEBUGSERVER_USED_LIBS})
-
-set(LLDB_CODESIGN_IDENTITY "lldb_codesign"
-  CACHE STRING "Identity used for code signing. Set to empty string to skip the signing step.")
-if (NOT ("${LLDB_CODESIGN_IDENTITY}" STREQUAL ""))
-  execute_process(
-    COMMAND xcrun -f codesign_allocate
-    OUTPUT_STRIP_TRAILING_WHITESPACE
-    OUTPUT_VARIABLE CODESIGN_ALLOCATE
-    )
-  add_custom_command(TARGET debugserver
-    POST_BUILD
-    # Note: --entitlements option removed (see comment above).
-    COMMAND ${CMAKE_COMMAND} -E env CODESIGN_ALLOCATE=${CODESIGN_ALLOCATE}
-            codesign --force --sign ${LLDB_CODESIGN_IDENTITY}
-            $<TARGET_FILE:debugserver>
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/bin
-  )
-endif()
diff --git a/tools/debugserver/source/MacOSX/DarwinLog/DarwinLogCollector.cpp b/tools/debugserver/source/MacOSX/DarwinLog/DarwinLogCollector.cpp
index 982367092ede9..1e833c4cb1658 100644
--- a/tools/debugserver/source/MacOSX/DarwinLog/DarwinLogCollector.cpp
+++ b/tools/debugserver/source/MacOSX/DarwinLog/DarwinLogCollector.cpp
@@ -50,6 +50,7 @@ bool LookupSPICalls() {
   static bool s_has_spi;
 
   std::call_once(s_once_flag, [] {
+    dlopen ("/System/Library/PrivateFrameworks/LoggingSupport.framework/LoggingSupport", RTLD_NOW);
     s_os_activity_stream_for_pid = (os_activity_stream_for_pid_t)dlsym(
         RTLD_DEFAULT, "os_activity_stream_for_pid");
     s_os_activity_stream_resume = (os_activity_stream_resume_t)dlsym(
@@ -691,7 +692,7 @@ void DarwinLogCollector::CancelActivityStream() {
 
   DNBLogThreadedIf(LOG_DARWIN_LOG, "DarwinLogCollector::%s(): canceling "
                                    "activity stream %p",
-                   __FUNCTION__, m_activity_stream);
+                   __FUNCTION__, reinterpret_cast<void *>(m_activity_stream));
   (*s_os_activity_stream_cancel)(m_activity_stream);
   m_activity_stream = nullptr;
 }
diff --git a/tools/debugserver/source/MacOSX/HasAVX.h b/tools/debugserver/source/MacOSX/HasAVX.h
deleted file mode 100644
index 43fbd5e514e2e..0000000000000
--- a/tools/debugserver/source/MacOSX/HasAVX.h
+++ /dev/null
@@ -1,27 +0,0 @@
-//===-- HasAVX.h ------------------------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef HasAVX_h
-#define HasAVX_h
-
-#if defined(__i386__) || defined(__x86_64__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int HasAVX();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
diff --git a/tools/debugserver/source/MacOSX/HasAVX.s b/tools/debugserver/source/MacOSX/HasAVX.s
deleted file mode 100644
index b66ccf14dbeed..0000000000000
--- a/tools/debugserver/source/MacOSX/HasAVX.s
+++ /dev/null
@@ -1,50 +0,0 @@
-//===-- HasAVX.s ---------------------------------------*- x86 Assembly -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#if defined (__i386__) || defined (__x86_64__)
-
-.globl _HasAVX
-
-_HasAVX:
-#if defined (__x86_64__)
-    pushq %rbp
-    movq %rsp, %rbp
-    pushq %rbx
-#else
-    pushl %ebp
-    movl %esp, %ebp
-    pushl %ebx
-#endif
-    mov $1, %eax
-    cpuid                                                                       // clobbers ebx
-    and $0x018000000, %ecx
-    cmp $0x018000000, %ecx
-    jne not_supported
-    mov $0, %ecx
-.byte 0x0f, 0x01, 0xd0    // xgetbv, for those assemblers that don't know it
-    and $0x06, %eax
-    cmp $0x06, %eax
-    jne not_supported
-    mov $1, %eax
-    jmp done
-not_supported:
-    mov $0, %eax
-done:
-#if defined (__x86_64__)
-    popq %rbx
-    movq %rbp, %rsp
-    popq %rbp
-#else
-    popl %ebx
-    movl %ebp, %esp
-    popl %ebp
-#endif
-    ret                                                                         // return
-
-#endif
diff --git a/tools/debugserver/source/MacOSX/MachProcess.mm b/tools/debugserver/source/MacOSX/MachProcess.mm
index 720f6bc8899ed..0daaca1db37ef 100644
--- a/tools/debugserver/source/MacOSX/MachProcess.mm
+++ b/tools/debugserver/source/MacOSX/MachProcess.mm
@@ -1269,7 +1269,7 @@ bool MachProcess::Interrupt() {
 bool MachProcess::Signal(int signal, const struct timespec *timeout_abstime) {
   DNBLogThreadedIf(LOG_PROCESS,
                    "MachProcess::Signal (signal = %d, timeout = %p)", signal,
-                   timeout_abstime);
+                   reinterpret_cast<const void *>(timeout_abstime));
   nub_state_t state = GetState();
   if (::kill(ProcessID(), signal) == 0) {
     // If we were running and we have a timeout, wait for the signal to stop
@@ -1277,20 +1277,21 @@ bool MachProcess::Signal(int signal, const struct timespec *timeout_abstime) {
       DNBLogThreadedIf(LOG_PROCESS, "MachProcess::Signal (signal = %d, timeout "
                                     "= %p) waiting for signal to stop "
                                     "process...",
-                       signal, timeout_abstime);
+                       signal, reinterpret_cast<const void *>(timeout_abstime));
       m_private_events.WaitForSetEvents(eEventProcessStoppedStateChanged,
                                         timeout_abstime);
       state = GetState();
       DNBLogThreadedIf(
           LOG_PROCESS,
           "MachProcess::Signal (signal = %d, timeout = %p) state = %s", signal,
-          timeout_abstime, DNBStateAsString(state));
+          reinterpret_cast<const void *>(timeout_abstime),
+          DNBStateAsString(state));
       return !IsRunning(state);
     }
     DNBLogThreadedIf(
         LOG_PROCESS,
         "MachProcess::Signal (signal = %d, timeout = %p) not waiting...",
-        signal, timeout_abstime);
+        signal, reinterpret_cast<const void *>(timeout_abstime));
     return true;
   }
   DNBError err(errno, DNBError::POSIX);
@@ -1596,7 +1597,8 @@ DNBBreakpoint *MachProcess::CreateBreakpoint(nub_addr_t addr, nub_size_t length,
   if (EnableBreakpoint(addr)) {
     DNBLogThreadedIf(LOG_BREAKPOINTS, "MachProcess::CreateBreakpoint ( addr = "
                                       "0x%8.8llx, length = %llu) => %p",
-                     (uint64_t)addr, (uint64_t)length, bp);
+                     (uint64_t)addr, (uint64_t)length,
+                     reinterpret_cast<void *>(bp));
     return bp;
   } else if (bp->Release() == 0) {
     m_breakpoints.Remove(addr);
@@ -1627,7 +1629,8 @@ DNBBreakpoint *MachProcess::CreateWatchpoint(nub_addr_t addr, nub_size_t length,
   if (EnableWatchpoint(addr)) {
     DNBLogThreadedIf(LOG_WATCHPOINTS, "MachProcess::CreateWatchpoint ( addr = "
                                       "0x%8.8llx, length = %llu) => %p",
-                     (uint64_t)addr, (uint64_t)length, wp);
+                     (uint64_t)addr, (uint64_t)length,
+                     reinterpret_cast<void *>(wp));
     return wp;
   } else {
     DNBLogThreadedIf(LOG_WATCHPOINTS, "MachProcess::CreateWatchpoint ( addr = "
@@ -2156,7 +2159,7 @@ void MachProcess::AppendSTDOUT(char *s, size_t len) {
 
 size_t MachProcess::GetAvailableSTDOUT(char *buf, size_t buf_size) {
   DNBLogThreadedIf(LOG_PROCESS, "MachProcess::%s (&%p[%llu]) ...", __FUNCTION__,
-                   buf, (uint64_t)buf_size);
+                   reinterpret_cast<void *>(buf), (uint64_t)buf_size);
   PTHREAD_MUTEX_LOCKER(locker, m_stdio_mutex);
   size_t bytes_available = m_stdout_data.size();
   if (bytes_available > 0) {
@@ -2316,7 +2319,7 @@ void MachProcess::SignalAsyncProfileData(const char *info) {
 
 size_t MachProcess::GetAsyncProfileData(char *buf, size_t buf_size) {
   DNBLogThreadedIf(LOG_PROCESS, "MachProcess::%s (&%p[%llu]) ...", __FUNCTION__,
-                   buf, (uint64_t)buf_size);
+                   reinterpret_cast<void *>(buf), (uint64_t)buf_size);
   PTHREAD_MUTEX_LOCKER(locker, m_profile_data_mutex);
   if (m_profile_data.empty())
     return 0;
@@ -2839,9 +2842,12 @@ pid_t MachProcess::LaunchForDebug(
   // Clear out and clean up from any current state
   Clear();
 
-  DNBLogThreadedIf(LOG_PROCESS, "%s( path = '%s', argv = %p, envp = %p, "
-                                "launch_flavor = %u, disable_aslr = %d )",
-                   __FUNCTION__, path, argv, envp, launch_flavor, disable_aslr);
+  DNBLogThreadedIf(LOG_PROCESS,
+                   "%s( path = '%s', argv = %p, envp = %p, "
+                   "launch_flavor = %u, disable_aslr = %d )",
+                   __FUNCTION__, path, reinterpret_cast<const void *>(argv),
+                   reinterpret_cast<const void *>(envp), launch_flavor,
+                   disable_aslr);
 
   // Fork a child process for debugging
   SetState(eStateLaunching);
@@ -2984,7 +2990,8 @@ pid_t MachProcess::PosixSpawnChildForPTraceDebugging(
   DNBLogThreadedIf(LOG_PROCESS, "%s ( path='%s', argv=%p, envp=%p, "
                                 "working_dir=%s, stdin=%s, stdout=%s "
                                 "stderr=%s, no-stdio=%i)",
-                   __FUNCTION__, path, argv, envp, working_directory,
+                   __FUNCTION__, path, reinterpret_cast<const void *>(argv),
+                   reinterpret_cast<const void *>(envp), working_directory,
                    stdin_path, stdout_path, stderr_path, no_stdio);
 
   err.SetError(::posix_spawnattr_init(&attr), DNBError::POSIX);
diff --git a/tools/debugserver/source/MacOSX/MachThread.cpp b/tools/debugserver/source/MacOSX/MachThread.cpp
index 36aa8c04bf2a7..5686e42e4a497 100644
--- a/tools/debugserver/source/MacOSX/MachThread.cpp
+++ b/tools/debugserver/source/MacOSX/MachThread.cpp
@@ -50,7 +50,7 @@ MachThread::MachThread(MachProcess *process, bool is_64_bit,
   DNBLogThreadedIf(LOG_THREAD | LOG_VERBOSE,
                    "MachThread::MachThread ( process = %p, tid = 0x%8.8" PRIx64
                    ", seq_id = %u )",
-                   &m_process, m_unique_id, m_seq_id);
+                   reinterpret_cast<void *>(&m_process), m_unique_id, m_seq_id);
 }
 
 MachThread::~MachThread() {
diff --git a/tools/debugserver/source/MacOSX/OsLogger.cpp b/tools/debugserver/source/MacOSX/OsLogger.cpp
index efecea30212f0..6cc04a8a7c839 100644
--- a/tools/debugserver/source/MacOSX/OsLogger.cpp
+++ b/tools/debugserver/source/MacOSX/OsLogger.cpp
@@ -8,8 +8,9 @@
 //===----------------------------------------------------------------------===//
 
 #include "OsLogger.h"
+#include <Availability.h>
 
-#if LLDB_USE_OS_LOG
+#if (LLDB_USE_OS_LOG) && (__MAC_OS_X_VERSION_MAX_ALLOWED >= 101200)
 
 #include <os/log.h>
 
@@ -64,3 +65,4 @@ DNBCallbackLog OsLogger::GetLogFunction() {
 DNBCallbackLog OsLogger::GetLogFunction() { return nullptr; }
 
 #endif
+
diff --git a/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp b/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
index 0974b168326d0..6cc5ae6c36c4b 100644
--- a/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
+++ b/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
@@ -339,60 +339,61 @@ kern_return_t DNBArchImplI386::GetGPRState(bool force) {
 kern_return_t DNBArchImplI386::GetFPUState(bool force) {
   if (force || m_state.GetError(e_regSetFPU, Read)) {
     if (DEBUG_FPU_REGS) {
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        m_state.context.fpu.avx.__fpu_reserved[0] = -1;
-        m_state.context.fpu.avx.__fpu_reserved[1] = -1;
-        *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
-        *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
-        m_state.context.fpu.avx.__fpu_ftw = 1;
-        m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
-        m_state.context.fpu.avx.__fpu_fop = 2;
-        m_state.context.fpu.avx.__fpu_ip = 3;
-        m_state.context.fpu.avx.__fpu_cs = 4;
-        m_state.context.fpu.avx.__fpu_rsrv2 = 5;
-        m_state.context.fpu.avx.__fpu_dp = 6;
-        m_state.context.fpu.avx.__fpu_ds = 7;
-        m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
-        m_state.context.fpu.avx.__fpu_mxcsr = 8;
-        m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
-        int i;
-        for (i = 0; i < 16; ++i) {
-          if (i < 10) {
-            m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
-            m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
-            m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
-            m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
-            m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
-            m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
-            m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
-            m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
-          } else {
-            m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
-          }
 
-          m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
-          m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
-          m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
-          m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
-          m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
-          m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
-          m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
-          m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
+      m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
+      m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
+      *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
+      *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
+      m_state.context.fpu.no_avx.__fpu_ftw = 1;
+      m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
+      m_state.context.fpu.no_avx.__fpu_fop = 2;
+      m_state.context.fpu.no_avx.__fpu_ip = 3;
+      m_state.context.fpu.no_avx.__fpu_cs = 4;
+      m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
+      m_state.context.fpu.no_avx.__fpu_dp = 6;
+      m_state.context.fpu.no_avx.__fpu_ds = 7;
+      m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
+      m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
+      m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
+      for (int i = 0; i < 16; ++i) {
+        if (i < 10) {
+          m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
+          m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
+          m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
+          m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
+          m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
+          m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
+          m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
+          m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
+        } else {
+          m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
         }
-        for (i = 0; i < sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
-          m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
-        m_state.context.fpu.avx.__fpu_reserved1 = -1;
-        for (i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
+
+        m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
+        m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
+        m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
+        m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
+        m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
+        m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
+        m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
+        m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
+      }
+      for (int i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
+        m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
+      m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
+
+      if (CPUHasAVX() || FORCE_AVX_REGS) {
+        for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
           m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
 
-        for (i = 0; i < 16; ++i) {
+        for (int i = 0; i < 16; ++i) {
           m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
           m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
           m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
@@ -402,83 +403,24 @@ kern_return_t DNBArchImplI386::GetFPUState(bool force) {
           m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
           m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
         }
-      } else {
-        m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
-        m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
-        *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
-        *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
-        m_state.context.fpu.no_avx.__fpu_ftw = 1;
-        m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
-        m_state.context.fpu.no_avx.__fpu_fop = 2;
-        m_state.context.fpu.no_avx.__fpu_ip = 3;
-        m_state.context.fpu.no_avx.__fpu_cs = 4;
-        m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
-        m_state.context.fpu.no_avx.__fpu_dp = 6;
-        m_state.context.fpu.no_avx.__fpu_ds = 7;
-        m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
-        m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
-        m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
-        int i;
-        for (i = 0; i < 16; ++i) {
-          if (i < 10) {
-            m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
-            m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
-            m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
-            m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
-            m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
-            m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
-            m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
-            m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
-          } else {
-            m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
-          }
-
-          m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
-          m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
-          m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
-          m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
-          m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
-          m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
-          m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
-          m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
-        }
-        for (i = 0; i < sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
-          m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
-        m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
       }
       m_state.SetError(e_regSetFPU, Read, 0);
     } else {
+      mach_msg_type_number_t count = e_regSetWordSizeFPU;
+      int flavor = __i386_FLOAT_STATE;
+
       if (CPUHasAVX() || FORCE_AVX_REGS) {
-        mach_msg_type_number_t count = e_regSetWordSizeAVX;
-        m_state.SetError(e_regSetFPU, Read,
-                         ::thread_get_state(
-                             m_thread->MachPortNumber(), __i386_AVX_STATE,
-                             (thread_state_t)&m_state.context.fpu.avx, &count));
-        DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, "
-                                     "%u (%u passed in)) => 0x%8.8x",
-                         m_thread->MachPortNumber(), __i386_AVX_STATE, count,
-                         e_regSetWordSizeAVX,
-                         m_state.GetError(e_regSetFPU, Read));
-      } else {
-        mach_msg_type_number_t count = e_regSetWordSizeFPU;
-        m_state.SetError(
-            e_regSetFPU, Read,
-            ::thread_get_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE,
-                               (thread_state_t)&m_state.context.fpu.no_avx,
-                               &count));
-        DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, "
-                                     "%u (%u passed in) => 0x%8.8x",
-                         m_thread->MachPortNumber(), __i386_FLOAT_STATE, count,
-                         e_regSetWordSizeFPU,
-                         m_state.GetError(e_regSetFPU, Read));
+        count = e_regSetWordSizeAVX;
+        flavor = __i386_AVX_STATE;
       }
+      m_state.SetError(e_regSetFPU, Read,
+                       ::thread_get_state(m_thread->MachPortNumber(), flavor,
+                                          (thread_state_t)&m_state.context.fpu,
+                                          &count));
+      DNBLogThreadedIf(LOG_THREAD,
+                       "::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
+                       m_thread->MachPortNumber(), flavor, (uint32_t)count,
+                       m_state.GetError(e_regSetFPU, Read));
     }
   }
   return m_state.GetError(e_regSetFPU, Read);
@@ -1460,239 +1402,138 @@ bool DNBArchImplI386::GetRegisterValue(uint32_t set, uint32_t reg,
       break;
 
     case e_regSetFPU:
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        switch (reg) {
-        case fpu_fcw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw));
-          return true;
-        case fpu_fsw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw));
-          return true;
-        case fpu_ftw:
-          value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw;
-          return true;
-        case fpu_fop:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_fop;
-          return true;
-        case fpu_ip:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_ip;
-          return true;
-        case fpu_cs:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_cs;
-          return true;
-        case fpu_dp:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_dp;
-          return true;
-        case fpu_ds:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_ds;
-          return true;
-        case fpu_mxcsr:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr;
-          return true;
-        case fpu_mxcsrmask:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask;
-          return true;
-
-        case fpu_stmm0:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, 10);
-          return true;
-        case fpu_stmm1:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, 10);
-          return true;
-        case fpu_stmm2:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, 10);
-          return true;
-        case fpu_stmm3:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, 10);
-          return true;
-        case fpu_stmm4:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, 10);
-          return true;
-        case fpu_stmm5:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, 10);
-          return true;
-        case fpu_stmm6:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, 10);
-          return true;
-        case fpu_stmm7:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, 10);
-          return true;
-
-        case fpu_xmm0:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, 16);
-          return true;
-        case fpu_xmm1:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, 16);
-          return true;
-        case fpu_xmm2:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, 16);
-          return true;
-        case fpu_xmm3:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, 16);
-          return true;
-        case fpu_xmm4:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, 16);
-          return true;
-        case fpu_xmm5:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, 16);
-          return true;
-        case fpu_xmm6:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, 16);
-          return true;
-        case fpu_xmm7:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, 16);
-          return true;
+      if (reg > fpu_xmm7 && !(CPUHasAVX() || FORCE_AVX_REGS))
+        return false;
+      switch (reg) {
+      case fpu_fcw:
+        value->value.uint16 =
+            *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw));
+        return true;
+      case fpu_fsw:
+        value->value.uint16 =
+            *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
+        return true;
+      case fpu_ftw:
+        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        return true;
+      case fpu_fop:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
+        return true;
+      case fpu_ip:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip;
+        return true;
+      case fpu_cs:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs;
+        return true;
+      case fpu_dp:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp;
+        return true;
+      case fpu_ds:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds;
+        return true;
+      case fpu_mxcsr:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr;
+        return true;
+      case fpu_mxcsrmask:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask;
+        return true;
+
+      case fpu_stmm0:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10);
+        return true;
+      case fpu_stmm1:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10);
+        return true;
+      case fpu_stmm2:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10);
+        return true;
+      case fpu_stmm3:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10);
+        return true;
+      case fpu_stmm4:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10);
+        return true;
+      case fpu_stmm5:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10);
+        return true;
+      case fpu_stmm6:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10);
+        return true;
+      case fpu_stmm7:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10);
+        return true;
+
+      case fpu_xmm0:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16);
+        return true;
+      case fpu_xmm1:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16);
+        return true;
+      case fpu_xmm2:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16);
+        return true;
+      case fpu_xmm3:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16);
+        return true;
+      case fpu_xmm4:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16);
+        return true;
+      case fpu_xmm5:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16);
+        return true;
+      case fpu_xmm6:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16);
+        return true;
+      case fpu_xmm7:
+        memcpy(&value->value.uint8,
+               m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16);
+        return true;
 
 #define MEMCPY_YMM(n)                                                          \
   memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg,  \
          16);                                                                  \
   memcpy((&value->value.uint8) + 16,                                           \
          m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16);
-        case fpu_ymm0:
-          MEMCPY_YMM(0);
-          return true;
-        case fpu_ymm1:
-          MEMCPY_YMM(1);
-          return true;
-        case fpu_ymm2:
-          MEMCPY_YMM(2);
-          return true;
-        case fpu_ymm3:
-          MEMCPY_YMM(3);
-          return true;
-        case fpu_ymm4:
-          MEMCPY_YMM(4);
-          return true;
-        case fpu_ymm5:
-          MEMCPY_YMM(5);
-          return true;
-        case fpu_ymm6:
-          MEMCPY_YMM(6);
-          return true;
-        case fpu_ymm7:
-          MEMCPY_YMM(7);
-          return true;
+      case fpu_ymm0:
+        MEMCPY_YMM(0);
+        return true;
+      case fpu_ymm1:
+        MEMCPY_YMM(1);
+        return true;
+      case fpu_ymm2:
+        MEMCPY_YMM(2);
+        return true;
+      case fpu_ymm3:
+        MEMCPY_YMM(3);
+        return true;
+      case fpu_ymm4:
+        MEMCPY_YMM(4);
+        return true;
+      case fpu_ymm5:
+        MEMCPY_YMM(5);
+        return true;
+      case fpu_ymm6:
+        MEMCPY_YMM(6);
+        return true;
+      case fpu_ymm7:
+        MEMCPY_YMM(7);
+        return true;
 #undef MEMCPY_YMM
-        }
-      } else {
-        switch (reg) {
-        case fpu_fcw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw));
-          return true;
-        case fpu_fsw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
-          return true;
-        case fpu_ftw:
-          value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
-          return true;
-        case fpu_fop:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
-          return true;
-        case fpu_ip:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip;
-          return true;
-        case fpu_cs:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs;
-          return true;
-        case fpu_dp:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp;
-          return true;
-        case fpu_ds:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds;
-          return true;
-        case fpu_mxcsr:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr;
-          return true;
-        case fpu_mxcsrmask:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask;
-          return true;
-
-        case fpu_stmm0:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10);
-          return true;
-        case fpu_stmm1:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10);
-          return true;
-        case fpu_stmm2:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10);
-          return true;
-        case fpu_stmm3:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10);
-          return true;
-        case fpu_stmm4:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10);
-          return true;
-        case fpu_stmm5:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10);
-          return true;
-        case fpu_stmm6:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10);
-          return true;
-        case fpu_stmm7:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10);
-          return true;
-
-        case fpu_xmm0:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16);
-          return true;
-        case fpu_xmm1:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16);
-          return true;
-        case fpu_xmm2:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16);
-          return true;
-        case fpu_xmm3:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16);
-          return true;
-        case fpu_xmm4:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16);
-          return true;
-        case fpu_xmm5:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16);
-          return true;
-        case fpu_xmm6:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16);
-          return true;
-        case fpu_xmm7:
-          memcpy(&value->value.uint8,
-                 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16);
-          return true;
-        }
       }
       break;
 
@@ -1752,291 +1593,164 @@ bool DNBArchImplI386::SetRegisterValue(uint32_t set, uint32_t reg,
       break;
 
     case e_regSetFPU:
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        switch (reg) {
-        case fpu_fcw:
-          *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_fsw:
-          *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_ftw:
-          m_state.context.fpu.avx.__fpu_ftw = value->value.uint8;
-          success = true;
-          break;
-        case fpu_fop:
-          m_state.context.fpu.avx.__fpu_fop = value->value.uint16;
-          success = true;
-          break;
-        case fpu_ip:
-          m_state.context.fpu.avx.__fpu_ip = value->value.uint32;
-          success = true;
-          break;
-        case fpu_cs:
-          m_state.context.fpu.avx.__fpu_cs = value->value.uint16;
-          success = true;
-          break;
-        case fpu_dp:
-          m_state.context.fpu.avx.__fpu_dp = value->value.uint32;
-          success = true;
-          break;
-        case fpu_ds:
-          m_state.context.fpu.avx.__fpu_ds = value->value.uint16;
-          success = true;
-          break;
-        case fpu_mxcsr:
-          m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32;
-          success = true;
-          break;
-        case fpu_mxcsrmask:
-          m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32;
-          success = true;
-          break;
-
-        case fpu_stmm0:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm1:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm2:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm3:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm4:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm5:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm6:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm7:
-          memcpy(m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-
-        case fpu_xmm0:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm1:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm2:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm3:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm4:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm5:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm6:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm7:
-          memcpy(m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
+      if (reg > fpu_xmm7 && !(CPUHasAVX() || FORCE_AVX_REGS))
+        return false;
+      switch (reg) {
+      case fpu_fcw:
+        *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
+            value->value.uint16;
+        success = true;
+        break;
+      case fpu_fsw:
+        *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) =
+            value->value.uint16;
+        success = true;
+        break;
+      case fpu_ftw:
+        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        success = true;
+        break;
+      case fpu_fop:
+        m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16;
+        success = true;
+        break;
+      case fpu_ip:
+        m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32;
+        success = true;
+        break;
+      case fpu_cs:
+        m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16;
+        success = true;
+        break;
+      case fpu_dp:
+        m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32;
+        success = true;
+        break;
+      case fpu_ds:
+        m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16;
+        success = true;
+        break;
+      case fpu_mxcsr:
+        m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32;
+        success = true;
+        break;
+      case fpu_mxcsrmask:
+        m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32;
+        success = true;
+        break;
+
+      case fpu_stmm0:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm1:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm2:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm3:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm4:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm5:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm6:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+      case fpu_stmm7:
+        memcpy(m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg,
+               &value->value.uint8, 10);
+        success = true;
+        break;
+
+      case fpu_xmm0:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm1:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm2:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm3:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm4:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm5:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm6:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
+      case fpu_xmm7:
+        memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg,
+               &value->value.uint8, 16);
+        success = true;
+        break;
 
 #define MEMCPY_YMM(n)                                                          \
   memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8,  \
          16);                                                                  \
   memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg,                      \
          (&value->value.uint8) + 16, 16);
-        case fpu_ymm0:
-          MEMCPY_YMM(0);
-          return true;
-        case fpu_ymm1:
-          MEMCPY_YMM(1);
-          return true;
-        case fpu_ymm2:
-          MEMCPY_YMM(2);
-          return true;
-        case fpu_ymm3:
-          MEMCPY_YMM(3);
-          return true;
-        case fpu_ymm4:
-          MEMCPY_YMM(4);
-          return true;
-        case fpu_ymm5:
-          MEMCPY_YMM(5);
-          return true;
-        case fpu_ymm6:
-          MEMCPY_YMM(6);
-          return true;
-        case fpu_ymm7:
-          MEMCPY_YMM(7);
-          return true;
+      case fpu_ymm0:
+        MEMCPY_YMM(0);
+        return true;
+      case fpu_ymm1:
+        MEMCPY_YMM(1);
+        return true;
+      case fpu_ymm2:
+        MEMCPY_YMM(2);
+        return true;
+      case fpu_ymm3:
+        MEMCPY_YMM(3);
+        return true;
+      case fpu_ymm4:
+        MEMCPY_YMM(4);
+        return true;
+      case fpu_ymm5:
+        MEMCPY_YMM(5);
+        return true;
+      case fpu_ymm6:
+        MEMCPY_YMM(6);
+        return true;
+      case fpu_ymm7:
+        MEMCPY_YMM(7);
+        return true;
 #undef MEMCPY_YMM
-        }
-      } else {
-        switch (reg) {
-        case fpu_fcw:
-          *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_fsw:
-          *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_ftw:
-          m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
-          success = true;
-          break;
-        case fpu_fop:
-          m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16;
-          success = true;
-          break;
-        case fpu_ip:
-          m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32;
-          success = true;
-          break;
-        case fpu_cs:
-          m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16;
-          success = true;
-          break;
-        case fpu_dp:
-          m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32;
-          success = true;
-          break;
-        case fpu_ds:
-          m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16;
-          success = true;
-          break;
-        case fpu_mxcsr:
-          m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32;
-          success = true;
-          break;
-        case fpu_mxcsrmask:
-          m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32;
-          success = true;
-          break;
-
-        case fpu_stmm0:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm1:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm2:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm3:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm4:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm5:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm6:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-        case fpu_stmm7:
-          memcpy(m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg,
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-
-        case fpu_xmm0:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm1:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm2:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm3:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm4:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm5:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm6:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        case fpu_xmm7:
-          memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg,
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        }
       }
       break;
 
@@ -2113,24 +1827,24 @@ nub_size_t DNBArchImplI386::GetRegisterContext(void *buf, nub_size_t buf_len) {
       memcpy(p, &m_state.context.gpr, sizeof(GPR));
       p += sizeof(GPR);
 
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        // Walk around the gaps in the FPU regs
-        memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
-        p += 5;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
-        p += 8;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
-        p += 6;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
-        p += 8;
-
-        // Work around the padding between the stmm registers as they are 16
-        // byte structs with 10 bytes of the value in each
-        for (size_t i = 0; i < 8; ++i) {
-          memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
-          p += 10;
-        }
+      // Walk around the gaps in the FPU regs
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
+      p += 5;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
+      p += 8;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
+      p += 6;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
+      p += 8;
+
+      // Work around the padding between the stmm registers as they are 16
+      // byte structs with 10 bytes of the value in each
+      for (size_t i = 0; i < 8; ++i) {
+        memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
+        p += 10;
+      }
 
+      if (CPUHasAVX() || FORCE_AVX_REGS) {
         // Interleave the XMM and YMMH registers to make the YMM registers
         for (size_t i = 0; i < 8; ++i) {
           memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
@@ -2139,23 +1853,6 @@ nub_size_t DNBArchImplI386::GetRegisterContext(void *buf, nub_size_t buf_len) {
           p += 16;
         }
       } else {
-        // Walk around the gaps in the FPU regs
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
-        p += 5;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
-        p += 8;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
-        p += 6;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
-        p += 8;
-
-        // Work around the padding between the stmm registers as they are 16
-        // byte structs with 10 bytes of the value in each
-        for (size_t i = 0; i < 8; ++i) {
-          memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
-          p += 10;
-        }
-
         // Copy the XMM registers in a single block
         memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16);
         p += 8 * 16;
@@ -2194,24 +1891,24 @@ nub_size_t DNBArchImplI386::SetRegisterContext(const void *buf,
     memcpy(&m_state.context.gpr, p, sizeof(GPR));
     p += sizeof(GPR);
 
-    if (CPUHasAVX() || FORCE_AVX_REGS) {
-      // Walk around the gaps in the FPU regs
-      memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
-      p += 5;
-      memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
-      p += 8;
-      memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
-      p += 6;
-      memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
-      p += 8;
-
-      // Work around the padding between the stmm registers as they are 16
-      // byte structs with 10 bytes of the value in each
-      for (size_t i = 0; i < 8; ++i) {
-        memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
-        p += 10;
-      }
+    // Copy fcw through mxcsrmask as there is no padding
+    memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
+    p += 5;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
+    p += 8;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
+    p += 6;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
+    p += 8;
+
+    // Work around the padding between the stmm registers as they are 16
+    // byte structs with 10 bytes of the value in each
+    for (size_t i = 0; i < 8; ++i) {
+      memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
+      p += 10;
+    }
 
+    if (CPUHasAVX() || FORCE_AVX_REGS) {
       // Interleave the XMM and YMMH registers to make the YMM registers
       for (size_t i = 0; i < 8; ++i) {
         memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
@@ -2220,23 +1917,6 @@ nub_size_t DNBArchImplI386::SetRegisterContext(const void *buf,
         p += 16;
       }
     } else {
-      // Copy fcw through mxcsrmask as there is no padding
-      memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
-      p += 5;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
-      p += 8;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
-      p += 6;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
-      p += 8;
-
-      // Work around the padding between the stmm registers as they are 16
-      // byte structs with 10 bytes of the value in each
-      for (size_t i = 0; i < 8; ++i) {
-        memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
-        p += 10;
-      }
-
       // Copy the XMM registers in a single block
       memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16);
       p += 8 * 16;
diff --git a/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h b/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
index 5b04266881876..2e9542b051c66 100644
--- a/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
+++ b/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.h
@@ -16,7 +16,6 @@
 
 #if defined(__i386__) || defined(__x86_64__)
 
-#include "../HasAVX.h"
 #include "DNBArch.h"
 #include "MachRegisterStatesI386.h"
 
diff --git a/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp b/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
index b8d35fe2f7c90..416b21f29958a 100644
--- a/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
+++ b/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
@@ -17,7 +17,6 @@
 #include <sys/sysctl.h>
 #include <sys/types.h>
 
-#include "../HasAVX.h"
 #include "DNBLog.h"
 #include "MacOSX/x86_64/DNBArchImplX86_64.h"
 #include "MachProcess.h"
@@ -60,42 +59,64 @@ static bool ForceAVXRegs() {
 #define FORCE_AVX_REGS (0)
 #endif
 
-extern "C" bool CPUHasAVX() {
-  enum AVXPresence { eAVXUnknown = -1, eAVXNotPresent = 0, eAVXPresent = 1 };
+bool DetectHardwareFeature(const char *feature) {
+  int answer = 0;
+  size_t answer_size = sizeof(answer);
+  int error = ::sysctlbyname(feature, &answer, &answer_size, NULL, 0);
+  return error == 0 && answer != 0;
+}
+
+enum AVXPresence { eAVXUnknown = -1, eAVXNotPresent = 0, eAVXPresent = 1 };
+
+bool LogAVXAndReturn(AVXPresence has_avx, int err, const char * os_ver) {
+  DNBLogThreadedIf(LOG_THREAD,
+                   "CPUHasAVX(): g_has_avx = %i (err = %i, os_ver = %s)",
+                   has_avx, err, os_ver);
+  return (has_avx == eAVXPresent);
+}
 
+extern "C" bool CPUHasAVX() {
   static AVXPresence g_has_avx = eAVXUnknown;
-  if (g_has_avx == eAVXUnknown) {
-    g_has_avx = eAVXNotPresent;
-
-    // Only xnu-2020 or later has AVX support, any versions before
-    // this have a busted thread_get_state RPC where it would truncate
-    // the thread state buffer (<rdar://problem/10122874>). So we need to
-    // verify the kernel version number manually or disable AVX support.
-    int mib[2];
-    char buffer[1024];
-    size_t length = sizeof(buffer);
-    uint64_t xnu_version = 0;
-    mib[0] = CTL_KERN;
-    mib[1] = KERN_VERSION;
-    int err = ::sysctl(mib, 2, &buffer, &length, NULL, 0);
-    if (err == 0) {
-      const char *xnu = strstr(buffer, "xnu-");
-      if (xnu) {
-        const char *xnu_version_cstr = xnu + 4;
-        xnu_version = strtoull(xnu_version_cstr, NULL, 0);
-        if (xnu_version >= 2020 && xnu_version != ULLONG_MAX) {
-          if (::HasAVX()) {
-            g_has_avx = eAVXPresent;
-          }
-        }
-      }
-    }
-    DNBLogThreadedIf(LOG_THREAD, "CPUHasAVX(): g_has_avx = %i (err = %i, errno "
-                                 "= %i, xnu_version = %llu)",
-                     g_has_avx, err, errno, xnu_version);
+  if (g_has_avx != eAVXUnknown)
+    return LogAVXAndReturn(g_has_avx, 0, "");
+
+  g_has_avx = eAVXNotPresent;
+
+  // OS X 10.7.3 and earlier have a bug in thread_get_state that truncated the
+  // size of the return. To work around this we have to disable AVX debugging
+  // on hosts prior to 10.7.3 (<rdar://problem/10122874>).
+  int mib[2];
+  char buffer[1024];
+  size_t length = sizeof(buffer);
+  mib[0] = CTL_KERN;
+  mib[1] = KERN_OSVERSION;
+
+  // KERN_OSVERSION returns the build number which is a number signifying the
+  // major version, a capitol letter signifying the minor version, and numbers
+  // signifying the build (ex: on 10.12.3, the returned value is 16D32).
+  int err = ::sysctl(mib, 2, &buffer, &length, NULL, 0);
+  if (err != 0)
+    return LogAVXAndReturn(g_has_avx, err, "");
+
+  size_t first_letter = 0;
+  for (; first_letter < length; ++first_letter) {
+    // This is looking for the first uppercase letter
+    if (isupper(buffer[first_letter]))
+      break;
   }
-
-  return (g_has_avx == eAVXPresent);
+  char letter = buffer[first_letter];
+  buffer[first_letter] = '\0';
+  auto major_ver = strtoull(buffer, NULL, 0);
+  buffer[first_letter] = letter;
+
+  // In this check we're looking to see that our major and minor version numer
+  // was >= 11E, which is the 10.7.4 release.
+  if (major_ver < 11 || (major_ver == 11 && letter < 'E'))
+    return LogAVXAndReturn(g_has_avx, err, buffer);
+  if (DetectHardwareFeature("hw.optional.avx1_0"))
+    g_has_avx = eAVXPresent;
+
+  return LogAVXAndReturn(g_has_avx, err, buffer);
 }
 
 uint64_t DNBArchImplX86_64::GetPC(uint64_t failValue) {
@@ -238,61 +259,65 @@ kern_return_t DNBArchImplX86_64::GetGPRState(bool force) {
 kern_return_t DNBArchImplX86_64::GetFPUState(bool force) {
   if (force || m_state.GetError(e_regSetFPU, Read)) {
     if (DEBUG_FPU_REGS) {
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        m_state.context.fpu.avx.__fpu_reserved[0] = -1;
-        m_state.context.fpu.avx.__fpu_reserved[1] = -1;
-        *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
-        *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
-        m_state.context.fpu.avx.__fpu_ftw = 1;
-        m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
-        m_state.context.fpu.avx.__fpu_fop = 2;
-        m_state.context.fpu.avx.__fpu_ip = 3;
-        m_state.context.fpu.avx.__fpu_cs = 4;
-        m_state.context.fpu.avx.__fpu_rsrv2 = UINT8_MAX;
-        m_state.context.fpu.avx.__fpu_dp = 5;
-        m_state.context.fpu.avx.__fpu_ds = 6;
-        m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
-        m_state.context.fpu.avx.__fpu_mxcsr = 8;
-        m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
-        int i;
-        for (i = 0; i < 16; ++i) {
-          if (i < 10) {
-            m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
-            m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
-            m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
-            m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
-            m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
-            m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
-            m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
-            m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
-          } else {
-            m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
-          }
-
-          m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E' + 2 * i;
-          m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F' + 2 * i;
+      m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
+      m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
+      *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
+      *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
+      m_state.context.fpu.no_avx.__fpu_ftw = 1;
+      m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
+      m_state.context.fpu.no_avx.__fpu_fop = 2;
+      m_state.context.fpu.no_avx.__fpu_ip = 3;
+      m_state.context.fpu.no_avx.__fpu_cs = 4;
+      m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
+      m_state.context.fpu.no_avx.__fpu_dp = 6;
+      m_state.context.fpu.no_avx.__fpu_ds = 7;
+      m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
+      m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
+      m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
+      for (int i = 0; i < 16; ++i) {
+        if (i < 10) {
+          m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
+          m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
+          m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
+          m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
+          m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
+          m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
+          m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
+          m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
+        } else {
+          m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
+          m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
+        }
 
+        m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
+        m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
+        m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
+        m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
+        m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
+        m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
+        m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
+        m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
+        m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8';
+        m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9';
+        m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A';
+        m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B';
+        m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C';
+        m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D';
+        m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E';
+        m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F';
+      }
+      for (int i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
+        m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
+      m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
+      
+      if (CPUHasAVX() || FORCE_AVX_REGS) {
+        for (int i = 0; i < 16; ++i) {
           m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0' + i;
           m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1' + i;
           m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2' + i;
@@ -310,97 +335,25 @@ kern_return_t DNBArchImplX86_64::GetFPUState(bool force) {
           m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E' + i;
           m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F' + i;
         }
-        for (i = 0; i < sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
-          m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
-        m_state.context.fpu.avx.__fpu_reserved1 = -1;
-        for (i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
+        for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
           m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
-        m_state.SetError(e_regSetFPU, Read, 0);
-      } else {
-        m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
-        m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
-        *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
-        *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
-        m_state.context.fpu.no_avx.__fpu_ftw = 1;
-        m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
-        m_state.context.fpu.no_avx.__fpu_fop = 2;
-        m_state.context.fpu.no_avx.__fpu_ip = 3;
-        m_state.context.fpu.no_avx.__fpu_cs = 4;
-        m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
-        m_state.context.fpu.no_avx.__fpu_dp = 6;
-        m_state.context.fpu.no_avx.__fpu_ds = 7;
-        m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
-        m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
-        m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
-        int i;
-        for (i = 0; i < 16; ++i) {
-          if (i < 10) {
-            m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
-            m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
-            m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
-            m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
-            m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
-            m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
-            m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
-            m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
-          } else {
-            m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
-            m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
-          }
-
-          m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
-          m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
-          m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
-          m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
-          m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
-          m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
-          m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
-          m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
-          m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8';
-          m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9';
-          m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A';
-          m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B';
-          m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C';
-          m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D';
-          m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E';
-          m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F';
-        }
-        for (i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
-          m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
-        m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
-        m_state.SetError(e_regSetFPU, Read, 0);
       }
+      m_state.SetError(e_regSetFPU, Read, 0);
     } else {
+      mach_msg_type_number_t count = e_regSetWordSizeFPU;
+      int flavor = __x86_64_FLOAT_STATE;
       if (CPUHasAVX() || FORCE_AVX_REGS) {
-        mach_msg_type_number_t count = e_regSetWordSizeAVX;
-        m_state.SetError(e_regSetFPU, Read,
-                         ::thread_get_state(
-                             m_thread->MachPortNumber(), __x86_64_AVX_STATE,
-                             (thread_state_t)&m_state.context.fpu.avx, &count));
-        DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, "
-                                     "%u (%u passed in) carp) => 0x%8.8x",
-                         m_thread->MachPortNumber(), __x86_64_AVX_STATE,
-                         (uint32_t)count, e_regSetWordSizeAVX,
-                         m_state.GetError(e_regSetFPU, Read));
-      } else {
-        mach_msg_type_number_t count = e_regSetWordSizeFPU;
-        m_state.SetError(
-            e_regSetFPU, Read,
-            ::thread_get_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE,
-                               (thread_state_t)&m_state.context.fpu.no_avx,
-                               &count));
-        DNBLogThreadedIf(LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, "
-                                     "%u (%u passed in) => 0x%8.8x",
-                         m_thread->MachPortNumber(), __x86_64_FLOAT_STATE,
-                         (uint32_t)count, e_regSetWordSizeFPU,
-                         m_state.GetError(e_regSetFPU, Read));
+        count = e_regSetWordSizeAVX;
+        flavor = __x86_64_AVX_STATE;
       }
+      m_state.SetError(e_regSetFPU, Read,
+                       ::thread_get_state(m_thread->MachPortNumber(), flavor,
+                                          (thread_state_t)&m_state.context.fpu,
+                                          &count));
+      DNBLogThreadedIf(LOG_THREAD,
+                       "::thread_get_state (0x%4.4x, %u, &fpu, %u => 0x%8.8x",
+                       m_thread->MachPortNumber(), flavor, (uint32_t)count,
+                       m_state.GetError(e_regSetFPU, Read));
     }
   }
   return m_state.GetError(e_regSetFPU, Read);
@@ -458,21 +411,17 @@ kern_return_t DNBArchImplX86_64::SetFPUState() {
     m_state.SetError(e_regSetFPU, Write, 0);
     return m_state.GetError(e_regSetFPU, Write);
   } else {
+    int flavor = __x86_64_FLOAT_STATE;
+    mach_msg_type_number_t count = e_regSetWordSizeFPU;
     if (CPUHasAVX() || FORCE_AVX_REGS) {
-      m_state.SetError(
-          e_regSetFPU, Write,
-          ::thread_set_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE,
-                             (thread_state_t)&m_state.context.fpu.avx,
-                             e_regSetWordSizeAVX));
-      return m_state.GetError(e_regSetFPU, Write);
-    } else {
-      m_state.SetError(
-          e_regSetFPU, Write,
-          ::thread_set_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE,
-                             (thread_state_t)&m_state.context.fpu.no_avx,
-                             e_regSetWordSizeFPU));
-      return m_state.GetError(e_regSetFPU, Write);
+      flavor = __x86_64_AVX_STATE;
+      count = e_regSetWordSizeAVX;
     }
+    m_state.SetError(
+          e_regSetFPU, Write,
+          ::thread_set_state(m_thread->MachPortNumber(), flavor,
+                             (thread_state_t)&m_state.context.fpu, count));
+   return m_state.GetError(e_regSetFPU, Write);
   }
 }
 
@@ -1814,163 +1763,96 @@ bool DNBArchImplX86_64::GetRegisterValue(uint32_t set, uint32_t reg,
       break;
 
     case e_regSetFPU:
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        switch (reg) {
-        case fpu_fcw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw));
-          return true;
-        case fpu_fsw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw));
-          return true;
-        case fpu_ftw:
-          value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw;
-          return true;
-        case fpu_fop:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_fop;
-          return true;
-        case fpu_ip:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_ip;
-          return true;
-        case fpu_cs:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_cs;
-          return true;
-        case fpu_dp:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_dp;
-          return true;
-        case fpu_ds:
-          value->value.uint16 = m_state.context.fpu.avx.__fpu_ds;
-          return true;
-        case fpu_mxcsr:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr;
-          return true;
-        case fpu_mxcsrmask:
-          value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask;
-          return true;
-
-        case fpu_stmm0:
-        case fpu_stmm1:
-        case fpu_stmm2:
-        case fpu_stmm3:
-        case fpu_stmm4:
-        case fpu_stmm5:
-        case fpu_stmm6:
-        case fpu_stmm7:
-          memcpy(&value->value.uint8,
-                 &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
-          return true;
-
-        case fpu_xmm0:
-        case fpu_xmm1:
-        case fpu_xmm2:
-        case fpu_xmm3:
-        case fpu_xmm4:
-        case fpu_xmm5:
-        case fpu_xmm6:
-        case fpu_xmm7:
-        case fpu_xmm8:
-        case fpu_xmm9:
-        case fpu_xmm10:
-        case fpu_xmm11:
-        case fpu_xmm12:
-        case fpu_xmm13:
-        case fpu_xmm14:
-        case fpu_xmm15:
-          memcpy(&value->value.uint8,
-                 &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
-          return true;
-
-        case fpu_ymm0:
-        case fpu_ymm1:
-        case fpu_ymm2:
-        case fpu_ymm3:
-        case fpu_ymm4:
-        case fpu_ymm5:
-        case fpu_ymm6:
-        case fpu_ymm7:
-        case fpu_ymm8:
-        case fpu_ymm9:
-        case fpu_ymm10:
-        case fpu_ymm11:
-        case fpu_ymm12:
-        case fpu_ymm13:
-        case fpu_ymm14:
-        case fpu_ymm15:
-          memcpy(&value->value.uint8,
-                 &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16);
-          memcpy((&value->value.uint8) + 16,
-                 &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16);
-          return true;
-        }
-      } else {
-        switch (reg) {
-        case fpu_fcw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw));
-          return true;
-        case fpu_fsw:
-          value->value.uint16 =
-              *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
-          return true;
-        case fpu_ftw:
-          value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
-          return true;
-        case fpu_fop:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
-          return true;
-        case fpu_ip:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip;
-          return true;
-        case fpu_cs:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs;
-          return true;
-        case fpu_dp:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp;
-          return true;
-        case fpu_ds:
-          value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds;
-          return true;
-        case fpu_mxcsr:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr;
-          return true;
-        case fpu_mxcsrmask:
-          value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask;
-          return true;
-
-        case fpu_stmm0:
-        case fpu_stmm1:
-        case fpu_stmm2:
-        case fpu_stmm3:
-        case fpu_stmm4:
-        case fpu_stmm5:
-        case fpu_stmm6:
-        case fpu_stmm7:
-          memcpy(&value->value.uint8,
-                 &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0),
-                 10);
-          return true;
-
-        case fpu_xmm0:
-        case fpu_xmm1:
-        case fpu_xmm2:
-        case fpu_xmm3:
-        case fpu_xmm4:
-        case fpu_xmm5:
-        case fpu_xmm6:
-        case fpu_xmm7:
-        case fpu_xmm8:
-        case fpu_xmm9:
-        case fpu_xmm10:
-        case fpu_xmm11:
-        case fpu_xmm12:
-        case fpu_xmm13:
-        case fpu_xmm14:
-        case fpu_xmm15:
-          memcpy(&value->value.uint8,
-                 &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
-          return true;
-        }
+      if (reg > fpu_xmm15 && !(CPUHasAVX() || FORCE_AVX_REGS))
+        return false;
+      switch (reg) {
+
+      case fpu_fcw:
+        value->value.uint16 =
+            *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw));
+        return true;
+      case fpu_fsw:
+        value->value.uint16 =
+            *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
+        return true;
+      case fpu_ftw:
+        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        return true;
+      case fpu_fop:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
+        return true;
+      case fpu_ip:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip;
+        return true;
+      case fpu_cs:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs;
+        return true;
+      case fpu_dp:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp;
+        return true;
+      case fpu_ds:
+        value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds;
+        return true;
+      case fpu_mxcsr:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr;
+        return true;
+      case fpu_mxcsrmask:
+        value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask;
+        return true;
+
+      case fpu_stmm0:
+      case fpu_stmm1:
+      case fpu_stmm2:
+      case fpu_stmm3:
+      case fpu_stmm4:
+      case fpu_stmm5:
+      case fpu_stmm6:
+      case fpu_stmm7:
+        memcpy(&value->value.uint8,
+               &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
+        return true;
+
+      case fpu_xmm0:
+      case fpu_xmm1:
+      case fpu_xmm2:
+      case fpu_xmm3:
+      case fpu_xmm4:
+      case fpu_xmm5:
+      case fpu_xmm6:
+      case fpu_xmm7:
+      case fpu_xmm8:
+      case fpu_xmm9:
+      case fpu_xmm10:
+      case fpu_xmm11:
+      case fpu_xmm12:
+      case fpu_xmm13:
+      case fpu_xmm14:
+      case fpu_xmm15:
+        memcpy(&value->value.uint8,
+               &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
+        return true;
+
+      case fpu_ymm0:
+      case fpu_ymm1:
+      case fpu_ymm2:
+      case fpu_ymm3:
+      case fpu_ymm4:
+      case fpu_ymm5:
+      case fpu_ymm6:
+      case fpu_ymm7:
+      case fpu_ymm8:
+      case fpu_ymm9:
+      case fpu_ymm10:
+      case fpu_ymm11:
+      case fpu_ymm12:
+      case fpu_ymm13:
+      case fpu_ymm14:
+      case fpu_ymm15:
+        memcpy(&value->value.uint8,
+               &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16);
+        memcpy((&value->value.uint8) + 16,
+               &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16);
+        return true;
       }
       break;
 
@@ -2035,188 +1917,108 @@ bool DNBArchImplX86_64::SetRegisterValue(uint32_t set, uint32_t reg,
         success = true;
       }
       break;
-
+      if (reg > fpu_xmm15 && !(CPUHasAVX() || FORCE_AVX_REGS))
+        return false;
     case e_regSetFPU:
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        switch (reg) {
-        case fpu_fcw:
-          *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_fsw:
-          *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_ftw:
-          m_state.context.fpu.avx.__fpu_ftw = value->value.uint8;
-          success = true;
-          break;
-        case fpu_fop:
-          m_state.context.fpu.avx.__fpu_fop = value->value.uint16;
-          success = true;
-          break;
-        case fpu_ip:
-          m_state.context.fpu.avx.__fpu_ip = value->value.uint32;
-          success = true;
-          break;
-        case fpu_cs:
-          m_state.context.fpu.avx.__fpu_cs = value->value.uint16;
-          success = true;
-          break;
-        case fpu_dp:
-          m_state.context.fpu.avx.__fpu_dp = value->value.uint32;
-          success = true;
-          break;
-        case fpu_ds:
-          m_state.context.fpu.avx.__fpu_ds = value->value.uint16;
-          success = true;
-          break;
-        case fpu_mxcsr:
-          m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32;
-          success = true;
-          break;
-        case fpu_mxcsrmask:
-          m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32;
-          success = true;
-          break;
-
-        case fpu_stmm0:
-        case fpu_stmm1:
-        case fpu_stmm2:
-        case fpu_stmm3:
-        case fpu_stmm4:
-        case fpu_stmm5:
-        case fpu_stmm6:
-        case fpu_stmm7:
-          memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0),
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-
-        case fpu_xmm0:
-        case fpu_xmm1:
-        case fpu_xmm2:
-        case fpu_xmm3:
-        case fpu_xmm4:
-        case fpu_xmm5:
-        case fpu_xmm6:
-        case fpu_xmm7:
-        case fpu_xmm8:
-        case fpu_xmm9:
-        case fpu_xmm10:
-        case fpu_xmm11:
-        case fpu_xmm12:
-        case fpu_xmm13:
-        case fpu_xmm14:
-        case fpu_xmm15:
-          memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0),
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-
-        case fpu_ymm0:
-        case fpu_ymm1:
-        case fpu_ymm2:
-        case fpu_ymm3:
-        case fpu_ymm4:
-        case fpu_ymm5:
-        case fpu_ymm6:
-        case fpu_ymm7:
-        case fpu_ymm8:
-        case fpu_ymm9:
-        case fpu_ymm10:
-        case fpu_ymm11:
-        case fpu_ymm12:
-        case fpu_ymm13:
-        case fpu_ymm14:
-        case fpu_ymm15:
-          memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0),
-                 &value->value.uint8, 16);
-          memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0),
-                 (&value->value.uint8) + 16, 16);
-          return true;
-        }
-      } else {
-        switch (reg) {
-        case fpu_fcw:
-          *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_fsw:
-          *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) =
-              value->value.uint16;
-          success = true;
-          break;
-        case fpu_ftw:
-          m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
-          success = true;
-          break;
-        case fpu_fop:
-          m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16;
-          success = true;
-          break;
-        case fpu_ip:
-          m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32;
-          success = true;
-          break;
-        case fpu_cs:
-          m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16;
-          success = true;
-          break;
-        case fpu_dp:
-          m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32;
-          success = true;
-          break;
-        case fpu_ds:
-          m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16;
-          success = true;
-          break;
-        case fpu_mxcsr:
-          m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32;
-          success = true;
-          break;
-        case fpu_mxcsrmask:
-          m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32;
-          success = true;
-          break;
-
-        case fpu_stmm0:
-        case fpu_stmm1:
-        case fpu_stmm2:
-        case fpu_stmm3:
-        case fpu_stmm4:
-        case fpu_stmm5:
-        case fpu_stmm6:
-        case fpu_stmm7:
-          memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0),
-                 &value->value.uint8, 10);
-          success = true;
-          break;
-
-        case fpu_xmm0:
-        case fpu_xmm1:
-        case fpu_xmm2:
-        case fpu_xmm3:
-        case fpu_xmm4:
-        case fpu_xmm5:
-        case fpu_xmm6:
-        case fpu_xmm7:
-        case fpu_xmm8:
-        case fpu_xmm9:
-        case fpu_xmm10:
-        case fpu_xmm11:
-        case fpu_xmm12:
-        case fpu_xmm13:
-        case fpu_xmm14:
-        case fpu_xmm15:
-          memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0),
-                 &value->value.uint8, 16);
-          success = true;
-          break;
-        }
+      switch (reg) {
+      case fpu_fcw:
+        *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) =
+            value->value.uint16;
+        success = true;
+        break;
+      case fpu_fsw:
+        *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) =
+            value->value.uint16;
+        success = true;
+        break;
+      case fpu_ftw:
+        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        success = true;
+        break;
+      case fpu_fop:
+        m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16;
+        success = true;
+        break;
+      case fpu_ip:
+        m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32;
+        success = true;
+        break;
+      case fpu_cs:
+        m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16;
+        success = true;
+        break;
+      case fpu_dp:
+        m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32;
+        success = true;
+        break;
+      case fpu_ds:
+        m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16;
+        success = true;
+        break;
+      case fpu_mxcsr:
+        m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32;
+        success = true;
+        break;
+      case fpu_mxcsrmask:
+        m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32;
+        success = true;
+        break;
+
+      case fpu_stmm0:
+      case fpu_stmm1:
+      case fpu_stmm2:
+      case fpu_stmm3:
+      case fpu_stmm4:
+      case fpu_stmm5:
+      case fpu_stmm6:
+      case fpu_stmm7:
+        memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0),
+               &value->value.uint8, 10);
+        success = true;
+        break;
+
+      case fpu_xmm0:
+      case fpu_xmm1:
+      case fpu_xmm2:
+      case fpu_xmm3:
+      case fpu_xmm4:
+      case fpu_xmm5:
+      case fpu_xmm6:
+      case fpu_xmm7:
+      case fpu_xmm8:
+      case fpu_xmm9:
+      case fpu_xmm10:
+      case fpu_xmm11:
+      case fpu_xmm12:
+      case fpu_xmm13:
+      case fpu_xmm14:
+      case fpu_xmm15:
+        memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0),
+               &value->value.uint8, 16);
+        success = true;
+        break;
+
+      case fpu_ymm0:
+      case fpu_ymm1:
+      case fpu_ymm2:
+      case fpu_ymm3:
+      case fpu_ymm4:
+      case fpu_ymm5:
+      case fpu_ymm6:
+      case fpu_ymm7:
+      case fpu_ymm8:
+      case fpu_ymm9:
+      case fpu_ymm10:
+      case fpu_ymm11:
+      case fpu_ymm12:
+      case fpu_ymm13:
+      case fpu_ymm14:
+      case fpu_ymm15:
+        memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0),
+               &value->value.uint8, 16);
+        memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0),
+               (&value->value.uint8) + 16, 16);
+        return true;
       }
       break;
 
@@ -2302,24 +2104,24 @@ nub_size_t DNBArchImplX86_64::GetRegisterContext(void *buf,
       memcpy(p, &m_state.context.gpr, sizeof(GPR));
       p += sizeof(GPR);
 
-      if (CPUHasAVX() || FORCE_AVX_REGS) {
-        // Walk around the gaps in the FPU regs
-        memcpy(p, &m_state.context.fpu.avx.__fpu_fcw, 5);
-        p += 5;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_fop, 8);
-        p += 8;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_dp, 6);
-        p += 6;
-        memcpy(p, &m_state.context.fpu.avx.__fpu_mxcsr, 8);
-        p += 8;
-
-        // Work around the padding between the stmm registers as they are 16
-        // byte structs with 10 bytes of the value in each
-        for (size_t i = 0; i < 8; ++i) {
-          memcpy(p, &m_state.context.fpu.avx.__fpu_stmm0 + i, 10);
-          p += 10;
-        }
+      // Walk around the gaps in the FPU regs
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
+      p += 5;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
+      p += 8;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
+      p += 6;
+      memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
+      p += 8;
+
+      // Work around the padding between the stmm registers as they are 16
+      // byte structs with 10 bytes of the value in each
+      for (size_t i = 0; i < 8; ++i) {
+        memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
+        p += 10;
+      }
 
+      if (CPUHasAVX() || FORCE_AVX_REGS) {
         // Interleave the XMM and YMMH registers to make the YMM registers
         for (size_t i = 0; i < 16; ++i) {
           memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16);
@@ -2328,23 +2130,6 @@ nub_size_t DNBArchImplX86_64::GetRegisterContext(void *buf,
           p += 16;
         }
       } else {
-        // Walk around the gaps in the FPU regs
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5);
-        p += 5;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8);
-        p += 8;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6);
-        p += 6;
-        memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8);
-        p += 8;
-
-        // Work around the padding between the stmm registers as they are 16
-        // byte structs with 10 bytes of the value in each
-        for (size_t i = 0; i < 8; ++i) {
-          memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10);
-          p += 10;
-        }
-
         // Copy the XMM registers in a single block
         memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 16 * 16);
         p += 16 * 16;
@@ -2384,24 +2169,24 @@ nub_size_t DNBArchImplX86_64::SetRegisterContext(const void *buf,
     memcpy(&m_state.context.gpr, p, sizeof(GPR));
     p += sizeof(GPR);
 
-    if (CPUHasAVX() || FORCE_AVX_REGS) {
-      // Walk around the gaps in the FPU regs
-      memcpy(&m_state.context.fpu.avx.__fpu_fcw, p, 5);
-      p += 5;
-      memcpy(&m_state.context.fpu.avx.__fpu_fop, p, 8);
-      p += 8;
-      memcpy(&m_state.context.fpu.avx.__fpu_dp, p, 6);
-      p += 6;
-      memcpy(&m_state.context.fpu.avx.__fpu_mxcsr, p, 8);
-      p += 8;
-
-      // Work around the padding between the stmm registers as they are 16
-      // byte structs with 10 bytes of the value in each
-      for (size_t i = 0; i < 8; ++i) {
-        memcpy(&m_state.context.fpu.avx.__fpu_stmm0 + i, p, 10);
-        p += 10;
-      }
+    // Copy fcw through mxcsrmask as there is no padding
+    memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
+    p += 5;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
+    p += 8;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
+    p += 6;
+    memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
+    p += 8;
+
+    // Work around the padding between the stmm registers as they are 16
+    // byte structs with 10 bytes of the value in each
+    for (size_t i = 0; i < 8; ++i) {
+      memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
+      p += 10;
+    }
 
+    if (CPUHasAVX() || FORCE_AVX_REGS) {
       // Interleave the XMM and YMMH registers to make the YMM registers
       for (size_t i = 0; i < 16; ++i) {
         memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16);
@@ -2410,23 +2195,6 @@ nub_size_t DNBArchImplX86_64::SetRegisterContext(const void *buf,
         p += 16;
       }
     } else {
-      // Copy fcw through mxcsrmask as there is no padding
-      memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
-      p += 5;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
-      p += 8;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);
-      p += 6;
-      memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8);
-      p += 8;
-
-      // Work around the padding between the stmm registers as they are 16
-      // byte structs with 10 bytes of the value in each
-      for (size_t i = 0; i < 8; ++i) {
-        memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10);
-        p += 10;
-      }
-
       // Copy the XMM registers in a single block
       memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 16 * 16);
       p += 16 * 16;
diff --git a/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h b/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h
index 5ed67611e6eff..60e61262ab694 100644
--- a/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h
+++ b/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h
@@ -86,7 +86,7 @@ typedef struct {
 typedef struct { uint8_t __xmm_reg[16]; } __x86_64_xmm_reg;
 
 typedef struct {
-  int32_t __fpu_reserved[2];
+  uint32_t __fpu_reserved[2];
   __x86_64_fp_control_t __fpu_fcw;
   __x86_64_fp_status_t __fpu_fsw;
   uint8_t __fpu_ftw;
@@ -125,7 +125,7 @@ typedef struct {
   __x86_64_xmm_reg __fpu_xmm14;
   __x86_64_xmm_reg __fpu_xmm15;
   uint8_t __fpu_rsrv4[6 * 16];
-  int32_t __fpu_reserved1;
+  uint32_t __fpu_reserved1;
 } __x86_64_float_state_t;
 
 typedef struct {
diff --git a/tools/debugserver/source/RNBRemote.cpp b/tools/debugserver/source/RNBRemote.cpp
index 71c6f717cadf1..4c1f27eb1cb86 100644
--- a/tools/debugserver/source/RNBRemote.cpp
+++ b/tools/debugserver/source/RNBRemote.cpp
@@ -3611,15 +3611,10 @@ rnb_err_t RNBRemote::HandlePacket_qSupported(const char *p) {
   snprintf(buf, sizeof(buf), "qXfer:features:read+;PacketSize=%x;qEcho+",
            max_packet_size);
 
-  // By default, don't enable compression.  It's only worth doing when we are
-  // working
-  // with a low speed communication channel.
   bool enable_compression = false;
   (void)enable_compression;
 
-// Enable compression when debugserver is running on a watchOS device where
-// communication may be over Bluetooth.
-#if defined(TARGET_OS_WATCH) && TARGET_OS_WATCH == 1
+#if (defined (TARGET_OS_WATCH) && TARGET_OS_WATCHOS == 1) || (defined (TARGET_OS_IOS) && TARGET_OS_IOS == 1) || (defined (TARGET_OS_TVOS) && TARGET_OS_TVOS == 1)
   enable_compression = true;
 #endif