4 files changed, 69 insertions, 14 deletions
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
index 4b9a326f608f8..0280d56a8fa70 100644
--- a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm
new file mode 100644
index 0000000000000..6d5fbcbb38035
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm
@@ -0,0 +1,33 @@
+;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuFlushTlb
+  AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+;  VOID
+;  );
+;
+CpuFlushTlb
+  tlbi  vmalle1                 // Invalidate Inst TLB and Data TLB
+  dsb   sy
+  isb
+  ret
+
+  END
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
index b08bdfb8f39de..4d55abde0d20a 100644
--- a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm
new file mode 100644
index 0000000000000..f7bbf8568a89c
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; CpuSleep() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuSleep
+  AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+;  Places the CPU in a sleep state until an interrupt is received.
+;
+;  Places the CPU in a sleep state until an interrupt is received. If interrupts
+;  are disabled prior to calling this function, then the CPU will be placed in a
+;  sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+;  VOID
+;  );
+;
+
+CpuSleep
+  wfi
+  ret
+
+  END