diff options
Diffstat (limited to 'contrib/gcc/config/arm/arm.c')
| -rw-r--r-- | contrib/gcc/config/arm/arm.c | 8969 |
1 files changed, 5627 insertions, 3342 deletions
diff --git a/contrib/gcc/config/arm/arm.c b/contrib/gcc/config/arm/arm.c index 2f0eaedbe13e6..dc7aa77b6d6a5 100644 --- a/contrib/gcc/config/arm/arm.c +++ b/contrib/gcc/config/arm/arm.c @@ -1,6 +1,6 @@ /* Output routines for GCC for ARM. Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, - 2002, 2003, 2004, 2005 Free Software Foundation, Inc. + 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -19,9 +19,9 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - + the Free Software Foundation, 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + #include "config.h" #include "system.h" #include "coretypes.h" @@ -51,6 +51,7 @@ #include "target.h" #include "target-def.h" #include "debug.h" +#include "langhooks.h" /* Forward definitions of types. */ typedef struct minipool_node Mnode; @@ -59,34 +60,32 @@ typedef struct minipool_fixup Mfix; const struct attribute_spec arm_attribute_table[]; /* Forward function declarations. */ +static arm_stack_offsets *arm_get_frame_offsets (void); static void arm_add_gc_roots (void); -static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT, - rtx, rtx, int, int); +static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, + HOST_WIDE_INT, rtx, rtx, int, int); static unsigned bit_count (unsigned long); static int arm_address_register_rtx_p (rtx, int); -static int arm_legitimate_index_p (enum machine_mode, rtx, int); +static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); inline static int thumb_index_register_rtx_p (rtx, int); +static int thumb_far_jump_used_p (void); +static bool thumb_force_lr_save (void); static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); -static rtx emit_multi_reg_push (int); static rtx emit_sfm (int, int); +static int arm_size_return_regs (void); #ifndef AOF_ASSEMBLER static bool arm_assemble_integer (rtx, unsigned int, int); #endif static const char *fp_const_from_val (REAL_VALUE_TYPE *); static arm_cc get_arm_condition_code (rtx); -static void init_fpa_table (void); static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); static rtx is_jump_table (rtx); static const char *output_multi_immediate (rtx *, const char *, const char *, int, HOST_WIDE_INT); -static void print_multi_reg (FILE *, const char *, int, int); static const char *shift_op (rtx, HOST_WIDE_INT *); static struct machine_function *arm_init_machine_status (void); -static int number_of_first_bit_set (int); -static void replace_symbols_in_block (tree, rtx, rtx); -static void thumb_exit (FILE *, int, rtx); -static void thumb_pushpop (FILE *, int, int, int *, int); +static void thumb_exit (FILE *, int); static rtx is_jump_table (rtx); static HOST_WIDE_INT get_jump_table_size (rtx); static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); @@ -110,13 +109,15 @@ static unsigned long arm_isr_value (tree); static unsigned long arm_compute_func_type (void); static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES +static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); +#endif static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); static int arm_comp_type_attributes (tree, tree); static void arm_set_default_type_attributes (tree); static int arm_adjust_cost (rtx, rtx, rtx, int); -static int arm_use_dfa_pipeline_interface (void); static int count_insns_for_constant (HOST_WIDE_INT, int); static int arm_get_strip_length (int); static bool arm_function_ok_for_sibcall (tree, tree); @@ -124,7 +125,11 @@ static void arm_internal_label (FILE *, const char *, unsigned long); static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); -static bool arm_rtx_costs (rtx, int, int, int *); +static bool arm_size_rtx_costs (rtx, int, int, int *); +static bool arm_slowmul_rtx_costs (rtx, int, int, int *); +static bool arm_fastmul_rtx_costs (rtx, int, int, int *); +static bool arm_xscale_rtx_costs (rtx, int, int, int *); +static bool arm_9e_rtx_costs (rtx, int, int, int *); static int arm_address_cost (rtx); static bool arm_memory_load_p (rtx); static bool arm_cirrus_insn_p (rtx); @@ -136,24 +141,60 @@ static rtx safe_vector_operand (rtx, enum machine_mode); static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static void emit_constant_insn (rtx cond, rtx pattern); +static rtx emit_set_insn (rtx, rtx); +static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, + tree, bool); #ifdef OBJECT_FORMAT_ELF -static void arm_elf_asm_named_section (const char *, unsigned int); +static void arm_elf_asm_constructor (rtx, int); #endif #ifndef ARM_PE static void arm_encode_section_info (tree, rtx, int); #endif + +static void arm_file_end (void); + #ifdef AOF_ASSEMBLER static void aof_globalize_label (FILE *, const char *); static void aof_dump_imports (FILE *); static void aof_dump_pic_table (FILE *); static void aof_file_start (void); static void aof_file_end (void); +static void aof_asm_init_sections (void); #endif +static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, + tree, int *, int); +static bool arm_pass_by_reference (CUMULATIVE_ARGS *, + enum machine_mode, tree, bool); +static bool arm_promote_prototypes (tree); +static bool arm_default_short_enums (void); +static bool arm_align_anon_bitfield (void); +static bool arm_return_in_msb (tree); +static bool arm_must_pass_in_stack (enum machine_mode, tree); +#ifdef TARGET_UNWIND_INFO +static void arm_unwind_emit (FILE *, rtx); +static bool arm_output_ttype (rtx); +#endif + +static tree arm_cxx_guard_type (void); +static bool arm_cxx_guard_mask_bit (void); +static tree arm_get_cookie_size (tree); +static bool arm_cookie_has_size (void); +static bool arm_cxx_cdtor_returns_this (void); +static bool arm_cxx_key_method_may_be_inline (void); +static void arm_cxx_determine_class_data_visibility (tree); +static bool arm_cxx_class_data_always_comdat (void); +static bool arm_cxx_use_aeabi_atexit (void); +static void arm_init_libfuncs (void); +static bool arm_handle_option (size_t, const char *, int); +static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); +static bool arm_cannot_copy_insn_p (rtx); +static bool arm_tls_symbol_p (rtx x); /* Initialize the GCC target structure. */ -#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES #undef TARGET_MERGE_DECL_ATTRIBUTES #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes #endif @@ -161,6 +202,9 @@ static void aof_file_end (void); #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE arm_attribute_table +#undef TARGET_ASM_FILE_END +#define TARGET_ASM_FILE_END arm_file_end + #ifdef AOF_ASSEMBLER #undef TARGET_ASM_BYTE_OP #define TARGET_ASM_BYTE_OP "\tDCB\t" @@ -187,6 +231,11 @@ static void aof_file_end (void); #undef TARGET_ASM_FUNCTION_EPILOGUE #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) +#undef TARGET_HANDLE_OPTION +#define TARGET_HANDLE_OPTION arm_handle_option + #undef TARGET_COMP_TYPE_ATTRIBUTES #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes @@ -196,9 +245,6 @@ static void aof_file_end (void); #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST arm_adjust_cost -#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE -#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface - #undef TARGET_ENCODE_SECTION_INFO #ifdef ARM_PE #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info @@ -220,11 +266,17 @@ static void aof_file_end (void); #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall +/* This will be overridden in arm_override_options. */ #undef TARGET_RTX_COSTS -#define TARGET_RTX_COSTS arm_rtx_costs +#define TARGET_RTX_COSTS arm_slowmul_rtx_costs #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST arm_address_cost +#undef TARGET_SHIFT_TRUNCATION_MASK +#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask +#undef TARGET_VECTOR_MODE_SUPPORTED_P +#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p + #undef TARGET_MACHINE_DEPENDENT_REORG #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg @@ -233,6 +285,89 @@ static void aof_file_end (void); #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN arm_expand_builtin +#undef TARGET_INIT_LIBFUNCS +#define TARGET_INIT_LIBFUNCS arm_init_libfuncs + +#undef TARGET_PROMOTE_FUNCTION_ARGS +#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true +#undef TARGET_PROMOTE_FUNCTION_RETURN +#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true +#undef TARGET_PROMOTE_PROTOTYPES +#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes +#undef TARGET_PASS_BY_REFERENCE +#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference +#undef TARGET_ARG_PARTIAL_BYTES +#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes + +#undef TARGET_SETUP_INCOMING_VARARGS +#define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs + +#undef TARGET_DEFAULT_SHORT_ENUMS +#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums + +#undef TARGET_ALIGN_ANON_BITFIELD +#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield + +#undef TARGET_NARROW_VOLATILE_BITFIELD +#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false + +#undef TARGET_CXX_GUARD_TYPE +#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type + +#undef TARGET_CXX_GUARD_MASK_BIT +#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit + +#undef TARGET_CXX_GET_COOKIE_SIZE +#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size + +#undef TARGET_CXX_COOKIE_HAS_SIZE +#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size + +#undef TARGET_CXX_CDTOR_RETURNS_THIS +#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this + +#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE +#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline + +#undef TARGET_CXX_USE_AEABI_ATEXIT +#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit + +#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY +#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ + arm_cxx_determine_class_data_visibility + +#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT +#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat + +#undef TARGET_RETURN_IN_MSB +#define TARGET_RETURN_IN_MSB arm_return_in_msb + +#undef TARGET_MUST_PASS_IN_STACK +#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack + +#ifdef TARGET_UNWIND_INFO +#undef TARGET_UNWIND_EMIT +#define TARGET_UNWIND_EMIT arm_unwind_emit + +/* EABI unwinding tables use a different format for the typeinfo tables. */ +#undef TARGET_ASM_TTYPE +#define TARGET_ASM_TTYPE arm_output_ttype + +#undef TARGET_ARM_EABI_UNWINDER +#define TARGET_ARM_EABI_UNWINDER true +#endif /* TARGET_UNWIND_INFO */ + +#undef TARGET_CANNOT_COPY_INSN_P +#define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p + +#ifdef HAVE_AS_TLS +#undef TARGET_HAVE_TLS +#define TARGET_HAVE_TLS true +#endif + +#undef TARGET_CANNOT_FORCE_CONST_MEM +#define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -252,25 +387,37 @@ int making_const_table; stored from the compare operation. */ rtx arm_compare_op0, arm_compare_op1; -/* What type of floating point are we tuning for? */ -enum fputype arm_fpu_tune; +/* The processor for which instructions should be scheduled. */ +enum processor_type arm_tune = arm_none; + +/* Which floating point model to use. */ +enum arm_fp_model arm_fp_model; -/* What type of floating point instructions are available? */ +/* Which floating point hardware is available. */ enum fputype arm_fpu_arch; -/* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ -enum prog_mode_type arm_prgmode; +/* Which floating point hardware to schedule for. */ +enum fputype arm_fpu_tune; + +/* Whether to use floating point hardware. */ +enum float_abi_type arm_float_abi; + +/* Which ABI to use. */ +enum arm_abi_type arm_abi; -/* Set by the -mfp=... option. */ -const char * target_fp_name = NULL; +/* Which thread pointer model to use. */ +enum arm_tp_type target_thread_pointer = TP_AUTO; /* Used to parse -mstructure_size_boundary command line option. */ -const char * structure_size_string = NULL; int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; +/* Used for Thumb call_via trampolines. */ +rtx thumb_call_via_label[14]; +static int thumb_call_reg_needed; + /* Bit values used to identify processor capabilities. */ #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ -#define FL_FAST_MULT (1 << 1) /* Fast multiply */ +#define FL_ARCH3M (1 << 1) /* Extended multiply */ #define FL_MODE26 (1 << 2) /* 26-bit mode support */ #define FL_MODE32 (1 << 3) /* 32-bit mode support */ #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ @@ -281,41 +428,71 @@ int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ #define FL_XSCALE (1 << 10) /* XScale */ #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ -#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ -#define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds +#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds media instructions. */ #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ +#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. + Note: ARM6 & 7 derivatives only. */ +#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ + +#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ + +#define FL_FOR_ARCH2 0 +#define FL_FOR_ARCH3 FL_MODE32 +#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) +#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) +#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) +#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) +#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) +#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) +#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) +#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE +#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) +#define FL_FOR_ARCH6J FL_FOR_ARCH6 +#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) +#define FL_FOR_ARCH6Z FL_FOR_ARCH6 +#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K /* The bits in this mask specify which instructions we are allowed to generate. */ static unsigned long insn_flags = 0; /* The bits in this mask specify which instruction scheduling options should - be used. Note - there is an overlap with the FL_FAST_MULT. For some - hardware we want to be able to generate the multiply instructions, but to - tune as if they were not present in the architecture. */ + be used. */ static unsigned long tune_flags = 0; /* The following are used in the arm.md file as equivalents to bits in the above two flag variables. */ -/* Nonzero if this is an "M" variant of the processor. */ -int arm_fast_multiply = 0; +/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ +int arm_arch3m = 0; /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ int arm_arch4 = 0; +/* Nonzero if this chip supports the ARM Architecture 4t extensions. */ +int arm_arch4t = 0; + /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ int arm_arch5 = 0; /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ int arm_arch5e = 0; +/* Nonzero if this chip supports the ARM Architecture 6 extensions. */ +int arm_arch6 = 0; + +/* Nonzero if this chip supports the ARM 6K extensions. */ +int arm_arch6k = 0; + /* Nonzero if this chip can benefit from load scheduling. */ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ -int arm_is_strong = 0; +int arm_tune_strongarm = 0; + +/* Nonzero if this chip is a Cirrus variant. */ +int arm_arch_cirrus = 0; /* Nonzero if this chip supports Intel Wireless MMX technology. */ int arm_arch_iwmmxt = 0; @@ -326,23 +503,27 @@ int arm_arch_xscale = 0; /* Nonzero if tuning for XScale */ int arm_tune_xscale = 0; -/* Nonzero if this chip is an ARM6 or an ARM7. */ -int arm_is_6_or_7 = 0; - -/* Nonzero if this chip is a Cirrus/DSP. */ -int arm_is_cirrus = 0; +/* Nonzero if we want to tune for stores that access the write-buffer. + This typically means an ARM6 or ARM7 with MMU or MPU. */ +int arm_tune_wbuf = 0; /* Nonzero if generating Thumb instructions. */ int thumb_code = 0; +/* Nonzero if we should define __THUMB_INTERWORK__ in the + preprocessor. + XXX This is a bit of a hack, it's intended to help work around + problems in GLD which doesn't understand that armv5t code is + interworking clean. */ +int arm_cpp_interwork = 0; + /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from PRINT_OPERAND to PRINT_OPERAND_ADDRESS. */ enum machine_mode output_memory_reference_mode; /* The register number to be used for the PIC offset register. */ -const char * arm_pic_register_string = NULL; -int arm_pic_register = INVALID_REGNUM; +unsigned arm_pic_register = INVALID_REGNUM; /* Set to 1 when a return insn is output, this means that the epilogue is not needed. */ @@ -375,7 +556,10 @@ static const char * const arm_condition_codes[] = struct processors { const char *const name; + enum processor_type core; + const char *arch; const unsigned long flags; + bool (* rtx_costs) (rtx, int, int, int *); }; /* Not all of these give usefully different compilation alternatives, @@ -383,103 +567,162 @@ struct processors static const struct processors all_cores[] = { /* ARM Cores */ - - {"arm2", FL_CO_PROC | FL_MODE26 }, - {"arm250", FL_CO_PROC | FL_MODE26 }, - {"arm3", FL_CO_PROC | FL_MODE26 }, - {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm610", FL_MODE26 | FL_MODE32 }, - {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - /* arm7m doesn't exist on its own, but only with D, (and I), but - those don't alter the code, so arm7m is sometimes used. */ - {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, - {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, - {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, - {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - {"arm710", FL_MODE26 | FL_MODE32 }, - {"arm720", FL_MODE26 | FL_MODE32 }, - {"arm710c", FL_MODE26 | FL_MODE32 }, - {"arm7100", FL_MODE26 | FL_MODE32 }, - {"arm7500", FL_MODE26 | FL_MODE32 }, - /* Doesn't have an external co-proc, but does have embedded fpa. */ - {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - /* V4 Architecture Processors */ - {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, - {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, - {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, - {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, - {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, - {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, - {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, - {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, - {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, - {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, - {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, - {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, - {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, - {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, - {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, - {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, - {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, - /* V5 Architecture Processors */ - {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, - {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, - {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, - {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, - {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, - {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, - /* V6 Architecture Processors */ - {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J }, - {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 }, - {NULL, 0} +#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ + {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, +#include "arm-cores.def" +#undef ARM_CORE + {NULL, arm_none, NULL, 0, NULL} }; static const struct processors all_architectures[] = { /* ARM Architectures */ - - { "armv2", FL_CO_PROC | FL_MODE26 }, - { "armv2a", FL_CO_PROC | FL_MODE26 }, - { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, - { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, - { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, + /* We don't specify rtx_costs here as it will be figured out + from the core. */ + + {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, + {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, + {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, + {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, + {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no implementations that support it, so we will leave it out for now. */ - { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, - { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, - { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, - { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, - { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J }, - { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, - {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, - { NULL, 0 } + {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, + {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, + {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, + {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, + {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, + {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, + {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, + {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, + {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, + {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, + {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, + {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, + {NULL, arm_none, NULL, 0 , NULL} +}; + +struct arm_cpu_select +{ + const char * string; + const char * name; + const struct processors * processors; }; /* This is a magic structure. The 'string' field is magically filled in with a pointer to the value specified by the user on the command line assuming that the user has specified such a value. */ -struct arm_cpu_select arm_select[] = +static struct arm_cpu_select arm_select[] = { - /* string name processors */ + /* string name processors */ { NULL, "-mcpu=", all_cores }, { NULL, "-march=", all_architectures }, { NULL, "-mtune=", all_cores } }; +/* Defines representing the indexes into the above table. */ +#define ARM_OPT_SET_CPU 0 +#define ARM_OPT_SET_ARCH 1 +#define ARM_OPT_SET_TUNE 2 + +/* The name of the preprocessor macro to define for this architecture. */ + +char arm_arch_name[] = "__ARM_ARCH_0UNK__"; + +struct fpu_desc +{ + const char * name; + enum fputype fpu; +}; + + +/* Available values for -mfpu=. */ + +static const struct fpu_desc all_fpus[] = +{ + {"fpa", FPUTYPE_FPA}, + {"fpe2", FPUTYPE_FPA_EMU2}, + {"fpe3", FPUTYPE_FPA_EMU2}, + {"maverick", FPUTYPE_MAVERICK}, + {"vfp", FPUTYPE_VFP} +}; + + +/* Floating point models used by the different hardware. + See fputype in arm.h. */ + +static const enum fputype fp_model_for_fpu[] = +{ + /* No FP hardware. */ + ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ + ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ + ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ + ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ + ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ + ARM_FP_MODEL_VFP /* FPUTYPE_VFP */ +}; + + +struct float_abi +{ + const char * name; + enum float_abi_type abi_type; +}; + + +/* Available values for -mfloat-abi=. */ + +static const struct float_abi all_float_abis[] = +{ + {"soft", ARM_FLOAT_ABI_SOFT}, + {"softfp", ARM_FLOAT_ABI_SOFTFP}, + {"hard", ARM_FLOAT_ABI_HARD} +}; + + +struct abi_name +{ + const char *name; + enum arm_abi_type abi_type; +}; + + +/* Available values for -mabi=. */ + +static const struct abi_name arm_all_abis[] = +{ + {"apcs-gnu", ARM_ABI_APCS}, + {"atpcs", ARM_ABI_ATPCS}, + {"aapcs", ARM_ABI_AAPCS}, + {"iwmmxt", ARM_ABI_IWMMXT}, + {"aapcs-linux", ARM_ABI_AAPCS_LINUX} +}; + +/* Supported TLS relocations. */ + +enum tls_reloc { + TLS_GD32, + TLS_LDM32, + TLS_LDO32, + TLS_IE32, + TLS_LE32 +}; + +/* Emit an insn that's a simple single-set. Both the operands must be known + to be valid. */ +inline static rtx +emit_set_insn (rtx x, rtx y) +{ + return emit_insn (gen_rtx_SET (VOIDmode, x, y)); +} + /* Return the number of bits set in VALUE. */ static unsigned bit_count (unsigned long value) { unsigned long count = 0; - + while (value) { count++; @@ -489,18 +732,159 @@ bit_count (unsigned long value) return count; } +/* Set up library functions unique to ARM. */ + +static void +arm_init_libfuncs (void) +{ + /* There are no special library functions unless we are using the + ARM BPABI. */ + if (!TARGET_BPABI) + return; + + /* The functions below are described in Section 4 of the "Run-Time + ABI for the ARM architecture", Version 1.0. */ + + /* Double-precision floating-point arithmetic. Table 2. */ + set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); + set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); + set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); + set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); + set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); + + /* Double-precision comparisons. Table 3. */ + set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); + set_optab_libfunc (ne_optab, DFmode, NULL); + set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); + set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); + set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); + set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); + set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); + + /* Single-precision floating-point arithmetic. Table 4. */ + set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); + set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); + set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); + set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); + set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); + + /* Single-precision comparisons. Table 5. */ + set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); + set_optab_libfunc (ne_optab, SFmode, NULL); + set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); + set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); + set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); + set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); + set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); + + /* Floating-point to integer conversions. Table 6. */ + set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); + set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); + set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); + set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); + set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); + set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); + set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); + set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); + + /* Conversions between floating types. Table 7. */ + set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); + set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); + + /* Integer to floating-point conversions. Table 8. */ + set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); + set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); + set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); + set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); + set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); + set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); + set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); + set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); + + /* Long long. Table 9. */ + set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); + set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); + set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); + set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); + set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); + set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); + set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); + set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); + + /* Integer (32/32->32) division. \S 4.3.1. */ + set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); + set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); + + /* The divmod functions are designed so that they can be used for + plain division, even though they return both the quotient and the + remainder. The quotient is returned in the usual location (i.e., + r0 for SImode, {r0, r1} for DImode), just as would be expected + for an ordinary division routine. Because the AAPCS calling + conventions specify that all of { r0, r1, r2, r3 } are + callee-saved registers, there is no need to tell the compiler + explicitly that those registers are clobbered by these + routines. */ + set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); + set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); + + /* For SImode division the ABI provides div-without-mod routines, + which are faster. */ + set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); + set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); + + /* We don't have mod libcalls. Fortunately gcc knows how to use the + divmod libcalls instead. */ + set_optab_libfunc (smod_optab, DImode, NULL); + set_optab_libfunc (umod_optab, DImode, NULL); + set_optab_libfunc (smod_optab, SImode, NULL); + set_optab_libfunc (umod_optab, SImode, NULL); +} + +/* Implement TARGET_HANDLE_OPTION. */ + +static bool +arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) +{ + switch (code) + { + case OPT_march_: + arm_select[1].string = arg; + return true; + + case OPT_mcpu_: + arm_select[0].string = arg; + return true; + + case OPT_mhard_float: + target_float_abi_name = "hard"; + return true; + + case OPT_msoft_float: + target_float_abi_name = "soft"; + return true; + + case OPT_mtune_: + arm_select[2].string = arg; + return true; + + default: + return true; + } +} + /* Fix up any incompatible options that the user has specified. This has now turned into a maze. */ void arm_override_options (void) { unsigned i; - + enum processor_type target_arch_cpu = arm_none; + /* Set up the flags based on the cpu/architecture selected by the user. */ for (i = ARRAY_SIZE (arm_select); i--;) { struct arm_cpu_select * ptr = arm_select + i; - + if (ptr->string != NULL && ptr->string[0] != '\0') { const struct processors * sel; @@ -508,21 +892,38 @@ arm_override_options (void) for (sel = ptr->processors; sel->name != NULL; sel++) if (streq (ptr->string, sel->name)) { - if (i == 2) - tune_flags = sel->flags; - else + /* Set the architecture define. */ + if (i != ARM_OPT_SET_TUNE) + sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); + + /* Determine the processor core for which we should + tune code-generation. */ + if (/* -mcpu= is a sensible default. */ + i == ARM_OPT_SET_CPU + /* -mtune= overrides -mcpu= and -march=. */ + || i == ARM_OPT_SET_TUNE) + arm_tune = (enum processor_type) (sel - ptr->processors); + + /* Remember the CPU associated with this architecture. + If no other option is used to set the CPU type, + we'll use this to guess the most suitable tuning + options. */ + if (i == ARM_OPT_SET_ARCH) + target_arch_cpu = sel->core; + + if (i != ARM_OPT_SET_TUNE) { /* If we have been given an architecture and a processor make sure that they are compatible. We only generate a warning though, and we prefer the CPU over the architecture. */ if (insn_flags != 0 && (insn_flags ^ sel->flags)) - warning ("switch -mcpu=%s conflicts with -march= switch", + warning (0, "switch -mcpu=%s conflicts with -march= switch", ptr->string); - + insn_flags = sel->flags; } - + break; } @@ -530,71 +931,41 @@ arm_override_options (void) error ("bad value (%s) for %s switch", ptr->string, ptr->name); } } - + + /* Guess the tuning options from the architecture if necessary. */ + if (arm_tune == arm_none) + arm_tune = target_arch_cpu; + /* If the user did not specify a processor, choose one for them. */ if (insn_flags == 0) { const struct processors * sel; unsigned int sought; - static const struct cpu_default - { - const int cpu; - const char *const name; - } - cpu_defaults[] = - { - { TARGET_CPU_arm2, "arm2" }, - { TARGET_CPU_arm6, "arm6" }, - { TARGET_CPU_arm610, "arm610" }, - { TARGET_CPU_arm710, "arm710" }, - { TARGET_CPU_arm7m, "arm7m" }, - { TARGET_CPU_arm7500fe, "arm7500fe" }, - { TARGET_CPU_arm7tdmi, "arm7tdmi" }, - { TARGET_CPU_arm8, "arm8" }, - { TARGET_CPU_arm810, "arm810" }, - { TARGET_CPU_arm9, "arm9" }, - { TARGET_CPU_strongarm, "strongarm" }, - { TARGET_CPU_xscale, "xscale" }, - { TARGET_CPU_ep9312, "ep9312" }, - { TARGET_CPU_iwmmxt, "iwmmxt" }, - { TARGET_CPU_arm926ej_s, "arm926ej-s" }, - { TARGET_CPU_arm1026ej_s, "arm1026ej-s" }, - { TARGET_CPU_arm1136j_s, "arm1136j_s" }, - { TARGET_CPU_arm1136jf_s, "arm1136jf_s" }, - { TARGET_CPU_generic, "arm" }, - { 0, 0 } - }; - const struct cpu_default * def; - - /* Find the default. */ - for (def = cpu_defaults; def->name; def++) - if (def->cpu == TARGET_CPU_DEFAULT) - break; + enum processor_type cpu; - /* Make sure we found the default CPU. */ - if (def->name == NULL) - abort (); - - /* Find the default CPU's flags. */ - for (sel = all_cores; sel->name != NULL; sel++) - if (streq (def->name, sel->name)) - break; - - if (sel->name == NULL) - abort (); + cpu = TARGET_CPU_DEFAULT; + if (cpu == arm_none) + { +#ifdef SUBTARGET_CPU_DEFAULT + /* Use the subtarget default CPU if none was specified by + configure. */ + cpu = SUBTARGET_CPU_DEFAULT; +#endif + /* Default to ARM6. */ + if (cpu == arm_none) + cpu = arm6; + } + sel = &all_cores[cpu]; insn_flags = sel->flags; - + /* Now check to see if the user has specified some command line switch that require certain abilities from the cpu. */ sought = 0; - + if (TARGET_INTERWORK || TARGET_THUMB) { sought |= (FL_THUMB | FL_MODE32); - - /* Force apcs-32 to be used for interworking. */ - target_flags |= ARM_FLAG_APCS_32; /* There are no ARM processors that support both APCS-26 and interworking. Therefore we force FL_MODE26 to be removed @@ -602,9 +973,7 @@ arm_override_options (void) below will always be able to find a compatible processor. */ insn_flags &= ~FL_MODE26; } - else if (!TARGET_APCS_32) - sought |= FL_MODE26; - + if (sought != 0 && ((sought & insn_flags) != sought)) { /* Try to locate a CPU type that supports all of the abilities @@ -618,7 +987,7 @@ arm_override_options (void) { unsigned current_bit_count = 0; const struct processors * best_fit = NULL; - + /* Ideally we would like to issue an error message here saying that it was not possible to find a CPU compatible with the default CPU, but which also supports the command @@ -626,12 +995,10 @@ arm_override_options (void) ought to use the -mcpu=<name> command line option to override the default CPU type. - Unfortunately this does not work with multilibing. We - need to be able to support multilibs for -mapcs-26 and for - -mthumb-interwork and there is no CPU that can support both - options. Instead if we cannot find a cpu that has both the - characteristics of the default cpu and the given command line - options we scan the array again looking for a best match. */ + If we cannot find a cpu that has both the + characteristics of the default cpu and the given + command line options we scan the array again looking + for a best match. */ for (sel = all_cores; sel->name != NULL; sel++) if ((sel->flags & sought) == sought) { @@ -646,184 +1013,275 @@ arm_override_options (void) } } - if (best_fit == NULL) - abort (); - else - sel = best_fit; + gcc_assert (best_fit); + sel = best_fit; } insn_flags = sel->flags; } + sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); + if (arm_tune == arm_none) + arm_tune = (enum processor_type) (sel - all_cores); } - - /* If tuning has not been specified, tune for whichever processor or - architecture has been selected. */ - if (tune_flags == 0) - tune_flags = insn_flags; + + /* The processor for which we should tune should now have been + chosen. */ + gcc_assert (arm_tune != arm_none); + + tune_flags = all_cores[(int)arm_tune].flags; + if (optimize_size) + targetm.rtx_costs = arm_size_rtx_costs; + else + targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs; /* Make sure that the processor choice does not conflict with any of the other command line choices. */ - if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) - { - /* If APCS-32 was not the default then it must have been set by the - user, so issue a warning message. If the user has specified - "-mapcs-32 -mcpu=arm2" then we loose here. */ - if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) - warning ("target CPU does not support APCS-32" ); - target_flags &= ~ARM_FLAG_APCS_32; - } - else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) - { - warning ("target CPU does not support APCS-26" ); - target_flags |= ARM_FLAG_APCS_32; - } - if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) { - warning ("target CPU does not support interworking" ); - target_flags &= ~ARM_FLAG_INTERWORK; + warning (0, "target CPU does not support interworking" ); + target_flags &= ~MASK_INTERWORK; } - + if (TARGET_THUMB && !(insn_flags & FL_THUMB)) { - warning ("target CPU does not support THUMB instructions"); - target_flags &= ~ARM_FLAG_THUMB; + warning (0, "target CPU does not support THUMB instructions"); + target_flags &= ~MASK_THUMB; } - if (!TARGET_APCS_32) - inform ("future releases of GCC will not support -mapcs-26"); - if (TARGET_APCS_FRAME && TARGET_THUMB) { - /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ - target_flags &= ~ARM_FLAG_APCS_FRAME; + /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ + target_flags &= ~MASK_APCS_FRAME; } + /* Callee super interworking implies thumb interworking. Adding + this to the flags here simplifies the logic elsewhere. */ + if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) + target_flags |= MASK_INTERWORK; + /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done from here where no function is being compiled currently. */ - if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) - && TARGET_ARM) - warning ("enabling backtrace support is only meaningful when compiling for the Thumb"); + if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) + warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) - warning ("enabling callee interworking support is only meaningful when compiling for the Thumb"); + warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); if (TARGET_ARM && TARGET_CALLER_INTERWORKING) - warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); + warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); - /* If interworking is enabled then APCS-32 must be selected as well. */ - if (TARGET_INTERWORK) - { - if (!TARGET_APCS_32) - warning ("interworking forces APCS-32 to be used" ); - target_flags |= ARM_FLAG_APCS_32; - } - if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) { - warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); - target_flags |= ARM_FLAG_APCS_FRAME; + warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); + target_flags |= MASK_APCS_FRAME; } - + if (TARGET_POKE_FUNCTION_NAME) - target_flags |= ARM_FLAG_APCS_FRAME; - + target_flags |= MASK_APCS_FRAME; + if (TARGET_APCS_REENT && flag_pic) error ("-fpic and -mapcs-reent are incompatible"); - + if (TARGET_APCS_REENT) - warning ("APCS reentrant code not supported. Ignored"); - + warning (0, "APCS reentrant code not supported. Ignored"); + /* If this target is normally configured to use APCS frames, warn if they are turned off and debugging is turned on. */ if (TARGET_ARM && write_symbols != NO_DEBUG && !TARGET_APCS_FRAME - && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) - warning ("-g with -mno-apcs-frame may not give sensible debugging"); - + && (TARGET_DEFAULT & MASK_APCS_FRAME)) + warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); + /* If stack checking is disabled, we can use r10 as the PIC register, which keeps r9 available. */ - if (flag_pic) + if (flag_pic && TARGET_SINGLE_PIC_BASE) arm_pic_register = TARGET_APCS_STACK ? 9 : 10; - + if (TARGET_APCS_FLOAT) - warning ("passing floating point arguments in fp regs not yet supported"); - - /* Initialize boolean versions of the flags, for use in the arm.md file. */ - arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; - arm_arch4 = (insn_flags & FL_ARCH4) != 0; - arm_arch5 = (insn_flags & FL_ARCH5) != 0; - arm_arch5e = (insn_flags & FL_ARCH5E) != 0; - arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; + warning (0, "passing floating point arguments in fp regs not yet supported"); - arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; - arm_is_strong = (tune_flags & FL_STRONG) != 0; - thumb_code = (TARGET_ARM == 0); - arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) - && !(tune_flags & FL_ARCH4))) != 0; - arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; - arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0; - arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + /* Initialize boolean versions of the flags, for use in the arm.md file. */ + arm_arch3m = (insn_flags & FL_ARCH3M) != 0; + arm_arch4 = (insn_flags & FL_ARCH4) != 0; + arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); + arm_arch5 = (insn_flags & FL_ARCH5) != 0; + arm_arch5e = (insn_flags & FL_ARCH5E) != 0; + arm_arch6 = (insn_flags & FL_ARCH6) != 0; + arm_arch6k = (insn_flags & FL_ARCH6K) != 0; + arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; + arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; + + arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; + arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; + thumb_code = (TARGET_ARM == 0); + arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; + arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + + /* V5 code we generate is completely interworking capable, so we turn off + TARGET_INTERWORK here to avoid many tests later on. */ + + /* XXX However, we must pass the right pre-processor defines to CPP + or GLD can get confused. This is a hack. */ + if (TARGET_INTERWORK) + arm_cpp_interwork = 1; - if (TARGET_IWMMXT && (! TARGET_ATPCS)) - target_flags |= ARM_FLAG_ATPCS; + if (arm_arch5) + target_flags &= ~MASK_INTERWORK; - if (arm_is_cirrus) + if (target_abi_name) { - arm_fpu_tune = FPUTYPE_MAVERICK; + for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) + { + if (streq (arm_all_abis[i].name, target_abi_name)) + { + arm_abi = arm_all_abis[i].abi_type; + break; + } + } + if (i == ARRAY_SIZE (arm_all_abis)) + error ("invalid ABI option: -mabi=%s", target_abi_name); + } + else + arm_abi = ARM_DEFAULT_ABI; + + if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) + error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); - /* Ignore -mhard-float if -mcpu=ep9312. */ - if (TARGET_HARD_FLOAT) - target_flags ^= ARM_FLAG_SOFT_FLOAT; + if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) + error ("iwmmxt abi requires an iwmmxt capable cpu"); + + arm_fp_model = ARM_FP_MODEL_UNKNOWN; + if (target_fpu_name == NULL && target_fpe_name != NULL) + { + if (streq (target_fpe_name, "2")) + target_fpu_name = "fpe2"; + else if (streq (target_fpe_name, "3")) + target_fpu_name = "fpe3"; + else + error ("invalid floating point emulation option: -mfpe=%s", + target_fpe_name); + } + if (target_fpu_name != NULL) + { + /* The user specified a FPU. */ + for (i = 0; i < ARRAY_SIZE (all_fpus); i++) + { + if (streq (all_fpus[i].name, target_fpu_name)) + { + arm_fpu_arch = all_fpus[i].fpu; + arm_fpu_tune = arm_fpu_arch; + arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; + break; + } + } + if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) + error ("invalid floating point option: -mfpu=%s", target_fpu_name); } else - /* Default value for floating point code... if no co-processor - bus, then schedule for emulated floating point. Otherwise, - assume the user has an FPA. - Note: this does not prevent use of floating point instructions, - -msoft-float does that. */ - arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3; - - if (target_fp_name) { - if (streq (target_fp_name, "2")) +#ifdef FPUTYPE_DEFAULT + /* Use the default if it is specified for this platform. */ + arm_fpu_arch = FPUTYPE_DEFAULT; + arm_fpu_tune = FPUTYPE_DEFAULT; +#else + /* Pick one based on CPU type. */ + /* ??? Some targets assume FPA is the default. + if ((insn_flags & FL_VFP) != 0) + arm_fpu_arch = FPUTYPE_VFP; + else + */ + if (arm_arch_cirrus) + arm_fpu_arch = FPUTYPE_MAVERICK; + else arm_fpu_arch = FPUTYPE_FPA_EMU2; - else if (streq (target_fp_name, "3")) - arm_fpu_arch = FPUTYPE_FPA_EMU3; +#endif + if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) + arm_fpu_tune = FPUTYPE_FPA; else - error ("invalid floating point emulation option: -mfpe-%s", - target_fp_name); + arm_fpu_tune = arm_fpu_arch; + arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; + gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); } - else - arm_fpu_arch = FPUTYPE_DEFAULT; - - if (TARGET_FPE) + + if (target_float_abi_name != NULL) { - if (arm_fpu_tune == FPUTYPE_FPA_EMU3) - arm_fpu_tune = FPUTYPE_FPA_EMU2; - else if (arm_fpu_tune == FPUTYPE_MAVERICK) - warning ("-mfpe switch not supported by ep9312 target cpu - ignored."); - else if (arm_fpu_tune != FPUTYPE_FPA) - arm_fpu_tune = FPUTYPE_FPA_EMU2; + /* The user specified a FP ABI. */ + for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) + { + if (streq (all_float_abis[i].name, target_float_abi_name)) + { + arm_float_abi = all_float_abis[i].abi_type; + break; + } + } + if (i == ARRAY_SIZE (all_float_abis)) + error ("invalid floating point abi: -mfloat-abi=%s", + target_float_abi_name); } - + else + arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; + + if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) + sorry ("-mfloat-abi=hard and VFP"); + + /* FPA and iWMMXt are incompatible because the insn encodings overlap. + VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon + will ever exist. GCC makes no attempt to support this combination. */ + if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) + sorry ("iWMMXt and hardware floating point"); + + /* If soft-float is specified then don't use FPU. */ + if (TARGET_SOFT_FLOAT) + arm_fpu_arch = FPUTYPE_NONE; + /* For arm2/3 there is no need to do any scheduling if there is only a floating point emulator, or we are doing software floating-point. */ - if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA) + if ((TARGET_SOFT_FLOAT + || arm_fpu_tune == FPUTYPE_FPA_EMU2 + || arm_fpu_tune == FPUTYPE_FPA_EMU3) && (tune_flags & FL_MODE32) == 0) flag_schedule_insns = flag_schedule_insns_after_reload = 0; - - arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; - + + if (target_thread_switch) + { + if (strcmp (target_thread_switch, "soft") == 0) + target_thread_pointer = TP_SOFT; + else if (strcmp (target_thread_switch, "auto") == 0) + target_thread_pointer = TP_AUTO; + else if (strcmp (target_thread_switch, "cp15") == 0) + target_thread_pointer = TP_CP15; + else + error ("invalid thread pointer option: -mtp=%s", target_thread_switch); + } + + /* Use the cp15 method if it is available. */ + if (target_thread_pointer == TP_AUTO) + { + if (arm_arch6k && !TARGET_THUMB) + target_thread_pointer = TP_CP15; + else + target_thread_pointer = TP_SOFT; + } + + if (TARGET_HARD_TP && TARGET_THUMB) + error ("can not use -mtp=cp15 with -mthumb"); + + /* Override the default structure alignment for AAPCS ABI. */ + if (TARGET_AAPCS_BASED) + arm_structure_size_boundary = 8; + if (structure_size_string != NULL) { int size = strtol (structure_size_string, NULL, 0); - - if (size == 8 || size == 32) + + if (size == 8 || size == 32 + || (ARM_DOUBLEWORD_ALIGN && size == 64)) arm_structure_size_boundary = size; else - warning ("structure size boundary can only be set to 8 or 32"); + warning (0, "structure size boundary can only be set to %s", + ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); } if (arm_pic_register_string != NULL) @@ -831,7 +1289,7 @@ arm_override_options (void) int pic_register = decode_reg_name (arm_pic_register_string); if (!flag_pic) - warning ("-mpic-register= is useless without -fpic"); + warning (0, "-mpic-register= is useless without -fpic"); /* Prevent the user from choosing an obviously stupid PIC register. */ else if (pic_register < 0 || call_used_regs[pic_register] @@ -851,10 +1309,6 @@ arm_override_options (void) if (optimize_size) { - /* There's some dispute as to whether this should be 1 or 2. However, - experiments seem to show that in pathological cases a setting of - 1 degrades less severely than a setting of 2. This could change if - other parts of the compiler change their behavior. */ arm_constant_limit = 1; /* If optimizing for size, bump the number of instructions that we @@ -866,7 +1320,7 @@ arm_override_options (void) /* For processors with load scheduling, it never costs more than 2 cycles to load a constant, and the load scheduler may well reduce that to 1. */ - if (tune_flags & FL_LDSCHED) + if (arm_ld_sched) arm_constant_limit = 1; /* On XScale the longer latency of a load makes it more difficult @@ -877,7 +1331,7 @@ arm_override_options (void) /* StrongARM has early execution of branches, so a sequence that is worth skipping is shorter. */ - if (arm_is_strong) + if (arm_tune_strongarm) max_insns_skipped = 3; } @@ -956,42 +1410,38 @@ arm_compute_func_type (void) unsigned long type = ARM_FT_UNKNOWN; tree a; tree attr; - - if (TREE_CODE (current_function_decl) != FUNCTION_DECL) - abort (); + + gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); /* Decide if the current function is volatile. Such functions never return, and many memory cycles can be saved by not storing register values that will never be needed again. This optimization was added to speed up context switching in a kernel application. */ if (optimize > 0 - && current_function_nothrow + && (TREE_NOTHROW (current_function_decl) + || !(flag_unwind_tables + || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) && TREE_THIS_VOLATILE (current_function_decl)) type |= ARM_FT_VOLATILE; - - if (current_function_needs_context) + + if (cfun->static_chain_decl != NULL) type |= ARM_FT_NESTED; attr = DECL_ATTRIBUTES (current_function_decl); - + a = lookup_attribute ("naked", attr); if (a != NULL_TREE) type |= ARM_FT_NAKED; - if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) - type |= ARM_FT_EXCEPTION_HANDLER; + a = lookup_attribute ("isr", attr); + if (a == NULL_TREE) + a = lookup_attribute ("interrupt", attr); + + if (a == NULL_TREE) + type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; else - { - a = lookup_attribute ("isr", attr); - if (a == NULL_TREE) - a = lookup_attribute ("interrupt", attr); - - if (a == NULL_TREE) - type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; - else - type |= arm_isr_value (TREE_VALUE (a)); - } - + type |= arm_isr_value (TREE_VALUE (a)); + return type; } @@ -1006,7 +1456,7 @@ arm_current_func_type (void) return cfun->machine->func_type; } -/* Return 1 if it is possible to return using a single instruction. +/* Return 1 if it is possible to return using a single instruction. If SIBLING is non-null, this is a test for a return before a sibling call. SIBLING is the call insn, so we can examine its register usage. */ @@ -1017,6 +1467,7 @@ use_return_insn (int iscond, rtx sibling) unsigned int func_type; unsigned long saved_int_regs; unsigned HOST_WIDE_INT stack_adjust; + arm_stack_offsets *offsets; /* Never use a return instruction before reload has run. */ if (!reload_completed) @@ -1033,13 +1484,14 @@ use_return_insn (int iscond, rtx sibling) if (IS_INTERRUPT (func_type) && frame_pointer_needed) return 0; - stack_adjust = arm_get_frame_size () + current_function_outgoing_args_size; + offsets = arm_get_frame_offsets (); + stack_adjust = offsets->outgoing_args - offsets->saved_regs; /* As do variadic functions. */ if (current_function_pretend_args_size || cfun->machine->uses_anonymous_args /* Or if the function calls __builtin_eh_return () */ - || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER + || current_function_calls_eh_return /* Or if the function calls alloca */ || current_function_calls_alloca /* Or if there is a stack adjustment. However, if the stack pointer @@ -1057,7 +1509,7 @@ use_return_insn (int iscond, rtx sibling) pointer won't be correctly restored if the instruction takes a page fault. We work around this problem by popping r3 along with the other registers, since that is never slower than executing - another instruction. + another instruction. We test for !arm_arch5 here, because code for any architecture less than this could potentially be run on one of the buggy @@ -1069,13 +1521,14 @@ use_return_insn (int iscond, rtx sibling) if (!call_used_regs[3]) return 0; - /* ... that it isn't being used for a return value (always true - until we implement return-in-regs), or for a tail-call - argument ... */ + /* ... that it isn't being used for a return value ... */ + if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) + return 0; + + /* ... or for a tail-call argument ... */ if (sibling) { - if (GET_CODE (sibling) != CALL_INSN) - abort (); + gcc_assert (GET_CODE (sibling) == CALL_INSN); if (find_regno_fusage (sibling, USE, 3)) return 0; @@ -1094,14 +1547,16 @@ use_return_insn (int iscond, rtx sibling) /* On StrongARM, conditional returns are expensive if they aren't taken and multiple registers have been stacked. */ - if (iscond && arm_is_strong) + if (iscond && arm_tune_strongarm) { - /* Conditional return when just the LR is stored is a simple + /* Conditional return when just the LR is stored is a simple conditional-load instruction, that's not expensive. */ if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) return 0; - if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) + if (flag_pic + && arm_pic_register != INVALID_REGNUM + && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) return 0; } @@ -1112,8 +1567,14 @@ use_return_insn (int iscond, rtx sibling) /* Can't be done if any of the FPA regs are pushed, since this also requires an insn. */ - if (TARGET_HARD_FLOAT) - for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) + if (TARGET_HARD_FLOAT && TARGET_FPA) + for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) + if (regs_ever_live[regno] && !call_used_regs[regno]) + return 0; + + /* Likewise VFP regs. */ + if (TARGET_HARD_FLOAT && TARGET_VFP) + for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) if (regs_ever_live[regno] && !call_used_regs[regno]) return 0; @@ -1130,29 +1591,34 @@ use_return_insn (int iscond, rtx sibling) int const_ok_for_arm (HOST_WIDE_INT i) { - unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; + int lowbit; - /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must + /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must be all zero, or all one. */ if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != ((~(unsigned HOST_WIDE_INT) 0) & ~(unsigned HOST_WIDE_INT) 0xffffffff))) return FALSE; - - /* Fast return for 0 and powers of 2 */ - if ((i & (i - 1)) == 0) + + i &= (unsigned HOST_WIDE_INT) 0xffffffff; + + /* Fast return for 0 and small values. We must do this for zero, since + the code below can't handle that one case. */ + if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) return TRUE; - do - { - if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) - return TRUE; - mask = - (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) - >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff; - } - while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); + /* Get the number of trailing zeros, rounded down to the nearest even + number. */ + lowbit = (ffs ((int) i) - 1) & ~1; + + if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) + return TRUE; + else if (lowbit <= 4 + && ((i & ~0xc000003f) == 0 + || (i & ~0xf000000f) == 0 + || (i & ~0xfc000003) == 0)) + return TRUE; return FALSE; } @@ -1178,7 +1644,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); default: - abort (); + gcc_unreachable (); } } @@ -1193,9 +1659,16 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) Return value is the number of insns emitted. */ int -arm_split_constant (enum rtx_code code, enum machine_mode mode, +arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, HOST_WIDE_INT val, rtx target, rtx source, int subtargets) { + rtx cond; + + if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) + cond = COND_EXEC_TEST (PATTERN (insn)); + else + cond = NULL_RTX; + if (subtargets || code == SET || (GET_CODE (target) == REG && GET_CODE (source) == REG && REGNO (target) != REGNO (source))) @@ -1210,35 +1683,37 @@ arm_split_constant (enum rtx_code code, enum machine_mode mode, Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c */ if (!after_arm_reorg - && (arm_gen_constant (code, mode, val, target, source, 1, 0) + && !cond + && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, + 1, 0) > arm_constant_limit + (code != SET))) { if (code == SET) { /* Currently SET is the only monadic value for CODE, all the rest are diadic. */ - emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); + emit_set_insn (target, GEN_INT (val)); return 1; } else { rtx temp = subtargets ? gen_reg_rtx (mode) : target; - emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); + emit_set_insn (temp, GEN_INT (val)); /* For MINUS, the value is subtracted from, since we never have subtraction of a constant. */ if (code == MINUS) - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_MINUS (mode, temp, source))); + emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); else - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx (code, mode, source, temp))); + emit_set_insn (target, + gen_rtx_fmt_ee (code, mode, source, temp)); return 2; } } } - return arm_gen_constant (code, mode, val, target, source, subtargets, 1); + return arm_gen_constant (code, mode, cond, val, target, source, subtargets, + 1); } static int @@ -1249,7 +1724,7 @@ count_insns_for_constant (HOST_WIDE_INT remainder, int i) do { int end; - + if (i <= 0) i += 32; if (remainder & (3 << (i - 2))) @@ -1268,11 +1743,23 @@ count_insns_for_constant (HOST_WIDE_INT remainder, int i) return num_insns; } +/* Emit an instruction with the indicated PATTERN. If COND is + non-NULL, conditionalize the execution of the instruction on COND + being true. */ + +static void +emit_constant_insn (rtx cond, rtx pattern) +{ + if (cond) + pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); + emit_insn (pattern); +} + /* As above, but extra parameter GENERATE which, if clear, suppresses RTL generation. */ static int -arm_gen_constant (enum rtx_code code, enum machine_mode mode, +arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, HOST_WIDE_INT val, rtx target, rtx source, int subtargets, int generate) { @@ -1310,8 +1797,9 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (remainder == 0xffffffff) { if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, - GEN_INT (ARM_SIGN_EXTEND (val)))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + GEN_INT (ARM_SIGN_EXTEND (val)))); return 1; } if (remainder == 0) @@ -1319,7 +1807,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (reload_completed && rtx_equal_p (target, source)) return 0; if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, source)); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, source)); return 1; } break; @@ -1328,7 +1817,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (remainder == 0) { if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, const0_rtx)); return 1; } if (remainder == 0xffffffff) @@ -1336,7 +1826,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (reload_completed && rtx_equal_p (target, source)) return 0; if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, source)); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, source)); return 1; } can_invert = 1; @@ -1348,19 +1839,19 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (reload_completed && rtx_equal_p (target, source)) return 0; if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, source)); - return 1; - } - if (remainder == 0xffffffff) - { - if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_NOT (mode, source))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, source)); return 1; } - /* We don't know how to handle this yet below. */ - abort (); + /* We don't know how to handle other cases yet. */ + gcc_assert (remainder == 0xffffffff); + + if (generate) + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_NOT (mode, source))); + return 1; case MINUS: /* We treat MINUS as (val - source), since (source - val) is always @@ -1368,16 +1859,18 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (remainder == 0) { if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_NEG (mode, source))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_NEG (mode, source))); return 1; } if (const_ok_for_arm (val)) { if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_MINUS (mode, GEN_INT (val), - source))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_MINUS (mode, GEN_INT (val), + source))); return 1; } can_negate = 1; @@ -1385,7 +1878,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, break; default: - abort (); + gcc_unreachable (); } /* If we can do it in one insn get out quickly. */ @@ -1394,10 +1887,12 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, || (can_invert && const_ok_for_arm (~val))) { if (generate) - emit_insn (gen_rtx_SET (VOIDmode, target, - (source ? gen_rtx (code, mode, source, - GEN_INT (val)) - : GEN_INT (val)))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + (source + ? gen_rtx_fmt_ee (code, mode, source, + GEN_INT (val)) + : GEN_INT (val)))); return 1; } @@ -1444,16 +1939,18 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (set_sign_bit_copies > 1) { if (const_ok_for_arm - (temp1 = ARM_SIGN_EXTEND (remainder + (temp1 = ARM_SIGN_EXTEND (remainder << (set_sign_bit_copies - 1)))) { if (generate) { rtx new_src = subtargets ? gen_reg_rtx (mode) : target; - emit_insn (gen_rtx_SET (VOIDmode, new_src, - GEN_INT (temp1))); - emit_insn (gen_ashrsi3 (target, new_src, - GEN_INT (set_sign_bit_copies - 1))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, new_src, + GEN_INT (temp1))); + emit_constant_insn (cond, + gen_ashrsi3 (target, new_src, + GEN_INT (set_sign_bit_copies - 1))); } return 2; } @@ -1465,11 +1962,48 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (generate) { rtx new_src = subtargets ? gen_reg_rtx (mode) : target; - emit_insn (gen_rtx_SET (VOIDmode, new_src, - GEN_INT (temp1))); - emit_insn (gen_ashrsi3 (target, new_src, - GEN_INT (set_sign_bit_copies - 1))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, new_src, + GEN_INT (temp1))); + emit_constant_insn (cond, + gen_ashrsi3 (target, new_src, + GEN_INT (set_sign_bit_copies - 1))); + } + return 2; + } + } + + /* See if we can calculate the value as the difference between two + valid immediates. */ + if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) + { + int topshift = clear_sign_bit_copies & ~1; + + temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) + & (0xff000000 >> topshift)); + + /* If temp1 is zero, then that means the 9 most significant + bits of remainder were 1 and we've caused it to overflow. + When topshift is 0 we don't need to do anything since we + can borrow from 'bit 32'. */ + if (temp1 == 0 && topshift != 0) + temp1 = 0x80000000 >> (topshift - 1); + + temp2 = ARM_SIGN_EXTEND (temp1 - remainder); + + if (const_ok_for_arm (temp2)) + { + if (generate) + { + rtx new_src = subtargets ? gen_reg_rtx (mode) : target; + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, new_src, + GEN_INT (temp1))); + emit_constant_insn (cond, + gen_addsi3 (target, new_src, + GEN_INT (-temp2))); } + return 2; } } @@ -1493,16 +2027,18 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx new_src = (subtargets ? (generate ? gen_reg_rtx (mode) : NULL_RTX) : target); - insns = arm_gen_constant (code, mode, temp2, new_src, + insns = arm_gen_constant (code, mode, cond, temp2, new_src, source, subtargets, generate); source = new_src; if (generate) - emit_insn (gen_rtx_SET - (VOIDmode, target, - gen_rtx_IOR (mode, - gen_rtx_ASHIFT (mode, source, - GEN_INT (i)), - source))); + emit_constant_insn + (cond, + gen_rtx_SET + (VOIDmode, target, + gen_rtx_IOR (mode, + gen_rtx_ASHIFT (mode, source, + GEN_INT (i)), + source))); return insns + 1; } } @@ -1516,12 +2052,13 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx new_src = (subtargets ? (generate ? gen_reg_rtx (mode) : NULL_RTX) : target); - insns = arm_gen_constant (code, mode, temp1, new_src, + insns = arm_gen_constant (code, mode, cond, temp1, new_src, source, subtargets, generate); source = new_src; if (generate) - emit_insn - (gen_rtx_SET (VOIDmode, target, + emit_constant_insn + (cond, + gen_rtx_SET (VOIDmode, target, gen_rtx_IOR (mode, gen_rtx_LSHIFTRT (mode, source, @@ -1548,9 +2085,13 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, { rtx sub = subtargets ? gen_reg_rtx (mode) : target; - emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx (code, mode, source, sub))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, sub, + GEN_INT (val))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_fmt_ee (code, mode, + source, sub))); } return 2; } @@ -1567,15 +2108,19 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx sub = subtargets ? gen_reg_rtx (mode) : target; rtx shift = GEN_INT (set_sign_bit_copies); - emit_insn (gen_rtx_SET (VOIDmode, sub, - gen_rtx_NOT (mode, - gen_rtx_ASHIFT (mode, - source, - shift)))); - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_NOT (mode, - gen_rtx_LSHIFTRT (mode, sub, - shift)))); + emit_constant_insn + (cond, + gen_rtx_SET (VOIDmode, sub, + gen_rtx_NOT (mode, + gen_rtx_ASHIFT (mode, + source, + shift)))); + emit_constant_insn + (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_NOT (mode, + gen_rtx_LSHIFTRT (mode, sub, + shift)))); } return 2; } @@ -1588,15 +2133,19 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx sub = subtargets ? gen_reg_rtx (mode) : target; rtx shift = GEN_INT (set_zero_bit_copies); - emit_insn (gen_rtx_SET (VOIDmode, sub, - gen_rtx_NOT (mode, - gen_rtx_LSHIFTRT (mode, - source, - shift)))); - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_NOT (mode, - gen_rtx_ASHIFT (mode, sub, - shift)))); + emit_constant_insn + (cond, + gen_rtx_SET (VOIDmode, sub, + gen_rtx_NOT (mode, + gen_rtx_LSHIFTRT (mode, + source, + shift)))); + emit_constant_insn + (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_NOT (mode, + gen_rtx_ASHIFT (mode, sub, + shift)))); } return 2; } @@ -1606,16 +2155,19 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (generate) { rtx sub = subtargets ? gen_reg_rtx (mode) : target; - emit_insn (gen_rtx_SET (VOIDmode, sub, - gen_rtx_NOT (mode, source))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, sub, + gen_rtx_NOT (mode, source))); source = sub; if (subtargets) sub = gen_reg_rtx (mode); - emit_insn (gen_rtx_SET (VOIDmode, sub, - gen_rtx_AND (mode, source, - GEN_INT (temp1)))); - emit_insn (gen_rtx_SET (VOIDmode, target, - gen_rtx_NOT (mode, sub))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, sub, + gen_rtx_AND (mode, source, + GEN_INT (temp1)))); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, target, + gen_rtx_NOT (mode, sub))); } return 3; } @@ -1634,14 +2186,16 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (generate) { rtx new_src = subtargets ? gen_reg_rtx (mode) : target; - insns = arm_gen_constant (AND, mode, remainder | shift_mask, + insns = arm_gen_constant (AND, mode, cond, + remainder | shift_mask, new_src, source, subtargets, 1); source = new_src; } else { rtx targ = subtargets ? NULL_RTX : target; - insns = arm_gen_constant (AND, mode, remainder | shift_mask, + insns = arm_gen_constant (AND, mode, cond, + remainder | shift_mask, targ, source, subtargets, 0); } } @@ -1661,14 +2215,15 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) { HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; - + if ((remainder | shift_mask) != 0xffffffff) { if (generate) { rtx new_src = subtargets ? gen_reg_rtx (mode) : target; - insns = arm_gen_constant (AND, mode, remainder | shift_mask, + insns = arm_gen_constant (AND, mode, cond, + remainder | shift_mask, new_src, source, subtargets, 1); source = new_src; } @@ -1676,7 +2231,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, { rtx targ = subtargets ? NULL_RTX : target; - insns = arm_gen_constant (AND, mode, remainder | shift_mask, + insns = arm_gen_constant (AND, mode, cond, + remainder | shift_mask, targ, source, subtargets, 0); } } @@ -1763,12 +2319,12 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rather than having to synthesize both large constants from scratch. Therefore, we calculate how many insns would be required to emit - the constant starting from `best_start', and also starting from - zero (ie with bit 31 first to be output). If `best_start' doesn't + the constant starting from `best_start', and also starting from + zero (i.e. with bit 31 first to be output). If `best_start' doesn't yield a shorter sequence, we may as well use zero. */ if (best_start != 0 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) - && (count_insns_for_constant (remainder, 0) <= + && (count_insns_for_constant (remainder, 0) <= count_insns_for_constant (remainder, best_start))) best_start = 0; @@ -1821,7 +2377,9 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, else temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); - emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx)); + emit_constant_insn (cond, + gen_rtx_SET (VOIDmode, new_src, + temp1_rtx)); source = new_src; } @@ -1849,9 +2407,12 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, immediate value easier to load. */ enum rtx_code -arm_canonicalize_comparison (enum rtx_code code, rtx * op1) +arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, + rtx * op1) { unsigned HOST_WIDE_INT i = INTVAL (*op1); + unsigned HOST_WIDE_INT maxval; + maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; switch (code) { @@ -1861,7 +2422,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx * op1) case GT: case LE: - if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) + if (i != maxval && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) { *op1 = GEN_INT (i + 1); @@ -1871,7 +2432,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx * op1) case GE: case LT: - if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) + if (i != ~maxval && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) { *op1 = GEN_INT (i - 1); @@ -1900,12 +2461,65 @@ arm_canonicalize_comparison (enum rtx_code code, rtx * op1) break; default: - abort (); + gcc_unreachable (); } return code; } + +/* Define how to find the value returned by a function. */ + +rtx +arm_function_value(tree type, tree func ATTRIBUTE_UNUSED) +{ + enum machine_mode mode; + int unsignedp ATTRIBUTE_UNUSED; + rtx r ATTRIBUTE_UNUSED; + + mode = TYPE_MODE (type); + /* Promote integer types. */ + if (INTEGRAL_TYPE_P (type)) + PROMOTE_FUNCTION_MODE (mode, unsignedp, type); + + /* Promotes small structs returned in a register to full-word size + for big-endian AAPCS. */ + if (arm_return_in_msb (type)) + { + HOST_WIDE_INT size = int_size_in_bytes (type); + if (size % UNITS_PER_WORD != 0) + { + size += UNITS_PER_WORD - size % UNITS_PER_WORD; + mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); + } + } + + return LIBCALL_VALUE(mode); +} + +/* Determine the amount of memory needed to store the possible return + registers of an untyped call. */ +int +arm_apply_result_size (void) +{ + int size = 16; + + if (TARGET_ARM) + { + if (TARGET_HARD_FLOAT_ABI) + { + if (TARGET_FPA) + size += 12; + if (TARGET_MAVERICK) + size += 8; + } + if (TARGET_IWMMXT_ABI) + size += 8; + } + + return size; +} + /* Decide whether a type should be returned in memory (true) or in a register (false). This is called by the macro RETURN_IN_MEMORY. */ @@ -1914,19 +2528,27 @@ arm_return_in_memory (tree type) { HOST_WIDE_INT size; - if (!AGGREGATE_TYPE_P (type)) - /* All simple types are returned in registers. */ + if (!AGGREGATE_TYPE_P (type) && + (TREE_CODE (type) != VECTOR_TYPE) && + !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) + /* All simple types are returned in registers. + For AAPCS, complex types are treated the same as aggregates. */ return 0; size = int_size_in_bytes (type); - if (TARGET_ATPCS) + if (arm_abi != ARM_ABI_APCS) { - /* ATPCS returns aggregate types in memory only if they are + /* ATPCS and later return aggregate types in memory only if they are larger than a word (or are variable size). */ return (size < 0 || size > UNITS_PER_WORD); } - + + /* To maximize backwards compatibility with previous versions of gcc, + return vectors up to 4 words in registers. */ + if (TREE_CODE (type) == VECTOR_TYPE) + return (size < 0 || size > (4 * UNITS_PER_WORD)); + /* For the arm-wince targets we choose to be compatible with Microsoft's ARM and Thumb compilers, which always return aggregates in memory. */ #ifndef ARM_WINCE @@ -1936,7 +2558,7 @@ arm_return_in_memory (tree type) we will want to return it via memory and not in a register. */ if (size < 0 || size > UNITS_PER_WORD) return 1; - + if (TREE_CODE (type) == RECORD_TYPE) { tree field; @@ -1946,14 +2568,14 @@ arm_return_in_memory (tree type) has an offset of zero. For practical purposes this means that the structure can have at most one non bit-field element and that this element must be the first one in the structure. */ - + /* Find the first field, ignoring non FIELD_DECL things which will have been created by C++. */ for (field = TYPE_FIELDS (type); field && TREE_CODE (field) != FIELD_DECL; field = TREE_CHAIN (field)) continue; - + if (field == NULL) return 0; /* An empty structure. Allowed by an extension to ANSI C. */ @@ -1976,14 +2598,14 @@ arm_return_in_memory (tree type) { if (TREE_CODE (field) != FIELD_DECL) continue; - + if (!DECL_BIT_FIELD_TYPE (field)) return 1; } return 0; } - + if (TREE_CODE (type) == UNION_TYPE) { tree field; @@ -1999,15 +2621,15 @@ arm_return_in_memory (tree type) if (FLOAT_TYPE_P (TREE_TYPE (field))) return 1; - + if (RETURN_IN_MEMORY (TREE_TYPE (field))) return 1; } - + return 0; } -#endif /* not ARM_WINCE */ - +#endif /* not ARM_WINCE */ + /* Return all other types in memory. */ return 1; } @@ -2017,15 +2639,14 @@ arm_return_in_memory (tree type) int arm_float_words_big_endian (void) { - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) return 0; /* For FPA, float words are always big-endian. For VFP, floats words follow the memory system mode. */ - if (TARGET_HARD_FLOAT) + if (TARGET_FPA) { - /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */ return 1; } @@ -2039,19 +2660,20 @@ arm_float_words_big_endian (void) for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is NULL. */ void -arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, +arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, rtx libname ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNUSED) { /* On the ARM, the offset starts at 0. */ - pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0); + pcum->nregs = 0; pcum->iwmmxt_nregs = 0; - + pcum->can_split = true; + pcum->call_cookie = CALL_NORMAL; if (TARGET_LONG_CALLS) pcum->call_cookie = CALL_LONG; - + /* Check for long call/short call attributes. The attributes override any command line option. */ if (fntype) @@ -2081,6 +2703,16 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, } } + +/* Return true if mode/type need doubleword alignment. */ +bool +arm_needs_doubleword_align (enum machine_mode mode, tree type) +{ + return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY + || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); +} + + /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. @@ -2096,92 +2728,81 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, rtx arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, - tree type ATTRIBUTE_UNUSED, int named) + tree type, int named) { - if (TARGET_REALLY_IWMMXT) + int nregs; + + /* Varargs vectors are treated the same as long long. + named_count avoids having to change the way arm handles 'named' */ + if (TARGET_IWMMXT_ABI + && arm_vector_mode_supported_p (mode) + && pcum->named_count > pcum->nargs + 1) { - if (VECTOR_MODE_SUPPORTED_P (mode)) + if (pcum->iwmmxt_nregs <= 9) + return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); + else { - /* varargs vectors are treated the same as long long. - named_count avoids having to change the way arm handles 'named' */ - if (pcum->named_count <= pcum->nargs + 1) - { - if (pcum->nregs == 1) - pcum->nregs += 1; - if (pcum->nregs <= 2) - return gen_rtx_REG (mode, pcum->nregs); - else - return NULL_RTX; - } - else if (pcum->iwmmxt_nregs <= 9) - return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); - else - return NULL_RTX; + pcum->can_split = false; + return NULL_RTX; } - else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1) - pcum->nregs += 1; } + /* Put doubleword aligned quantities in even register pairs. */ + if (pcum->nregs & 1 + && ARM_DOUBLEWORD_ALIGN + && arm_needs_doubleword_align (mode, type)) + pcum->nregs++; + if (mode == VOIDmode) /* Compute operand 2 of the call insn. */ return GEN_INT (pcum->call_cookie); - - if (!named || pcum->nregs >= NUM_ARG_REGS) + + /* Only allow splitting an arg between regs and memory if all preceding + args were allocated to regs. For args passed by reference we only count + the reference pointer. */ + if (pcum->can_split) + nregs = 1; + else + nregs = ARM_NUM_REGS2 (mode, type); + + if (!named || pcum->nregs + nregs > NUM_ARG_REGS) return NULL_RTX; - + return gen_rtx_REG (mode, pcum->nregs); } -/* Variable sized types are passed by reference. This is a GCC - extension to the ARM ABI. */ - -int -arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, - enum machine_mode mode ATTRIBUTE_UNUSED, - tree type, int named ATTRIBUTE_UNUSED) +static int +arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, + tree type, bool named ATTRIBUTE_UNUSED) { - return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; -} - -/* Implement va_arg. */ + int nregs = pcum->nregs; -rtx -arm_va_arg (tree valist, tree type) -{ - /* Variable sized types are passed by reference. */ - if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) - { - rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type)); - return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr)); - } + if (arm_vector_mode_supported_p (mode)) + return 0; - if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT) - { - tree minus_eight; - tree t; + if (NUM_ARG_REGS > nregs + && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) + && pcum->can_split) + return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; - /* Maintain 64-bit alignment of the valist pointer by - constructing: valist = ((valist + (8 - 1)) & -8). */ - minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1); - t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0); - t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t); - t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight); - t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + return 0; +} - /* This is to stop the combine pass optimizing - away the alignment adjustment. */ - mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); - } +/* Variable sized types are passed by reference. This is a GCC + extension to the ARM ABI. */ - return std_expand_builtin_va_arg (valist, type); +static bool +arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type, bool named ATTRIBUTE_UNUSED) +{ + return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; } /* Encode the current state of the #pragma [no_]long_calls. */ typedef enum { - OFF, /* No #pramgma [no_]long_calls is in effect. */ + OFF, /* No #pragma [no_]long_calls is in effect. */ LONG, /* #pragma long_calls is in effect. */ SHORT /* #pragma no_long_calls is in effect. */ } arm_pragma_enum; @@ -2217,7 +2838,7 @@ const struct attribute_spec arm_attribute_table[] = /* Whereas these functions are always known to reside within the 26 bit addressing range. */ { "short_call", 0, 0, false, true, true, NULL }, - /* Interrupt Service Routines have special prologue and epilogue requirements. */ + /* Interrupt Service Routines have special prologue and epilogue requirements. */ { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, @@ -2234,6 +2855,10 @@ const struct attribute_spec arm_attribute_table[] = { "dllimport", 0, 0, true, false, false, NULL }, { "dllexport", 0, 0, true, false, false, NULL }, { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, +#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES + { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, + { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, + { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, #endif { NULL, 0, 0, false, false, false, NULL } }; @@ -2246,7 +2871,7 @@ arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, { if (TREE_CODE (*node) != FUNCTION_DECL) { - warning ("`%s' attribute only applies to functions", + warning (OPT_Wattributes, "%qs attribute only applies to functions", IDENTIFIER_POINTER (name)); *no_add_attrs = true; } @@ -2264,7 +2889,7 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, { if (TREE_CODE (*node) != FUNCTION_DECL) { - warning ("`%s' attribute only applies to functions", + warning (OPT_Wattributes, "%qs attribute only applies to functions", IDENTIFIER_POINTER (name)); *no_add_attrs = true; } @@ -2278,7 +2903,8 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, { if (arm_isr_value (args) == ARM_FT_UNKNOWN) { - warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); + warning (OPT_Wattributes, "%qs attribute ignored", + IDENTIFIER_POINTER (name)); *no_add_attrs = true; } } @@ -2287,7 +2913,7 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) && arm_isr_value (args) != ARM_FT_UNKNOWN) { - *node = build_type_copy (*node); + *node = build_variant_type_copy (*node); TREE_TYPE (*node) = build_type_attribute_variant (TREE_TYPE (*node), tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); @@ -2305,7 +2931,8 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, } else { - warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); + warning (OPT_Wattributes, "%qs attribute ignored", + IDENTIFIER_POINTER (name)); } } } @@ -2313,6 +2940,31 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, return NULL_TREE; } +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES +/* Handle the "notshared" attribute. This attribute is another way of + requesting hidden visibility. ARM's compiler supports + "__declspec(notshared)"; we support the same thing via an + attribute. */ + +static tree +arm_handle_notshared_attribute (tree *node, + tree name ATTRIBUTE_UNUSED, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, + bool *no_add_attrs) +{ + tree decl = TYPE_NAME (*node); + + if (decl) + { + DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; + DECL_VISIBILITY_SPECIFIED (decl) = 1; + *no_add_attrs = false; + } + return NULL_TREE; +} +#endif + /* Return 0 if the attributes for two types are incompatible, 1 if they are compatible, and 2 if they are nearly compatible (which causes a warning to be generated). */ @@ -2320,7 +2972,7 @@ static int arm_comp_type_attributes (tree type1, tree type2) { int l1, l2, s1, s2; - + /* Check for mismatch of non-default calling convention. */ if (TREE_CODE (type1) != FUNCTION_TYPE) return 1; @@ -2342,7 +2994,7 @@ arm_comp_type_attributes (tree type1, tree type2) if ((l1 & s2) || (l2 & s1)) return 0; } - + /* Check for mismatched ISR attribute. */ l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; if (! l1) @@ -2416,7 +3068,7 @@ current_file_function_operand (rtx sym_ref) return 1; /* The current function is always defined within the current compilation - unit. if it s a weak definition however, then this may not be the real + unit. If it s a weak definition however, then this may not be the real definition of the function, and so we have to say no. */ if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) && !DECL_WEAK (current_function_decl)) @@ -2432,16 +3084,19 @@ current_file_function_operand (rtx sym_ref) a. has an __attribute__((long call)) or b. is within the scope of a #pragma long_calls or c. the -mlong-calls command line switch has been specified + . and either: + 1. -ffunction-sections is in effect + or 2. the current function has __attribute__ ((section)) + or 3. the target function has __attribute__ ((section)) However we do not generate a long call if the function: - + d. has an __attribute__ ((short_call)) or e. is inside the scope of a #pragma no_long_calls - or f. has an __attribute__ ((section)) - or g. is defined within the current compilation unit. - + or f. is defined within the current compilation unit. + This function will be called by C fragments contained in the machine - description file. CALL_REF and CALL_COOKIE correspond to the matched + description file. SYM_REF and CALL_COOKIE correspond to the matched rtl operands. CALL_SYMBOL is used to distinguish between two different callers of the function. It is set to 1 in the "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" @@ -2464,12 +3119,18 @@ arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) if (call_cookie & CALL_SHORT) return 0; - if (TARGET_LONG_CALLS && flag_function_sections) - return 1; - + if (TARGET_LONG_CALLS) + { + if (flag_function_sections + || DECL_SECTION_NAME (current_function_decl)) + /* c.3 is handled by the definition of the + ARM_DECLARE_FUNCTION_SIZE macro. */ + return 1; + } + if (current_file_function_operand (sym_ref)) return 0; - + return (call_cookie & CALL_LONG) || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) || TARGET_LONG_CALLS; @@ -2502,7 +3163,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) return false; /* If we are interworking and the function is not declared static - then we can't tail-call it unless we know that it exists in this + then we can't tail-call it unless we know that it exists in this compilation unit (since it might be a Thumb routine). */ if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) return false; @@ -2519,16 +3180,14 @@ arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) /* Addressing mode support functions. */ /* Return nonzero if X is a legitimate immediate operand when compiling - for PIC. */ + for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ int legitimate_pic_operand_p (rtx x) { - if (CONSTANT_P (x) - && flag_pic - && (GET_CODE (x) == SYMBOL_REF - || (GET_CODE (x) == CONST - && GET_CODE (XEXP (x, 0)) == PLUS - && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) + if (GET_CODE (x) == SYMBOL_REF + || (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) return 0; return 1; @@ -2546,12 +3205,53 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) rtx insn; int subregs = 0; + /* If this function doesn't have a pic register, create one now. + A lot of the logic here is made obscure by the fact that this + routine gets called as part of the rtx cost estimation + process. We don't want those calls to affect any assumptions + about the real function; and further, we can't call + entry_of_function() until we start the real expansion + process. */ + if (!current_function_uses_pic_offset_table) + { + gcc_assert (!no_new_pseudos); + if (arm_pic_register != INVALID_REGNUM) + { + cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); + + /* Play games to avoid marking the function as needing pic + if we are being called as part of the cost-estimation + process. */ + if (!ir_type()) + current_function_uses_pic_offset_table = 1; + } + else + { + rtx seq; + + cfun->machine->pic_reg = gen_reg_rtx (Pmode); + + /* Play games to avoid marking the function as needing pic + if we are being called as part of the cost-estimation + process. */ + if (!ir_type()) + { + current_function_uses_pic_offset_table = 1; + start_sequence (); + + arm_load_pic_register (0UL); + + seq = get_insns (); + end_sequence (); + emit_insn_after (seq, entry_of_function ()); + } + } + } + if (reg == 0) { - if (no_new_pseudos) - abort (); - else - reg = gen_reg_rtx (Pmode); + gcc_assert (!no_new_pseudos); + reg = gen_reg_rtx (Pmode); subregs = 1; } @@ -2572,21 +3272,19 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) emit_insn (gen_pic_load_addr_thumb (address, orig)); if ((GET_CODE (orig) == LABEL_REF - || (GET_CODE (orig) == SYMBOL_REF && + || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) && NEED_GOT_RELOC) - pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); + pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); else { - pic_ref = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, pic_offset_table_rtx, - address)); - RTX_UNCHANGING_P (pic_ref) = 1; + pic_ref = gen_const_mem (Pmode, + gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, + address)); } insn = emit_move_insn (reg, pic_ref); #endif - current_function_uses_pic_offset_table = 1; /* Put a REG_EQUAL note on this insn, so that it can be optimized by loop. */ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, @@ -2598,36 +3296,33 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) rtx base, offset; if (GET_CODE (XEXP (orig, 0)) == PLUS - && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) + && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) + return orig; + + if (GET_CODE (XEXP (orig, 0)) == UNSPEC + && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) return orig; if (reg == 0) { - if (no_new_pseudos) - abort (); - else - reg = gen_reg_rtx (Pmode); + gcc_assert (!no_new_pseudos); + reg = gen_reg_rtx (Pmode); } - if (GET_CODE (XEXP (orig, 0)) == PLUS) - { - base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); - offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, - base == reg ? 0 : reg); - } - else - abort (); + gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); + + base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); + offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, + base == reg ? 0 : reg); if (GET_CODE (offset) == CONST_INT) { /* The base register doesn't really matter, we only want to test the index for the appropriate mode. */ - if (!arm_legitimate_index_p (mode, offset, 0)) + if (!arm_legitimate_index_p (mode, offset, SET, 0)) { - if (!no_new_pseudos) - offset = force_reg (Pmode, offset); - else - abort (); + gcc_assert (!no_new_pseudos); + offset = force_reg (Pmode, offset); } if (GET_CODE (offset) == CONST_INT) @@ -2648,31 +3343,89 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) return orig; } -/* Generate code to load the PIC register. PROLOGUE is true if - called from arm_expand_prologue (in which case we want the - generated insns at the start of the function); false if called - by an exception receiver that needs the PIC register reloaded - (in which case the insns are just dumped at the current location). */ + +/* Find a spare low register to use during the prolog of a function. */ + +static int +thumb_find_work_register (unsigned long pushed_regs_mask) +{ + int reg; + + /* Check the argument registers first as these are call-used. The + register allocation order means that sometimes r3 might be used + but earlier argument registers might not, so check them all. */ + for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) + if (!regs_ever_live[reg]) + return reg; + + /* Before going on to check the call-saved registers we can try a couple + more ways of deducing that r3 is available. The first is when we are + pushing anonymous arguments onto the stack and we have less than 4 + registers worth of fixed arguments(*). In this case r3 will be part of + the variable argument list and so we can be sure that it will be + pushed right at the start of the function. Hence it will be available + for the rest of the prologue. + (*): ie current_function_pretend_args_size is greater than 0. */ + if (cfun->machine->uses_anonymous_args + && current_function_pretend_args_size > 0) + return LAST_ARG_REGNUM; + + /* The other case is when we have fixed arguments but less than 4 registers + worth. In this case r3 might be used in the body of the function, but + it is not being used to convey an argument into the function. In theory + we could just check current_function_args_size to see how many bytes are + being passed in argument registers, but it seems that it is unreliable. + Sometimes it will have the value 0 when in fact arguments are being + passed. (See testcase execute/20021111-1.c for an example). So we also + check the args_info.nregs field as well. The problem with this field is + that it makes no allowances for arguments that are passed to the + function but which are not used. Hence we could miss an opportunity + when a function has an unused argument in r3. But it is better to be + safe than to be sorry. */ + if (! cfun->machine->uses_anonymous_args + && current_function_args_size >= 0 + && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) + && cfun->args_info.nregs < 4) + return LAST_ARG_REGNUM; + + /* Otherwise look for a call-saved register that is going to be pushed. */ + for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) + if (pushed_regs_mask & (1 << reg)) + return reg; + + /* Something went wrong - thumb_compute_save_reg_mask() + should have arranged for a suitable register to be pushed. */ + gcc_unreachable (); +} + +static GTY(()) int pic_labelno; + +/* Generate code to load the PIC register. In thumb mode SCRATCH is a + low register. */ + void -arm_finalize_pic (int prologue ATTRIBUTE_UNUSED) +arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) { #ifndef AOF_ASSEMBLER - rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; + rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx; rtx global_offset_table; if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) return; - if (!flag_pic) - abort (); + gcc_assert (flag_pic); - start_sequence (); - l1 = gen_label_rtx (); + /* We use an UNSPEC rather than a LABEL_REF because this label never appears + in the code stream. */ + + labelno = GEN_INT (pic_labelno++); + l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); + l1 = gen_rtx_CONST (VOIDmode, l1); global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); /* On the ARM the PC register contains 'dot + 8' at the time of the addition, on the Thumb it is 'dot + 4'. */ - pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); + pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4); if (GOT_PCREL) pic_tmp2 = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); @@ -2680,31 +3433,38 @@ arm_finalize_pic (int prologue ATTRIBUTE_UNUSED) pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); - + if (TARGET_ARM) { - emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); - emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); + emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx)); + emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg, + cfun->machine->pic_reg, labelno)); } else { - emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); - emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); + if (arm_pic_register != INVALID_REGNUM + && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM) + { + /* We will have pushed the pic register, so we should always be + able to find a work register. */ + pic_tmp = gen_rtx_REG (SImode, + thumb_find_work_register (saved_regs)); + emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx)); + emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); + } + else + emit_insn (gen_pic_load_addr_thumb (cfun->machine->pic_reg, pic_rtx)); + emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg, + cfun->machine->pic_reg, labelno)); } - seq = get_insns (); - end_sequence (); - if (prologue) - emit_insn_after (seq, get_insns ()); - else - emit_insn (seq); - /* Need to emit this whether or not we obey regdecls, since setjmp/longjmp can cause life info to screw up. */ - emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); + emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg)); #endif /* AOF_ASSEMBLER */ } + /* Return nonzero if X is valid as an ARM state addressing register. */ static int arm_address_register_rtx_p (rtx x, int strict_p) @@ -2725,28 +3485,62 @@ arm_address_register_rtx_p (rtx x, int strict_p) || regno == ARG_POINTER_REGNUM); } +/* Return TRUE if this rtx is the difference of a symbol and a label, + and will reduce to a PC-relative relocation in the object file. + Expressions like this can be left alone when generating PIC, rather + than forced through the GOT. */ +static int +pcrel_constant_p (rtx x) +{ + if (GET_CODE (x) == MINUS) + return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); + + return FALSE; +} + /* Return nonzero if X is a valid ARM state address operand. */ int -arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) +arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, + int strict_p) { + bool use_ldrd; + enum rtx_code code = GET_CODE (x); + if (arm_address_register_rtx_p (x, strict_p)) return 1; - else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) + use_ldrd = (TARGET_LDRD + && (mode == DImode + || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); + + if (code == POST_INC || code == PRE_DEC + || ((code == PRE_INC || code == POST_DEC) + && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) return arm_address_register_rtx_p (XEXP (x, 0), strict_p); - else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY) - && GET_MODE_SIZE (mode) <= 4 + else if ((code == POST_MODIFY || code == PRE_MODIFY) && arm_address_register_rtx_p (XEXP (x, 0), strict_p) && GET_CODE (XEXP (x, 1)) == PLUS && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) - return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p); + { + rtx addend = XEXP (XEXP (x, 1), 1); + + /* Don't allow ldrd post increment by register because it's hard + to fixup invalid register choices. */ + if (use_ldrd + && GET_CODE (x) == POST_MODIFY + && GET_CODE (addend) == REG) + return 0; + + return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) + && arm_legitimate_index_p (mode, addend, outer, strict_p)); + } /* After reload constants split into minipools will have addresses from a LABEL_REF. */ else if (reload_completed - && (GET_CODE (x) == LABEL_REF - || (GET_CODE (x) == CONST + && (code == LABEL_REF + || (code == CONST && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) @@ -2755,28 +3549,15 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) else if (mode == TImode) return 0; - else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) - { - if (GET_CODE (x) == PLUS - && arm_address_register_rtx_p (XEXP (x, 0), strict_p) - && GET_CODE (XEXP (x, 1)) == CONST_INT) - { - HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); - - if (val == 4 || val == -4 || val == -8) - return 1; - } - } - - else if (GET_CODE (x) == PLUS) + else if (code == PLUS) { rtx xop0 = XEXP (x, 0); rtx xop1 = XEXP (x, 1); return ((arm_address_register_rtx_p (xop0, strict_p) - && arm_legitimate_index_p (mode, xop1, strict_p)) + && arm_legitimate_index_p (mode, xop1, outer, strict_p)) || (arm_address_register_rtx_p (xop1, strict_p) - && arm_legitimate_index_p (mode, xop0, strict_p))); + && arm_legitimate_index_p (mode, xop0, outer, strict_p))); } #if 0 @@ -2787,20 +3568,16 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) rtx xop1 = XEXP (x, 1); return (arm_address_register_rtx_p (xop0, strict_p) - && arm_legitimate_index_p (mode, xop1, strict_p)); + && arm_legitimate_index_p (mode, xop1, outer, strict_p)); } #endif else if (GET_MODE_CLASS (mode) != MODE_FLOAT - && GET_CODE (x) == SYMBOL_REF + && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x) && ! (flag_pic - && symbol_mentioned_p (get_pool_constant (x)))) - return 1; - - else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC) - && (GET_MODE_SIZE (mode) <= 4) - && arm_address_register_rtx_p (XEXP (x, 0), strict_p)) + && symbol_mentioned_p (get_pool_constant (x)) + && ! pcrel_constant_p (get_pool_constant (x)))) return 1; return 0; @@ -2809,63 +3586,87 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) /* Return nonzero if INDEX is valid for an address index operand in ARM state. */ static int -arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) +arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, + int strict_p) { HOST_WIDE_INT range; enum rtx_code code = GET_CODE (index); - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + /* Standard coprocessor addressing modes. */ + if (TARGET_HARD_FLOAT + && (TARGET_FPA || TARGET_MAVERICK) + && (GET_MODE_CLASS (mode) == MODE_FLOAT + || (TARGET_MAVERICK && mode == DImode))) return (code == CONST_INT && INTVAL (index) < 1024 && INTVAL (index) > -1024 && (INTVAL (index) & 3) == 0); - if (TARGET_CIRRUS - && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode)) - return (code == CONST_INT - && INTVAL (index) < 255 - && INTVAL (index) > -255); + if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) + { + /* For DImode assume values will usually live in core regs + and only allow LDRD addressing modes. */ + if (!TARGET_LDRD || mode != DImode) + return (code == CONST_INT + && INTVAL (index) < 1024 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + } if (arm_address_register_rtx_p (index, strict_p) - && GET_MODE_SIZE (mode) <= 4) + && (GET_MODE_SIZE (mode) <= 4)) return 1; - if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) - return (code == CONST_INT - && INTVAL (index) < 256 - && INTVAL (index) > -256); - - /* XXX What about ldrsb? */ - if (GET_MODE_SIZE (mode) <= 4 && code == MULT - && (!arm_arch4 || (mode) != HImode)) + if (mode == DImode || mode == DFmode) { - rtx xiop0 = XEXP (index, 0); - rtx xiop1 = XEXP (index, 1); + if (code == CONST_INT) + { + HOST_WIDE_INT val = INTVAL (index); + + if (TARGET_LDRD) + return val > -256 && val < 256; + else + return val > -4096 && val < 4092; + } - return ((arm_address_register_rtx_p (xiop0, strict_p) - && power_of_two_operand (xiop1, SImode)) - || (arm_address_register_rtx_p (xiop1, strict_p) - && power_of_two_operand (xiop0, SImode))); + return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); } if (GET_MODE_SIZE (mode) <= 4 - && (code == LSHIFTRT || code == ASHIFTRT - || code == ASHIFT || code == ROTATERT) - && (!arm_arch4 || (mode) != HImode)) + && ! (arm_arch4 + && (mode == HImode + || (mode == QImode && outer == SIGN_EXTEND)))) { - rtx op = XEXP (index, 1); + if (code == MULT) + { + rtx xiop0 = XEXP (index, 0); + rtx xiop1 = XEXP (index, 1); - return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) - && GET_CODE (op) == CONST_INT - && INTVAL (op) > 0 - && INTVAL (op) <= 31); + return ((arm_address_register_rtx_p (xiop0, strict_p) + && power_of_two_operand (xiop1, SImode)) + || (arm_address_register_rtx_p (xiop1, strict_p) + && power_of_two_operand (xiop0, SImode))); + } + else if (code == LSHIFTRT || code == ASHIFTRT + || code == ASHIFT || code == ROTATERT) + { + rtx op = XEXP (index, 1); + + return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) + && GET_CODE (op) == CONST_INT + && INTVAL (op) > 0 + && INTVAL (op) <= 31); + } } - /* XXX For ARM v4 we may be doing a sign-extend operation during the - load, but that has a restricted addressing range and we are unable - to tell here whether that is the case. To be safe we restrict all - loads to that range. */ + /* For ARM v4 we may be doing a sign-extend operation during the + load. */ if (arm_arch4) - range = (mode == HImode || mode == QImode) ? 256 : 4096; + { + if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) + range = 256; + else + range = 4096; + } else range = (mode == HImode) ? 4095 : 4096; @@ -2907,7 +3708,7 @@ thumb_index_register_rtx_p (rtx x, int strict_p) } /* Return nonzero if x is a legitimate Thumb-state address. - + The AP may be eliminated to either the SP or the FP, so we use the least common denominator, e.g. SImode, and offsets from 0 to 64. @@ -2944,7 +3745,7 @@ thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) /* This is PC relative data before arm_reorg runs. */ else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) && GET_CODE (x) == SYMBOL_REF - && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic) + && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) return 1; /* This is PC relative data after arm_reorg runs. */ @@ -3006,8 +3807,9 @@ thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) && GET_MODE_SIZE (mode) == 4 && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x) - && !(flag_pic - && symbol_mentioned_p (get_pool_constant (x)))) + && ! (flag_pic + && symbol_mentioned_p (get_pool_constant (x)) + && ! pcrel_constant_p (get_pool_constant (x)))) return 1; return 0; @@ -3033,11 +3835,166 @@ thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) } } +/* Build the SYMBOL_REF for __tls_get_addr. */ + +static GTY(()) rtx tls_get_addr_libfunc; + +static rtx +get_tls_get_addr (void) +{ + if (!tls_get_addr_libfunc) + tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); + return tls_get_addr_libfunc; +} + +static rtx +arm_load_tp (rtx target) +{ + if (!target) + target = gen_reg_rtx (SImode); + + if (TARGET_HARD_TP) + { + /* Can return in any reg. */ + emit_insn (gen_load_tp_hard (target)); + } + else + { + /* Always returned in r0. Immediately copy the result into a pseudo, + otherwise other uses of r0 (e.g. setting up function arguments) may + clobber the value. */ + + rtx tmp; + + emit_insn (gen_load_tp_soft ()); + + tmp = gen_rtx_REG (SImode, 0); + emit_move_insn (target, tmp); + } + return target; +} + +static rtx +load_tls_operand (rtx x, rtx reg) +{ + rtx tmp; + + if (reg == NULL_RTX) + reg = gen_reg_rtx (SImode); + + tmp = gen_rtx_CONST (SImode, x); + + emit_move_insn (reg, tmp); + + return reg; +} + +static rtx +arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) +{ + rtx insns, label, labelno, sum; + + start_sequence (); + + labelno = GEN_INT (pic_labelno++); + label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); + label = gen_rtx_CONST (VOIDmode, label); + + sum = gen_rtx_UNSPEC (Pmode, + gen_rtvec (4, x, GEN_INT (reloc), label, + GEN_INT (TARGET_ARM ? 8 : 4)), + UNSPEC_TLS); + reg = load_tls_operand (sum, reg); + + if (TARGET_ARM) + emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); + else + emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); + + *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ + Pmode, 1, reg, Pmode); + + insns = get_insns (); + end_sequence (); + + return insns; +} + +rtx +legitimize_tls_address (rtx x, rtx reg) +{ + rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; + unsigned int model = SYMBOL_REF_TLS_MODEL (x); + + switch (model) + { + case TLS_MODEL_GLOBAL_DYNAMIC: + insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); + dest = gen_reg_rtx (Pmode); + emit_libcall_block (insns, dest, ret, x); + return dest; + + case TLS_MODEL_LOCAL_DYNAMIC: + insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); + + /* Attach a unique REG_EQUIV, to allow the RTL optimizers to + share the LDM result with other LD model accesses. */ + eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), + UNSPEC_TLS); + dest = gen_reg_rtx (Pmode); + emit_libcall_block (insns, dest, ret, eqv); + + /* Load the addend. */ + addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), + UNSPEC_TLS); + addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); + return gen_rtx_PLUS (Pmode, dest, addend); + + case TLS_MODEL_INITIAL_EXEC: + labelno = GEN_INT (pic_labelno++); + label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); + label = gen_rtx_CONST (VOIDmode, label); + sum = gen_rtx_UNSPEC (Pmode, + gen_rtvec (4, x, GEN_INT (TLS_IE32), label, + GEN_INT (TARGET_ARM ? 8 : 4)), + UNSPEC_TLS); + reg = load_tls_operand (sum, reg); + + if (TARGET_ARM) + emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); + else + { + emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); + emit_move_insn (reg, gen_const_mem (SImode, reg)); + } + + tp = arm_load_tp (NULL_RTX); + + return gen_rtx_PLUS (Pmode, tp, reg); + + case TLS_MODEL_LOCAL_EXEC: + tp = arm_load_tp (NULL_RTX); + + reg = gen_rtx_UNSPEC (Pmode, + gen_rtvec (2, x, GEN_INT (TLS_LE32)), + UNSPEC_TLS); + reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); + + return gen_rtx_PLUS (Pmode, tp, reg); + + default: + abort (); + } +} + /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. */ rtx arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) { + if (arm_tls_symbol_p (x)) + return legitimize_tls_address (x, NULL_RTX); + if (GET_CODE (x) == PLUS) { rtx xop0 = XEXP (x, 0); @@ -3056,7 +4013,10 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) rtx base_reg, val; n = INTVAL (xop1); - if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) + /* VFP addressing modes actually allow greater offsets, but for + now we just stick with the lowest common denominator. */ + if (mode == DImode + || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) { low_n = n & 0x0f; n &= ~0x0f; @@ -3074,11 +4034,9 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) } base_reg = gen_reg_rtx (SImode); - val = force_operand (gen_rtx_PLUS (SImode, xop0, - GEN_INT (n)), NULL_RTX); + val = force_operand (plus_constant (xop0, n), NULL_RTX); emit_move_insn (base_reg, val); - x = (low_n == 0 ? base_reg - : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); + x = plus_constant (base_reg, low_n); } else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) x = gen_rtx_PLUS (SImode, xop0, xop1); @@ -3101,6 +4059,34 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) x = gen_rtx_MINUS (SImode, xop0, xop1); } + /* Make sure to take full advantage of the pre-indexed addressing mode + with absolute addresses which often allows for the base register to + be factorized for multiple adjacent memory references, and it might + even allows for the mini pool to be avoided entirely. */ + else if (GET_CODE (x) == CONST_INT && optimize > 0) + { + unsigned int bits; + HOST_WIDE_INT mask, base, index; + rtx base_reg; + + /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only + use a 8 bit index. So let's use a 12 bit index for SImode only and + hope that arm_gen_constant will enable ldrb to use more bits. */ + bits = (mode == SImode) ? 12 : 8; + mask = (1 << bits) - 1; + base = INTVAL (x) & ~mask; + index = INTVAL (x) & mask; + if (bit_count (base & 0xffffffff) > (32 - bits)/2) + { + /* It'll most probably be more efficient to generate the base + with more bits set and use a negative index instead. */ + base |= mask; + index -= mask; + } + base_reg = force_reg (SImode, GEN_INT (base)); + x = plus_constant (base_reg, index); + } + if (flag_pic) { /* We need to find and carefully transform any SYMBOL and LABEL @@ -3114,8 +4100,164 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) return x; } - +/* Try machine-dependent ways of modifying an illegitimate Thumb address + to be legitimate. If we find one, return the new, valid address. */ +rtx +thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) +{ + if (arm_tls_symbol_p (x)) + return legitimize_tls_address (x, NULL_RTX); + + if (GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 1)) == CONST_INT + && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) + || INTVAL (XEXP (x, 1)) < 0)) + { + rtx xop0 = XEXP (x, 0); + rtx xop1 = XEXP (x, 1); + HOST_WIDE_INT offset = INTVAL (xop1); + + /* Try and fold the offset into a biasing of the base register and + then offsetting that. Don't do this when optimizing for space + since it can cause too many CSEs. */ + if (optimize_size && offset >= 0 + && offset < 256 + 31 * GET_MODE_SIZE (mode)) + { + HOST_WIDE_INT delta; + + if (offset >= 256) + delta = offset - (256 - GET_MODE_SIZE (mode)); + else if (offset < 32 * GET_MODE_SIZE (mode) + 8) + delta = 31 * GET_MODE_SIZE (mode); + else + delta = offset & (~31 * GET_MODE_SIZE (mode)); + + xop0 = force_operand (plus_constant (xop0, offset - delta), + NULL_RTX); + x = plus_constant (xop0, delta); + } + else if (offset < 0 && offset > -256) + /* Small negative offsets are best done with a subtract before the + dereference, forcing these into a register normally takes two + instructions. */ + x = force_operand (x, NULL_RTX); + else + { + /* For the remaining cases, force the constant into a register. */ + xop1 = force_reg (SImode, xop1); + x = gen_rtx_PLUS (SImode, xop0, xop1); + } + } + else if (GET_CODE (x) == PLUS + && s_register_operand (XEXP (x, 1), SImode) + && !s_register_operand (XEXP (x, 0), SImode)) + { + rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); + + x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); + } + + if (flag_pic) + { + /* We need to find and carefully transform any SYMBOL and LABEL + references; so go back to the original address expression. */ + rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); + + if (new_x != orig_x) + x = new_x; + } + + return x; +} + +rtx +thumb_legitimize_reload_address (rtx *x_p, + enum machine_mode mode, + int opnum, int type, + int ind_levels ATTRIBUTE_UNUSED) +{ + rtx x = *x_p; + + if (GET_CODE (x) == PLUS + && GET_MODE_SIZE (mode) < 4 + && REG_P (XEXP (x, 0)) + && XEXP (x, 0) == stack_pointer_rtx + && GET_CODE (XEXP (x, 1)) == CONST_INT + && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) + { + rtx orig_x = x; + + x = copy_rtx (x); + push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), + Pmode, VOIDmode, 0, 0, opnum, type); + return x; + } + + /* If both registers are hi-regs, then it's better to reload the + entire expression rather than each register individually. That + only requires one reload register rather than two. */ + if (GET_CODE (x) == PLUS + && REG_P (XEXP (x, 0)) + && REG_P (XEXP (x, 1)) + && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) + && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) + { + rtx orig_x = x; + + x = copy_rtx (x); + push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), + Pmode, VOIDmode, 0, 0, opnum, type); + return x; + } + + return NULL; +} + +/* Test for various thread-local symbols. */ + +/* Return TRUE if X is a thread-local symbol. */ + +static bool +arm_tls_symbol_p (rtx x) +{ + if (! TARGET_HAVE_TLS) + return false; + + if (GET_CODE (x) != SYMBOL_REF) + return false; + + return SYMBOL_REF_TLS_MODEL (x) != 0; +} + +/* Helper for arm_tls_referenced_p. */ + +static int +arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) +{ + if (GET_CODE (*x) == SYMBOL_REF) + return SYMBOL_REF_TLS_MODEL (*x) != 0; + + /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are + TLS offsets, not real symbol references. */ + if (GET_CODE (*x) == UNSPEC + && XINT (*x, 1) == UNSPEC_TLS) + return -1; + + return 0; +} + +/* Return TRUE if X contains any TLS symbol references. */ + +bool +arm_tls_referenced_p (rtx x) +{ + if (! TARGET_HAVE_TLS) + return false; + + return for_each_rtx (&x, arm_tls_operand_p_1, NULL); +} + #define REG_OR_SUBREG_REG(X) \ (GET_CODE (X) == REG \ || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) @@ -3126,129 +4268,132 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) #ifndef COSTS_N_INSNS #define COSTS_N_INSNS(N) ((N) * 4 - 2) #endif -/* Worker routine for arm_rtx_costs. */ static inline int -arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) +thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { enum machine_mode mode = GET_MODE (x); - enum rtx_code subcode; - int extra_cost; - if (TARGET_THUMB) + switch (code) { - switch (code) + case ASHIFT: + case ASHIFTRT: + case LSHIFTRT: + case ROTATERT: + case PLUS: + case MINUS: + case COMPARE: + case NEG: + case NOT: + return COSTS_N_INSNS (1); + + case MULT: + if (GET_CODE (XEXP (x, 1)) == CONST_INT) { - case ASHIFT: - case ASHIFTRT: - case LSHIFTRT: - case ROTATERT: - case PLUS: - case MINUS: - case COMPARE: - case NEG: - case NOT: - return COSTS_N_INSNS (1); - - case MULT: - if (GET_CODE (XEXP (x, 1)) == CONST_INT) - { - int cycles = 0; - unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); - - while (i) - { - i >>= 2; - cycles++; - } - return COSTS_N_INSNS (2) + cycles; + int cycles = 0; + unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); + + while (i) + { + i >>= 2; + cycles++; } - return COSTS_N_INSNS (1) + 16; - - case SET: - return (COSTS_N_INSNS (1) - + 4 * ((GET_CODE (SET_SRC (x)) == MEM) - + GET_CODE (SET_DEST (x)) == MEM)); - - case CONST_INT: - if (outer == SET) - { - if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) - return 0; - if (thumb_shiftable_const (INTVAL (x))) - return COSTS_N_INSNS (2); - return COSTS_N_INSNS (3); - } - else if ((outer == PLUS || outer == COMPARE) - && INTVAL (x) < 256 && INTVAL (x) > -256) + return COSTS_N_INSNS (2) + cycles; + } + return COSTS_N_INSNS (1) + 16; + + case SET: + return (COSTS_N_INSNS (1) + + 4 * ((GET_CODE (SET_SRC (x)) == MEM) + + GET_CODE (SET_DEST (x)) == MEM)); + + case CONST_INT: + if (outer == SET) + { + if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) return 0; - else if (outer == AND - && INTVAL (x) < 256 && INTVAL (x) >= -256) - return COSTS_N_INSNS (1); - else if (outer == ASHIFT || outer == ASHIFTRT - || outer == LSHIFTRT) - return 0; - return COSTS_N_INSNS (2); - - case CONST: - case CONST_DOUBLE: - case LABEL_REF: - case SYMBOL_REF: + if (thumb_shiftable_const (INTVAL (x))) + return COSTS_N_INSNS (2); return COSTS_N_INSNS (3); - - case UDIV: - case UMOD: - case DIV: - case MOD: - return 100; - - case TRUNCATE: - return 99; + } + else if ((outer == PLUS || outer == COMPARE) + && INTVAL (x) < 256 && INTVAL (x) > -256) + return 0; + else if (outer == AND + && INTVAL (x) < 256 && INTVAL (x) >= -256) + return COSTS_N_INSNS (1); + else if (outer == ASHIFT || outer == ASHIFTRT + || outer == LSHIFTRT) + return 0; + return COSTS_N_INSNS (2); - case AND: - case XOR: - case IOR: - /* XXX guess. */ - return 8; + case CONST: + case CONST_DOUBLE: + case LABEL_REF: + case SYMBOL_REF: + return COSTS_N_INSNS (3); - case ADDRESSOF: - case MEM: - /* XXX another guess. */ - /* Memory costs quite a lot for the first word, but subsequent words - load at the equivalent of a single insn each. */ - return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) - + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) - ? 4 : 0)); - - case IF_THEN_ELSE: - /* XXX a guess. */ - if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) - return 14; - return 2; + case UDIV: + case UMOD: + case DIV: + case MOD: + return 100; + + case TRUNCATE: + return 99; + + case AND: + case XOR: + case IOR: + /* XXX guess. */ + return 8; + + case MEM: + /* XXX another guess. */ + /* Memory costs quite a lot for the first word, but subsequent words + load at the equivalent of a single insn each. */ + return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) + + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + ? 4 : 0)); + + case IF_THEN_ELSE: + /* XXX a guess. */ + if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) + return 14; + return 2; + + case ZERO_EXTEND: + /* XXX still guessing. */ + switch (GET_MODE (XEXP (x, 0))) + { + case QImode: + return (1 + (mode == DImode ? 4 : 0) + + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + + case HImode: + return (4 + (mode == DImode ? 4 : 0) + + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + + case SImode: + return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); - case ZERO_EXTEND: - /* XXX still guessing. */ - switch (GET_MODE (XEXP (x, 0))) - { - case QImode: - return (1 + (mode == DImode ? 4 : 0) - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); - - case HImode: - return (4 + (mode == DImode ? 4 : 0) - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); - - case SImode: - return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); - - default: - return 99; - } - default: return 99; } + + default: + return 99; } - +} + + +/* Worker routine for arm_rtx_costs. */ +static inline int +arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) +{ + enum machine_mode mode = GET_MODE (x); + enum rtx_code subcode; + int extra_cost; + switch (code) { case MEM: @@ -3275,7 +4420,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) case ASHIFT: case LSHIFTRT: case ASHIFTRT: if (mode == DImode) return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) - + ((GET_CODE (XEXP (x, 0)) == REG + + ((GET_CODE (XEXP (x, 0)) == REG || (GET_CODE (XEXP (x, 0)) == SUBREG && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) ? 0 : 8)); @@ -3300,11 +4445,11 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) if (GET_MODE_CLASS (mode) == MODE_FLOAT) return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) + && arm_const_double_rtx (XEXP (x, 1)))) ? 0 : 8) + ((REG_OR_SUBREG_REG (XEXP (x, 0)) || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpa (XEXP (x, 0)))) + && arm_const_double_rtx (XEXP (x, 0)))) ? 0 : 8)); if (((GET_CODE (XEXP (x, 0)) == CONST_INT @@ -3324,16 +4469,24 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) return 1; /* Fall through */ - case PLUS: + case PLUS: + if (GET_CODE (XEXP (x, 0)) == MULT) + { + extra_cost = rtx_cost (XEXP (x, 0), code); + if (!REG_OR_SUBREG_REG (XEXP (x, 1))) + extra_cost += 4 * ARM_NUM_REGS (mode); + return extra_cost; + } + if (GET_MODE_CLASS (mode) == MODE_FLOAT) return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) + ((REG_OR_SUBREG_REG (XEXP (x, 1)) || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) + && arm_const_double_rtx (XEXP (x, 1)))) ? 0 : 8)); /* Fall through */ - case AND: case XOR: case IOR: + case AND: case XOR: case IOR: extra_cost = 0; /* Normally the frame registers will be spilt into reg+const during @@ -3379,65 +4532,11 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) return 8; case MULT: - /* There is no point basing this on the tuning, since it is always the - fast variant if it exists at all. */ - if (arm_fast_multiply && mode == DImode - && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) - && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND - || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) - return 8; - - if (GET_MODE_CLASS (mode) == MODE_FLOAT - || mode == DImode) - return 30; - - if (GET_CODE (XEXP (x, 1)) == CONST_INT) - { - unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) - & (unsigned HOST_WIDE_INT) 0xffffffff); - int cost, const_ok = const_ok_for_arm (i); - int j, booth_unit_size; - - if (arm_tune_xscale) - { - unsigned HOST_WIDE_INT masked_const; - - /* The cost will be related to two insns. - First a load of the constant (MOV or LDR), then a multiply. */ - cost = 2; - if (! const_ok) - cost += 1; /* LDR is probably more expensive because - of longer result latency. */ - masked_const = i & 0xffff8000; - if (masked_const != 0 && masked_const != 0xffff8000) - { - masked_const = i & 0xf8000000; - if (masked_const == 0 || masked_const == 0xf8000000) - cost += 1; - else - cost += 2; - } - return cost; - } - - /* Tune as appropriate. */ - cost = const_ok ? 4 : 8; - booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); - for (j = 0; i && j < 32; j += booth_unit_size) - { - i >>= booth_unit_size; - cost += 2; - } - - return cost; - } - - return (((tune_flags & FL_FAST_MULT) ? 8 : 30) - + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) - + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); + /* This should have been handled by the CPU specific routines. */ + gcc_unreachable (); case TRUNCATE: - if (arm_fast_multiply && mode == SImode + if (arm_arch3m && mode == SImode && GET_CODE (XEXP (x, 0)) == LSHIFTRT && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) @@ -3495,48 +4594,527 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) return 1; default: - break; + gcc_unreachable (); } - abort (); + gcc_unreachable (); - case CONST_INT: - if (const_ok_for_arm (INTVAL (x))) - return outer == SET ? 2 : -1; - else if (outer == AND - && const_ok_for_arm (~INTVAL (x))) - return -1; - else if ((outer == COMPARE - || outer == PLUS || outer == MINUS) - && const_ok_for_arm (-INTVAL (x))) - return -1; - else + case CONST_INT: + if (const_ok_for_arm (INTVAL (x))) + return outer == SET ? 2 : -1; + else if (outer == AND + && const_ok_for_arm (~INTVAL (x))) + return -1; + else if ((outer == COMPARE + || outer == PLUS || outer == MINUS) + && const_ok_for_arm (-INTVAL (x))) + return -1; + else return 5; - - case CONST: - case LABEL_REF: - case SYMBOL_REF: + + case CONST: + case LABEL_REF: + case SYMBOL_REF: return 6; - - case CONST_DOUBLE: - if (const_double_rtx_ok_for_fpa (x)) - return outer == SET ? 2 : -1; - else if ((outer == COMPARE || outer == PLUS) - && neg_const_double_rtx_ok_for_fpa (x)) - return -1; + + case CONST_DOUBLE: + if (arm_const_double_rtx (x)) + return outer == SET ? 2 : -1; + else if ((outer == COMPARE || outer == PLUS) + && neg_const_double_rtx_ok_for_fpa (x)) + return -1; return 7; - + default: return 99; } } +/* RTX costs when optimizing for size. */ static bool -arm_rtx_costs (rtx x, int code, int outer_code, int *total) +arm_size_rtx_costs (rtx x, int code, int outer_code, int *total) { - *total = arm_rtx_costs_1 (x, code, outer_code); - return true; + enum machine_mode mode = GET_MODE (x); + + if (TARGET_THUMB) + { + /* XXX TBD. For now, use the standard costs. */ + *total = thumb_rtx_costs (x, code, outer_code); + return true; + } + + switch (code) + { + case MEM: + /* A memory access costs 1 insn if the mode is small, or the address is + a single register, otherwise it costs one insn per word. */ + if (REG_P (XEXP (x, 0))) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return true; + + case DIV: + case MOD: + case UDIV: + case UMOD: + /* Needs a libcall, so it costs about this. */ + *total = COSTS_N_INSNS (2); + return false; + + case ROTATE: + if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) + { + *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code); + return true; + } + /* Fall through */ + case ROTATERT: + case ASHIFT: + case LSHIFTRT: + case ASHIFTRT: + if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) + { + *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code); + return true; + } + else if (mode == SImode) + { + *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code); + /* Slightly disparage register shifts, but not by much. */ + if (GET_CODE (XEXP (x, 1)) != CONST_INT) + *total += 1 + rtx_cost (XEXP (x, 1), code); + return true; + } + + /* Needs a libcall. */ + *total = COSTS_N_INSNS (2); + return false; + + case MINUS: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + { + *total = COSTS_N_INSNS (1); + return false; + } + + if (mode == SImode) + { + enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); + enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); + + if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT + || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT + || subcode1 == ROTATE || subcode1 == ROTATERT + || subcode1 == ASHIFT || subcode1 == LSHIFTRT + || subcode1 == ASHIFTRT) + { + /* It's just the cost of the two operands. */ + *total = 0; + return false; + } + + *total = COSTS_N_INSNS (1); + return false; + } + + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return false; + + case PLUS: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + { + *total = COSTS_N_INSNS (1); + return false; + } + + /* Fall through */ + case AND: case XOR: case IOR: + if (mode == SImode) + { + enum rtx_code subcode = GET_CODE (XEXP (x, 0)); + + if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT + || subcode == LSHIFTRT || subcode == ASHIFTRT + || (code == AND && subcode == NOT)) + { + /* It's just the cost of the two operands. */ + *total = 0; + return false; + } + } + + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return false; + + case MULT: + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + return false; + + case NEG: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + *total = COSTS_N_INSNS (1); + /* Fall through */ + case NOT: + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + + return false; + + case IF_THEN_ELSE: + *total = 0; + return false; + + case COMPARE: + if (cc_register (XEXP (x, 0), VOIDmode)) + * total = 0; + else + *total = COSTS_N_INSNS (1); + return false; + + case ABS: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); + return false; + + case SIGN_EXTEND: + *total = 0; + if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) + { + if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) + *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); + } + if (mode == DImode) + *total += COSTS_N_INSNS (1); + return false; + + case ZERO_EXTEND: + *total = 0; + if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) + { + switch (GET_MODE (XEXP (x, 0))) + { + case QImode: + *total += COSTS_N_INSNS (1); + break; + + case HImode: + *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); + + case SImode: + break; + + default: + *total += COSTS_N_INSNS (2); + } + } + + if (mode == DImode) + *total += COSTS_N_INSNS (1); + + return false; + + case CONST_INT: + if (const_ok_for_arm (INTVAL (x))) + *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0); + else if (const_ok_for_arm (~INTVAL (x))) + *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); + else if (const_ok_for_arm (-INTVAL (x))) + { + if (outer_code == COMPARE || outer_code == PLUS + || outer_code == MINUS) + *total = 0; + else + *total = COSTS_N_INSNS (1); + } + else + *total = COSTS_N_INSNS (2); + return true; + + case CONST: + case LABEL_REF: + case SYMBOL_REF: + *total = COSTS_N_INSNS (2); + return true; + + case CONST_DOUBLE: + *total = COSTS_N_INSNS (4); + return true; + + default: + if (mode != VOIDmode) + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + else + *total = COSTS_N_INSNS (4); /* How knows? */ + return false; + } +} + +/* RTX costs for cores with a slow MUL implementation. */ + +static bool +arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total) +{ + enum machine_mode mode = GET_MODE (x); + + if (TARGET_THUMB) + { + *total = thumb_rtx_costs (x, code, outer_code); + return true; + } + + switch (code) + { + case MULT: + if (GET_MODE_CLASS (mode) == MODE_FLOAT + || mode == DImode) + { + *total = 30; + return true; + } + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) + & (unsigned HOST_WIDE_INT) 0xffffffff); + int cost, const_ok = const_ok_for_arm (i); + int j, booth_unit_size; + + /* Tune as appropriate. */ + cost = const_ok ? 4 : 8; + booth_unit_size = 2; + for (j = 0; i && j < 32; j += booth_unit_size) + { + i >>= booth_unit_size; + cost += 2; + } + + *total = cost; + return true; + } + + *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) + + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); + return true; + + default: + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; + } } + +/* RTX cost for cores with a fast multiply unit (M variants). */ + +static bool +arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total) +{ + enum machine_mode mode = GET_MODE (x); + + if (TARGET_THUMB) + { + *total = thumb_rtx_costs (x, code, outer_code); + return true; + } + + switch (code) + { + case MULT: + /* There is no point basing this on the tuning, since it is always the + fast variant if it exists at all. */ + if (mode == DImode + && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) + && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) + { + *total = 8; + return true; + } + + + if (GET_MODE_CLASS (mode) == MODE_FLOAT + || mode == DImode) + { + *total = 30; + return true; + } + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) + & (unsigned HOST_WIDE_INT) 0xffffffff); + int cost, const_ok = const_ok_for_arm (i); + int j, booth_unit_size; + + /* Tune as appropriate. */ + cost = const_ok ? 4 : 8; + booth_unit_size = 8; + for (j = 0; i && j < 32; j += booth_unit_size) + { + i >>= booth_unit_size; + cost += 2; + } + + *total = cost; + return true; + } + + *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) + + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); + return true; + + default: + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; + } +} + + +/* RTX cost for XScale CPUs. */ + +static bool +arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total) +{ + enum machine_mode mode = GET_MODE (x); + + if (TARGET_THUMB) + { + *total = thumb_rtx_costs (x, code, outer_code); + return true; + } + + switch (code) + { + case MULT: + /* There is no point basing this on the tuning, since it is always the + fast variant if it exists at all. */ + if (mode == DImode + && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) + && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) + { + *total = 8; + return true; + } + + + if (GET_MODE_CLASS (mode) == MODE_FLOAT + || mode == DImode) + { + *total = 30; + return true; + } + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) + & (unsigned HOST_WIDE_INT) 0xffffffff); + int cost, const_ok = const_ok_for_arm (i); + unsigned HOST_WIDE_INT masked_const; + + /* The cost will be related to two insns. + First a load of the constant (MOV or LDR), then a multiply. */ + cost = 2; + if (! const_ok) + cost += 1; /* LDR is probably more expensive because + of longer result latency. */ + masked_const = i & 0xffff8000; + if (masked_const != 0 && masked_const != 0xffff8000) + { + masked_const = i & 0xf8000000; + if (masked_const == 0 || masked_const == 0xf8000000) + cost += 1; + else + cost += 2; + } + *total = cost; + return true; + } + + *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) + + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); + return true; + + case COMPARE: + /* A COMPARE of a MULT is slow on XScale; the muls instruction + will stall until the multiplication is complete. */ + if (GET_CODE (XEXP (x, 0)) == MULT) + *total = 4 + rtx_cost (XEXP (x, 0), code); + else + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; + + default: + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; + } +} + + +/* RTX costs for 9e (and later) cores. */ + +static bool +arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total) +{ + enum machine_mode mode = GET_MODE (x); + int nonreg_cost; + int cost; + + if (TARGET_THUMB) + { + switch (code) + { + case MULT: + *total = COSTS_N_INSNS (3); + return true; + + default: + *total = thumb_rtx_costs (x, code, outer_code); + return true; + } + } + + switch (code) + { + case MULT: + /* There is no point basing this on the tuning, since it is always the + fast variant if it exists at all. */ + if (mode == DImode + && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) + && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) + { + *total = 3; + return true; + } + + + if (GET_MODE_CLASS (mode) == MODE_FLOAT) + { + *total = 30; + return true; + } + if (mode == DImode) + { + cost = 7; + nonreg_cost = 8; + } + else + { + cost = 2; + nonreg_cost = 4; + } + + + *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost) + + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost); + return true; + + default: + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; + } +} /* All address computations that can be done are free, but rtx cost returns the same for practically all of them. So we weight the different types of address here in the order (most pref first): @@ -3553,13 +5131,10 @@ arm_arm_address_cost (rtx x) if (c == PLUS || c == MINUS) { - char cl0 = GET_RTX_CLASS (GET_CODE (XEXP (x, 0))); - char cl1 = GET_RTX_CLASS (GET_CODE (XEXP (x, 1))); - if (GET_CODE (XEXP (x, 0)) == CONST_INT) return 2; - if (cl0 == '2' || cl0 == 'c' || cl1 == '2' || cl1 == 'c') + if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) return 3; return 4; @@ -3590,12 +5165,6 @@ arm_address_cost (rtx x) } static int -arm_use_dfa_pipeline_interface (void) -{ - return true; -} - -static int arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) { rtx i_pat, d_pat; @@ -3614,11 +5183,12 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) operand for INSN. If we have a shifted input operand and the instruction we depend on is another ALU instruction, then we may have to account for an additional stall. */ - if (shift_opnum != 0 && attr_type == TYPE_NORMAL) + if (shift_opnum != 0 + && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) { rtx shifted_operand; int opno; - + /* Get the shifted operand. */ extract_insn (insn); shifted_operand = recog_data.operand[shift_opnum]; @@ -3659,9 +5229,9 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) rtx src_mem = XEXP (SET_SRC (i_pat), 0); /* This is a load after a store, there is no conflict if the load reads from a cached area. Assume that loads from the stack, and from the - constant pool are cached, and that others will miss. This is a + constant pool are cached, and that others will miss. This is a hack. */ - + if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) || reg_mentioned_p (stack_pointer_rtx, src_mem) || reg_mentioned_p (frame_pointer_rtx, src_mem) @@ -3672,47 +5242,51 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) return cost; } -static int fpa_consts_inited = 0; +static int fp_consts_inited = 0; -static const char * const strings_fpa[8] = +/* Only zero is valid for VFP. Other values are also valid for FPA. */ +static const char * const strings_fp[8] = { "0", "1", "2", "3", "4", "5", "0.5", "10" }; -static REAL_VALUE_TYPE values_fpa[8]; +static REAL_VALUE_TYPE values_fp[8]; static void -init_fpa_table (void) +init_fp_table (void) { int i; REAL_VALUE_TYPE r; - for (i = 0; i < 8; i++) + if (TARGET_VFP) + fp_consts_inited = 1; + else + fp_consts_inited = 8; + + for (i = 0; i < fp_consts_inited; i++) { - r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); - values_fpa[i] = r; + r = REAL_VALUE_ATOF (strings_fp[i], DFmode); + values_fp[i] = r; } - - fpa_consts_inited = 1; } -/* Return TRUE if rtx X is a valid immediate FPA constant. */ +/* Return TRUE if rtx X is a valid immediate FP constant. */ int -const_double_rtx_ok_for_fpa (rtx x) +arm_const_double_rtx (rtx x) { REAL_VALUE_TYPE r; int i; - - if (!fpa_consts_inited) - init_fpa_table (); - + + if (!fp_consts_inited) + init_fp_table (); + REAL_VALUE_FROM_CONST_DOUBLE (r, x); if (REAL_VALUE_MINUS_ZERO (r)) return 0; - for (i = 0; i < 8; i++) - if (REAL_VALUES_EQUAL (r, values_fpa[i])) + for (i = 0; i < fp_consts_inited; i++) + if (REAL_VALUES_EQUAL (r, values_fp[i])) return 1; return 0; @@ -3724,17 +5298,17 @@ neg_const_double_rtx_ok_for_fpa (rtx x) { REAL_VALUE_TYPE r; int i; - - if (!fpa_consts_inited) - init_fpa_table (); - + + if (!fp_consts_inited) + init_fp_table (); + REAL_VALUE_FROM_CONST_DOUBLE (r, x); r = REAL_VALUE_NEGATE (r); if (REAL_VALUE_MINUS_ZERO (r)) return 0; for (i = 0; i < 8; i++) - if (REAL_VALUES_EQUAL (r, values_fpa[i])) + if (REAL_VALUES_EQUAL (r, values_fp[i])) return 1; return 0; @@ -3742,244 +5316,6 @@ neg_const_double_rtx_ok_for_fpa (rtx x) /* Predicates for `match_operand' and `match_operator'. */ -/* s_register_operand is the same as register_operand, but it doesn't accept - (SUBREG (MEM)...). - - This function exists because at the time it was put in it led to better - code. SUBREG(MEM) always needs a reload in the places where - s_register_operand is used, and this seemed to lead to excessive - reloading. */ -int -s_register_operand (rtx op, enum machine_mode mode) -{ - if (GET_MODE (op) != mode && mode != VOIDmode) - return 0; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - /* We don't consider registers whose class is NO_REGS - to be a register operand. */ - /* XXX might have to check for lo regs only for thumb ??? */ - return (GET_CODE (op) == REG - && (REGNO (op) >= FIRST_PSEUDO_REGISTER - || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); -} - -/* A hard register operand (even before reload. */ -int -arm_hard_register_operand (rtx op, enum machine_mode mode) -{ - if (GET_MODE (op) != mode && mode != VOIDmode) - return 0; - - return (GET_CODE (op) == REG - && REGNO (op) < FIRST_PSEUDO_REGISTER); -} - -/* Only accept reg, subreg(reg), const_int. */ -int -reg_or_int_operand (rtx op, enum machine_mode mode) -{ - if (GET_CODE (op) == CONST_INT) - return 1; - - if (GET_MODE (op) != mode && mode != VOIDmode) - return 0; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - /* We don't consider registers whose class is NO_REGS - to be a register operand. */ - return (GET_CODE (op) == REG - && (REGNO (op) >= FIRST_PSEUDO_REGISTER - || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); -} - -/* Return 1 if OP is an item in memory, given that we are in reload. */ -int -arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - int regno = true_regnum (op); - - return (!CONSTANT_P (op) - && (regno == -1 - || (GET_CODE (op) == REG - && REGNO (op) >= FIRST_PSEUDO_REGISTER))); -} - -/* Return 1 if OP is a valid memory address, but not valid for a signed byte - memory access (architecture V4). - MODE is QImode if called when computing constraints, or VOIDmode when - emitting patterns. In this latter case we cannot use memory_operand() - because it will fail on badly formed MEMs, which is precisely what we are - trying to catch. */ -int -bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) != MEM) - return 0; - - op = XEXP (op, 0); - - /* A sum of anything more complex than reg + reg or reg + const is bad. */ - if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) - && (!s_register_operand (XEXP (op, 0), VOIDmode) - || (!s_register_operand (XEXP (op, 1), VOIDmode) - && GET_CODE (XEXP (op, 1)) != CONST_INT))) - return 1; - - /* Big constants are also bad. */ - if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT - && (INTVAL (XEXP (op, 1)) > 0xff - || -INTVAL (XEXP (op, 1)) > 0xff)) - return 1; - - /* Everything else is good, or can will automatically be made so. */ - return 0; -} - -/* Return TRUE for valid operands for the rhs of an ARM instruction. */ -int -arm_rhs_operand (rtx op, enum machine_mode mode) -{ - return (s_register_operand (op, mode) - || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); -} - -/* Return TRUE for valid operands for the - rhs of an ARM instruction, or a load. */ -int -arm_rhsm_operand (rtx op, enum machine_mode mode) -{ - return (s_register_operand (op, mode) - || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) - || memory_operand (op, mode)); -} - -/* Return TRUE for valid operands for the rhs of an ARM instruction, or if a - constant that is valid when negated. */ -int -arm_add_operand (rtx op, enum machine_mode mode) -{ - if (TARGET_THUMB) - return thumb_cmp_operand (op, mode); - - return (s_register_operand (op, mode) - || (GET_CODE (op) == CONST_INT - && (const_ok_for_arm (INTVAL (op)) - || const_ok_for_arm (-INTVAL (op))))); -} - -/* Return TRUE for valid ARM constants (or when valid if negated). */ -int -arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT - && (const_ok_for_arm (INTVAL (op)) - || const_ok_for_arm (-INTVAL (op)))); -} - -int -arm_not_operand (rtx op, enum machine_mode mode) -{ - return (s_register_operand (op, mode) - || (GET_CODE (op) == CONST_INT - && (const_ok_for_arm (INTVAL (op)) - || const_ok_for_arm (~INTVAL (op))))); -} - -/* Return TRUE if the operand is a memory reference which contains an - offsettable address. */ -int -offsettable_memory_operand (rtx op, enum machine_mode mode) -{ - if (mode == VOIDmode) - mode = GET_MODE (op); - - return (mode == GET_MODE (op) - && GET_CODE (op) == MEM - && offsettable_address_p (reload_completed | reload_in_progress, - mode, XEXP (op, 0))); -} - -/* Return TRUE if the operand is a memory reference which is, or can be - made word aligned by adjusting the offset. */ -int -alignable_memory_operand (rtx op, enum machine_mode mode) -{ - rtx reg; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (mode != GET_MODE (op) || GET_CODE (op) != MEM) - return 0; - - op = XEXP (op, 0); - - return ((GET_CODE (reg = op) == REG - || (GET_CODE (op) == SUBREG - && GET_CODE (reg = SUBREG_REG (op)) == REG) - || (GET_CODE (op) == PLUS - && GET_CODE (XEXP (op, 1)) == CONST_INT - && (GET_CODE (reg = XEXP (op, 0)) == REG - || (GET_CODE (XEXP (op, 0)) == SUBREG - && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) - && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); -} - -/* Similar to s_register_operand, but does not allow hard integer - registers. */ -int -f_register_operand (rtx op, enum machine_mode mode) -{ - if (GET_MODE (op) != mode && mode != VOIDmode) - return 0; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - /* We don't consider registers whose class is NO_REGS - to be a register operand. */ - return (GET_CODE (op) == REG - && (REGNO (op) >= FIRST_PSEUDO_REGISTER - || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); -} - -/* Return TRUE for valid operands for the rhs of an FPA instruction. */ -int -fpa_rhs_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (GET_MODE (op) != mode && mode != VOIDmode) - return FALSE; - - if (GET_CODE (op) == CONST_DOUBLE) - return const_double_rtx_ok_for_fpa (op); - - return FALSE; -} - -int -fpa_add_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (GET_MODE (op) != mode && mode != VOIDmode) - return FALSE; - - if (GET_CODE (op) == CONST_DOUBLE) - return (const_double_rtx_ok_for_fpa (op) - || neg_const_double_rtx_ok_for_fpa (op)); - - return FALSE; -} - /* Return nonzero if OP is a valid Cirrus memory address pattern. */ int cirrus_memory_offset (rtx op) @@ -4017,43 +5353,70 @@ cirrus_memory_offset (rtx op) return 0; } -/* Return nonzero if OP is a Cirrus or general register. */ +/* Return TRUE if OP is a valid coprocessor memory address pattern. + WB if true if writeback address modes are allowed. */ + int -cirrus_register_operand (rtx op, enum machine_mode mode) +arm_coproc_mem_operand (rtx op, bool wb) { - if (GET_MODE (op) != mode && mode != VOIDmode) - return FALSE; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); + rtx ind; - return (GET_CODE (op) == REG - && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS - || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); -} + /* Reject eliminable registers. */ + if (! (reload_in_progress || reload_completed) + && ( reg_mentioned_p (frame_pointer_rtx, op) + || reg_mentioned_p (arg_pointer_rtx, op) + || reg_mentioned_p (virtual_incoming_args_rtx, op) + || reg_mentioned_p (virtual_outgoing_args_rtx, op) + || reg_mentioned_p (virtual_stack_dynamic_rtx, op) + || reg_mentioned_p (virtual_stack_vars_rtx, op))) + return FALSE; -/* Return nonzero if OP is a cirrus FP register. */ -int -cirrus_fp_register (rtx op, enum machine_mode mode) -{ - if (GET_MODE (op) != mode && mode != VOIDmode) + /* Constants are converted into offsets from labels. */ + if (GET_CODE (op) != MEM) return FALSE; - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); + ind = XEXP (op, 0); - return (GET_CODE (op) == REG - && (REGNO (op) >= FIRST_PSEUDO_REGISTER - || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); -} + if (reload_completed + && (GET_CODE (ind) == LABEL_REF + || (GET_CODE (ind) == CONST + && GET_CODE (XEXP (ind, 0)) == PLUS + && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) + return TRUE; -/* Return nonzero if OP is a 6bit constant (0..63). */ -int -cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT - && INTVAL (op) >= 0 - && INTVAL (op) < 64); + /* Match: (mem (reg)). */ + if (GET_CODE (ind) == REG) + return arm_address_register_rtx_p (ind, 0); + + /* Autoincremment addressing modes. */ + if (wb + && (GET_CODE (ind) == PRE_INC + || GET_CODE (ind) == POST_INC + || GET_CODE (ind) == PRE_DEC + || GET_CODE (ind) == POST_DEC)) + return arm_address_register_rtx_p (XEXP (ind, 0), 0); + + if (wb + && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) + && arm_address_register_rtx_p (XEXP (ind, 0), 0) + && GET_CODE (XEXP (ind, 1)) == PLUS + && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) + ind = XEXP (ind, 1); + + /* Match: + (plus (reg) + (const)). */ + if (GET_CODE (ind) == PLUS + && GET_CODE (XEXP (ind, 0)) == REG + && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) + && GET_CODE (XEXP (ind, 1)) == CONST_INT + && INTVAL (XEXP (ind, 1)) > -1024 + && INTVAL (XEXP (ind, 1)) < 1024 + && (INTVAL (XEXP (ind, 1)) & 3) == 0) + return TRUE; + + return FALSE; } /* Return true if X is a register that will be eliminated later on. */ @@ -4066,6 +5429,30 @@ arm_eliminable_register (rtx x) && REGNO (x) <= LAST_VIRTUAL_REGISTER)); } +/* Return GENERAL_REGS if a scratch register required to reload x to/from + coprocessor registers. Otherwise return NO_REGS. */ + +enum reg_class +coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) +{ + if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) + return NO_REGS; + + return GENERAL_REGS; +} + +/* Values which must be returned in the most-significant end of the return + register. */ + +static bool +arm_return_in_msb (tree valtype) +{ + return (TARGET_AAPCS_BASED + && BYTES_BIG_ENDIAN + && (AGGREGATE_TYPE_P (valtype) + || TREE_CODE (valtype) == COMPLEX_TYPE)); +} + /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. Use by the Cirrus Maverick code which has to workaround a hardware bug triggered by such instructions. */ @@ -4107,7 +5494,7 @@ arm_cirrus_insn_p (rtx insn) { enum attr_cirrus attr; - /* get_attr aborts on USE and CLOBBER. */ + /* get_attr cannot accept USE or CLOBBER. */ if (!insn || GET_CODE (insn) != INSN || GET_CODE (PATTERN (insn)) == USE @@ -4179,10 +5566,11 @@ cirrus_reorg (rtx first) /* Get Arm register number for ldr insn. */ if (GET_CODE (lhs) == REG) arm_regno = REGNO (lhs); - else if (GET_CODE (rhs) == REG) - arm_regno = REGNO (rhs); else - abort (); + { + gcc_assert (GET_CODE (rhs) == REG); + arm_regno = REGNO (rhs); + } /* Next insn. */ first = next_nonnote_insn (first); @@ -4208,7 +5596,7 @@ cirrus_reorg (rtx first) } } - /* get_attr aborts on USE and CLOBBER. */ + /* get_attr cannot accept USE or CLOBBER. */ if (!first || GET_CODE (first) != INSN || GET_CODE (PATTERN (first)) == USE @@ -4238,262 +5626,6 @@ cirrus_reorg (rtx first) } } -/* Return nonzero if OP is a constant power of two. */ -int -power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) == CONST_INT) - { - HOST_WIDE_INT value = INTVAL (op); - - return value != 0 && (value & (value - 1)) == 0; - } - - return FALSE; -} - -/* Return TRUE for a valid operand of a DImode operation. - Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). - Note that this disallows MEM(REG+REG), but allows - MEM(PRE/POST_INC/DEC(REG)). */ -int -di_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) - return FALSE; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - switch (GET_CODE (op)) - { - case CONST_DOUBLE: - case CONST_INT: - return TRUE; - - case MEM: - return memory_address_p (DImode, XEXP (op, 0)); - - default: - return FALSE; - } -} - -/* Like di_operand, but don't accept constants. */ -int -nonimmediate_di_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) - return FALSE; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - if (GET_CODE (op) == MEM) - return memory_address_p (DImode, XEXP (op, 0)); - - return FALSE; -} - -/* Return TRUE for a valid operand of a DFmode operation when -msoft-float. - Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). - Note that this disallows MEM(REG+REG), but allows - MEM(PRE/POST_INC/DEC(REG)). */ -int -soft_df_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (mode != VOIDmode && GET_MODE (op) != mode) - return FALSE; - - if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) - return FALSE; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - switch (GET_CODE (op)) - { - case CONST_DOUBLE: - return TRUE; - - case MEM: - return memory_address_p (DFmode, XEXP (op, 0)); - - default: - return FALSE; - } -} - -/* Like soft_df_operand, but don't accept constants. */ -int -nonimmediate_soft_df_operand (rtx op, enum machine_mode mode) -{ - if (s_register_operand (op, mode)) - return TRUE; - - if (mode != VOIDmode && GET_MODE (op) != mode) - return FALSE; - - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - - if (GET_CODE (op) == MEM) - return memory_address_p (DFmode, XEXP (op, 0)); - return FALSE; -} - -/* Return TRUE for valid index operands. */ -int -index_operand (rtx op, enum machine_mode mode) -{ - return (s_register_operand (op, mode) - || (immediate_operand (op, mode) - && (GET_CODE (op) != CONST_INT - || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); -} - -/* Return TRUE for valid shifts by a constant. This also accepts any - power of two on the (somewhat overly relaxed) assumption that the - shift operator in this case was a mult. */ -int -const_shift_operand (rtx op, enum machine_mode mode) -{ - return (power_of_two_operand (op, mode) - || (immediate_operand (op, mode) - && (GET_CODE (op) != CONST_INT - || (INTVAL (op) < 32 && INTVAL (op) > 0)))); -} - -/* Return TRUE for arithmetic operators which can be combined with a multiply - (shift). */ -int -shiftable_operator (rtx x, enum machine_mode mode) -{ - enum rtx_code code; - - if (GET_MODE (x) != mode) - return FALSE; - - code = GET_CODE (x); - - return (code == PLUS || code == MINUS - || code == IOR || code == XOR || code == AND); -} - -/* Return TRUE for binary logical operators. */ -int -logical_binary_operator (rtx x, enum machine_mode mode) -{ - enum rtx_code code; - - if (GET_MODE (x) != mode) - return FALSE; - - code = GET_CODE (x); - - return (code == IOR || code == XOR || code == AND); -} - -/* Return TRUE for shift operators. */ -int -shift_operator (rtx x,enum machine_mode mode) -{ - enum rtx_code code; - - if (GET_MODE (x) != mode) - return FALSE; - - code = GET_CODE (x); - - if (code == MULT) - return power_of_two_operand (XEXP (x, 1), mode); - - return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT - || code == ROTATERT); -} - -/* Return TRUE if x is EQ or NE. */ -int -equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return GET_CODE (x) == EQ || GET_CODE (x) == NE; -} - -/* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ -int -arm_comparison_operator (rtx x, enum machine_mode mode) -{ - return (comparison_operator (x, mode) - && GET_CODE (x) != LTGT - && GET_CODE (x) != UNEQ); -} - -/* Return TRUE for SMIN SMAX UMIN UMAX operators. */ -int -minmax_operator (rtx x, enum machine_mode mode) -{ - enum rtx_code code = GET_CODE (x); - - if (GET_MODE (x) != mode) - return FALSE; - - return code == SMIN || code == SMAX || code == UMIN || code == UMAX; -} - -/* Return TRUE if this is the condition code register, if we aren't given - a mode, accept any class CCmode register. */ -int -cc_register (rtx x, enum machine_mode mode) -{ - if (mode == VOIDmode) - { - mode = GET_MODE (x); - - if (GET_MODE_CLASS (mode) != MODE_CC) - return FALSE; - } - - if ( GET_MODE (x) == mode - && GET_CODE (x) == REG - && REGNO (x) == CC_REGNUM) - return TRUE; - - return FALSE; -} - -/* Return TRUE if this is the condition code register, if we aren't given - a mode, accept any class CCmode register which indicates a dominance - expression. */ -int -dominant_cc_register (rtx x, enum machine_mode mode) -{ - if (mode == VOIDmode) - { - mode = GET_MODE (x); - - if (GET_MODE_CLASS (mode) != MODE_CC) - return FALSE; - } - - if (mode != CC_DNEmode && mode != CC_DEQmode - && mode != CC_DLEmode && mode != CC_DLTmode - && mode != CC_DGEmode && mode != CC_DGTmode - && mode != CC_DLEUmode && mode != CC_DLTUmode - && mode != CC_DGEUmode && mode != CC_DGTUmode) - return FALSE; - - return cc_register (x, mode); -} - /* Return TRUE if X references a SYMBOL_REF. */ int symbol_mentioned_p (rtx x) @@ -4504,8 +5636,13 @@ symbol_mentioned_p (rtx x) if (GET_CODE (x) == SYMBOL_REF) return 1; + /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they + are constant offsets, not symbols. */ + if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) + return 0; + fmt = GET_RTX_FORMAT (GET_CODE (x)); - + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) { if (fmt[i] == 'E') @@ -4533,6 +5670,11 @@ label_mentioned_p (rtx x) if (GET_CODE (x) == LABEL_REF) return 1; + /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing + instruction, but they are constant offsets, not symbols. */ + if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) + return 0; + fmt = GET_RTX_FORMAT (GET_CODE (x)); for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) { @@ -4551,27 +5693,76 @@ label_mentioned_p (rtx x) return 0; } +int +tls_mentioned_p (rtx x) +{ + switch (GET_CODE (x)) + { + case CONST: + return tls_mentioned_p (XEXP (x, 0)); + + case UNSPEC: + if (XINT (x, 1) == UNSPEC_TLS) + return 1; + + default: + return 0; + } +} + +/* Must not copy a SET whose source operand is PC-relative. */ + +static bool +arm_cannot_copy_insn_p (rtx insn) +{ + rtx pat = PATTERN (insn); + + if (GET_CODE (pat) == PARALLEL + && GET_CODE (XVECEXP (pat, 0, 0)) == SET) + { + rtx rhs = SET_SRC (XVECEXP (pat, 0, 0)); + + if (GET_CODE (rhs) == UNSPEC + && XINT (rhs, 1) == UNSPEC_PIC_BASE) + return TRUE; + + if (GET_CODE (rhs) == MEM + && GET_CODE (XEXP (rhs, 0)) == UNSPEC + && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) + return TRUE; + } + + return FALSE; +} + enum rtx_code minmax_code (rtx x) { enum rtx_code code = GET_CODE (x); - if (code == SMAX) - return GE; - else if (code == SMIN) - return LE; - else if (code == UMIN) - return LEU; - else if (code == UMAX) - return GEU; - - abort (); + switch (code) + { + case SMAX: + return GE; + case SMIN: + return LE; + case UMIN: + return LEU; + case UMAX: + return GEU; + default: + gcc_unreachable (); + } } /* Return 1 if memory locations are adjacent. */ int adjacent_mem_locations (rtx a, rtx b) { + /* We don't guarantee to preserve the order of these memory refs. */ + if (volatile_refs_p (a) || volatile_refs_p (b)) + return 0; + if ((GET_CODE (XEXP (a, 0)) == REG || (GET_CODE (XEXP (a, 0)) == PLUS && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) @@ -4611,6 +5802,17 @@ adjacent_mem_locations (rtx a, rtx b) return 0; val_diff = val1 - val0; + + if (arm_ld_sched) + { + /* If the target has load delay slots, then there's no benefit + to using an ldm instruction unless the offset is zero and + we are optimizing for size. */ + return (optimize_size && (REGNO (reg0) == REGNO (reg1)) + && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) + && (val_diff == 4 || val_diff == -4)); + } + return ((REGNO (reg0) == REGNO (reg1)) && (val_diff == 4 || val_diff == -4)); } @@ -4618,124 +5820,6 @@ adjacent_mem_locations (rtx a, rtx b) return 0; } -/* Return 1 if OP is a load multiple operation. It is known to be - parallel and the first section will be tested. */ -int -load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - HOST_WIDE_INT count = XVECLEN (op, 0); - int dest_regno; - rtx src_addr; - HOST_WIDE_INT i = 1, base = 0; - rtx elt; - - if (count <= 1 - || GET_CODE (XVECEXP (op, 0, 0)) != SET) - return 0; - - /* Check to see if this might be a write-back. */ - if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) - { - i++; - base = 1; - - /* Now check it more carefully. */ - if (GET_CODE (SET_DEST (elt)) != REG - || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG - || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT - || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) - return 0; - } - - /* Perform a quick check so we don't blow up below. */ - if (count <= i - || GET_CODE (XVECEXP (op, 0, i - 1)) != SET - || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG - || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) - return 0; - - dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); - src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); - - for (; i < count; i++) - { - elt = XVECEXP (op, 0, i); - - if (GET_CODE (elt) != SET - || GET_CODE (SET_DEST (elt)) != REG - || GET_MODE (SET_DEST (elt)) != SImode - || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) - || GET_CODE (SET_SRC (elt)) != MEM - || GET_MODE (SET_SRC (elt)) != SImode - || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS - || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) - || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT - || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) - return 0; - } - - return 1; -} - -/* Return 1 if OP is a store multiple operation. It is known to be - parallel and the first section will be tested. */ -int -store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - HOST_WIDE_INT count = XVECLEN (op, 0); - int src_regno; - rtx dest_addr; - HOST_WIDE_INT i = 1, base = 0; - rtx elt; - - if (count <= 1 - || GET_CODE (XVECEXP (op, 0, 0)) != SET) - return 0; - - /* Check to see if this might be a write-back. */ - if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) - { - i++; - base = 1; - - /* Now check it more carefully. */ - if (GET_CODE (SET_DEST (elt)) != REG - || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG - || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT - || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) - return 0; - } - - /* Perform a quick check so we don't blow up below. */ - if (count <= i - || GET_CODE (XVECEXP (op, 0, i - 1)) != SET - || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM - || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) - return 0; - - src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); - dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); - - for (; i < count; i++) - { - elt = XVECEXP (op, 0, i); - - if (GET_CODE (elt) != SET - || GET_CODE (SET_SRC (elt)) != REG - || GET_MODE (SET_SRC (elt)) != SImode - || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) - || GET_CODE (SET_DEST (elt)) != MEM - || GET_MODE (SET_DEST (elt)) != SImode - || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS - || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) - || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT - || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) - return 0; - } - - return 1; -} - int load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, HOST_WIDE_INT *load_offset) @@ -4748,11 +5832,10 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, /* Can only handle 2, 3, or 4 insns at present, though could be easily extended if required. */ - if (nops < 2 || nops > 4) - abort (); + gcc_assert (nops >= 2 && nops <= 4); /* Loop over the operands and check that the memory references are - suitable (ie immediate offsets from the same base register). At + suitable (i.e. immediate offsets from the same base register). At the same time, extract the target register, and the memory offsets. */ for (i = 0; i < nops; i++) @@ -4764,8 +5847,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, if (GET_CODE (operands[nops + i]) == SUBREG) operands[nops + i] = alter_subreg (operands + (nops + i)); - if (GET_CODE (operands[nops + i]) != MEM) - abort (); + gcc_assert (GET_CODE (operands[nops + i]) == MEM); /* Don't reorder volatile memory references; it doesn't seem worth looking for the case where the order is ok anyway. */ @@ -4793,7 +5875,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, : REGNO (SUBREG_REG (operands[i]))); order[0] = 0; } - else + else { if (base_reg != (int) REGNO (reg)) /* Not addressed from the same base register. */ @@ -4879,15 +5961,15 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, scratch register (one of the result regs) and then doing a load multiple actually becomes slower (and no smaller in code size). That is the transformation - + ldr rd1, [rbase + offset] ldr rd2, [rbase + offset + 4] - + to - + add rd1, rbase, offset ldmia rd1, {rd1, rd2} - + produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles + any stalls on rd2'. On ARMs with only one cache access per cycle, the first sequence could never complete in less @@ -4903,7 +5985,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, /* Can't do it without setting up the offset, only do this if it takes no more than one insn. */ - return (const_ok_for_arm (unsorted_offsets[order[0]]) + return (const_ok_for_arm (unsorted_offsets[order[0]]) || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; } @@ -4949,10 +6031,10 @@ emit_ldm_seq (rtx *operands, int nops) break; default: - abort (); + gcc_unreachable (); } - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, + sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); for (i = 1; i < nops; i++) @@ -4977,11 +6059,10 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, /* Can only handle 2, 3, or 4 insns at present, though could be easily extended if required. */ - if (nops < 2 || nops > 4) - abort (); + gcc_assert (nops >= 2 && nops <= 4); /* Loop over the operands and check that the memory references are - suitable (ie immediate offsets from the same base register). At + suitable (i.e. immediate offsets from the same base register). At the same time, extract the target register, and the memory offsets. */ for (i = 0; i < nops; i++) @@ -4993,8 +6074,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, if (GET_CODE (operands[nops + i]) == SUBREG) operands[nops + i] = alter_subreg (operands + (nops + i)); - if (GET_CODE (operands[nops + i]) != MEM) - abort (); + gcc_assert (GET_CODE (operands[nops + i]) == MEM); /* Don't reorder volatile memory references; it doesn't seem worth looking for the case where the order is ok anyway. */ @@ -5022,7 +6102,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, : REGNO (SUBREG_REG (operands[i]))); order[0] = 0; } - else + else { if (base_reg != (int) REGNO (reg)) /* Not addressed from the same base register. */ @@ -5126,10 +6206,10 @@ emit_stm_seq (rtx *operands, int nops) break; default: - abort (); + gcc_unreachable (); } - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, + sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); for (i = 1; i < nops; i++) @@ -5141,18 +6221,6 @@ emit_stm_seq (rtx *operands, int nops) output_asm_insn (buf, operands); return ""; } - -int -multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) != PARALLEL - || (GET_CODE (XVECEXP (op, 0, 0)) != SET) - || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) - || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) - return 0; - - return 1; -} /* Routines for use in generating RTL. */ @@ -5167,7 +6235,7 @@ arm_gen_load_multiple (int base_regno, int count, rtx from, int up, rtx mem, addr; /* XScale has load-store double instructions, but they have stricter - alignment requirements than load-store multiple, so we can not + alignment requirements than load-store multiple, so we cannot use them. For XScale ldm requires 2 + NREGS cycles to complete and blocks @@ -5197,9 +6265,9 @@ arm_gen_load_multiple (int base_regno, int count, rtx from, int up, if (arm_tune_xscale && count <= 2 && ! optimize_size) { rtx seq; - + start_sequence (); - + for (i = 0; i < count; i++) { addr = plus_constant (from, i * 4 * sign); @@ -5216,7 +6284,7 @@ arm_gen_load_multiple (int base_regno, int count, rtx from, int up, seq = get_insns (); end_sequence (); - + return seq; } @@ -5225,8 +6293,7 @@ arm_gen_load_multiple (int base_regno, int count, rtx from, int up, if (write_back) { XVECEXP (result, 0, 0) - = gen_rtx_SET (GET_MODE (from), from, - plus_constant (from, count * 4 * sign)); + = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); i = 1; count++; } @@ -5261,9 +6328,9 @@ arm_gen_store_multiple (int base_regno, int count, rtx to, int up, if (arm_tune_xscale && count <= 2 && ! optimize_size) { rtx seq; - + start_sequence (); - + for (i = 0; i < count; i++) { addr = plus_constant (to, i * 4 * sign); @@ -5280,7 +6347,7 @@ arm_gen_store_multiple (int base_regno, int count, rtx to, int up, seq = get_insns (); end_sequence (); - + return seq; } @@ -5289,7 +6356,7 @@ arm_gen_store_multiple (int base_regno, int count, rtx to, int up, if (write_back) { XVECEXP (result, 0, 0) - = gen_rtx_SET (GET_MODE (to), to, + = gen_rtx_SET (VOIDmode, to, plus_constant (to, count * 4 * sign)); i = 1; count++; @@ -5311,7 +6378,7 @@ arm_gen_store_multiple (int base_regno, int count, rtx to, int up, } int -arm_gen_movstrqi (rtx *operands) +arm_gen_movmemqi (rtx *operands) { HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; HOST_WIDE_INT srcoffset, dstoffset; @@ -5328,7 +6395,7 @@ arm_gen_movstrqi (rtx *operands) dstbase = operands[0]; srcbase = operands[1]; - + dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); @@ -5336,7 +6403,7 @@ arm_gen_movstrqi (rtx *operands) out_words_to_go = INTVAL (operands[2]) / 4; last_bytes = INTVAL (operands[2]) & 3; dstoffset = srcoffset = 0; - + if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); @@ -5346,7 +6413,7 @@ arm_gen_movstrqi (rtx *operands) emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, srcbase, &srcoffset)); else - emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, + emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, FALSE, srcbase, &srcoffset)); if (out_words_to_go) @@ -5354,10 +6421,9 @@ arm_gen_movstrqi (rtx *operands) if (out_words_to_go > 4) emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, dstbase, &dstoffset)); - else if (out_words_to_go != 1) emit_insn (arm_gen_store_multiple (0, out_words_to_go, - dst, TRUE, + dst, TRUE, (last_bytes == 0 ? FALSE : TRUE), dstbase, &dstoffset)); @@ -5388,22 +6454,19 @@ arm_gen_movstrqi (rtx *operands) mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); emit_move_insn (mem, sreg); in_words_to_go--; - - if (in_words_to_go) /* Sanity check */ - abort (); + + gcc_assert (!in_words_to_go); /* Sanity check */ } if (in_words_to_go) { - if (in_words_to_go < 0) - abort (); + gcc_assert (in_words_to_go > 0); mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); part_bytes_reg = copy_to_mode_reg (SImode, mem); } - if (last_bytes && part_bytes_reg == NULL) - abort (); + gcc_assert (!last_bytes || part_bytes_reg); if (BYTES_BIG_ENDIAN && last_bytes) { @@ -5413,7 +6476,7 @@ arm_gen_movstrqi (rtx *operands) emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8 * (4 - last_bytes)))); part_bytes_reg = tmp; - + while (last_bytes) { mem = adjust_automodify_address (dstbase, QImode, @@ -5428,7 +6491,7 @@ arm_gen_movstrqi (rtx *operands) part_bytes_reg = tmp; } } - + } else { @@ -5440,14 +6503,13 @@ arm_gen_movstrqi (rtx *operands) if (last_bytes) { rtx tmp = gen_reg_rtx (SImode); - - emit_insn (gen_addsi3 (dst, dst, GEN_INT (2))); + emit_insn (gen_addsi3 (dst, dst, const2_rtx)); emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); part_bytes_reg = tmp; dstoffset += 2; } } - + if (last_bytes) { mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); @@ -5458,42 +6520,13 @@ arm_gen_movstrqi (rtx *operands) return 1; } -/* Generate a memory reference for a half word, such that it will be loaded - into the top 16 bits of the word. We can assume that the address is - known to be alignable and of the form reg, or plus (reg, const). */ - -rtx -arm_gen_rotated_half_load (rtx memref) -{ - HOST_WIDE_INT offset = 0; - rtx base = XEXP (memref, 0); - - if (GET_CODE (base) == PLUS) - { - offset = INTVAL (XEXP (base, 1)); - base = XEXP (base, 0); - } - - /* If we aren't allowed to generate unaligned addresses, then fail. */ - if (TARGET_MMU_TRAPS - && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) - return NULL; - - base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); - - if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) - return base; - - return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); -} - /* Select a dominance comparison mode if possible for a test of the general form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. - COND_OR == DOM_CC_X_AND_Y => (X && Y) + COND_OR == DOM_CC_X_AND_Y => (X && Y) COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) - COND_OR == DOM_CC_X_OR_Y => (X || Y) + COND_OR == DOM_CC_X_OR_Y => (X || Y) In all cases OP will be either EQ or NE, but we don't need to know which - here. If we are unable to support a dominance comparison we return + here. If we are unable to support a dominance comparison we return CC mode. This will then fail to match for the RTL expressions that generate this call. */ enum machine_mode @@ -5519,7 +6552,7 @@ arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) /* If the comparisons are not equal, and one doesn't dominate the other, then we can't do this. */ - if (cond1 != cond2 + if (cond1 != cond2 && !comparison_dominates_p (cond1, cond2) && (swapped = 1, !comparison_dominates_p (cond2, cond1))) return CCmode; @@ -5534,78 +6567,108 @@ arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) switch (cond1) { case EQ: - if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y) + if (cond_or == DOM_CC_X_AND_Y) return CC_DEQmode; switch (cond2) { + case EQ: return CC_DEQmode; case LE: return CC_DLEmode; case LEU: return CC_DLEUmode; case GE: return CC_DGEmode; case GEU: return CC_DGEUmode; - default: break; + default: gcc_unreachable (); } - break; - case LT: - if (cond2 == LT || cond_or == DOM_CC_X_AND_Y) + if (cond_or == DOM_CC_X_AND_Y) return CC_DLTmode; - if (cond2 == LE) - return CC_DLEmode; - if (cond2 == NE) - return CC_DNEmode; - break; + + switch (cond2) + { + case LT: + return CC_DLTmode; + case LE: + return CC_DLEmode; + case NE: + return CC_DNEmode; + default: + gcc_unreachable (); + } case GT: - if (cond2 == GT || cond_or == DOM_CC_X_AND_Y) + if (cond_or == DOM_CC_X_AND_Y) return CC_DGTmode; - if (cond2 == GE) - return CC_DGEmode; - if (cond2 == NE) - return CC_DNEmode; - break; - + + switch (cond2) + { + case GT: + return CC_DGTmode; + case GE: + return CC_DGEmode; + case NE: + return CC_DNEmode; + default: + gcc_unreachable (); + } + case LTU: - if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y) + if (cond_or == DOM_CC_X_AND_Y) return CC_DLTUmode; - if (cond2 == LEU) - return CC_DLEUmode; - if (cond2 == NE) - return CC_DNEmode; - break; + + switch (cond2) + { + case LTU: + return CC_DLTUmode; + case LEU: + return CC_DLEUmode; + case NE: + return CC_DNEmode; + default: + gcc_unreachable (); + } case GTU: - if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y) + if (cond_or == DOM_CC_X_AND_Y) return CC_DGTUmode; - if (cond2 == GEU) - return CC_DGEUmode; - if (cond2 == NE) - return CC_DNEmode; - break; + + switch (cond2) + { + case GTU: + return CC_DGTUmode; + case GEU: + return CC_DGEUmode; + case NE: + return CC_DNEmode; + default: + gcc_unreachable (); + } /* The remaining cases only occur when both comparisons are the same. */ case NE: + gcc_assert (cond1 == cond2); return CC_DNEmode; case LE: + gcc_assert (cond1 == cond2); return CC_DLEmode; case GE: + gcc_assert (cond1 == cond2); return CC_DGEmode; case LEU: + gcc_assert (cond1 == cond2); return CC_DLEUmode; case GEU: + gcc_assert (cond1 == cond2); return CC_DGEUmode; default: - break; + gcc_unreachable (); } - - abort (); } enum machine_mode @@ -5633,15 +6696,15 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) case LE: case GT: case GE: - if (TARGET_CIRRUS) + if (TARGET_HARD_FLOAT && TARGET_MAVERICK) return CCFPmode; return CCFPEmode; default: - abort (); + gcc_unreachable (); } } - + /* A compare with a shifted operand. Because of canonicalization, the comparison will have to be swapped when we emit the assembler. */ if (GET_MODE (y) == SImode && GET_CODE (y) == REG @@ -5650,7 +6713,14 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) || GET_CODE (x) == ROTATERT)) return CC_SWPmode; - /* This is a special case that is used by combine to allow a + /* This operation is performed swapped, but since we only rely on the Z + flag we don't need an additional mode. */ + if (GET_MODE (y) == SImode && REG_P (y) + && GET_CODE (x) == NEG + && (op == EQ || op == NE)) + return CC_Zmode; + + /* This is a special case that is used by combine to allow a comparison of a shifted byte load to be split into a zero-extend followed by a comparison of the shifted integer (only valid for equalities and unsigned inequalities). */ @@ -5672,21 +6742,21 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) if (GET_CODE (x) == IF_THEN_ELSE && (XEXP (x, 2) == const0_rtx || XEXP (x, 2) == const1_rtx) - && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' - && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') - return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), + && COMPARISON_P (XEXP (x, 0)) + && COMPARISON_P (XEXP (x, 1))) + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), INTVAL (XEXP (x, 2))); /* Alternate canonicalizations of the above. These are somewhat cleaner. */ if (GET_CODE (x) == AND - && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' - && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') + && COMPARISON_P (XEXP (x, 0)) + && COMPARISON_P (XEXP (x, 1))) return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), DOM_CC_X_AND_Y); if (GET_CODE (x) == IOR - && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' - && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') + && COMPARISON_P (XEXP (x, 0)) + && COMPARISON_P (XEXP (x, 1))) return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), DOM_CC_X_OR_Y); @@ -5696,7 +6766,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) if (TARGET_THUMB && GET_MODE (x) == SImode && (op == EQ || op == NE) - && (GET_CODE (x) == ZERO_EXTRACT)) + && GET_CODE (x) == ZERO_EXTRACT + && XEXP (x, 1) == const1_rtx) return CC_Nmode; /* An operation that sets the condition codes as a side-effect, the @@ -5736,8 +6807,7 @@ arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) enum machine_mode mode = SELECT_CC_MODE (code, x, y); rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); - emit_insn (gen_rtx_SET (VOIDmode, cc_reg, - gen_rtx_COMPARE (mode, x, y))); + emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); return cc_reg; } @@ -5791,7 +6861,7 @@ arm_reload_in_hi (rtx *operands) { rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); - emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); + emit_set_insn (base_plus, base); base = base_plus; } else if (GET_CODE (base) == PLUS) @@ -5818,8 +6888,7 @@ arm_reload_in_hi (rtx *operands) ^ (HOST_WIDE_INT) 0x80000000) - (HOST_WIDE_INT) 0x80000000); - if (hi + lo != offset) - abort (); + gcc_assert (hi + lo == offset); if (hi != 0) { @@ -5846,24 +6915,23 @@ arm_reload_in_hi (rtx *operands) plus_constant (base, offset)))); emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), - gen_rtx_MEM (QImode, + gen_rtx_MEM (QImode, plus_constant (base, offset + 1)))); if (!BYTES_BIG_ENDIAN) - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), - gen_rtx_IOR (SImode, - gen_rtx_ASHIFT - (SImode, - gen_rtx_SUBREG (SImode, operands[0], 0), - GEN_INT (8)), - scratch))); + emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), + gen_rtx_IOR (SImode, + gen_rtx_ASHIFT + (SImode, + gen_rtx_SUBREG (SImode, operands[0], 0), + GEN_INT (8)), + scratch)); else - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), - gen_rtx_IOR (SImode, - gen_rtx_ASHIFT (SImode, scratch, - GEN_INT (8)), - gen_rtx_SUBREG (SImode, operands[0], - 0)))); + emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), + gen_rtx_IOR (SImode, + gen_rtx_ASHIFT (SImode, scratch, + GEN_INT (8)), + gen_rtx_SUBREG (SImode, operands[0], 0))); } /* Handle storing a half-word to memory during reload by synthesizing as two @@ -5938,7 +7006,7 @@ arm_reload_out_hi (rtx *operands) } } - emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); + emit_set_insn (base_plus, base); base = base_plus; } else if (GET_CODE (base) == PLUS) @@ -5965,8 +7033,7 @@ arm_reload_out_hi (rtx *operands) ^ (HOST_WIDE_INT) 0x80000000) - (HOST_WIDE_INT) 0x80000000); - if (hi + lo != offset) - abort (); + gcc_assert (hi + lo == offset); if (hi != 0) { @@ -6008,7 +7075,7 @@ arm_reload_out_hi (rtx *operands) if (BYTES_BIG_ENDIAN) { - emit_insn (gen_movqi (gen_rtx_MEM (QImode, + emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset + 1)), gen_lowpart (QImode, outval))); emit_insn (gen_lshrsi3 (scratch, @@ -6029,6 +7096,60 @@ arm_reload_out_hi (rtx *operands) gen_lowpart (QImode, scratch))); } } + +/* Return true if a type must be passed in memory. For AAPCS, small aggregates + (padded to the size of a word) should be passed in a register. */ + +static bool +arm_must_pass_in_stack (enum machine_mode mode, tree type) +{ + if (TARGET_AAPCS_BASED) + return must_pass_in_stack_var_size (mode, type); + else + return must_pass_in_stack_var_size_or_pad (mode, type); +} + + +/* For use by FUNCTION_ARG_PADDING (MODE, TYPE). + Return true if an argument passed on the stack should be padded upwards, + i.e. if the least-significant byte has useful data. + For legacy APCS ABIs we use the default. For AAPCS based ABIs small + aggregate types are placed in the lowest memory address. */ + +bool +arm_pad_arg_upward (enum machine_mode mode, tree type) +{ + if (!TARGET_AAPCS_BASED) + return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; + + if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) + return false; + + return true; +} + + +/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). + For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant + byte of the register has useful data, and return the opposite if the + most significant byte does. + For AAPCS, small aggregates and small complex types are always padded + upwards. */ + +bool +arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, + tree type, int first ATTRIBUTE_UNUSED) +{ + if (TARGET_AAPCS_BASED + && BYTES_BIG_ENDIAN + && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) + && int_size_in_bytes (type) <= 4) + return true; + + /* Otherwise, use default padding. */ + return !BYTES_BIG_ENDIAN; +} + /* Print a symbolic form of X to the debug file, F. */ static void @@ -6205,6 +7326,7 @@ struct minipool_fixup static Mnode * minipool_vector_head; static Mnode * minipool_vector_tail; static rtx minipool_vector_label; +static int minipool_pad; /* The linked list of all minipool fixes required for this function. */ Mfix * minipool_fix_head; @@ -6218,7 +7340,7 @@ static rtx is_jump_table (rtx insn) { rtx table; - + if (GET_CODE (insn) == JUMP_INSN && JUMP_LABEL (insn) != NULL && ((table = next_real_insn (JUMP_LABEL (insn))) @@ -6241,11 +7363,7 @@ get_jump_table_size (rtx insn) { /* ADDR_VECs only take room if read-only data does into the text section. */ - if (JUMP_TABLES_IN_TEXT_SECTION -#if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP) - || 1 -#endif - ) + if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) { rtx body = PATTERN (insn); int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; @@ -6263,10 +7381,8 @@ static Mnode * move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, HOST_WIDE_INT max_address) { - /* This should never be true and the code below assumes these are - different. */ - if (mp == max_mp) - abort (); + /* The code below assumes these are different. */ + gcc_assert (mp != max_mp); if (max_mp == NULL) { @@ -6292,7 +7408,7 @@ move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, mp->next = max_mp; mp->prev = max_mp->prev; max_mp->prev = mp; - + if (mp->prev != NULL) mp->prev->next = mp; else @@ -6322,16 +7438,16 @@ add_minipool_forward_ref (Mfix *fix) /* If set, max_mp is the first pool_entry that has a lower constraint than the one we are trying to add. */ Mnode * max_mp = NULL; - HOST_WIDE_INT max_address = fix->address + fix->forwards; + HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; Mnode * mp; - - /* If this fix's address is greater than the address of the first - entry, then we can't put the fix in this pool. We subtract the - size of the current fix to ensure that if the table is fully - packed we still have enough room to insert this value by suffling - the other fixes forwards. */ + + /* If the minipool starts before the end of FIX->INSN then this FIX + can not be placed into the current pool. Furthermore, adding the + new constant pool entry may cause the pool to start FIX_SIZE bytes + earlier. */ if (minipool_vector_head && - fix->address >= minipool_vector_head->max_address - fix->fix_size) + (fix->address + get_attr_length (fix->insn) + >= minipool_vector_head->max_address - fix->fix_size)) return NULL; /* Scan the pool to see if a constant with the same value has @@ -6361,7 +7477,7 @@ add_minipool_forward_ref (Mfix *fix) we have not already found an insertion point, then make sure that all such 8-byte aligned quantities are placed at the start of the pool. */ - if (TARGET_REALLY_IWMMXT + if (ARM_DOUBLEWORD_ALIGN && max_mp == NULL && fix->fix_size == 8 && mp->fix_size != 8) @@ -6377,7 +7493,7 @@ add_minipool_forward_ref (Mfix *fix) any existing entry. Otherwise, we insert the new fix before MAX_MP and, if necessary, adjust the constraints on the other entries. */ - mp = xmalloc (sizeof (* mp)); + mp = XNEW (Mnode); mp->fix_size = fix->fix_size; mp->mode = fix->mode; mp->value = fix->value; @@ -6438,10 +7554,8 @@ move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, { HOST_WIDE_INT offset; - /* This should never be true, and the code below assumes these are - different. */ - if (mp == min_mp) - abort (); + /* The code below assumes these are different. */ + gcc_assert (mp != min_mp); if (min_mp == NULL) { @@ -6485,10 +7599,10 @@ move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, } return min_mp; -} +} /* Add a constant to the minipool for a backward reference. Returns the - node added or NULL if the constant will not fit in this pool. + node added or NULL if the constant will not fit in this pool. Note that the code for insertion for a backwards reference can be somewhat confusing because the calculated offsets for each fix do @@ -6527,8 +7641,8 @@ add_minipool_backward_ref (Mfix *fix) && rtx_equal_p (fix->value, mp->value) /* Check that there is enough slack to move this entry to the end of the table (this is conservative). */ - && (mp->max_address - > (minipool_barrier->address + && (mp->max_address + > (minipool_barrier->address + minipool_vector_tail->offset + minipool_vector_tail->fix_size))) { @@ -6545,7 +7659,8 @@ add_minipool_backward_ref (Mfix *fix) { /* For now, we do not allow the insertion of 8-byte alignment requiring nodes anywhere but at the start of the pool. */ - if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8) + if (ARM_DOUBLEWORD_ALIGN + && fix->fix_size == 8 && mp->fix_size != 8) return NULL; else min_mp = mp; @@ -6564,7 +7679,7 @@ add_minipool_backward_ref (Mfix *fix) we have not already found an insertion point, then make sure that all such 8-byte aligned quantities are placed at the start of the pool. */ - else if (TARGET_REALLY_IWMMXT + else if (ARM_DOUBLEWORD_ALIGN && min_mp == NULL && fix->fix_size == 8 && mp->fix_size < 8) @@ -6576,7 +7691,7 @@ add_minipool_backward_ref (Mfix *fix) } /* We need to create a new entry. */ - mp = xmalloc (sizeof (* mp)); + mp = XNEW (Mnode); mp->fix_size = fix->fix_size; mp->mode = fix->mode; mp->value = fix->value; @@ -6605,7 +7720,7 @@ add_minipool_backward_ref (Mfix *fix) mp->next = min_mp->next; mp->prev = min_mp; min_mp->next = mp; - + if (mp->next != NULL) mp->next->prev = mp; else @@ -6648,7 +7763,7 @@ assign_minipool_offsets (Mfix *barrier) for (mp = minipool_vector_head; mp != NULL; mp = mp->next) { mp->offset = offset; - + if (mp->refcount > 0) offset += mp->fix_size; } @@ -6662,7 +7777,7 @@ dump_minipool (rtx scan) Mnode * nmp; int align64 = 0; - if (TARGET_REALLY_IWMMXT) + if (ARM_DOUBLEWORD_ALIGN) for (mp = minipool_vector_head; mp != NULL; mp = mp->next) if (mp->refcount > 0 && mp->fix_size == 8) { @@ -6670,8 +7785,8 @@ dump_minipool (rtx scan) break; } - if (rtl_dump_file) - fprintf (rtl_dump_file, + if (dump_file) + fprintf (dump_file, ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); @@ -6683,14 +7798,14 @@ dump_minipool (rtx scan) { if (mp->refcount > 0) { - if (rtl_dump_file) + if (dump_file) { - fprintf (rtl_dump_file, + fprintf (dump_file, ";; Offset %u, min %ld, max %ld ", (unsigned) mp->offset, (unsigned long) mp->min_address, (unsigned long) mp->max_address); - arm_print_value (rtl_dump_file, mp->value); - fputc ('\n', rtl_dump_file); + arm_print_value (dump_file, mp->value); + fputc ('\n', dump_file); } switch (mp->fix_size) @@ -6720,8 +7835,7 @@ dump_minipool (rtx scan) #endif default: - abort (); - break; + gcc_unreachable (); } } @@ -6752,7 +7866,7 @@ arm_barrier_cost (rtx insn) case CODE_LABEL: /* It will always be better to place the table before the label, rather than after it. */ - return 50; + return 50; case INSN: case CALL_INSN: @@ -6776,8 +7890,10 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) HOST_WIDE_INT count = 0; rtx barrier; rtx from = fix->insn; - rtx selected = from; + /* The instruction after which we will insert the jump. */ + rtx selected = NULL; int selected_cost; + /* The address at which the jump instruction will be placed. */ HOST_WIDE_INT selected_address; Mfix * new_fix; HOST_WIDE_INT max_count = max_address - fix->address; @@ -6793,8 +7909,7 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) /* This code shouldn't have been called if there was a natural barrier within range. */ - if (GET_CODE (from) == BARRIER) - abort (); + gcc_assert (GET_CODE (from) != BARRIER); /* Count the length of this insn. */ count += get_attr_length (from); @@ -6810,7 +7925,8 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) still put the pool after the table. */ new_cost = arm_barrier_cost (from); - if (count < max_count && new_cost <= selected_cost) + if (count < max_count + && (!selected || new_cost <= selected_cost)) { selected = tmp; selected_cost = new_cost; @@ -6823,8 +7939,9 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) } new_cost = arm_barrier_cost (from); - - if (count < max_count && new_cost <= selected_cost) + + if (count < max_count + && (!selected || new_cost <= selected_cost)) { selected = from; selected_cost = new_cost; @@ -6834,6 +7951,9 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) from = NEXT_INSN (from); } + /* Make sure that we found a place to insert the jump. */ + gcc_assert (selected); + /* Create a new JUMP_INSN that branches around a barrier. */ from = emit_jump_insn_after (gen_jump (label), selected); JUMP_LABEL (from) = label; @@ -6899,32 +8019,30 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, fix->minipool = NULL; /* If an insn doesn't have a range defined for it, then it isn't - expecting to be reworked by this code. Better to abort now than + expecting to be reworked by this code. Better to stop now than to generate duff assembly code. */ - if (fix->forwards == 0 && fix->backwards == 0) - abort (); + gcc_assert (fix->forwards || fix->backwards); - /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary. - So there might be an empty word before the start of the pool. - Hence we reduce the forward range by 4 to allow for this - possibility. */ - if (TARGET_REALLY_IWMMXT && fix->fix_size == 8) - fix->forwards -= 4; + /* If an entry requires 8-byte alignment then assume all constant pools + require 4 bytes of padding. Trying to do this later on a per-pool + basis is awkward because existing pool entries have to be modified. */ + if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8) + minipool_pad = 4; - if (rtl_dump_file) + if (dump_file) { - fprintf (rtl_dump_file, + fprintf (dump_file, ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", GET_MODE_NAME (mode), - INSN_UID (insn), (unsigned long) address, + INSN_UID (insn), (unsigned long) address, -1 * (long)fix->backwards, (long)fix->forwards); - arm_print_value (rtl_dump_file, fix->value); - fprintf (rtl_dump_file, "\n"); + arm_print_value (dump_file, fix->value); + fprintf (dump_file, "\n"); } /* Add it to the chain of fixes. */ fix->next = NULL; - + if (minipool_fix_head != NULL) minipool_fix_tail->next = fix; else @@ -6933,9 +8051,72 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, minipool_fix_tail = fix; } +/* Return the cost of synthesizing a 64-bit constant VAL inline. + Returns the number of insns needed, or 99 if we don't know how to + do it. */ +int +arm_const_double_inline_cost (rtx val) +{ + rtx lowpart, highpart; + enum machine_mode mode; + + mode = GET_MODE (val); + + if (mode == VOIDmode) + mode = DImode; + + gcc_assert (GET_MODE_SIZE (mode) == 8); + + lowpart = gen_lowpart (SImode, val); + highpart = gen_highpart_mode (SImode, mode, val); + + gcc_assert (GET_CODE (lowpart) == CONST_INT); + gcc_assert (GET_CODE (highpart) == CONST_INT); + + return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), + NULL_RTX, NULL_RTX, 0, 0) + + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), + NULL_RTX, NULL_RTX, 0, 0)); +} + +/* Return true if it is worthwhile to split a 64-bit constant into two + 32-bit operations. This is the case if optimizing for size, or + if we have load delay slots, or if one 32-bit part can be done with + a single data operation. */ +bool +arm_const_double_by_parts (rtx val) +{ + enum machine_mode mode = GET_MODE (val); + rtx part; + + if (optimize_size || arm_ld_sched) + return true; + + if (mode == VOIDmode) + mode = DImode; + + part = gen_highpart_mode (SImode, mode, val); + + gcc_assert (GET_CODE (part) == CONST_INT); + + if (const_ok_for_arm (INTVAL (part)) + || const_ok_for_arm (~INTVAL (part))) + return true; + + part = gen_lowpart (SImode, val); + + gcc_assert (GET_CODE (part) == CONST_INT); + + if (const_ok_for_arm (INTVAL (part)) + || const_ok_for_arm (~INTVAL (part))) + return true; + + return false; +} + /* Scan INSN and note any of its operands that need fixing. If DO_PUSHES is false we do not actually push any of the fixups - needed. The function returns TRUE is any fixups were needed/pushed. + needed. The function returns TRUE if any fixups were needed/pushed. This is used by arm_memory_load_p() which needs to know about loads of constants that will be converted into minipool loads. */ static bool @@ -6952,7 +8133,8 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) if (recog_data.n_alternatives == 0) return false; - /* Fill in recog_op_alt with information about the constraints of this insn. */ + /* Fill in recog_op_alt with information about the constraints of + this insn. */ preprocess_constraints (); for (opno = 0; opno < recog_data.n_operands; opno++) @@ -6987,7 +8169,7 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) /* Casting the address of something to a mode narrower than a word can cause avoid_constant_pool_reference() to return the pool reference itself. That's no good to - us here. Lets just hope that we can use the + us here. Lets just hope that we can use the constant pool value directly. */ if (op == cop) cop = get_pool_constant (XEXP (op, 0)); @@ -7021,8 +8203,8 @@ arm_reorg (void) /* The first insn must always be a note, or the code below won't scan it properly. */ insn = get_insns (); - if (GET_CODE (insn) != NOTE) - abort (); + gcc_assert (GET_CODE (insn) == NOTE); + minipool_pad = 0; /* Scan all the insns and record the operands that will need fixing. */ for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) @@ -7053,7 +8235,7 @@ arm_reorg (void) } fix = minipool_fix_head; - + /* Now scan the fixups and perform the required changes. */ while (fix) { @@ -7093,7 +8275,7 @@ arm_reorg (void) the next mini-pool. */ if (last_barrier != NULL) { - /* Reduce the refcount for those fixes that won't go into this + /* Reduce the refcount for those fixes that won't go into this pool after all. */ for (fdel = last_barrier->next; fdel && fdel != ftmp; @@ -7116,16 +8298,17 @@ arm_reorg (void) /* The last item on the list of fixes must be a barrier, so we can never run off the end of the list of fixes without last_barrier being set. */ - if (ftmp == NULL) - abort (); + gcc_assert (ftmp); max_address = minipool_vector_head->max_address; /* Check that there isn't another fix that is in range that we couldn't fit into this pool because the pool was already too large: we need to put the pool before such an - instruction. */ + instruction. The pool itself may come just after the + fix because create_fix_barrier also allows space for a + jump instruction. */ if (ftmp->address < max_address) - max_address = ftmp->address; + max_address = ftmp->address + 1; last_barrier = create_fix_barrier (last_added_fix, max_address); } @@ -7149,7 +8332,7 @@ arm_reorg (void) if (GET_CODE (this_fix->insn) != BARRIER) { rtx addr - = plus_constant (gen_rtx_LABEL_REF (VOIDmode, + = plus_constant (gen_rtx_LABEL_REF (VOIDmode, minipool_vector_label), this_fix->minipool->offset); *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); @@ -7178,16 +8361,16 @@ fp_immediate_constant (rtx x) { REAL_VALUE_TYPE r; int i; - - if (!fpa_consts_inited) - init_fpa_table (); - + + if (!fp_consts_inited) + init_fp_table (); + REAL_VALUE_FROM_CONST_DOUBLE (r, x); for (i = 0; i < 8; i++) - if (REAL_VALUES_EQUAL (r, values_fpa[i])) - return strings_fpa[i]; + if (REAL_VALUES_EQUAL (r, values_fp[i])) + return strings_fp[i]; - abort (); + gcc_unreachable (); } /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ @@ -7196,75 +8379,200 @@ fp_const_from_val (REAL_VALUE_TYPE *r) { int i; - if (!fpa_consts_inited) - init_fpa_table (); + if (!fp_consts_inited) + init_fp_table (); for (i = 0; i < 8; i++) - if (REAL_VALUES_EQUAL (*r, values_fpa[i])) - return strings_fpa[i]; + if (REAL_VALUES_EQUAL (*r, values_fp[i])) + return strings_fp[i]; - abort (); + gcc_unreachable (); } /* Output the operands of a LDM/STM instruction to STREAM. MASK is the ARM register set mask of which only bits 0-15 are important. REG is the base register, either the frame pointer or the stack pointer, INSTR is the possibly suffixed load or store instruction. */ + static void -print_multi_reg (FILE *stream, const char *instr, int reg, int mask) +print_multi_reg (FILE *stream, const char *instr, unsigned reg, + unsigned long mask) { - int i; - int not_first = FALSE; + unsigned i; + bool not_first = FALSE; fputc ('\t', stream); asm_fprintf (stream, instr, reg); fputs (", {", stream); - + for (i = 0; i <= LAST_ARM_REGNUM; i++) if (mask & (1 << i)) { if (not_first) fprintf (stream, ", "); - + asm_fprintf (stream, "%r", i); not_first = TRUE; } - fprintf (stream, "}"); - - /* Add a ^ character for the 26-bit ABI, but only if we were loading - the PC. Otherwise we would generate an UNPREDICTABLE instruction. - Strictly speaking the instruction would be unpredicatble only if - we were writing back the base register as well, but since we never - want to generate an LDM type 2 instruction (register bank switching) - which is what you get if the PC is not being loaded, we do not need - to check for writeback. */ - if (! TARGET_APCS_32 - && ((mask & (1 << PC_REGNUM)) != 0)) - fprintf (stream, "^"); - - fprintf (stream, "\n"); + fprintf (stream, "}\n"); } + +/* Output a FLDMX instruction to STREAM. + BASE if the register containing the address. + REG and COUNT specify the register range. + Extra registers may be added to avoid hardware bugs. */ + +static void +arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count) +{ + int i; + + /* Workaround ARM10 VFPr1 bug. */ + if (count == 2 && !arm_arch6) + { + if (reg == 15) + reg--; + count++; + } + + fputc ('\t', stream); + asm_fprintf (stream, "fldmfdx\t%r!, {", base); + + for (i = reg; i < reg + count; i++) + { + if (i > reg) + fputs (", ", stream); + asm_fprintf (stream, "d%d", i); + } + fputs ("}\n", stream); + +} + + +/* Output the assembly for a store multiple. */ + +const char * +vfp_output_fstmx (rtx * operands) +{ + char pattern[100]; + int p; + int base; + int i; + + strcpy (pattern, "fstmfdx\t%m0!, {%P1"); + p = strlen (pattern); + + gcc_assert (GET_CODE (operands[1]) == REG); + + base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; + for (i = 1; i < XVECLEN (operands[2], 0); i++) + { + p += sprintf (&pattern[p], ", d%d", base + i); + } + strcpy (&pattern[p], "}"); + + output_asm_insn (pattern, operands); + return ""; +} + + +/* Emit RTL to save block of VFP register pairs to the stack. Returns the + number of bytes pushed. */ + +static int +vfp_emit_fstmx (int base_reg, int count) +{ + rtx par; + rtx dwarf; + rtx tmp, reg; + int i; + + /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two + register pairs are stored by a store multiple insn. We avoid this + by pushing an extra pair. */ + if (count == 2 && !arm_arch6) + { + if (base_reg == LAST_VFP_REGNUM - 3) + base_reg -= 2; + count++; + } + + /* ??? The frame layout is implementation defined. We describe + standard format 1 (equivalent to a FSTMD insn and unused pad word). + We really need some way of representing the whole block so that the + unwinder can figure it out at runtime. */ + par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); + + reg = gen_rtx_REG (DFmode, base_reg); + base_reg += 2; + + XVECEXP (par, 0, 0) + = gen_rtx_SET (VOIDmode, + gen_frame_mem (BLKmode, + gen_rtx_PRE_DEC (BLKmode, + stack_pointer_rtx)), + gen_rtx_UNSPEC (BLKmode, + gen_rtvec (1, reg), + UNSPEC_PUSH_MULT)); + + tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, + plus_constant (stack_pointer_rtx, -(count * 8 + 4))); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, 0) = tmp; + + tmp = gen_rtx_SET (VOIDmode, + gen_frame_mem (DFmode, stack_pointer_rtx), + reg); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, 1) = tmp; + + for (i = 1; i < count; i++) + { + reg = gen_rtx_REG (DFmode, base_reg); + base_reg += 2; + XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); + + tmp = gen_rtx_SET (VOIDmode, + gen_frame_mem (DFmode, + plus_constant (stack_pointer_rtx, + i * 8)), + reg); + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, i + 1) = tmp; + } + + par = emit_insn (par); + REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, + REG_NOTES (par)); + RTX_FRAME_RELATED_P (par) = 1; + + return count * 8 + 4; +} + + /* Output a 'call' insn. */ const char * output_call (rtx *operands) { - /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ + gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ + /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ if (REGNO (operands[0]) == LR_REGNUM) { operands[0] = gen_rtx_REG (SImode, IP_REGNUM); output_asm_insn ("mov%?\t%0, %|lr", operands); } - + output_asm_insn ("mov%?\t%|lr, %|pc", operands); - - if (TARGET_INTERWORK) + + if (TARGET_INTERWORK || arm_arch4t) output_asm_insn ("bx%?\t%0", operands); else output_asm_insn ("mov%?\t%|pc, %0", operands); - + return ""; } @@ -7272,7 +8580,7 @@ output_call (rtx *operands) const char * output_call_mem (rtx *operands) { - if (TARGET_INTERWORK) + if (TARGET_INTERWORK && !arm_arch5) { output_asm_insn ("ldr%?\t%|ip, %0", operands); output_asm_insn ("mov%?\t%|lr, %|pc", operands); @@ -7284,8 +8592,16 @@ output_call_mem (rtx *operands) first instruction. It's safe to use IP as the target of the load since the call will kill it anyway. */ output_asm_insn ("ldr%?\t%|ip, %0", operands); - output_asm_insn ("mov%?\t%|lr, %|pc", operands); - output_asm_insn ("mov%?\t%|pc, %|ip", operands); + if (arm_arch5) + output_asm_insn ("blx%?\t%|ip", operands); + else + { + output_asm_insn ("mov%?\t%|lr, %|pc", operands); + if (arm_arch4t) + output_asm_insn ("bx%?\t%|ip", operands); + else + output_asm_insn ("mov%?\t%|pc, %|ip", operands); + } } else { @@ -7296,6 +8612,7 @@ output_call_mem (rtx *operands) return ""; } + /* Output a move from arm registers to an fpa registers. OPERANDS[0] is an fpa register. OPERANDS[1] is the first registers of an arm register pair. */ @@ -7305,16 +8622,15 @@ output_mov_long_double_fpa_from_arm (rtx *operands) int arm_reg0 = REGNO (operands[1]); rtx ops[3]; - if (arm_reg0 == IP_REGNUM) - abort (); + gcc_assert (arm_reg0 != IP_REGNUM); ops[0] = gen_rtx_REG (SImode, arm_reg0); ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); - + output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); - + return ""; } @@ -7327,8 +8643,7 @@ output_mov_long_double_arm_from_fpa (rtx *operands) int arm_reg0 = REGNO (operands[0]); rtx ops[3]; - if (arm_reg0 == IP_REGNUM) - abort (); + gcc_assert (arm_reg0 != IP_REGNUM); ops[0] = gen_rtx_REG (SImode, arm_reg0); ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); @@ -7383,9 +8698,8 @@ output_mov_double_fpa_from_arm (rtx *operands) int arm_reg0 = REGNO (operands[1]); rtx ops[2]; - if (arm_reg0 == IP_REGNUM) - abort (); - + gcc_assert (arm_reg0 != IP_REGNUM); + ops[0] = gen_rtx_REG (SImode, arm_reg0); ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); @@ -7402,8 +8716,7 @@ output_mov_double_arm_from_fpa (rtx *operands) int arm_reg0 = REGNO (operands[0]); rtx ops[2]; - if (arm_reg0 == IP_REGNUM) - abort (); + gcc_assert (arm_reg0 != IP_REGNUM); ops[0] = gen_rtx_REG (SImode, arm_reg0); ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); @@ -7427,267 +8740,177 @@ output_move_double (rtx *operands) int reg0 = REGNO (operands[0]); otherops[0] = gen_rtx_REG (SImode, 1 + reg0); - - if (code1 == REG) - { - int reg1 = REGNO (operands[1]); - if (reg1 == IP_REGNUM) - abort (); - /* Ensure the second source is not overwritten. */ - if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) - output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); - else - output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); - } - else if (code1 == CONST_VECTOR) - { - HOST_WIDE_INT hint = 0; + gcc_assert (code1 == MEM); /* Constraints should ensure this. */ - switch (GET_MODE (operands[1])) - { - case V2SImode: - otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1))); - operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0))); - break; - - case V4HImode: - if (BYTES_BIG_ENDIAN) - { - hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2)); - hint <<= 16; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); - } - else - { - hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3)); - hint <<= 16; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); - } + switch (GET_CODE (XEXP (operands[1], 0))) + { + case REG: + output_asm_insn ("ldm%?ia\t%m1, %M0", operands); + break; - otherops[1] = GEN_INT (hint); - hint = 0; + case PRE_INC: + gcc_assert (TARGET_LDRD); + output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands); + break; - if (BYTES_BIG_ENDIAN) - { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); - hint <<= 16; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); - } - else - { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); - hint <<= 16; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); - } + case PRE_DEC: + output_asm_insn ("ldm%?db\t%m1!, %M0", operands); + break; - operands[1] = GEN_INT (hint); - break; + case POST_INC: + output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); + break; - case V8QImode: - if (BYTES_BIG_ENDIAN) - { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); - } - else - { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); - } + case POST_DEC: + gcc_assert (TARGET_LDRD); + output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands); + break; - otherops[1] = GEN_INT (hint); - hint = 0; + case PRE_MODIFY: + case POST_MODIFY: + otherops[0] = operands[0]; + otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); + otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); - if (BYTES_BIG_ENDIAN) + if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) + { + if (reg_overlap_mentioned_p (otherops[0], otherops[2])) { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); + /* Registers overlap so split out the increment. */ + output_asm_insn ("add%?\t%1, %1, %2", otherops); + output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops); } else { - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); - hint <<= 8; - hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); + /* IWMMXT allows offsets larger than ldrd can handle, + fix these up with a pair of ldr. */ + if (GET_CODE (otherops[2]) == CONST_INT + && (INTVAL(otherops[2]) <= -256 + || INTVAL(otherops[2]) >= 256)) + { + output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); + otherops[0] = gen_rtx_REG (SImode, 1 + reg0); + output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); + } + else + output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops); } - - operands[1] = GEN_INT (hint); - break; - - default: - abort (); - } - output_mov_immediate (operands); - output_mov_immediate (otherops); - } - else if (code1 == CONST_DOUBLE) - { - if (GET_MODE (operands[1]) == DFmode) - { - REAL_VALUE_TYPE r; - long l[2]; - - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); - REAL_VALUE_TO_TARGET_DOUBLE (r, l); - otherops[1] = GEN_INT (l[1]); - operands[1] = GEN_INT (l[0]); - } - else if (GET_MODE (operands[1]) != VOIDmode) - abort (); - else if (WORDS_BIG_ENDIAN) - { - otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); - } - else - { - otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); - operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - } - - output_mov_immediate (operands); - output_mov_immediate (otherops); - } - else if (code1 == CONST_INT) - { -#if HOST_BITS_PER_WIDE_INT > 32 - /* If HOST_WIDE_INT is more than 32 bits, the intval tells us - what the upper word is. */ - if (WORDS_BIG_ENDIAN) - { - otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); - operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); } else { - otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); - operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); - } -#else - /* Sign extend the intval into the high-order word. */ - if (WORDS_BIG_ENDIAN) - { - otherops[1] = operands[1]; - operands[1] = (INTVAL (operands[1]) < 0 - ? constm1_rtx : const0_rtx); + /* IWMMXT allows offsets larger than ldrd can handle, + fix these up with a pair of ldr. */ + if (GET_CODE (otherops[2]) == CONST_INT + && (INTVAL(otherops[2]) <= -256 + || INTVAL(otherops[2]) >= 256)) + { + otherops[0] = gen_rtx_REG (SImode, 1 + reg0); + output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); + otherops[0] = operands[0]; + output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); + } + else + /* We only allow constant increments, so this is safe. */ + output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops); } - else - otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; -#endif - output_mov_immediate (otherops); - output_mov_immediate (operands); - } - else if (code1 == MEM) - { - switch (GET_CODE (XEXP (operands[1], 0))) - { - case REG: - output_asm_insn ("ldm%?ia\t%m1, %M0", operands); - break; - - case PRE_INC: - abort (); /* Should never happen now. */ - break; - - case PRE_DEC: - output_asm_insn ("ldm%?db\t%m1!, %M0", operands); - break; - - case POST_INC: - output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); - break; + break; - case POST_DEC: - abort (); /* Should never happen now. */ - break; + case LABEL_REF: + case CONST: + output_asm_insn ("adr%?\t%0, %1", operands); + output_asm_insn ("ldm%?ia\t%0, %M0", operands); + break; - case LABEL_REF: - case CONST: - output_asm_insn ("adr%?\t%0, %1", operands); - output_asm_insn ("ldm%?ia\t%0, %M0", operands); - break; + default: + if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), + GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) + { + otherops[0] = operands[0]; + otherops[1] = XEXP (XEXP (operands[1], 0), 0); + otherops[2] = XEXP (XEXP (operands[1], 0), 1); - default: - if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), - GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) + if (GET_CODE (XEXP (operands[1], 0)) == PLUS) { - otherops[0] = operands[0]; - otherops[1] = XEXP (XEXP (operands[1], 0), 0); - otherops[2] = XEXP (XEXP (operands[1], 0), 1); - - if (GET_CODE (XEXP (operands[1], 0)) == PLUS) + if (GET_CODE (otherops[2]) == CONST_INT) { - if (GET_CODE (otherops[2]) == CONST_INT) + switch ((int) INTVAL (otherops[2])) { - switch ((int) INTVAL (otherops[2])) - { - case -8: - output_asm_insn ("ldm%?db\t%1, %M0", otherops); - return ""; - case -4: - output_asm_insn ("ldm%?da\t%1, %M0", otherops); - return ""; - case 4: - output_asm_insn ("ldm%?ib\t%1, %M0", otherops); - return ""; - } - - if (!(const_ok_for_arm (INTVAL (otherops[2])))) - output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); - else - output_asm_insn ("add%?\t%0, %1, %2", otherops); + case -8: + output_asm_insn ("ldm%?db\t%1, %M0", otherops); + return ""; + case -4: + output_asm_insn ("ldm%?da\t%1, %M0", otherops); + return ""; + case 4: + output_asm_insn ("ldm%?ib\t%1, %M0", otherops); + return ""; } - else - output_asm_insn ("add%?\t%0, %1, %2", otherops); } - else - output_asm_insn ("sub%?\t%0, %1, %2", otherops); - - return "ldm%?ia\t%0, %M0"; - } - else - { - otherops[1] = adjust_address (operands[1], SImode, 4); - /* Take care of overlapping base/data reg. */ - if (reg_mentioned_p (operands[0], operands[1])) + if (TARGET_LDRD + && (GET_CODE (otherops[2]) == REG + || (GET_CODE (otherops[2]) == CONST_INT + && INTVAL (otherops[2]) > -256 + && INTVAL (otherops[2]) < 256))) { - output_asm_insn ("ldr%?\t%0, %1", otherops); - output_asm_insn ("ldr%?\t%0, %1", operands); + if (reg_overlap_mentioned_p (otherops[0], + otherops[2])) + { + /* Swap base and index registers over to + avoid a conflict. */ + otherops[1] = XEXP (XEXP (operands[1], 0), 1); + otherops[2] = XEXP (XEXP (operands[1], 0), 0); + } + /* If both registers conflict, it will usually + have been fixed by a splitter. */ + if (reg_overlap_mentioned_p (otherops[0], otherops[2])) + { + output_asm_insn ("add%?\t%1, %1, %2", otherops); + output_asm_insn ("ldr%?d\t%0, [%1]", + otherops); + } + else + output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops); + return ""; } - else + + if (GET_CODE (otherops[2]) == CONST_INT) { - output_asm_insn ("ldr%?\t%0, %1", operands); - output_asm_insn ("ldr%?\t%0, %1", otherops); + if (!(const_ok_for_arm (INTVAL (otherops[2])))) + output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); + else + output_asm_insn ("add%?\t%0, %1, %2", otherops); } + else + output_asm_insn ("add%?\t%0, %1, %2", otherops); + } + else + output_asm_insn ("sub%?\t%0, %1, %2", otherops); + + return "ldm%?ia\t%0, %M0"; + } + else + { + otherops[1] = adjust_address (operands[1], SImode, 4); + /* Take care of overlapping base/data reg. */ + if (reg_mentioned_p (operands[0], operands[1])) + { + output_asm_insn ("ldr%?\t%0, %1", otherops); + output_asm_insn ("ldr%?\t%0, %1", operands); + } + else + { + output_asm_insn ("ldr%?\t%0, %1", operands); + output_asm_insn ("ldr%?\t%0, %1", otherops); } } } - else - abort (); /* Constraints should prevent this. */ } - else if (code0 == MEM && code1 == REG) + else { - if (REGNO (operands[1]) == IP_REGNUM) - abort (); + /* Constraints should ensure this. */ + gcc_assert (code0 == MEM && code1 == REG); + gcc_assert (REGNO (operands[1]) != IP_REGNUM); switch (GET_CODE (XEXP (operands[0], 0))) { @@ -7696,7 +8919,8 @@ output_move_double (rtx *operands) break; case PRE_INC: - abort (); /* Should never happen now. */ + gcc_assert (TARGET_LDRD); + output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands); break; case PRE_DEC: @@ -7708,11 +8932,47 @@ output_move_double (rtx *operands) break; case POST_DEC: - abort (); /* Should never happen now. */ + gcc_assert (TARGET_LDRD); + output_asm_insn ("str%?d\t%1, [%m0], #-8", operands); + break; + + case PRE_MODIFY: + case POST_MODIFY: + otherops[0] = operands[1]; + otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); + otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); + + /* IWMMXT allows offsets larger than ldrd can handle, + fix these up with a pair of ldr. */ + if (GET_CODE (otherops[2]) == CONST_INT + && (INTVAL(otherops[2]) <= -256 + || INTVAL(otherops[2]) >= 256)) + { + rtx reg1; + reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); + if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) + { + output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); + otherops[0] = reg1; + output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); + } + else + { + otherops[0] = reg1; + output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); + otherops[0] = operands[1]; + output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); + } + } + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) + output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops); + else + output_asm_insn ("str%?d\t%0, [%1], %2", otherops); break; case PLUS: - if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) + otherops[2] = XEXP (XEXP (operands[0], 0), 1); + if (GET_CODE (otherops[2]) == CONST_INT) { switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) { @@ -7729,6 +8989,17 @@ output_move_double (rtx *operands) return ""; } } + if (TARGET_LDRD + && (GET_CODE (otherops[2]) == REG + || (GET_CODE (otherops[2]) == CONST_INT + && INTVAL (otherops[2]) > -256 + && INTVAL (otherops[2]) < 256))) + { + otherops[0] = operands[1]; + otherops[1] = XEXP (XEXP (operands[0], 0), 0); + output_asm_insn ("str%?d\t%0, [%1, %2]", otherops); + return ""; + } /* Fall through */ default: @@ -7738,46 +9009,6 @@ output_move_double (rtx *operands) output_asm_insn ("str%?\t%1, %0", otherops); } } - else - /* Constraints should prevent this. */ - abort (); - - return ""; -} - - -/* Output an arbitrary MOV reg, #n. - OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ -const char * -output_mov_immediate (rtx *operands) -{ - HOST_WIDE_INT n = INTVAL (operands[1]); - - /* Try to use one MOV. */ - if (const_ok_for_arm (n)) - output_asm_insn ("mov%?\t%0, %1", operands); - - /* Try to use one MVN. */ - else if (const_ok_for_arm (~n)) - { - operands[1] = GEN_INT (~n); - output_asm_insn ("mvn%?\t%0, %1", operands); - } - else - { - int n_ones = 0; - int i; - - /* If all else fails, make it out of ORRs or BICs as appropriate. */ - for (i = 0; i < 32; i++) - if (n & 1 << i) - n_ones++; - - if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ - output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); - else - output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); - } return ""; } @@ -7841,7 +9072,7 @@ output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, } } } - + return ""; } @@ -7870,7 +9101,7 @@ arithmetic_instr (rtx op, int shift_first_arg) return "and"; default: - abort (); + gcc_unreachable (); } } @@ -7885,12 +9116,20 @@ shift_op (rtx op, HOST_WIDE_INT *amountp) const char * mnem; enum rtx_code code = GET_CODE (op); - if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) - *amountp = -1; - else if (GET_CODE (XEXP (op, 1)) == CONST_INT) - *amountp = INTVAL (XEXP (op, 1)); - else - abort (); + switch (GET_CODE (XEXP (op, 1))) + { + case REG: + case SUBREG: + *amountp = -1; + break; + + case CONST_INT: + *amountp = INTVAL (XEXP (op, 1)); + break; + + default: + gcc_unreachable (); + } switch (code) { @@ -7906,6 +9145,12 @@ shift_op (rtx op, HOST_WIDE_INT *amountp) mnem = "lsr"; break; + case ROTATE: + gcc_assert (*amountp != -1); + *amountp = 32 - *amountp; + + /* Fall through. */ + case ROTATERT: mnem = "ror"; break; @@ -7913,14 +9158,12 @@ shift_op (rtx op, HOST_WIDE_INT *amountp) case MULT: /* We never have to worry about the amount being other than a power of 2, since this case can never be reloaded from a reg. */ - if (*amountp != -1) - *amountp = int_log2 (*amountp); - else - abort (); + gcc_assert (*amountp != -1); + *amountp = int_log2 (*amountp); return "asl"; default: - abort (); + gcc_unreachable (); } if (*amountp != -1) @@ -7930,7 +9173,7 @@ shift_op (rtx op, HOST_WIDE_INT *amountp) shift. >=32 is not a valid shift for "asl", so we must try and output a shift that produces the correct arithmetical result. Using lsr #32 is identical except for the fact that the carry bit - is not set correctly if we set the flags; but we never use the + is not set correctly if we set the flags; but we never use the carry bit from such an operation, so we can ignore that. */ if (code == ROTATERT) /* Rotate is just modulo 32. */ @@ -7945,7 +9188,7 @@ shift_op (rtx op, HOST_WIDE_INT *amountp) /* Shifts of 0 are no-ops. */ if (*amountp == 0) return NULL; - } + } return mnem; } @@ -7959,16 +9202,21 @@ int_log2 (HOST_WIDE_INT power) while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) { - if (shift > 31) - abort (); + gcc_assert (shift <= 31); shift++; } return shift; } -/* Output a .ascii pseudo-op, keeping track of lengths. This is because - /bin/as is horribly restrictive. */ +/* Output a .ascii pseudo-op, keeping track of lengths. This is + because /bin/as is horribly restrictive. The judgement about + whether or not each character is 'printable' (and can be output as + is) or not (and must be printed with an octal escape) must be made + with reference to the *host* character set -- the situation is + similar to that discussed in the comments above pp_c_char in + c-pretty-print.c. */ + #define MAX_ASCII_LEN 51 void @@ -7978,7 +9226,7 @@ output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) int len_so_far = 0; fputs ("\t.ascii\t\"", stream); - + for (i = 0; i < len; i++) { int c = p[i]; @@ -7989,71 +9237,34 @@ output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) len_so_far = 0; } - switch (c) + if (ISPRINT (c)) { - case TARGET_TAB: - fputs ("\\t", stream); - len_so_far += 2; - break; - - case TARGET_FF: - fputs ("\\f", stream); - len_so_far += 2; - break; - - case TARGET_BS: - fputs ("\\b", stream); - len_so_far += 2; - break; - - case TARGET_CR: - fputs ("\\r", stream); - len_so_far += 2; - break; - - case TARGET_NEWLINE: - fputs ("\\n", stream); - c = p [i + 1]; - if ((c >= ' ' && c <= '~') - || c == TARGET_TAB) - /* This is a good place for a line break. */ - len_so_far = MAX_ASCII_LEN; - else - len_so_far += 2; - break; - - case '\"': - case '\\': - putc ('\\', stream); - len_so_far++; - /* Drop through. */ - - default: - if (c >= ' ' && c <= '~') + if (c == '\\' || c == '\"') { - putc (c, stream); + putc ('\\', stream); len_so_far++; } - else - { - fprintf (stream, "\\%03o", c); - len_so_far += 4; - } - break; + putc (c, stream); + len_so_far++; + } + else + { + fprintf (stream, "\\%03o", c); + len_so_far += 4; } } fputs ("\"\n", stream); } -/* Compute the register sabe mask for registers 0 through 12 - inclusive. This code is used by both arm_compute_save_reg_mask - and arm_compute_initial_elimination_offset. */ +/* Compute the register save mask for registers 0 through 12 + inclusive. This code is used by arm_compute_save_reg_mask. */ + static unsigned long arm_compute_save_reg0_reg12_mask (void) { unsigned long func_type = arm_current_func_type (); - unsigned int save_reg_mask = 0; + unsigned long save_reg_mask = 0; unsigned int reg; if (IS_INTERRUPT (func_type)) @@ -8074,11 +9285,18 @@ arm_compute_save_reg0_reg12_mask (void) max_reg = 7; else max_reg = 12; - + for (reg = 0; reg <= max_reg; reg++) if (regs_ever_live[reg] || (! current_function_is_leaf && call_used_regs [reg])) save_reg_mask |= (1 << reg); + + /* Also save the pic base register if necessary. */ + if (flag_pic + && !TARGET_SINGLE_PIC_BASE + && arm_pic_register != INVALID_REGNUM + && current_function_uses_pic_offset_table) + save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; } else { @@ -8098,11 +9316,27 @@ arm_compute_save_reg0_reg12_mask (void) /* If we aren't loading the PIC register, don't stack it even though it may be live. */ if (flag_pic - && ! TARGET_SINGLE_PIC_BASE - && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) + && !TARGET_SINGLE_PIC_BASE + && arm_pic_register != INVALID_REGNUM + && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] + || current_function_uses_pic_offset_table)) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; } + /* Save registers so the exception handler can modify them. */ + if (current_function_calls_eh_return) + { + unsigned int i; + + for (i = 0; ; i++) + { + reg = EH_RETURN_DATA_REGNO (i); + if (reg == INVALID_REGNUM) + break; + save_reg_mask |= 1 << reg; + } + } + return save_reg_mask; } @@ -8147,7 +9381,8 @@ arm_compute_save_reg_mask (void) if (regs_ever_live [LR_REGNUM] || (save_reg_mask && optimize_size - && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)) + && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL + && !current_function_calls_eh_return)) save_reg_mask |= 1 << LR_REGNUM; if (cfun->machine->lr_save_eliminated) @@ -8184,6 +9419,97 @@ arm_compute_save_reg_mask (void) return save_reg_mask; } + +/* Compute a bit mask of which registers need to be + saved on the stack for the current function. */ +static unsigned long +thumb_compute_save_reg_mask (void) +{ + unsigned long mask; + unsigned reg; + + mask = 0; + for (reg = 0; reg < 12; reg ++) + if (regs_ever_live[reg] && !call_used_regs[reg]) + mask |= 1 << reg; + + if (flag_pic + && !TARGET_SINGLE_PIC_BASE + && arm_pic_register != INVALID_REGNUM + && current_function_uses_pic_offset_table) + mask |= 1 << PIC_OFFSET_TABLE_REGNUM; + + /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ + if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) + mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; + + /* LR will also be pushed if any lo regs are pushed. */ + if (mask & 0xff || thumb_force_lr_save ()) + mask |= (1 << LR_REGNUM); + + /* Make sure we have a low work register if we need one. + We will need one if we are going to push a high register, + but we are not currently intending to push a low register. */ + if ((mask & 0xff) == 0 + && ((mask & 0x0f00) || TARGET_BACKTRACE)) + { + /* Use thumb_find_work_register to choose which register + we will use. If the register is live then we will + have to push it. Use LAST_LO_REGNUM as our fallback + choice for the register to select. */ + reg = thumb_find_work_register (1 << LAST_LO_REGNUM); + + if (! call_used_regs[reg]) + mask |= 1 << reg; + } + + return mask; +} + + +/* Return the number of bytes required to save VFP registers. */ +static int +arm_get_vfp_saved_size (void) +{ + unsigned int regno; + int count; + int saved; + + saved = 0; + /* Space for saved VFP registers. */ + if (TARGET_HARD_FLOAT && TARGET_VFP) + { + count = 0; + for (regno = FIRST_VFP_REGNUM; + regno < LAST_VFP_REGNUM; + regno += 2) + { + if ((!regs_ever_live[regno] || call_used_regs[regno]) + && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1])) + { + if (count > 0) + { + /* Workaround ARM10 VFPr1 bug. */ + if (count == 2 && !arm_arch6) + count++; + saved += count * 8 + 4; + } + count = 0; + } + else + count++; + } + if (count > 0) + { + if (count == 2 && !arm_arch6) + count++; + saved += count * 8 + 4; + } + } + return saved; +} + + /* Generate a function exit sequence. If REALLY_RETURN is false, then do everything bar the final return instruction. */ const char * @@ -8191,9 +9517,10 @@ output_return_instruction (rtx operand, int really_return, int reverse) { char conditional[10]; char instr[100]; - int reg; + unsigned reg; unsigned long live_regs_mask; unsigned long func_type; + arm_stack_offsets *offsets; func_type = arm_current_func_type (); @@ -8208,20 +9535,19 @@ output_return_instruction (rtx operand, int really_return, int reverse) if (really_return) { rtx ops[2]; - + /* Otherwise, trap an attempted return by aborting. */ ops[0] = operand; - ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" + ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); assemble_external_libcall (ops[1]); output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); } - + return ""; } - if (current_function_calls_alloca && !really_return) - abort (); + gcc_assert (!current_function_calls_alloca || really_return); sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); @@ -8233,8 +9559,8 @@ output_return_instruction (rtx operand, int really_return, int reverse) { const char * return_reg; - /* If we do not have any special requirements for function exit - (eg interworking, or ISR) then we can load the return address + /* If we do not have any special requirements for function exit + (e.g. interworking, or ISR) then we can load the return address directly into the PC. Otherwise we must load it into LR. */ if (really_return && ! TARGET_INTERWORK) @@ -8256,11 +9582,7 @@ output_return_instruction (rtx operand, int really_return, int reverse) live_regs_mask |= (1 << SP_REGNUM); } else - { - if (! IS_INTERRUPT (func_type) - && ! TARGET_REALLY_IWMMXT) - abort (); - } + gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); } /* On some ARM architectures it is faster to use LDR rather than @@ -8269,16 +9591,15 @@ output_return_instruction (rtx operand, int really_return, int reverse) we have to use LDM to load the PC so that the CPSR is also restored. */ for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) - { - if (live_regs_mask == (unsigned int)(1 << reg)) - break; - } + if (live_regs_mask == (1U << reg)) + break; + if (reg <= LAST_ARM_REGNUM && (reg != LR_REGNUM - || ! really_return - || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type)))) + || ! really_return + || ! IS_INTERRUPT (func_type))) { - sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, + sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, (reg == LR_REGNUM) ? return_reg : reg_names[reg]); } else @@ -8292,18 +9613,18 @@ output_return_instruction (rtx operand, int really_return, int reverse) points to the base of the saved core registers. */ if (live_regs_mask & (1 << SP_REGNUM)) { - unsigned HOST_WIDE_INT stack_adjust = - arm_get_frame_size () + current_function_outgoing_args_size; - - if (stack_adjust != 0 && stack_adjust != 4) - abort (); + unsigned HOST_WIDE_INT stack_adjust; + + offsets = arm_get_frame_offsets (); + stack_adjust = offsets->outgoing_args - offsets->saved_regs; + gcc_assert (stack_adjust == 0 || stack_adjust == 4); if (stack_adjust && arm_arch5) sprintf (instr, "ldm%sib\t%%|sp, {", conditional); else { - /* If we can't use ldmib (SA110 bug), then try to pop r3 - instead. */ + /* If we can't use ldmib (SA110 bug), + then try to pop r3 instead. */ if (stack_adjust) live_regs_mask |= 1 << 3; sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); @@ -8331,24 +9652,12 @@ output_return_instruction (rtx operand, int really_return, int reverse) memcpy (p + 2, reg_names[reg], l); p += l + 2; } - + if (live_regs_mask & (1 << LR_REGNUM)) { sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); - /* Decide if we need to add the ^ symbol to the end of the - register list. This causes the saved condition codes - register to be copied into the current condition codes - register. We do the copy if we are conforming to the 32-bit - ABI and this is an interrupt function, or if we are - conforming to the 26-bit ABI. There is a special case for - the 26-bit ABI however, which is if we are writing back the - stack pointer but not loading the PC. In this case adding - the ^ symbol would create a type 2 LDM instruction, where - writeback is UNPREDICTABLE. We are safe in leaving the ^ - character off in this case however, since the actual return - instruction will be a MOVS which will restore the CPSR. */ - if ((TARGET_APCS_32 && IS_INTERRUPT (func_type)) - || (! TARGET_APCS_32 && really_return)) + /* If returning from an interrupt, restore the CPSR. */ + if (IS_INTERRUPT (func_type)) strcat (p, "^"); } else @@ -8387,13 +9696,11 @@ output_return_instruction (rtx operand, int really_return, int reverse) break; default: - /* ARMv5 implementations always provide BX, so interworking - is the default unless APCS-26 is in use. */ - if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32) - sprintf (instr, "bx%s\t%%|lr", conditional); + /* Use bx if it's available. */ + if (arm_arch5 || arm_arch4t) + sprintf (instr, "bx%s\t%%|lr", conditional); else - sprintf (instr, "mov%s%s\t%%|pc, %%|lr", - conditional, TARGET_APCS_32 ? "" : "s"); + sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); break; } @@ -8438,7 +9745,7 @@ arm_poke_function_name (FILE *stream, const char *name) length = strlen (name) + 1; alignlength = ROUND_UP_WORD (length); - + ASM_OUTPUT_ASCII (stream, name, length); ASM_OUTPUT_ALIGN (stream, 2); x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); @@ -8457,13 +9764,12 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) thumb_output_function_prologue (f, frame_size); return; } - + /* Sanity check. */ - if (arm_ccfsm_state || arm_target_insn) - abort (); + gcc_assert (!arm_ccfsm_state && !arm_target_insn); func_type = arm_current_func_type (); - + switch ((int) ARM_FUNC_TYPE (func_type)) { default: @@ -8472,9 +9778,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) case ARM_FT_INTERWORKED: asm_fprintf (f, "\t%@ Function supports interworking.\n"); break; - case ARM_FT_EXCEPTION_HANDLER: - asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); - break; case ARM_FT_ISR: asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); break; @@ -8485,7 +9788,7 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); break; } - + if (IS_NAKED (func_type)) asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); @@ -8494,7 +9797,7 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) if (IS_NESTED (func_type)) asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); - + asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", current_function_args_size, current_function_pretend_args_size, frame_size); @@ -8506,12 +9809,15 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) if (cfun->machine->lr_save_eliminated) asm_fprintf (f, "\t%@ link register save eliminated.\n"); + if (current_function_calls_eh_return) + asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); + #ifdef AOF_ASSEMBLER if (flag_pic) asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); #endif - return_used_this_function = 0; + return_used_this_function = 0; } const char * @@ -8520,15 +9826,15 @@ arm_output_epilogue (rtx sibling) int reg; unsigned long saved_regs_mask; unsigned long func_type; - /* Floats_offset is the offset from the "virtual" frame. In an APCS + /* Floats_offset is the offset from the "virtual" frame. In an APCS frame that is $fp + 4 for a non-variadic function. */ int floats_offset = 0; rtx operands[3]; - int frame_size = arm_get_frame_size (); FILE * f = asm_out_file; - rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; unsigned int lrm_count = 0; int really_return = (sibling == NULL); + int start_reg; + arm_stack_offsets *offsets; /* If we have already generated the return instruction then it is futile to generate anything else. */ @@ -8544,58 +9850,56 @@ arm_output_epilogue (rtx sibling) if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) { rtx op; - + /* A volatile function should never return. Call abort. */ op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); assemble_external_libcall (op); output_asm_insn ("bl\t%a0", &op); - + return ""; } - if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER - && ! really_return) - /* If we are throwing an exception, then we really must - be doing a return, so we can't tail-call. */ - abort (); - + /* If we are throwing an exception, then we really must be doing a + return, so we can't tail-call. */ + gcc_assert (!current_function_calls_eh_return || really_return); + + offsets = arm_get_frame_offsets (); saved_regs_mask = arm_compute_save_reg_mask (); if (TARGET_IWMMXT) lrm_count = bit_count (saved_regs_mask); - /* XXX We should adjust floats_offset for any anonymous args, and then - re-adjust vfp_offset below to compensate. */ - + floats_offset = offsets->saved_args; /* Compute how far away the floats will be. */ for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) if (saved_regs_mask & (1 << reg)) floats_offset += 4; - + if (frame_pointer_needed) { - int vfp_offset = 4; + /* This variable is for the Virtual Frame Pointer, not VFP regs. */ + int vfp_offset = offsets->frame; if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) if (regs_ever_live[reg] && !call_used_regs[reg]) { floats_offset += 12; - asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", + asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", reg, FP_REGNUM, floats_offset - vfp_offset); } } else { - int start_reg = LAST_ARM_FP_REGNUM; + start_reg = LAST_FPA_REGNUM; - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) { if (regs_ever_live[reg] && !call_used_regs[reg]) { floats_offset += 12; - + /* We can't unstack more than four registers at once. */ if (start_reg - reg == 3) { @@ -8621,6 +9925,39 @@ arm_output_epilogue (rtx sibling) FP_REGNUM, floats_offset - vfp_offset); } + if (TARGET_HARD_FLOAT && TARGET_VFP) + { + int saved_size; + + /* The fldmx insn does not have base+offset addressing modes, + so we use IP to hold the address. */ + saved_size = arm_get_vfp_saved_size (); + + if (saved_size > 0) + { + floats_offset += saved_size; + asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, + FP_REGNUM, floats_offset - vfp_offset); + } + start_reg = FIRST_VFP_REGNUM; + for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) + { + if ((!regs_ever_live[reg] || call_used_regs[reg]) + && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) + { + if (start_reg != reg) + arm_output_fldmx (f, IP_REGNUM, + (start_reg - FIRST_VFP_REGNUM) / 2, + (reg - start_reg) / 2); + start_reg = reg + 2; + } + } + if (start_reg != reg) + arm_output_fldmx (f, IP_REGNUM, + (start_reg - FIRST_VFP_REGNUM) / 2, + (reg - start_reg) / 2); + } + if (TARGET_IWMMXT) { /* The frame pointer is guaranteed to be non-double-word aligned. @@ -8631,13 +9968,13 @@ arm_output_epilogue (rtx sibling) We can ignore floats_offset since that was already included in the live_regs_mask. */ lrm_count += (lrm_count % 2 ? 2 : 1); - - for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + + for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) if (regs_ever_live[reg] && !call_used_regs[reg]) { - asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", + asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", reg, FP_REGNUM, lrm_count * 4); - lrm_count += 2; + lrm_count += 2; } } @@ -8645,8 +9982,7 @@ arm_output_epilogue (rtx sibling) frame generation actually contains the old stack pointer. So a quick way to unwind the stack is just pop the IP register directly into the stack pointer. */ - if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) - abort (); + gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); saved_regs_mask &= ~ (1 << IP_REGNUM); saved_regs_mask |= (1 << SP_REGNUM); @@ -8654,7 +9990,9 @@ arm_output_epilogue (rtx sibling) only need to restore the LR register (the return address), but to save time we can load it directly into the PC, unless we need a special function exit sequence, or we are not really returning. */ - if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) + if (really_return + && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL + && !current_function_calls_eh_return) /* Delete the LR from the register mask, so that the LR on the stack is loaded into the PC in the register mask. */ saved_regs_mask &= ~ (1 << LR_REGNUM); @@ -8670,8 +10008,7 @@ arm_output_epilogue (rtx sibling) be reset correctly to the original value, should an interrupt occur. If the stack pointer already points at the right place, then omit the subtraction. */ - if (((frame_size + current_function_outgoing_args_size + floats_offset) - != 4 * (1 + (int) bit_count (saved_regs_mask))) + if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) || current_function_calls_alloca) asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, 4 * bit_count (saved_regs_mask)); @@ -8685,26 +10022,25 @@ arm_output_epilogue (rtx sibling) else { /* Restore stack pointer if necessary. */ - if (frame_size + current_function_outgoing_args_size != 0) + if (offsets->outgoing_args != offsets->saved_regs) { operands[0] = operands[1] = stack_pointer_rtx; - operands[2] = GEN_INT (frame_size - + current_function_outgoing_args_size); + operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs); output_add_immediate (operands); } if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { - for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) + for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) if (regs_ever_live[reg] && !call_used_regs[reg]) asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", reg, SP_REGNUM); } else { - int start_reg = FIRST_ARM_FP_REGNUM; + start_reg = FIRST_FPA_REGNUM; - for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) + for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) { if (regs_ever_live[reg] && !call_used_regs[reg]) { @@ -8721,7 +10057,7 @@ arm_output_epilogue (rtx sibling) asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", start_reg, reg - start_reg, SP_REGNUM); - + start_reg = reg + 1; } } @@ -8732,16 +10068,37 @@ arm_output_epilogue (rtx sibling) start_reg, reg - start_reg, SP_REGNUM); } + if (TARGET_HARD_FLOAT && TARGET_VFP) + { + start_reg = FIRST_VFP_REGNUM; + for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) + { + if ((!regs_ever_live[reg] || call_used_regs[reg]) + && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) + { + if (start_reg != reg) + arm_output_fldmx (f, SP_REGNUM, + (start_reg - FIRST_VFP_REGNUM) / 2, + (reg - start_reg) / 2); + start_reg = reg + 2; + } + } + if (start_reg != reg) + arm_output_fldmx (f, SP_REGNUM, + (start_reg - FIRST_VFP_REGNUM) / 2, + (reg - start_reg) / 2); + } if (TARGET_IWMMXT) for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) if (regs_ever_live[reg] && !call_used_regs[reg]) - asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM); + asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); /* If we can, restore the LR into the PC. */ if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL && really_return && current_function_pretend_args_size == 0 - && saved_regs_mask & (1 << LR_REGNUM)) + && saved_regs_mask & (1 << LR_REGNUM) + && !current_function_calls_eh_return) { saved_regs_mask &= ~ (1 << LR_REGNUM); saved_regs_mask |= (1 << PC_REGNUM); @@ -8751,18 +10108,13 @@ arm_output_epilogue (rtx sibling) to load use the LDR instruction - it is faster. */ if (saved_regs_mask == (1 << LR_REGNUM)) { - /* The exception handler ignores the LR, so we do - not really need to load it off the stack. */ - if (eh_ofs) - asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); - else - asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); + asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); } else if (saved_regs_mask) { if (saved_regs_mask & (1 << SP_REGNUM)) /* Note - write back to the stack register is not enabled - (ie "ldmfd sp!..."). We know that the stack pointer is + (i.e. "ldmfd sp!..."). We know that the stack pointer is in the list of registers and if we add writeback the instruction becomes UNPREDICTABLE. */ print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); @@ -8779,21 +10131,18 @@ arm_output_epilogue (rtx sibling) } } - if (! really_return - || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL - && current_function_pretend_args_size == 0 - && saved_regs_mask & (1 << PC_REGNUM))) + /* We may have already restored PC directly from the stack. */ + if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) return ""; + /* Stack adjustment for exception handler. */ + if (current_function_calls_eh_return) + asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, + ARM_EH_STACKADJ_REGNUM); + /* Generate the return instruction. */ switch ((int) ARM_FUNC_TYPE (func_type)) { - case ARM_FT_EXCEPTION_HANDLER: - /* Even in 26-bit mode we do a mov (rather than a movs) - because we don't have the PSR bits set in the address. */ - asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); - break; - case ARM_FT_ISR: case ARM_FT_FIQ: asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); @@ -8808,21 +10157,10 @@ arm_output_epilogue (rtx sibling) break; default: - if (frame_pointer_needed) - /* If we used the frame pointer then the return address - will have been loaded off the stack directly into the - PC, so there is no need to issue a MOV instruction - here. */ - ; - else if (current_function_pretend_args_size == 0 - && (saved_regs_mask & (1 << LR_REGNUM))) - /* Similarly we may have been able to load LR into the PC - even if we did not create a stack frame. */ - ; - else if (TARGET_APCS_32) - asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); + if (arm_arch5 || arm_arch4t) + asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); else - asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); + asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); break; } @@ -8831,10 +10169,29 @@ arm_output_epilogue (rtx sibling) static void arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, - HOST_WIDE_INT frame_size) + HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) { + arm_stack_offsets *offsets; + if (TARGET_THUMB) { + int regno; + + /* Emit any call-via-reg trampolines that are needed for v4t support + of call_reg and call_value_reg type insns. */ + for (regno = 0; regno < LR_REGNUM; regno++) + { + rtx label = cfun->machine->call_via[regno]; + + if (label != NULL) + { + switch_to_section (function_section (current_function_decl)); + targetm.asm_out.internal_label (asm_out_file, "L", + CODE_LABEL_NUMBER (label)); + asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); + } + } + /* ??? Probably not safe to set this here, since it assumes that a function will be emitted as assembly immediately after we generate RTL for it. This does not happen for inline functions. */ @@ -8843,13 +10200,12 @@ arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, else { /* We need to take into account any stack-frame rounding. */ - frame_size = arm_get_frame_size (); + offsets = arm_get_frame_offsets (); - if (use_return_insn (FALSE, NULL) - && return_used_this_function - && (frame_size + current_function_outgoing_args_size) != 0 - && !frame_pointer_needed) - abort (); + gcc_assert (!use_return_insn (FALSE, NULL) + || !return_used_this_function + || offsets->saved_regs == offsets->outgoing_args + || frame_pointer_needed); /* Reset the ARM-specific per-function variables. */ after_arm_reorg = 0; @@ -8861,7 +10217,7 @@ arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, semantics of the operation, we need to annotate the insn for the benefit of DWARF2 frame unwind information. */ static rtx -emit_multi_reg_push (int mask) +emit_multi_reg_push (unsigned long mask) { int num_regs = 0; int num_dwarf_regs; @@ -8875,8 +10231,7 @@ emit_multi_reg_push (int mask) if (mask & (1 << i)) num_regs++; - if (num_regs == 0 || num_regs > 16) - abort (); + gcc_assert (num_regs && num_regs <= 16); /* We don't record the PC in the dwarf frame information. */ num_dwarf_regs = num_regs; @@ -8888,7 +10243,7 @@ emit_multi_reg_push (int mask) by the push_multi pattern in the arm.md file. The insn looks something like this: - (parallel [ + (parallel [ (set (mem:BLK (pre_dec:BLK (reg:SI sp))) (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) (use (reg:SI 11 fp)) @@ -8904,7 +10259,7 @@ emit_multi_reg_push (int mask) stack decrement per instruction. The RTL we generate for the note looks something like this: - (sequence [ + (sequence [ (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) (set (mem:SI (reg:SI sp)) (reg:SI r4)) (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) @@ -8914,7 +10269,7 @@ emit_multi_reg_push (int mask) This sequence is used both by the code to support stack unwinding for exceptions handlers and the code to generate dwarf2 frame debugging. */ - + par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); dwarf_par_index = 1; @@ -8927,9 +10282,9 @@ emit_multi_reg_push (int mask) XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (BLKmode, - gen_rtx_PRE_DEC (BLKmode, - stack_pointer_rtx)), + gen_frame_mem (BLKmode, + gen_rtx_PRE_DEC (BLKmode, + stack_pointer_rtx)), gen_rtx_UNSPEC (BLKmode, gen_rtvec (1, reg), UNSPEC_PUSH_MULT)); @@ -8937,7 +10292,7 @@ emit_multi_reg_push (int mask) if (i != PC_REGNUM) { tmp = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (SImode, stack_pointer_rtx), + gen_frame_mem (SImode, stack_pointer_rtx), reg); RTX_FRAME_RELATED_P (tmp) = 1; XVECEXP (dwarf, 0, dwarf_par_index) = tmp; @@ -8958,11 +10313,12 @@ emit_multi_reg_push (int mask) if (i != PC_REGNUM) { - tmp = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (SImode, + tmp + = gen_rtx_SET (VOIDmode, + gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, 4 * j)), - reg); + reg); RTX_FRAME_RELATED_P (tmp) = 1; XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; } @@ -8972,20 +10328,32 @@ emit_multi_reg_push (int mask) } par = emit_insn (par); - - tmp = gen_rtx_SET (SImode, + + tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, - gen_rtx_PLUS (SImode, - stack_pointer_rtx, - GEN_INT (-4 * num_regs))); + plus_constant (stack_pointer_rtx, -4 * num_regs)); RTX_FRAME_RELATED_P (tmp) = 1; XVECEXP (dwarf, 0, 0) = tmp; - + REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, REG_NOTES (par)); return par; } +/* Calculate the size of the return value that is passed in registers. */ +static int +arm_size_return_regs (void) +{ + enum machine_mode mode; + + if (current_function_return_rtx != 0) + mode = GET_MODE (current_function_return_rtx); + else + mode = DECL_MODE (DECL_RESULT (current_function_decl)); + + return GET_MODE_SIZE (mode); +} + static rtx emit_sfm (int base_reg, int count) { @@ -8995,48 +10363,67 @@ emit_sfm (int base_reg, int count) int i; par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); - dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); reg = gen_rtx_REG (XFmode, base_reg++); XVECEXP (par, 0, 0) - = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (BLKmode, - gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), + = gen_rtx_SET (VOIDmode, + gen_frame_mem (BLKmode, + gen_rtx_PRE_DEC (BLKmode, + stack_pointer_rtx)), gen_rtx_UNSPEC (BLKmode, gen_rtvec (1, reg), UNSPEC_PUSH_MULT)); - tmp - = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (XFmode, - gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), - reg); + tmp = gen_rtx_SET (VOIDmode, + gen_frame_mem (XFmode, stack_pointer_rtx), reg); RTX_FRAME_RELATED_P (tmp) = 1; - XVECEXP (dwarf, 0, count - 1) = tmp; - + XVECEXP (dwarf, 0, 1) = tmp; + for (i = 1; i < count; i++) { reg = gen_rtx_REG (XFmode, base_reg++); XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); - tmp = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (XFmode, - gen_rtx_PRE_DEC (BLKmode, - stack_pointer_rtx)), + tmp = gen_rtx_SET (VOIDmode, + gen_frame_mem (XFmode, + plus_constant (stack_pointer_rtx, + i * 12)), reg); RTX_FRAME_RELATED_P (tmp) = 1; - XVECEXP (dwarf, 0, count - i - 1) = tmp; + XVECEXP (dwarf, 0, i + 1) = tmp; } + tmp = gen_rtx_SET (VOIDmode, + stack_pointer_rtx, + plus_constant (stack_pointer_rtx, -12 * count)); + + RTX_FRAME_RELATED_P (tmp) = 1; + XVECEXP (dwarf, 0, 0) = tmp; + par = emit_insn (par); REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, REG_NOTES (par)); return par; } + +/* Return true if the current function needs to save/restore LR. */ + +static bool +thumb_force_lr_save (void) +{ + return !cfun->machine->lr_save_eliminated + && (!leaf_function_p () + || thumb_far_jump_used_p () + || regs_ever_live [LR_REGNUM]); +} + + /* Compute the distance from register FROM to register TO. These can be the arg pointer (26), the soft frame pointer (25), the stack pointer (13) or the hard frame pointer (11). + In thumb mode r7 is used as the soft frame pointer, if needed. Typical stack layout looks like this: old stack pointer -> | | @@ -9059,7 +10446,7 @@ emit_sfm (int base_reg, int count) | | \ | | local | | variables - | | / + locals base pointer -> | | / -- | | \ | | outgoing @@ -9076,60 +10463,131 @@ emit_sfm (int base_reg, int count) The sign of the number returned reflects the direction of stack growth, so the values are positive for all eliminations except - from the soft frame pointer to the hard frame pointer. */ -unsigned int -arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) + from the soft frame pointer to the hard frame pointer. + + SFP may point just inside the local variables block to ensure correct + alignment. */ + + +/* Calculate stack offsets. These are used to calculate register elimination + offsets and in prologue/epilogue code. */ + +static arm_stack_offsets * +arm_get_frame_offsets (void) { - unsigned int local_vars = arm_get_frame_size (); - unsigned int outgoing_args = current_function_outgoing_args_size; - unsigned int stack_frame; - unsigned int call_saved_registers; + struct arm_stack_offsets *offsets; unsigned long func_type; - - func_type = arm_current_func_type (); + int leaf; + int saved; + HOST_WIDE_INT frame_size; - /* Volatile functions never return, so there is - no need to save call saved registers. */ - call_saved_registers = 0; - if (! IS_VOLATILE (func_type)) + offsets = &cfun->machine->stack_offsets; + + /* We need to know if we are a leaf function. Unfortunately, it + is possible to be called after start_sequence has been called, + which causes get_insns to return the insns for the sequence, + not the function, which will cause leaf_function_p to return + the incorrect result. + + to know about leaf functions once reload has completed, and the + frame size cannot be changed after that time, so we can safely + use the cached value. */ + + if (reload_completed) + return offsets; + + /* Initially this is the size of the local variables. It will translated + into an offset once we have determined the size of preceding data. */ + frame_size = ROUND_UP_WORD (get_frame_size ()); + + leaf = leaf_function_p (); + + /* Space for variadic functions. */ + offsets->saved_args = current_function_pretend_args_size; + + offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0); + + if (TARGET_ARM) { - unsigned int reg_mask; - unsigned int reg; + unsigned int regno; - /* Make sure that we compute which registers will be saved - on the stack using the same algorithm that is used by - the prologue creation code. */ - reg_mask = arm_compute_save_reg_mask (); - - /* Now count the number of bits set in save_reg_mask. - If we have already counted the registers in the stack - frame, do not count them again. Non call-saved registers - might be saved in the call-save area of the stack, if - doing so will preserve the stack's alignment. Hence we - must count them here. For each set bit we need 4 bytes - of stack space. */ - if (frame_pointer_needed) - reg_mask &= 0x07ff; - call_saved_registers += 4 * bit_count (reg_mask); + saved = bit_count (arm_compute_save_reg_mask ()) * 4; - /* If the hard floating point registers are going to be - used then they must be saved on the stack as well. - Each register occupies 12 bytes of stack space. */ - for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) - call_saved_registers += 12; + /* We know that SP will be doubleword aligned on entry, and we must + preserve that condition at any subroutine call. We also require the + soft frame pointer to be doubleword aligned. */ if (TARGET_REALLY_IWMMXT) - /* Check for the call-saved iWMMXt registers. */ - for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) - if (regs_ever_live[reg] && ! call_used_regs [reg]) - call_saved_registers += 8; + { + /* Check for the call-saved iWMMXt registers. */ + for (regno = FIRST_IWMMXT_REGNUM; + regno <= LAST_IWMMXT_REGNUM; + regno++) + if (regs_ever_live [regno] && ! call_used_regs [regno]) + saved += 8; + } + + func_type = arm_current_func_type (); + if (! IS_VOLATILE (func_type)) + { + /* Space for saved FPA registers. */ + for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + saved += 12; + + /* Space for saved VFP registers. */ + if (TARGET_HARD_FLOAT && TARGET_VFP) + saved += arm_get_vfp_saved_size (); + } + } + else /* TARGET_THUMB */ + { + saved = bit_count (thumb_compute_save_reg_mask ()) * 4; + if (TARGET_BACKTRACE) + saved += 16; + } + + /* Saved registers include the stack frame. */ + offsets->saved_regs = offsets->saved_args + saved; + offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; + /* A leaf function does not need any stack alignment if it has nothing + on the stack. */ + if (leaf && frame_size == 0) + { + offsets->outgoing_args = offsets->soft_frame; + return offsets; + } + + /* Ensure SFP has the correct alignment. */ + if (ARM_DOUBLEWORD_ALIGN + && (offsets->soft_frame & 7)) + offsets->soft_frame += 4; + + offsets->locals_base = offsets->soft_frame + frame_size; + offsets->outgoing_args = (offsets->locals_base + + current_function_outgoing_args_size); + + if (ARM_DOUBLEWORD_ALIGN) + { + /* Ensure SP remains doubleword aligned. */ + if (offsets->outgoing_args & 7) + offsets->outgoing_args += 4; + gcc_assert (!(offsets->outgoing_args & 7)); } - /* The stack frame contains 4 registers - the old frame pointer, - the old stack pointer, the return address and PC of the start - of the function. */ - stack_frame = frame_pointer_needed ? 16 : 0; + return offsets; +} + + +/* Calculate the relative offsets for the different stack pointers. Positive + offsets are in the direction of stack growth. */ + +HOST_WIDE_INT +arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) +{ + arm_stack_offsets *offsets; + + offsets = arm_get_frame_offsets (); /* OK, now we have enough information to compute the distances. There must be an entry in these switch tables for each pair @@ -9146,29 +10604,27 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) case FRAME_POINTER_REGNUM: /* This is the reverse of the soft frame pointer to hard frame pointer elimination below. */ - if (call_saved_registers == 0 && stack_frame == 0) - return 0; - return (call_saved_registers + stack_frame - 4); + return offsets->soft_frame - offsets->saved_args; case ARM_HARD_FRAME_POINTER_REGNUM: /* If there is no stack frame then the hard frame pointer and the arg pointer coincide. */ - if (stack_frame == 0 && call_saved_registers != 0) + if (offsets->frame == offsets->saved_regs) return 0; /* FIXME: Not sure about this. Maybe we should always return 0 ? */ return (frame_pointer_needed - && current_function_needs_context + && cfun->static_chain_decl != NULL && ! cfun->machine->uses_anonymous_args) ? 4 : 0; case STACK_POINTER_REGNUM: /* If nothing has been pushed on the stack at all then this will return -4. This *is* correct! */ - return call_saved_registers + stack_frame + local_vars + outgoing_args - 4; + return offsets->outgoing_args - (offsets->saved_args + 4); default: - abort (); + gcc_unreachable (); } - break; + gcc_unreachable (); case FRAME_POINTER_REGNUM: switch (to) @@ -9181,17 +10637,16 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) stack frame. The soft frame pointer to the bottom entry in the stack frame. If there is no stack frame at all, then they are identical. */ - if (call_saved_registers == 0 && stack_frame == 0) - return 0; - return - (call_saved_registers + stack_frame - 4); + + return offsets->frame - offsets->soft_frame; case STACK_POINTER_REGNUM: - return local_vars + outgoing_args; + return offsets->outgoing_args - offsets->soft_frame; default: - abort (); + gcc_unreachable (); } - break; + gcc_unreachable (); default: /* You cannot eliminate from the stack pointer. @@ -9199,89 +10654,10 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) pointer to the stack pointer, but this will never happen, since if a stack frame is not needed the hard frame pointer will never be used. */ - abort (); + gcc_unreachable (); } } -/* Calculate the size of the stack frame, taking into account any - padding that is required to ensure stack-alignment. */ -HOST_WIDE_INT -arm_get_frame_size (void) -{ - int regno; - - int base_size = ROUND_UP_WORD (get_frame_size ()); - int entry_size = 0; - unsigned long func_type = arm_current_func_type (); - int leaf; - - if (! TARGET_ARM) - abort(); - - if (! TARGET_ATPCS) - return base_size; - - /* We need to know if we are a leaf function. Unfortunately, it - is possible to be called after start_sequence has been called, - which causes get_insns to return the insns for the sequence, - not the function, which will cause leaf_function_p to return - the incorrect result. - - To work around this, we cache the computed frame size. This - works because we will only be calling RTL expanders that need - to know about leaf functions once reload has completed, and the - frame size cannot be changed after that time, so we can safely - use the cached value. */ - - if (reload_completed) - return cfun->machine->frame_size; - - leaf = leaf_function_p (); - - /* A leaf function does not need any stack alignment if it has nothing - on the stack. */ - if (leaf && base_size == 0) - { - cfun->machine->frame_size = 0; - return 0; - } - - /* We know that SP will be word aligned on entry, and we must - preserve that condition at any subroutine call. But those are - the only constraints. */ - - /* Space for variadic functions. */ - if (current_function_pretend_args_size) - entry_size += current_function_pretend_args_size; - - /* Space for saved registers. */ - entry_size += bit_count (arm_compute_save_reg_mask ()) * 4; - - /* Space for saved FPA registers. */ - if (! IS_VOLATILE (func_type)) - { - for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) - entry_size += 12; - } - - if (TARGET_REALLY_IWMMXT) - { - /* Check for the call-saved iWMMXt registers. */ - for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) - if (regs_ever_live [regno] && ! call_used_regs [regno]) - entry_size += 8; - } - - if ((entry_size + base_size + current_function_outgoing_args_size) & 7) - base_size += 4; - if ((entry_size + base_size + current_function_outgoing_args_size) & 7) - abort (); - - cfun->machine->frame_size = base_size; - - return base_size; -} /* Generate the prologue instructions for entry into an ARM function. */ void @@ -9295,7 +10671,9 @@ arm_expand_prologue (void) unsigned long func_type; int fp_offset = 0; int saved_pretend_args = 0; - unsigned int args_to_push; + int saved_regs = 0; + unsigned HOST_WIDE_INT args_to_push; + arm_stack_offsets *offsets; func_type = arm_current_func_type (); @@ -9305,7 +10683,7 @@ arm_expand_prologue (void) /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ args_to_push = current_function_pretend_args_size; - + /* Compute which register we will have to save onto the stack. */ live_regs_mask = arm_compute_save_reg_mask (); @@ -9325,7 +10703,7 @@ arm_expand_prologue (void) stack decrement per function, and this is not it. If this instruction is labeled as being part of the frame creation sequence then dwarf2out_frame_debug_expr will - abort when it encounters the assignment of IP to FP + die when it encounters the assignment of IP to FP later on, since the use of SP here establishes SP as the CFA register and not IP. @@ -9339,7 +10717,7 @@ arm_expand_prologue (void) To get around this need to find somewhere to store IP whilst the frame is being created. We try the following places in order: - + 1. The last argument register. 2. A slot on the stack above the frame. (This only works if the function is not a varargs function). @@ -9352,25 +10730,19 @@ arm_expand_prologue (void) inherited from the caller. */ if (regs_ever_live[3] == 0) - { - insn = gen_rtx_REG (SImode, 3); - insn = gen_rtx_SET (SImode, insn, ip_rtx); - insn = emit_insn (insn); - } + insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); else if (args_to_push == 0) { rtx dwarf; - insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); - insn = gen_rtx_MEM (SImode, insn); - insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); - insn = emit_insn (insn); + insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); + insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); fp_offset = 4; /* Just tell the dwarf backend that we adjusted SP. */ dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, - gen_rtx_PLUS (SImode, stack_pointer_rtx, - GEN_INT (-fp_offset))); + plus_constant (stack_pointer_rtx, + -fp_offset)); RTX_FRAME_RELATED_P (insn) = 1; REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, REG_NOTES (insn)); @@ -9383,7 +10755,7 @@ arm_expand_prologue (void) ((0xf0 >> (args_to_push / 4)) & 0xf); else insn = emit_insn - (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (- args_to_push))); RTX_FRAME_RELATED_P (insn) = 1; @@ -9393,21 +10765,12 @@ arm_expand_prologue (void) args_to_push = 0; /* Now reuse r3 to preserve IP. */ - insn = gen_rtx_REG (SImode, 3); - insn = gen_rtx_SET (SImode, insn, ip_rtx); - (void) emit_insn (insn); + emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); } } - if (fp_offset) - { - insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); - insn = gen_rtx_SET (SImode, ip_rtx, insn); - } - else - insn = gen_movsi (ip_rtx, stack_pointer_rtx); - - insn = emit_insn (insn); + insn = emit_set_insn (ip_rtx, + plus_constant (stack_pointer_rtx, fp_offset)); RTX_FRAME_RELATED_P (insn) = 1; } @@ -9419,7 +10782,7 @@ arm_expand_prologue (void) ((0xf0 >> (args_to_push / 4)) & 0xf); else insn = emit_insn - (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (- args_to_push))); RTX_FRAME_RELATED_P (insn) = 1; } @@ -9432,50 +10795,53 @@ arm_expand_prologue (void) if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) && (live_regs_mask & (1 << LR_REGNUM)) != 0 && ! frame_pointer_needed) - emit_insn (gen_rtx_SET (SImode, - gen_rtx_REG (SImode, LR_REGNUM), - gen_rtx_PLUS (SImode, - gen_rtx_REG (SImode, LR_REGNUM), - GEN_INT (-4)))); + { + rtx lr = gen_rtx_REG (SImode, LR_REGNUM); + + emit_set_insn (lr, plus_constant (lr, -4)); + } if (live_regs_mask) { insn = emit_multi_reg_push (live_regs_mask); + saved_regs += bit_count (live_regs_mask) * 4; RTX_FRAME_RELATED_P (insn) = 1; } if (TARGET_IWMMXT) - for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) if (regs_ever_live[reg] && ! call_used_regs [reg]) { insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); - insn = gen_rtx_MEM (V2SImode, insn); - insn = emit_insn (gen_rtx_SET (VOIDmode, insn, - gen_rtx_REG (V2SImode, reg))); + insn = gen_frame_mem (V2SImode, insn); + insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); RTX_FRAME_RELATED_P (insn) = 1; + saved_regs += 8; } if (! IS_VOLATILE (func_type)) { + int start_reg; + /* Save any floating point call-saved registers used by this function. */ if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) if (regs_ever_live[reg] && !call_used_regs[reg]) { insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); - insn = gen_rtx_MEM (XFmode, insn); - insn = emit_insn (gen_rtx_SET (VOIDmode, insn, - gen_rtx_REG (XFmode, reg))); + insn = gen_frame_mem (XFmode, insn); + insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); RTX_FRAME_RELATED_P (insn) = 1; + saved_regs += 12; } } else { - int start_reg = LAST_ARM_FP_REGNUM; + start_reg = LAST_FPA_REGNUM; - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) { if (regs_ever_live[reg] && !call_used_regs[reg]) { @@ -9483,6 +10849,7 @@ arm_expand_prologue (void) { insn = emit_sfm (reg, 4); RTX_FRAME_RELATED_P (insn) = 1; + saved_regs += 48; start_reg = reg - 1; } } @@ -9492,6 +10859,7 @@ arm_expand_prologue (void) { insn = emit_sfm (reg + 1, start_reg - reg); RTX_FRAME_RELATED_P (insn) = 1; + saved_regs += (start_reg - reg) * 12; } start_reg = reg - 1; } @@ -9500,9 +10868,29 @@ arm_expand_prologue (void) if (start_reg != reg) { insn = emit_sfm (reg + 1, start_reg - reg); + saved_regs += (start_reg - reg) * 12; RTX_FRAME_RELATED_P (insn) = 1; } } + if (TARGET_HARD_FLOAT && TARGET_VFP) + { + start_reg = FIRST_VFP_REGNUM; + + for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) + { + if ((!regs_ever_live[reg] || call_used_regs[reg]) + && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) + { + if (start_reg != reg) + saved_regs += vfp_emit_fstmx (start_reg, + (reg - start_reg) / 2); + start_reg = reg + 2; + } + } + if (start_reg != reg) + saved_regs += vfp_emit_fstmx (start_reg, + (reg - start_reg) / 2); + } } if (frame_pointer_needed) @@ -9511,7 +10899,7 @@ arm_expand_prologue (void) insn = GEN_INT (-(4 + args_to_push + fp_offset)); insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); RTX_FRAME_RELATED_P (insn) = 1; - + if (IS_NESTED (func_type)) { /* Recover the static chain register. */ @@ -9520,25 +10908,26 @@ arm_expand_prologue (void) insn = gen_rtx_REG (SImode, 3); else /* if (current_function_pretend_args_size == 0) */ { - insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, - GEN_INT (4)); - insn = gen_rtx_MEM (SImode, insn); + insn = plus_constant (hard_frame_pointer_rtx, 4); + insn = gen_frame_mem (SImode, insn); } - emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); + emit_set_insn (ip_rtx, insn); /* Add a USE to stop propagate_one_insn() from barfing. */ emit_insn (gen_prologue_use (ip_rtx)); } } - amount = GEN_INT (-(arm_get_frame_size () - + current_function_outgoing_args_size)); - - if (amount != const0_rtx) + offsets = arm_get_frame_offsets (); + if (offsets->outgoing_args != offsets->saved_args + saved_regs) { /* This add can produce multiple insns for a large constant, so we need to get tricky. */ rtx last = get_last_insn (); + + amount = GEN_INT (offsets->saved_args + saved_regs + - offsets->outgoing_args); + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount)); do @@ -9556,10 +10945,17 @@ arm_expand_prologue (void) hard_frame_pointer_rtx)); } + + if (flag_pic && arm_pic_register != INVALID_REGNUM) + arm_load_pic_register (0UL); + /* If we are profiling, make sure no instructions are scheduled before the call to mcount. Similarly if the user has requested no - scheduling in the prolog. */ - if (current_function_profile || TARGET_NO_SCHED_PRO) + scheduling in the prolog. Similarly if we want non-call exceptions + using the EABI unwinder, to prevent faulting instructions from being + swapped with a stack adjustment. */ + if (current_function_profile || !TARGET_SCHED_PROLOG + || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) emit_insn (gen_blockage ()); /* If the link register is being kept alive, with the return address in it, @@ -9596,7 +10992,7 @@ arm_print_operand (FILE *stream, rtx x, int code) case '_': fputs (user_label_prefix, stream); return; - + case '|': fputs (REGISTER_PREFIX, stream); return; @@ -9604,8 +11000,17 @@ arm_print_operand (FILE *stream, rtx x, int code) case '?': if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) { - if (TARGET_THUMB || current_insn_predicate != NULL) - abort (); + if (TARGET_THUMB) + { + output_operand_lossage ("predicated Thumb instruction"); + break; + } + if (current_insn_predicate != NULL) + { + output_operand_lossage + ("predicated instruction in conditional sequence"); + break; + } fputs (arm_condition_codes[arm_current_cc], stream); } @@ -9614,7 +11019,10 @@ arm_print_operand (FILE *stream, rtx x, int code) enum arm_cond_code code; if (TARGET_THUMB) - abort (); + { + output_operand_lossage ("predicated Thumb instruction"); + break; + } code = get_arm_condition_code (current_insn_predicate); fputs (arm_condition_codes[code], stream); @@ -9665,11 +11073,19 @@ arm_print_operand (FILE *stream, rtx x, int code) case 'S': { HOST_WIDE_INT val; - const char * shift = shift_op (x, &val); + const char *shift; + + if (!shift_operator (x, SImode)) + { + output_operand_lossage ("invalid shift operand"); + break; + } + + shift = shift_op (x, &val); if (shift) { - fprintf (stream, ", %s ", shift_op (x, &val)); + fprintf (stream, ", %s ", shift); if (val == -1) arm_print_operand (stream, XEXP (x, 1), 0); else @@ -9679,19 +11095,19 @@ arm_print_operand (FILE *stream, rtx x, int code) return; /* An explanation of the 'Q', 'R' and 'H' register operands: - + In a pair of registers containing a DI or DF value the 'Q' operand returns the register number of the register containing the least significant part of the value. The 'R' operand returns the register number of the register containing the most significant part of the value. - + The 'H' operand returns the higher of the two register numbers. On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the same as the 'Q' operand, since the most significant part of the value is held in the lower number register. The reverse is true on systems where WORDS_BIG_ENDIAN is false. - + The purpose of these operands is to distinguish between cases where the endian-ness of the values is important (for example when they are added together), and cases where the endian-ness @@ -9706,25 +11122,37 @@ arm_print_operand (FILE *stream, rtx x, int code) of the memory location is actually held in one of the registers being overwritten by the load. */ case 'Q': - if (REGNO (x) > LAST_ARM_REGNUM) - abort (); + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); return; case 'R': - if (REGNO (x) > LAST_ARM_REGNUM) - abort (); + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); return; case 'H': - if (REGNO (x) > LAST_ARM_REGNUM) - abort (); + if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + asm_fprintf (stream, "%r", REGNO (x) + 1); return; case 'm': - asm_fprintf (stream, "%r", + asm_fprintf (stream, "%r", GET_CODE (XEXP (x, 0)) == REG ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); return; @@ -9739,16 +11167,30 @@ arm_print_operand (FILE *stream, rtx x, int code) /* CONST_TRUE_RTX means always -- that's the default. */ if (x == const_true_rtx) return; - + + if (!COMPARISON_P (x)) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + fputs (arm_condition_codes[get_arm_condition_code (x)], stream); return; case 'D': - /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever + /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever want to do that. */ if (x == const_true_rtx) - abort (); + { + output_operand_lossage ("instruction never exectued"); + return; + } + if (!COMPARISON_P (x)) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE (get_arm_condition_code (x))], @@ -9764,8 +11206,8 @@ arm_print_operand (FILE *stream, rtx x, int code) case 'X': /* Cirrus register in D mode. */ case 'Y': /* Cirrus register in FX mode. */ case 'Z': /* Cirrus register in DX mode. */ - if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) - abort (); + gcc_assert (GET_CODE (x) == REG + && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); fprintf (stream, "mv%s%s", code == 'W' ? "f" @@ -9780,7 +11222,10 @@ arm_print_operand (FILE *stream, rtx x, int code) int mode = GET_MODE (x); if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) - abort (); + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } fprintf (stream, "mv%s%s", mode == DFmode ? "d" @@ -9796,7 +11241,11 @@ arm_print_operand (FILE *stream, rtx x, int code) || REGNO (x) < FIRST_IWMMXT_GR_REGNUM || REGNO (x) > LAST_IWMMXT_GR_REGNUM) /* Bad value for wCG register number. */ - abort (); + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + else fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); return; @@ -9807,7 +11256,11 @@ arm_print_operand (FILE *stream, rtx x, int code) || INTVAL (x) < 0 || INTVAL (x) >= 16) /* Bad value for wC register number. */ - abort (); + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + else { static const char * wc_reg_names [16] = @@ -9817,30 +11270,68 @@ arm_print_operand (FILE *stream, rtx x, int code) "wCGR0", "wCGR1", "wCGR2", "wCGR3", "wC12", "wC13", "wC14", "wC15" }; - + fprintf (stream, wc_reg_names [INTVAL (x)]); } return; + /* Print a VFP double precision register name. */ + case 'P': + { + int mode = GET_MODE (x); + int num; + + if (mode != DImode && mode != DFmode) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + if (GET_CODE (x) != REG + || !IS_VFP_REGNUM (REGNO (x))) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + num = REGNO(x) - FIRST_VFP_REGNUM; + if (num & 1) + { + output_operand_lossage ("invalid operand for code '%c'", code); + return; + } + + fprintf (stream, "d%d", num >> 1); + } + return; + default: if (x == 0) - abort (); + { + output_operand_lossage ("missing operand"); + return; + } - if (GET_CODE (x) == REG) - asm_fprintf (stream, "%r", REGNO (x)); - else if (GET_CODE (x) == MEM) + switch (GET_CODE (x)) { + case REG: + asm_fprintf (stream, "%r", REGNO (x)); + break; + + case MEM: output_memory_reference_mode = GET_MODE (x); output_address (XEXP (x, 0)); - } - else if (GET_CODE (x) == CONST_DOUBLE) - fprintf (stream, "#%s", fp_immediate_constant (x)); - else if (GET_CODE (x) == NEG) - abort (); /* This should never happen now. */ - else - { + break; + + case CONST_DOUBLE: + fprintf (stream, "#%s", fp_immediate_constant (x)); + break; + + default: + gcc_assert (GET_CODE (x) != NEG); fputc ('#', stream); output_addr_const (stream, x); + break; } } } @@ -9874,12 +11365,11 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) return true; } - if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x))) + if (arm_vector_mode_supported_p (GET_MODE (x))) { int i, units; - if (GET_CODE (x) != CONST_VECTOR) - abort (); + gcc_assert (GET_CODE (x) == CONST_VECTOR); units = CONST_VECTOR_NUNITS (x); @@ -9889,7 +11379,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) case V4HImode: size = 2; break; case V8QImode: size = 1; break; default: - abort (); + gcc_unreachable (); } for (i = 0; i < units; i++) @@ -9906,6 +11396,26 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) return default_assemble_integer (x, size, aligned_p); } + + +/* Add a function to the list of static constructors. */ + +static void +arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) +{ + if (!TARGET_AAPCS_BASED) + { + default_named_section_asm_out_constructor (symbol, priority); + return; + } + + /* Put these in the .init_array section, using a special relocation. */ + switch_to_section (ctors_section); + assemble_align (POINTER_SIZE); + fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("(target1)\n", asm_out_file); +} #endif /* A finite state machine takes care of noticing whether or not instructions @@ -9967,8 +11477,7 @@ get_arm_condition_code (rtx comparison) case CC_DLTUmode: code = ARM_CC; dominance: - if (comp_code != EQ && comp_code != NE) - abort (); + gcc_assert (comp_code == EQ || comp_code == NE); if (comp_code == EQ) return ARM_INVERSE_CONDITION_CODE (code); @@ -9981,7 +11490,7 @@ get_arm_condition_code (rtx comparison) case EQ: return ARM_EQ; case GE: return ARM_PL; case LT: return ARM_MI; - default: abort (); + default: gcc_unreachable (); } case CC_Zmode: @@ -9989,7 +11498,7 @@ get_arm_condition_code (rtx comparison) { case NE: return ARM_NE; case EQ: return ARM_EQ; - default: abort (); + default: gcc_unreachable (); } case CC_Nmode: @@ -9997,7 +11506,7 @@ get_arm_condition_code (rtx comparison) { case NE: return ARM_MI; case EQ: return ARM_PL; - default: abort (); + default: gcc_unreachable (); } case CCFPEmode: @@ -10022,7 +11531,7 @@ get_arm_condition_code (rtx comparison) /* UNEQ and LTGT do not have a representation. */ case UNEQ: /* Fall through. */ case LTGT: /* Fall through. */ - default: abort (); + default: gcc_unreachable (); } case CC_SWPmode: @@ -10038,7 +11547,7 @@ get_arm_condition_code (rtx comparison) case GTU: return ARM_CC; case LEU: return ARM_CS; case LTU: return ARM_HI; - default: abort (); + default: gcc_unreachable (); } case CC_Cmode: @@ -10046,9 +11555,9 @@ get_arm_condition_code (rtx comparison) { case LTU: return ARM_CS; case GEU: return ARM_CC; - default: abort (); + default: gcc_unreachable (); } - + case CCmode: switch (comp_code) { @@ -10062,13 +11571,11 @@ get_arm_condition_code (rtx comparison) case GTU: return ARM_HI; case LEU: return ARM_LS; case LTU: return ARM_CC; - default: abort (); + default: gcc_unreachable (); } - default: abort (); + default: gcc_unreachable (); } - - abort (); } void @@ -10086,10 +11593,10 @@ arm_final_prescan_insn (rtx insn) means that we have to grub around within the jump expression to find out what the conditions are when the jump isn't taken. */ int jump_clobbers = 0; - + /* If we start with a return insn, we only succeed if we find another one. */ int seeking_return = 0; - + /* START_INSN will hold the insn from where we start looking. This is the first insn after the following code_label if REVERSE is true. */ rtx start_insn = insn; @@ -10146,12 +11653,11 @@ arm_final_prescan_insn (rtx insn) return; } - if (arm_ccfsm_state != 0 && !reverse) - abort (); + gcc_assert (!arm_ccfsm_state || reverse); if (GET_CODE (insn) != JUMP_INSN) return; - /* This jump might be paralleled with a clobber of the condition codes + /* This jump might be paralleled with a clobber of the condition codes the jump should always come first */ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) body = XVECEXP (body, 0, 0); @@ -10166,14 +11672,14 @@ arm_final_prescan_insn (rtx insn) int then_not_else = TRUE; rtx this_insn = start_insn, label = 0; - /* If the jump cannot be done with one instruction, we cannot + /* If the jump cannot be done with one instruction, we cannot conditionally execute the instruction in the inverse case. */ if (get_attr_conds (insn) == CONDS_JUMP_CLOB) { jump_clobbers = 1; return; } - + /* Register the insn jumped to. */ if (reverse) { @@ -10195,7 +11701,7 @@ arm_final_prescan_insn (rtx insn) then_not_else = FALSE; } else - abort (); + gcc_unreachable (); /* See how many insns this branch skips, and what kind of insns. If all insns are okay, and the label or unconditional branch to the same @@ -10231,8 +11737,8 @@ arm_final_prescan_insn (rtx insn) case BARRIER: /* Succeed if the following insn is the target label. - Otherwise fail. - If return insns are used then the last insn in a function + Otherwise fail. + If return insns are used then the last insn in a function will be a barrier. */ this_insn = next_nonnote_insn (this_insn); if (this_insn && this_insn == label) @@ -10251,32 +11757,37 @@ arm_final_prescan_insn (rtx insn) break; case CALL_INSN: - /* If using 32-bit addresses the cc is not preserved over - calls. */ - if (TARGET_APCS_32) + /* The AAPCS says that conditional calls should not be + used since they make interworking inefficient (the + linker can't transform BL<cond> into BLX). That's + only a problem if the machine has BLX. */ + if (arm_arch5) { - /* Succeed if the following insn is the target label, - or if the following two insns are a barrier and - the target label. */ - this_insn = next_nonnote_insn (this_insn); - if (this_insn && GET_CODE (this_insn) == BARRIER) - this_insn = next_nonnote_insn (this_insn); + fail = TRUE; + break; + } + + /* Succeed if the following insn is the target label, or + if the following two insns are a barrier and the + target label. */ + this_insn = next_nonnote_insn (this_insn); + if (this_insn && GET_CODE (this_insn) == BARRIER) + this_insn = next_nonnote_insn (this_insn); - if (this_insn && this_insn == label - && insns_skipped < max_insns_skipped) + if (this_insn && this_insn == label + && insns_skipped < max_insns_skipped) + { + if (jump_clobbers) { - if (jump_clobbers) - { - arm_ccfsm_state = 2; - this_insn = next_nonnote_insn (this_insn); - } - else - arm_ccfsm_state = 1; - succeed = TRUE; + arm_ccfsm_state = 2; + this_insn = next_nonnote_insn (this_insn); } else - fail = TRUE; + arm_ccfsm_state = 1; + succeed = TRUE; } + else + fail = TRUE; break; case JUMP_INSN: @@ -10299,7 +11810,7 @@ arm_final_prescan_insn (rtx insn) else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) fail = TRUE; } - /* Fail if a conditional return is undesirable (eg on a + /* Fail if a conditional return is undesirable (e.g. on a StrongARM), but still allow this if optimizing for size. */ else if (GET_CODE (scanbody) == RETURN && !use_return_insn (TRUE, NULL) @@ -10323,7 +11834,7 @@ arm_final_prescan_insn (rtx insn) } } else - fail = TRUE; /* Unrecognized jump (eg epilogue). */ + fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ break; @@ -10357,14 +11868,16 @@ arm_final_prescan_insn (rtx insn) { if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) arm_target_label = CODE_LABEL_NUMBER (label); - else if (seeking_return || arm_ccfsm_state == 2) + else { + gcc_assert (seeking_return || arm_ccfsm_state == 2); + while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) { this_insn = next_nonnote_insn (this_insn); - if (this_insn && (GET_CODE (this_insn) == BARRIER - || GET_CODE (this_insn) == CODE_LABEL)) - abort (); + gcc_assert (!this_insn + || (GET_CODE (this_insn) != BARRIER + && GET_CODE (this_insn) != CODE_LABEL)); } if (!this_insn) { @@ -10376,13 +11889,10 @@ arm_final_prescan_insn (rtx insn) } arm_target_insn = this_insn; } - else - abort (); if (jump_clobbers) { - if (reverse) - abort (); - arm_current_cc = + gcc_assert (!reverse); + arm_current_cc = get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), 0), 0), 1)); if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) @@ -10402,7 +11912,7 @@ arm_final_prescan_insn (rtx insn) if (reverse || then_not_else) arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); } - + /* Restore recog_data (getting the attributes of other insns can destroy this array, but final.c assumes that it remains intact across this call; since the insn has been recognized already we @@ -10412,13 +11922,15 @@ arm_final_prescan_insn (rtx insn) } /* Returns true if REGNO is a valid register - for holding a quantity of tyoe MODE. */ + for holding a quantity of type MODE. */ int arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) { if (GET_MODE_CLASS (mode) == MODE_CC) - return regno == CC_REGNUM; - + return (regno == CC_REGNUM + || (TARGET_HARD_FLOAT && TARGET_VFP + && regno == VFPCC_REGNUM)); + if (TARGET_THUMB) /* For the Thumb we only allow values bigger than SImode in registers 0 - 6, so that there is always a second low @@ -10427,7 +11939,8 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) start of an even numbered register pair. */ return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); - if (IS_CIRRUS_REGNUM (regno)) + if (TARGET_HARD_FLOAT && TARGET_MAVERICK + && IS_CIRRUS_REGNUM (regno)) /* We have outlawed SI values in Cirrus registers because they reside in the lower 32 bits, but SF values reside in the upper 32 bits. This causes gcc all sorts of grief. We can't @@ -10435,26 +11948,44 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) get sign extended to 64bits-- aldyh. */ return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); - if (IS_IWMMXT_GR_REGNUM (regno)) - return mode == SImode; + if (TARGET_HARD_FLOAT && TARGET_VFP + && IS_VFP_REGNUM (regno)) + { + if (mode == SFmode || mode == SImode) + return TRUE; - if (IS_IWMMXT_REGNUM (regno)) - return VALID_IWMMXT_REG_MODE (mode); + /* DFmode values are only valid in even register pairs. */ + if (mode == DFmode) + return ((regno - FIRST_VFP_REGNUM) & 1) == 0; + return FALSE; + } + if (TARGET_REALLY_IWMMXT) + { + if (IS_IWMMXT_GR_REGNUM (regno)) + return mode == SImode; + + if (IS_IWMMXT_REGNUM (regno)) + return VALID_IWMMXT_REG_MODE (mode); + } + + /* We allow any value to be stored in the general registers. + Restrict doubleword quantities to even register pairs so that we can + use ldrd. */ if (regno <= LAST_ARM_REGNUM) - /* We allow any value to be stored in the general registers. */ - return 1; + return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); - if ( regno == FRAME_POINTER_REGNUM + if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) /* We only allow integers in the fake hard registers. */ return GET_MODE_CLASS (mode) == MODE_INT; /* The only registers left are the FPA registers which we only allow to hold FP values. */ - return GET_MODE_CLASS (mode) == MODE_FLOAT - && regno >= FIRST_ARM_FP_REGNUM - && regno <= LAST_ARM_FP_REGNUM; + return (TARGET_HARD_FLOAT && TARGET_FPA + && GET_MODE_CLASS (mode) == MODE_FLOAT + && regno >= FIRST_FPA_REGNUM + && regno <= LAST_FPA_REGNUM); } int @@ -10475,13 +12006,16 @@ arm_regno_class (int regno) || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) return GENERAL_REGS; - - if (regno == CC_REGNUM) + + if (regno == CC_REGNUM || regno == VFPCC_REGNUM) return NO_REGS; if (IS_CIRRUS_REGNUM (regno)) return CIRRUS_REGS; + if (IS_VFP_REGNUM (regno)) + return VFP_REGS; + if (IS_IWMMXT_REGNUM (regno)) return IWMMXT_REGS; @@ -10510,13 +12044,13 @@ arm_debugger_arg_offset (int value, rtx addr) an offset of 0 is correct. */ if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) return 0; - + /* If we are using the stack pointer to point at the argument, then an offset of 0 is correct. */ if ((TARGET_THUMB || !frame_pointer_needed) && REGNO (addr) == SP_REGNUM) return 0; - + /* Oh dear. The argument is pointed to by a register rather than being held in a register, or being stored at a known offset from the frame pointer. Since GDB only understands @@ -10526,12 +12060,12 @@ arm_debugger_arg_offset (int value, rtx addr) looking to see where this register gets its value. If the register is initialized from the frame pointer plus an offset then we are in luck and we can continue, otherwise we give up. - + This code is exercised by producing debugging information for a function with arguments like this: - + double func (double a, double b, int c, double d) {return d;} - + Without this code the stab for parameter 'd' will be set to an offset of 0 from the frame pointer, rather than 8. */ @@ -10546,10 +12080,10 @@ arm_debugger_arg_offset (int value, rtx addr) a constant integer then... */ - + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { - if ( GET_CODE (insn) == INSN + if ( GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS @@ -10559,15 +12093,15 @@ arm_debugger_arg_offset (int value, rtx addr) ) { value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); - + break; } } - + if (value == 0) { debug_rtx (addr); - warning ("unable to compute real location of stacked parameter"); + warning (0, "unable to compute real location of stacked parameter"); value = 8; /* XXX magic hack */ } @@ -10578,7 +12112,8 @@ arm_debugger_arg_offset (int value, rtx addr) do \ { \ if ((MASK) & insn_flags) \ - builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \ + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \ + BUILT_IN_MD, NULL, NULL_TREE); \ } \ while (0) @@ -10617,8 +12152,8 @@ static const struct builtin_description bdesc_2arg[] = IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) - IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH) - IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH) + IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) + IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) @@ -10659,7 +12194,7 @@ static const struct builtin_description bdesc_2arg[] = #define IWMMXT_BUILTIN2(code, builtin) \ { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, - + IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) @@ -10677,13 +12212,13 @@ static const struct builtin_description bdesc_2arg[] = IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) - IWMMXT_BUILTIN2 (lshrdi3, WSRLDI) + IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) - IWMMXT_BUILTIN2 (ashrdi3, WSRADI) + IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) @@ -10726,6 +12261,10 @@ arm_init_iwmmxt_builtins (void) size_t i; tree endlink = void_list_node; + tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); + tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); + tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); + tree int_ftype_int = build_function_type (integer_type_node, tree_cons (NULL_TREE, integer_type_node, endlink)); @@ -10940,7 +12479,7 @@ arm_init_iwmmxt_builtins (void) break; default: - abort (); + gcc_unreachable (); } def_mbuiltin (d->mask, d->name, type, d->code); @@ -11039,8 +12578,23 @@ arm_init_iwmmxt_builtins (void) } static void +arm_init_tls_builtins (void) +{ + tree ftype; + tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL); + tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow); + + ftype = build_function_type (ptr_type_node, void_list_node); + lang_hooks.builtin_function ("__builtin_thread_pointer", ftype, + ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, + NULL, const_nothrow); +} + +static void arm_init_builtins (void) { + arm_init_tls_builtins (); + if (TARGET_REALLY_IWMMXT) arm_init_iwmmxt_builtins (); } @@ -11070,8 +12624,8 @@ arm_expand_binop_builtin (enum insn_code icode, rtx pat; tree arg0 = TREE_VALUE (arglist); tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; enum machine_mode mode1 = insn_data[icode].operand[2].mode; @@ -11086,10 +12640,7 @@ arm_expand_binop_builtin (enum insn_code icode, || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - /* In case the insn wants input operands in modes different from - the result, abort. */ - if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1) - abort (); + gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); @@ -11111,7 +12662,7 @@ arm_expand_unop_builtin (enum insn_code icode, { rtx pat; tree arg0 = TREE_VALUE (arglist); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; @@ -11184,8 +12735,8 @@ arm_expand_builtin (tree exp, arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; @@ -11217,9 +12768,9 @@ arm_expand_builtin (tree exp, arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; @@ -11248,14 +12799,14 @@ arm_expand_builtin (tree exp, case ARM_BUILTIN_SETWCX: arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - emit_insn (gen_iwmmxt_tmcr (op0, op1)); + op0 = force_reg (SImode, expand_normal (arg0)); + op1 = expand_normal (arg1); + emit_insn (gen_iwmmxt_tmcr (op1, op0)); return 0; case ARM_BUILTIN_GETWCX: arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); target = gen_reg_rtx (SImode); emit_insn (gen_iwmmxt_tmrc (target, op0)); return target; @@ -11264,8 +12815,8 @@ arm_expand_builtin (tree exp, icode = CODE_FOR_iwmmxt_wshufh; arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); tmode = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; @@ -11319,9 +12870,9 @@ arm_expand_builtin (tree exp, arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; @@ -11342,12 +12893,15 @@ arm_expand_builtin (tree exp, return 0; emit_insn (pat); return target; - + case ARM_BUILTIN_WZERO: target = gen_reg_rtx (DImode); emit_insn (gen_iwmmxt_clrdi (target)); return target; + case ARM_BUILTIN_THREAD_POINTER: + return arm_load_tp (target); + default: break; } @@ -11364,42 +12918,11 @@ arm_expand_builtin (tree exp, return NULL_RTX; } -/* Recursively search through all of the blocks in a function - checking to see if any of the variables created in that - function match the RTX called 'orig'. If they do then - replace them with the RTX called 'new'. */ -static void -replace_symbols_in_block (tree block, rtx orig, rtx new) -{ - for (; block; block = BLOCK_CHAIN (block)) - { - tree sym; - - if (!TREE_USED (block)) - continue; - - for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) - { - if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) - || DECL_IGNORED_P (sym) - || TREE_CODE (sym) != VAR_DECL - || DECL_EXTERNAL (sym) - || !rtx_equal_p (DECL_RTL (sym), orig) - ) - continue; - - SET_DECL_RTL (sym, new); - } - - replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); - } -} - /* Return the number (counting from 0) of the least significant set bit in MASK. */ inline static int -number_of_first_bit_set (int mask) +number_of_first_bit_set (unsigned mask) { int bit; @@ -11411,11 +12934,121 @@ number_of_first_bit_set (int mask) return bit; } +/* Emit code to push or pop registers to or from the stack. F is the + assembly file. MASK is the registers to push or pop. PUSH is + nonzero if we should push, and zero if we should pop. For debugging + output, if pushing, adjust CFA_OFFSET by the amount of space added + to the stack. REAL_REGS should have the same number of bits set as + MASK, and will be used instead (in the same order) to describe which + registers were saved - this is used to mark the save slots when we + push high registers after moving them to low registers. */ +static void +thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, + unsigned long real_regs) +{ + int regno; + int lo_mask = mask & 0xFF; + int pushed_words = 0; + + gcc_assert (mask); + + if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) + { + /* Special case. Do not generate a POP PC statement here, do it in + thumb_exit() */ + thumb_exit (f, -1); + return; + } + + if (ARM_EABI_UNWIND_TABLES && push) + { + fprintf (f, "\t.save\t{"); + for (regno = 0; regno < 15; regno++) + { + if (real_regs & (1 << regno)) + { + if (real_regs & ((1 << regno) -1)) + fprintf (f, ", "); + asm_fprintf (f, "%r", regno); + } + } + fprintf (f, "}\n"); + } + + fprintf (f, "\t%s\t{", push ? "push" : "pop"); + + /* Look at the low registers first. */ + for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) + { + if (lo_mask & 1) + { + asm_fprintf (f, "%r", regno); + + if ((lo_mask & ~1) != 0) + fprintf (f, ", "); + + pushed_words++; + } + } + + if (push && (mask & (1 << LR_REGNUM))) + { + /* Catch pushing the LR. */ + if (mask & 0xFF) + fprintf (f, ", "); + + asm_fprintf (f, "%r", LR_REGNUM); + + pushed_words++; + } + else if (!push && (mask & (1 << PC_REGNUM))) + { + /* Catch popping the PC. */ + if (TARGET_INTERWORK || TARGET_BACKTRACE + || current_function_calls_eh_return) + { + /* The PC is never poped directly, instead + it is popped into r3 and then BX is used. */ + fprintf (f, "}\n"); + + thumb_exit (f, -1); + + return; + } + else + { + if (mask & 0xFF) + fprintf (f, ", "); + + asm_fprintf (f, "%r", PC_REGNUM); + } + } + + fprintf (f, "}\n"); + + if (push && pushed_words && dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + int pushed_mask = real_regs; + + *cfa_offset += pushed_words * 4; + dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); + + pushed_words = 0; + pushed_mask = real_regs; + for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) + { + if (pushed_mask & 1) + dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); + } + } +} + /* Generate code to return from a thumb function. If 'reg_containing_return_addr' is -1, then the return address is actually on the stack, at the stack pointer. */ static void -thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) +thumb_exit (FILE *f, int reg_containing_return_addr) { unsigned regs_available_for_popping; unsigned regs_to_pop; @@ -11430,15 +13063,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) regs_to_pop = 0; pops_needed = 0; - /* There is an assumption here, that if eh_ofs is not NULL, the - normal return address will have been pushed. */ - if (reg_containing_return_addr == -1 || eh_ofs) + if (reg_containing_return_addr == -1) { - /* When we are generating a return for __builtin_eh_return, - reg_containing_return_addr must specify the return regno. */ - if (eh_ofs && reg_containing_return_addr == -1) - abort (); - regs_to_pop |= 1 << LR_REGNUM; ++pops_needed; } @@ -11454,8 +13080,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) return. */ if (pops_needed == 0) { - if (eh_ofs) - asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); + if (current_function_calls_eh_return) + asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); return; @@ -11465,17 +13091,10 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) just pop the return address straight into the PC. */ else if (!TARGET_INTERWORK && !TARGET_BACKTRACE - && !is_called_in_ARM_mode (current_function_decl)) + && !is_called_in_ARM_mode (current_function_decl) + && !current_function_calls_eh_return) { - if (eh_ofs) - { - asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); - asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); - asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); - } - else - asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); - + asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); return; } @@ -11484,11 +13103,10 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) /* If returning via __builtin_eh_return, the bottom three registers all contain information needed for the return. */ - if (eh_ofs) + if (current_function_calls_eh_return) size = 12; else { -#ifdef RTX_CODE /* If we can deduce the registers used from the function's return value. This is more reliable that examining regs_ever_live[] because that will be set if the register is @@ -11498,7 +13116,6 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) if (current_function_return_rtx != 0) mode = GET_MODE (current_function_return_rtx); else -#endif mode = DECL_MODE (DECL_RESULT (current_function_decl)); size = GET_MODE_SIZE (mode); @@ -11538,7 +13155,7 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) /* If we have any popping registers left over, remove them. */ if (available > 0) regs_available_for_popping &= ~available; - + /* Otherwise if we need another popping register we can use the fourth argument register. */ else if (pops_needed) @@ -11556,15 +13173,15 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) /* Register a4 is being used to hold part of the return value, but we have dire need of a free, low register. */ restore_a4 = TRUE; - + asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); } - + if (reg_containing_return_addr != LAST_ARG_REGNUM) { /* The fourth argument register is available. */ regs_available_for_popping |= 1 << LAST_ARG_REGNUM; - + --pops_needed; } } @@ -11578,7 +13195,7 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) { /* The return address was popped into the lowest numbered register. */ regs_to_pop &= ~(1 << LR_REGNUM); - + reg_containing_return_addr = number_of_first_bit_set (regs_available_for_popping); @@ -11591,7 +13208,7 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) if (regs_available_for_popping) { int frame_pointer; - + /* Work out which register currently contains the frame pointer. */ frame_pointer = number_of_first_bit_set (regs_available_for_popping); @@ -11602,18 +13219,18 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) /* (Temporarily) remove it from the mask of popped registers. */ regs_available_for_popping &= ~(1 << frame_pointer); regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); - + if (regs_available_for_popping) { int stack_pointer; - + /* We popped the stack pointer as well, find the register that contains it. */ stack_pointer = number_of_first_bit_set (regs_available_for_popping); /* Move it into the stack register. */ asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); - + /* At this point we have popped all necessary registers, so do not worry about restoring regs_available_for_popping to its correct value: @@ -11630,7 +13247,7 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) regs_available_for_popping |= (1 << frame_pointer); } } - + /* If we still have registers left on the stack, but we no longer have any registers into which we can pop them, then we must move the return address into the link register and make available the register that @@ -11638,10 +13255,10 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) if (regs_available_for_popping == 0 && pops_needed > 0) { regs_available_for_popping |= 1 << reg_containing_return_addr; - + asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, reg_containing_return_addr); - + reg_containing_return_addr = LR_REGNUM; } @@ -11651,7 +13268,7 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) { int popped_into; int move_to; - + thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, regs_available_for_popping); @@ -11666,13 +13283,13 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) --pops_needed; } - + /* If we still have not popped everything then we must have only had one register available to us and we are now popping the SP. */ if (pops_needed > 0) { int popped_into; - + thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, regs_available_for_popping); @@ -11693,107 +13310,17 @@ thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); reg_containing_return_addr = LR_REGNUM; } - + asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); } - if (eh_ofs) - asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); + if (current_function_calls_eh_return) + asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); /* Return to caller. */ asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); } -/* Emit code to push or pop registers to or from the stack. F is the - assembly file. MASK is the registers to push or pop. PUSH is - non-zero if we should push, and zero if we should pop. For debugging - output, if pushing, adjust CFA_OFFSET by the amount of space added - to the stack. REAL_REGS should have the same number of bits set as - MASK, and will be used instead (in the same order) to describe which - registers were saved - this is used to mark the save slots when we - push high registers after moving them to low registers. */ -static void -thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs) -{ - int regno; - int lo_mask = mask & 0xFF; - int pushed_words = 0; - - if (lo_mask == 0 && !push && (mask & (1 << 15))) - { - /* Special case. Do not generate a POP PC statement here, do it in - thumb_exit() */ - thumb_exit (f, -1, NULL_RTX); - return; - } - - fprintf (f, "\t%s\t{", push ? "push" : "pop"); - - /* Look at the low registers first. */ - for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) - { - if (lo_mask & 1) - { - asm_fprintf (f, "%r", regno); - - if ((lo_mask & ~1) != 0) - fprintf (f, ", "); - - pushed_words++; - } - } - - if (push && (mask & (1 << LR_REGNUM))) - { - /* Catch pushing the LR. */ - if (mask & 0xFF) - fprintf (f, ", "); - - asm_fprintf (f, "%r", LR_REGNUM); - - pushed_words++; - } - else if (!push && (mask & (1 << PC_REGNUM))) - { - /* Catch popping the PC. */ - if (TARGET_INTERWORK || TARGET_BACKTRACE) - { - /* The PC is never poped directly, instead - it is popped into r3 and then BX is used. */ - fprintf (f, "}\n"); - - thumb_exit (f, -1, NULL_RTX); - - return; - } - else - { - if (mask & 0xFF) - fprintf (f, ", "); - - asm_fprintf (f, "%r", PC_REGNUM); - } - } - - fprintf (f, "}\n"); - - if (push && pushed_words && dwarf2out_do_frame ()) - { - char *l = dwarf2out_cfi_label (); - int pushed_mask = real_regs; - - *cfa_offset += pushed_words * 4; - dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); - - pushed_words = 0; - pushed_mask = real_regs; - for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) - { - if (pushed_mask & 1) - dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); - } - } -} void thumb_final_prescan_insn (rtx insn) @@ -11811,7 +13338,7 @@ thumb_shiftable_const (unsigned HOST_WIDE_INT val) if (val == 0) /* XXX */ return 0; - + for (i = 0; i < 25; i++) if ((val & (mask << i)) == val) return 1; @@ -11821,14 +13348,14 @@ thumb_shiftable_const (unsigned HOST_WIDE_INT val) /* Returns nonzero if the current function contains, or might contain a far jump. */ -int -thumb_far_jump_used_p (int in_prologue) +static int +thumb_far_jump_used_p (void) { rtx insn; /* This test is only important for leaf functions. */ /* assert (!leaf_function_p ()); */ - + /* If we have already decided that far jumps may be used, do not bother checking again, and always return true even if it turns out that they are not being used. Once we have made @@ -11840,7 +13367,7 @@ thumb_far_jump_used_p (int in_prologue) /* If this function is not being called from the prologue/epilogue generation code then it must be being called from the INITIAL_ELIMINATION_OFFSET macro. */ - if (!in_prologue) + if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) { /* In this case we know that we are being asked about the elimination of the arg pointer register. If that register is not being used, @@ -11859,7 +13386,10 @@ thumb_far_jump_used_p (int in_prologue) A false negative will not result in bad code being generated, but it will result in a needless push and pop of the link register. We - hope that this does not occur too often. */ + hope that this does not occur too often. + + If we need doubleword stack alignment this could affect the other + elimination offsets so we can't risk getting it wrong. */ if (regs_ever_live [ARG_POINTER_REGNUM]) cfun->machine->arg_pointer_live = 1; else if (!cfun->machine->arg_pointer_live) @@ -11883,7 +13413,7 @@ thumb_far_jump_used_p (int in_prologue) return 1; } } - + return 0; } @@ -11891,14 +13421,13 @@ thumb_far_jump_used_p (int in_prologue) int is_called_in_ARM_mode (tree func) { - if (TREE_CODE (func) != FUNCTION_DECL) - abort (); + gcc_assert (TREE_CODE (func) == FUNCTION_DECL); - /* Ignore the problem about functions whoes address is taken. */ + /* Ignore the problem about functions whose address is taken. */ if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) return TRUE; -#ifdef ARM_PE +#ifdef ARM_PE return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; #else return FALSE; @@ -11910,11 +13439,10 @@ const char * thumb_unexpanded_epilogue (void) { int regno; - int live_regs_mask = 0; + unsigned long live_regs_mask = 0; int high_regs_pushed = 0; - int leaf_function = leaf_function_p (); int had_to_push_lr; - rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; + int size; if (return_used_this_function) return ""; @@ -11922,16 +13450,17 @@ thumb_unexpanded_epilogue (void) if (IS_NAKED (arm_current_func_type ())) return ""; - for (regno = 0; regno <= LAST_LO_REGNUM; regno++) - if (THUMB_REG_PUSHED_P (regno)) - live_regs_mask |= 1 << regno; + live_regs_mask = thumb_compute_save_reg_mask (); + high_regs_pushed = bit_count (live_regs_mask & 0x0f00); - for (regno = 8; regno < 13; regno++) - if (THUMB_REG_PUSHED_P (regno)) - high_regs_pushed++; + /* If we can deduce the registers used from the function's return value. + This is more reliable that examining regs_ever_live[] because that + will be set if the register is ever used in the function, not just if + the register is used to hold a return value. */ + size = arm_size_return_regs (); /* The prolog may have pushed some high registers to use as - work registers. eg the testsuite file: + work registers. e.g. the testsuite file: gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c compiles to produce: push {r4, r5, r6, r7, lr} @@ -11939,41 +13468,27 @@ thumb_unexpanded_epilogue (void) mov r6, r8 push {r6, r7} as part of the prolog. We have to undo that pushing here. */ - + if (high_regs_pushed) { - int mask = live_regs_mask; + unsigned long mask = live_regs_mask & 0xff; int next_hi_reg; - int size; - int mode; - -#ifdef RTX_CODE - /* If we can deduce the registers used from the function's return value. - This is more reliable that examining regs_ever_live[] because that - will be set if the register is ever used in the function, not just if - the register is used to hold a return value. */ - - if (current_function_return_rtx != 0) - mode = GET_MODE (current_function_return_rtx); - else -#endif - mode = DECL_MODE (DECL_RESULT (current_function_decl)); - size = GET_MODE_SIZE (mode); - - /* Unless we are returning a type of size > 12 register r3 is - available. */ - if (size < 13) + /* The available low registers depend on the size of the value we are + returning. */ + if (size <= 12) mask |= 1 << 3; + if (size <= 8) + mask |= 1 << 2; if (mask == 0) /* Oh dear! We have no low registers into which we can pop high registers! */ internal_error ("no low registers available for popping high registers"); - + for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) - if (THUMB_REG_PUSHED_P (next_hi_reg)) + if (live_regs_mask & (1 << next_hi_reg)) break; while (high_regs_pushed) @@ -12000,33 +13515,23 @@ thumb_unexpanded_epilogue (void) { asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, regno); - + for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) - if (THUMB_REG_PUSHED_P (next_hi_reg)) + if (live_regs_mask & (1 << next_hi_reg)) break; } } } + live_regs_mask &= ~0x0f00; } - had_to_push_lr = (live_regs_mask || !leaf_function - || thumb_far_jump_used_p (1)); - - if (TARGET_BACKTRACE - && ((live_regs_mask & 0xFF) == 0) - && regs_ever_live [LAST_ARG_REGNUM] != 0) - { - /* The stack backtrace structure creation code had to - push R7 in order to get a work register, so we pop - it now. */ - live_regs_mask |= (1 << LAST_LO_REGNUM); - } - + had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; + live_regs_mask &= 0xff; + if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) { - if (had_to_push_lr - && !is_called_in_ARM_mode (current_function_decl) - && !eh_ofs) + /* Pop the return address into the PC. */ + if (had_to_push_lr) live_regs_mask |= 1 << PC_REGNUM; /* Either no argument registers were pushed or a backtrace @@ -12035,43 +13540,54 @@ thumb_unexpanded_epilogue (void) if (live_regs_mask) thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, live_regs_mask); - - if (eh_ofs) - thumb_exit (asm_out_file, 2, eh_ofs); + /* We have either just popped the return address into the - PC or it is was kept in LR for the entire function or - it is still on the stack because we do not want to - return by doing a pop {pc}. */ - else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) - thumb_exit (asm_out_file, - (had_to_push_lr - && is_called_in_ARM_mode (current_function_decl)) ? - -1 : LR_REGNUM, NULL_RTX); + PC or it is was kept in LR for the entire function. */ + if (!had_to_push_lr) + thumb_exit (asm_out_file, LR_REGNUM); } else { /* Pop everything but the return address. */ - live_regs_mask &= ~(1 << PC_REGNUM); - if (live_regs_mask) thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, live_regs_mask); if (had_to_push_lr) - /* Get the return address into a temporary register. */ - thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, - 1 << LAST_ARG_REGNUM); - + { + if (size > 12) + { + /* We have no free low regs, so save one. */ + asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, + LAST_ARG_REGNUM); + } + + /* Get the return address into a temporary register. */ + thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, + 1 << LAST_ARG_REGNUM); + + if (size > 12) + { + /* Move the return address to lr. */ + asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, + LAST_ARG_REGNUM); + /* Restore the low register. */ + asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, + IP_REGNUM); + regno = LR_REGNUM; + } + else + regno = LAST_ARG_REGNUM; + } + else + regno = LR_REGNUM; + /* Remove the argument registers that were pushed onto the stack. */ asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", SP_REGNUM, SP_REGNUM, current_function_pretend_args_size); - - if (eh_ofs) - thumb_exit (asm_out_file, 2, eh_ofs); - else - thumb_exit (asm_out_file, - had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); + + thumb_exit (asm_out_file, regno); } return ""; @@ -12084,7 +13600,7 @@ arm_init_machine_status (void) struct machine_function *machine; machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); -#if ARM_FT_UNKNOWN != 0 +#if ARM_FT_UNKNOWN != 0 machine->func_type = ARM_FT_UNKNOWN; #endif return machine; @@ -12098,14 +13614,7 @@ arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) if (count != 0) return NULL_RTX; - if (TARGET_APCS_32) - return get_hard_reg_initial_val (Pmode, LR_REGNUM); - else - { - rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), - GEN_INT (RETURN_ADDR_MASK26)); - return get_func_hard_reg_initial_val (cfun, lr); - } + return get_hard_reg_initial_val (Pmode, LR_REGNUM); } /* Do anything needed before RTL is emitted for each function. */ @@ -12114,106 +13623,86 @@ arm_init_expanders (void) { /* Arrange to initialize and mark the machine per-function status. */ init_machine_status = arm_init_machine_status; -} - -HOST_WIDE_INT -thumb_get_frame_size (void) -{ - int regno; - int base_size = ROUND_UP_WORD (get_frame_size ()); - int count_regs = 0; - int entry_size = 0; - int leaf; - - if (! TARGET_THUMB) - abort (); + /* This is to stop the combine pass optimizing away the alignment + adjustment of va_arg. */ + /* ??? It is claimed that this should not be necessary. */ + if (cfun) + mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); +} - if (! TARGET_ATPCS) - return base_size; - /* We need to know if we are a leaf function. Unfortunately, it - is possible to be called after start_sequence has been called, - which causes get_insns to return the insns for the sequence, - not the function, which will cause leaf_function_p to return - the incorrect result. - - To work around this, we cache the computed frame size. This - works because we will only be calling RTL expanders that need - to know about leaf functions once reload has completed, and the - frame size cannot be changed after that time, so we can safely - use the cached value. */ +/* Like arm_compute_initial_elimination offset. Simpler because there + isn't an ABI specified frame pointer for Thumb. Instead, we set it + to point at the base of the local variables after static stack + space for a function has been allocated. */ - if (reload_completed) - return cfun->machine->frame_size; +HOST_WIDE_INT +thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) +{ + arm_stack_offsets *offsets; - leaf = leaf_function_p (); + offsets = arm_get_frame_offsets (); - /* A leaf function does not need any stack alignment if it has nothing - on the stack. */ - if (leaf && base_size == 0) + switch (from) { - cfun->machine->frame_size = 0; - return 0; - } - - /* We know that SP will be word aligned on entry, and we must - preserve that condition at any subroutine call. But those are - the only constraints. */ - - /* Space for variadic functions. */ - if (current_function_pretend_args_size) - entry_size += current_function_pretend_args_size; + case ARG_POINTER_REGNUM: + switch (to) + { + case STACK_POINTER_REGNUM: + return offsets->outgoing_args - offsets->saved_args; - /* Space for pushed lo registers. */ - for (regno = 0; regno <= LAST_LO_REGNUM; regno++) - if (THUMB_REG_PUSHED_P (regno)) - count_regs++; + case FRAME_POINTER_REGNUM: + return offsets->soft_frame - offsets->saved_args; - /* Space for backtrace structure. */ - if (TARGET_BACKTRACE) - { - if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0) - entry_size += 20; - else - entry_size += 16; - } + case ARM_HARD_FRAME_POINTER_REGNUM: + return offsets->saved_regs - offsets->saved_args; - if (count_regs || !leaf || thumb_far_jump_used_p (1)) - count_regs++; /* LR */ + case THUMB_HARD_FRAME_POINTER_REGNUM: + return offsets->locals_base - offsets->saved_args; - entry_size += count_regs * 4; - count_regs = 0; + default: + gcc_unreachable (); + } + break; - /* Space for pushed hi regs. */ - for (regno = 8; regno < 13; regno++) - if (THUMB_REG_PUSHED_P (regno)) - count_regs++; + case FRAME_POINTER_REGNUM: + switch (to) + { + case STACK_POINTER_REGNUM: + return offsets->outgoing_args - offsets->soft_frame; - entry_size += count_regs * 4; + case ARM_HARD_FRAME_POINTER_REGNUM: + return offsets->saved_regs - offsets->soft_frame; - if ((entry_size + base_size + current_function_outgoing_args_size) & 7) - base_size += 4; - if ((entry_size + base_size + current_function_outgoing_args_size) & 7) - abort (); + case THUMB_HARD_FRAME_POINTER_REGNUM: + return offsets->locals_base - offsets->soft_frame; - cfun->machine->frame_size = base_size; + default: + gcc_unreachable (); + } + break; - return base_size; + default: + gcc_unreachable (); + } } + /* Generate the rest of a function's prologue. */ void thumb_expand_prologue (void) { rtx insn, dwarf; - HOST_WIDE_INT amount = (thumb_get_frame_size () - + current_function_outgoing_args_size); + HOST_WIDE_INT amount; + arm_stack_offsets *offsets; unsigned long func_type; + int regno; + unsigned long live_regs_mask; func_type = arm_current_func_type (); - + /* Naked functions don't have prologues. */ if (IS_NAKED (func_type)) return; @@ -12224,16 +13713,20 @@ thumb_expand_prologue (void) return; } - if (frame_pointer_needed) - { - insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); - RTX_FRAME_RELATED_P (insn) = 1; - } + live_regs_mask = thumb_compute_save_reg_mask (); + /* Load the pic register before setting the frame pointer, + so we can use r7 as a temporary work register. */ + if (flag_pic && arm_pic_register != INVALID_REGNUM) + arm_load_pic_register (live_regs_mask); + + if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) + emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), + stack_pointer_rtx); + offsets = arm_get_frame_offsets (); + amount = offsets->outgoing_args - offsets->saved_regs; if (amount) { - amount = ROUND_UP_WORD (amount); - if (amount < 512) { insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, @@ -12242,7 +13735,6 @@ thumb_expand_prologue (void) } else { - int regno; rtx reg; /* The stack decrement is too big for an immediate value in a single @@ -12260,17 +13752,17 @@ thumb_expand_prologue (void) been pushed at the start of the prologue and so we can corrupt it now. */ for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) - if (THUMB_REG_PUSHED_P (regno) + if (live_regs_mask & (1 << regno) && !(frame_pointer_needed && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) break; if (regno > LAST_LO_REGNUM) /* Very unlikely. */ { - rtx spare = gen_rtx (REG, SImode, IP_REGNUM); + rtx spare = gen_rtx_REG (SImode, IP_REGNUM); /* Choose an arbitrary, non-argument low register. */ - reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); + reg = gen_rtx_REG (SImode, LAST_LO_REGNUM); /* Save it by copying it into a high, scratch register. */ emit_insn (gen_movsi (spare, reg)); @@ -12282,9 +13774,9 @@ thumb_expand_prologue (void) insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); RTX_FRAME_RELATED_P (insn) = 1; - dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, plus_constant (stack_pointer_rtx, - GEN_INT (- amount))); + -amount)); RTX_FRAME_RELATED_P (dwarf) = 1; REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, @@ -12292,7 +13784,7 @@ thumb_expand_prologue (void) /* Restore the low register's original value. */ emit_insn (gen_movsi (reg, spare)); - + /* Emit a USE of the restored scratch register, so that flow analysis will not consider the restore redundant. The register won't be used again in this function and isn't @@ -12301,16 +13793,16 @@ thumb_expand_prologue (void) } else { - reg = gen_rtx (REG, SImode, regno); + reg = gen_rtx_REG (SImode, regno); emit_insn (gen_movsi (reg, GEN_INT (- amount))); insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); RTX_FRAME_RELATED_P (insn) = 1; - dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, plus_constant (stack_pointer_rtx, - GEN_INT (- amount))); + -amount)); RTX_FRAME_RELATED_P (dwarf) = 1; REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, @@ -12318,46 +13810,90 @@ thumb_expand_prologue (void) } } } - - if (current_function_profile || TARGET_NO_SCHED_PRO) + + if (frame_pointer_needed) + { + amount = offsets->outgoing_args - offsets->locals_base; + + if (amount < 1024) + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, GEN_INT (amount))); + else + { + emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + stack_pointer_rtx)); + dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, + plus_constant (stack_pointer_rtx, amount)); + RTX_FRAME_RELATED_P (dwarf) = 1; + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, + REG_NOTES (insn)); + } + + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* If we are profiling, make sure no instructions are scheduled before + the call to mcount. Similarly if the user has requested no + scheduling in the prolog. Similarly if we want non-call exceptions + using the EABI unwinder, to prevent faulting instructions from being + swapped with a stack adjustment. */ + if (current_function_profile || !TARGET_SCHED_PROLOG + || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) emit_insn (gen_blockage ()); + + cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); + if (live_regs_mask & 0xff) + cfun->machine->lr_save_eliminated = 0; + + /* If the link register is being kept alive, with the return address in it, + then make sure that it does not get reused by the ce2 pass. */ + if (cfun->machine->lr_save_eliminated) + emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); } + void thumb_expand_epilogue (void) { - HOST_WIDE_INT amount = (thumb_get_frame_size () - + current_function_outgoing_args_size); + HOST_WIDE_INT amount; + arm_stack_offsets *offsets; int regno; /* Naked functions don't have prologues. */ if (IS_NAKED (arm_current_func_type ())) return; + offsets = arm_get_frame_offsets (); + amount = offsets->outgoing_args - offsets->saved_regs; + if (frame_pointer_needed) - emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); - else if (amount) { - amount = ROUND_UP_WORD (amount); - + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + amount = offsets->locals_base - offsets->saved_regs; + } + + if (amount) + { if (amount < 512) emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (amount))); else { /* r3 is always free in the epilogue. */ - rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM); + rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); emit_insn (gen_movsi (reg, GEN_INT (amount))); emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); } } - + /* Emit a USE (stack_pointer_rtx), so that the stack adjustment will not be deleted. */ emit_insn (gen_prologue_use (stack_pointer_rtx)); - if (current_function_profile || TARGET_NO_SCHED_PRO) + if (current_function_profile || !TARGET_SCHED_PROLOG) emit_insn (gen_blockage ()); /* Emit a clobber for each insn that will be restored in the epilogue, @@ -12373,8 +13909,9 @@ thumb_expand_epilogue (void) static void thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { - int live_regs_mask = 0; - int high_regs_pushed = 0; + unsigned long live_regs_mask = 0; + unsigned long l_mask; + unsigned high_regs_pushed = 0; int cfa_offset = 0; int regno; @@ -12385,12 +13922,11 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { const char * name; - if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) - abort (); - if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) - abort (); + gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); + gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) + == SYMBOL_REF); name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); - + /* Generate code sequence to switch us into Thumb mode. */ /* The .code 32 directive has already been emitted by ASM_DECLARE_FUNCTION_NAME. */ @@ -12403,29 +13939,34 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) is called from a Thumb encoded function elsewhere in the same file. Hence the definition of STUB_NAME here must agree with the definition in gas/config/tc-arm.c. */ - + #define STUB_NAME ".real_start_of" - + fprintf (f, "\t.code\t16\n"); #ifdef ARM_PE if (arm_dllexport_name_p (name)) name = arm_strip_name_encoding (name); -#endif +#endif asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); fprintf (f, "\t.thumb_func\n"); asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); } - + if (current_function_pretend_args_size) { + /* Output unwind directive for the stack adjustment. */ + if (ARM_EABI_UNWIND_TABLES) + fprintf (f, "\t.pad #%d\n", + current_function_pretend_args_size); + if (cfun->machine->uses_anonymous_args) { int num_pushes; - + fprintf (f, "\tpush\t{"); num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); - + for (regno = LAST_ARG_REGNUM + 1 - num_pushes; regno <= LAST_ARG_REGNUM; regno++) @@ -12435,7 +13976,7 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) fprintf (f, "}\n"); } else - asm_fprintf (f, "\tsub\t%r, %r, #%d\n", + asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, SP_REGNUM, current_function_pretend_args_size); @@ -12445,31 +13986,31 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (dwarf2out_do_frame ()) { char *l = dwarf2out_cfi_label (); + cfa_offset = cfa_offset + current_function_pretend_args_size; dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); } } - for (regno = 0; regno <= LAST_LO_REGNUM; regno++) - if (THUMB_REG_PUSHED_P (regno)) - live_regs_mask |= 1 << regno; - - if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1)) - live_regs_mask |= 1 << LR_REGNUM; + /* Get the registers we are going to push. */ + live_regs_mask = thumb_compute_save_reg_mask (); + /* Extract a mask of the ones we can give to the Thumb's push instruction. */ + l_mask = live_regs_mask & 0x40ff; + /* Then count how many other high registers will need to be pushed. */ + high_regs_pushed = bit_count (live_regs_mask & 0x0f00); if (TARGET_BACKTRACE) { - int offset; - int work_register = 0; - int wr; - + unsigned offset; + unsigned work_register; + /* We have been asked to create a stack backtrace structure. The code looks like this: - + 0 .align 2 0 func: 0 sub SP, #16 Reserve space for 4 registers. - 2 push {R7} Get a work register. + 2 push {R7} Push low registers. 4 add R7, SP, #20 Get the stack pointer before the push. 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). 8 mov R7, PC Get hold of the start of this code plus 12. @@ -12481,25 +14022,11 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 20 add R7, SP, #16 Point at the start of the backtrace structure. 22 mov FP, R7 Put this value into the frame pointer. */ - if ((live_regs_mask & 0xFF) == 0) - { - /* See if the a4 register is free. */ + work_register = thumb_find_work_register (live_regs_mask); - if (regs_ever_live [LAST_ARG_REGNUM] == 0) - work_register = LAST_ARG_REGNUM; - else /* We must push a register of our own. */ - live_regs_mask |= (1 << LAST_LO_REGNUM); - } + if (ARM_EABI_UNWIND_TABLES) + asm_fprintf (f, "\t.pad #16\n"); - if (work_register == 0) - { - /* Select a register from the list that will be pushed to - use as our work register. */ - for (work_register = (LAST_LO_REGNUM + 1); work_register--;) - if ((1 << work_register) & live_regs_mask) - break; - } - asm_fprintf (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", SP_REGNUM, SP_REGNUM); @@ -12507,26 +14034,28 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (dwarf2out_do_frame ()) { char *l = dwarf2out_cfi_label (); + cfa_offset = cfa_offset + 16; dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); } - if (live_regs_mask) - thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); - - for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) - if (wr & live_regs_mask) - offset += 4; - + if (l_mask) + { + thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); + offset = bit_count (l_mask) * UNITS_PER_WORD; + } + else + offset = 0; + asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, offset + 16 + current_function_pretend_args_size); - + asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, offset + 4); /* Make sure that the instruction fetching the PC is in the right place to calculate "start of backtrace creation code + 12". */ - if (live_regs_mask) + if (l_mask) { asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, @@ -12546,7 +14075,7 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, offset + 12); } - + asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, offset + 8); @@ -12555,67 +14084,68 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", ARM_HARD_FRAME_POINTER_REGNUM, work_register); } - else if (live_regs_mask) - thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); - - for (regno = 8; regno < 13; regno++) - if (THUMB_REG_PUSHED_P (regno)) - high_regs_pushed++; + /* Optimization: If we are not pushing any low registers but we are going + to push some high registers then delay our first push. This will just + be a push of LR and we can combine it with the push of the first high + register. */ + else if ((l_mask & 0xff) != 0 + || (high_regs_pushed == 0 && l_mask)) + thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); if (high_regs_pushed) { - int pushable_regs = 0; - int mask = live_regs_mask & 0xff; - int next_hi_reg; + unsigned pushable_regs; + unsigned next_hi_reg; for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) - if (THUMB_REG_PUSHED_P (next_hi_reg)) + if (live_regs_mask & (1 << next_hi_reg)) break; - pushable_regs = mask; + pushable_regs = l_mask & 0xff; if (pushable_regs == 0) - { - /* Desperation time -- this probably will never happen. */ - if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)) - asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); - mask = 1 << LAST_ARG_REGNUM; - } + pushable_regs = 1 << thumb_find_work_register (live_regs_mask); while (high_regs_pushed > 0) { - int real_regs_mask = 0; + unsigned long real_regs_mask = 0; - for (regno = LAST_LO_REGNUM; regno >= 0; regno--) + for (regno = LAST_LO_REGNUM; regno >= 0; regno --) { - if (mask & (1 << regno)) + if (pushable_regs & (1 << regno)) { asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); - - high_regs_pushed--; + + high_regs_pushed --; real_regs_mask |= (1 << next_hi_reg); - + if (high_regs_pushed) { - for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; - next_hi_reg--) - if (THUMB_REG_PUSHED_P (next_hi_reg)) + for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; + next_hi_reg --) + if (live_regs_mask & (1 << next_hi_reg)) break; } else { - mask &= ~((1 << regno) - 1); + pushable_regs &= ~((1 << regno) - 1); break; } } } - thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask); + /* If we had to find a work register and we have not yet + saved the LR then add it to the list of regs to push. */ + if (l_mask == (1 << LR_REGNUM)) + { + thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), + 1, &cfa_offset, + real_regs_mask | (1 << LR_REGNUM)); + l_mask = 0; + } + else + thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); } - - if (pushable_regs == 0 - && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))) - asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); } } @@ -12630,22 +14160,18 @@ thumb_load_double_from_address (rtx *operands) rtx offset; rtx arg1; rtx arg2; - - if (GET_CODE (operands[0]) != REG) - abort (); - - if (GET_CODE (operands[1]) != MEM) - abort (); + + gcc_assert (GET_CODE (operands[0]) == REG); + gcc_assert (GET_CODE (operands[1]) == MEM); /* Get the memory address. */ addr = XEXP (operands[1], 0); - + /* Work out how the memory address is computed. */ switch (GET_CODE (addr)) { case REG: - operands[2] = gen_rtx (MEM, SImode, - plus_constant (XEXP (operands[1], 0), 4)); + operands[2] = adjust_address (operands[1], SImode, 4); if (REGNO (operands[0]) == REGNO (addr)) { @@ -12658,27 +14184,25 @@ thumb_load_double_from_address (rtx *operands) output_asm_insn ("ldr\t%H0, %2", operands); } break; - + case CONST: /* Compute <address> + 4 for the high order load. */ - operands[2] = gen_rtx (MEM, SImode, - plus_constant (XEXP (operands[1], 0), 4)); - + operands[2] = adjust_address (operands[1], SImode, 4); + output_asm_insn ("ldr\t%0, %1", operands); output_asm_insn ("ldr\t%H0, %2", operands); break; - + case PLUS: arg1 = XEXP (addr, 0); arg2 = XEXP (addr, 1); - + if (CONSTANT_P (arg1)) base = arg2, offset = arg1; else base = arg1, offset = arg2; - - if (GET_CODE (base) != REG) - abort (); + + gcc_assert (GET_CODE (base) == REG); /* Catch the case of <address> = <reg> + <reg> */ if (GET_CODE (offset) == REG) @@ -12686,17 +14210,17 @@ thumb_load_double_from_address (rtx *operands) int reg_offset = REGNO (offset); int reg_base = REGNO (base); int reg_dest = REGNO (operands[0]); - + /* Add the base and offset registers together into the higher destination register. */ asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", reg_dest + 1, reg_base, reg_offset); - + /* Load the lower destination register from the address in the higher destination register. */ asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", reg_dest, reg_dest + 1); - + /* Load the higher destination register from its own address plus 4. */ asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", @@ -12705,9 +14229,8 @@ thumb_load_double_from_address (rtx *operands) else { /* Compute <address> + 4 for the high order load. */ - operands[2] = gen_rtx (MEM, SImode, - plus_constant (XEXP (operands[1], 0), 4)); - + operands[2] = adjust_address (operands[1], SImode, 4); + /* If the computed address is held in the low order register then load the high order register first, otherwise always load the low order register first. */ @@ -12727,18 +14250,16 @@ thumb_load_double_from_address (rtx *operands) case LABEL_REF: /* With no registers to worry about we can just load the value directly. */ - operands[2] = gen_rtx (MEM, SImode, - plus_constant (XEXP (operands[1], 0), 4)); - + operands[2] = adjust_address (operands[1], SImode, 4); + output_asm_insn ("ldr\t%H0, %2", operands); output_asm_insn ("ldr\t%0, %1", operands); break; - + default: - abort (); - break; + gcc_unreachable (); } - + return ""; } @@ -12779,21 +14300,52 @@ thumb_output_move_mem_multiple (int n, rtx *operands) operands[4] = operands[5]; operands[5] = tmp; } - + output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); break; default: - abort (); + gcc_unreachable (); + } + + return ""; +} + +/* Output a call-via instruction for thumb state. */ +const char * +thumb_call_via_reg (rtx reg) +{ + int regno = REGNO (reg); + rtx *labelp; + + gcc_assert (regno < LR_REGNUM); + + /* If we are in the normal text section we can use a single instance + per compilation unit. If we are doing function sections, then we need + an entry per section, since we can't rely on reachability. */ + if (in_section == text_section) + { + thumb_call_reg_needed = 1; + + if (thumb_call_via_label[regno] == NULL) + thumb_call_via_label[regno] = gen_label_rtx (); + labelp = thumb_call_via_label + regno; + } + else + { + if (cfun->machine->call_via[regno] == NULL) + cfun->machine->call_via[regno] = gen_label_rtx (); + labelp = cfun->machine->call_via + regno; } + output_asm_insn ("bl\t%a0", labelp); return ""; } /* Routines for generating rtl. */ void -thumb_expand_movstrqi (rtx *operands) +thumb_expand_movmemqi (rtx *operands) { rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); @@ -12805,90 +14357,54 @@ thumb_expand_movstrqi (rtx *operands) emit_insn (gen_movmem12b (out, in, out, in)); len -= 12; } - + if (len >= 8) { emit_insn (gen_movmem8b (out, in, out, in)); len -= 8; } - + if (len >= 4) { rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in))); - emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg)); + emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); + emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); len -= 4; offset += 4; } - + if (len >= 2) { rtx reg = gen_reg_rtx (HImode); - emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode, - plus_constant (in, offset)))); - emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)), + emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, + plus_constant (in, offset)))); + emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), reg)); len -= 2; offset += 2; } - + if (len) { rtx reg = gen_reg_rtx (QImode); - emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode, - plus_constant (in, offset)))); - emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)), + emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, + plus_constant (in, offset)))); + emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), reg)); } } -int -thumb_cmp_operand (rtx op, enum machine_mode mode) -{ - return ((GET_CODE (op) == CONST_INT - && INTVAL (op) < 256 - && INTVAL (op) >= 0) - || s_register_operand (op, mode)); -} - -int -thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT - && INTVAL (op) < 0 - && INTVAL (op) > -256); -} - -/* Return TRUE if a result can be stored in OP without clobbering the - condition code register. Prior to reload we only accept a - register. After reload we have to be able to handle memory as - well, since a pseudo may not get a hard reg and reload cannot - handle output-reloads on jump insns. - - We could possibly handle mem before reload as well, but that might - complicate things with the need to handle increment - side-effects. */ - -int -thumb_cbrch_target_operand (rtx op, enum machine_mode mode) -{ - return (s_register_operand (op, mode) - || ((reload_in_progress || reload_completed) - && memory_operand (op, mode))); -} - -/* Handle storing a half-word to memory during reload. */ void thumb_reload_out_hi (rtx *operands) { emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); } -/* Handle reading a half-word from memory during reload. */ +/* Handle reading a half-word from memory during reload. */ void thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) { - abort (); + gcc_unreachable (); } /* Return the length of a function name prefix @@ -12899,7 +14415,7 @@ arm_get_strip_length (int c) switch (c) { ARM_NAME_ENCODING_LENGTHS - default: return 0; + default: return 0; } } @@ -12909,7 +14425,7 @@ const char * arm_strip_name_encoding (const char *name) { int skip; - + while ((skip = arm_get_strip_length (* name))) name += skip; @@ -12937,6 +14453,31 @@ arm_asm_output_labelref (FILE *stream, const char *name) asm_fprintf (stream, "%U%s", name); } +static void +arm_file_end (void) +{ + int regno; + + if (! thumb_call_reg_needed) + return; + + switch_to_section (text_section); + asm_fprintf (asm_out_file, "\t.code 16\n"); + ASM_OUTPUT_ALIGN (asm_out_file, 1); + + for (regno = 0; regno < LR_REGNUM; regno++) + { + rtx label = thumb_call_via_label[regno]; + + if (label != 0) + { + targetm.asm_out.internal_label (asm_out_file, "L", + CODE_LABEL_NUMBER (label)); + asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); + } + } +} + rtx aof_pic_label; #ifdef AOF_ASSEMBLER @@ -12984,7 +14525,7 @@ aof_dump_pic_table (FILE *f) PIC_OFFSET_TABLE_REGNUM, PIC_OFFSET_TABLE_REGNUM); fputs ("|x$adcons|\n", f); - + for (chain = aof_pic_chain; chain; chain = chain->next) { fputs ("\tDCD\t", f); @@ -12995,25 +14536,56 @@ aof_dump_pic_table (FILE *f) int arm_text_section_count = 1; -char * -aof_text_section (void ) +/* A get_unnamed_section callback for switching to the text section. */ + +static void +aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) { - static char buf[100]; - sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", + fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY", arm_text_section_count++); if (flag_pic) - strcat (buf, ", PIC, REENTRANT"); - return buf; + fprintf (asm_out_file, ", PIC, REENTRANT"); + fprintf (asm_out_file, "\n"); } static int arm_data_section_count = 1; -char * -aof_data_section (void) +/* A get_unnamed_section callback for switching to the data section. */ + +static void +aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED) { - static char buf[100]; - sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); - return buf; + fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n", + arm_data_section_count++); +} + +/* Implement TARGET_ASM_INIT_SECTIONS. + + AOF Assembler syntax is a nightmare when it comes to areas, since once + we change from one area to another, we can't go back again. Instead, + we must create a new area with the same attributes and add the new output + to that. Unfortunately, there is nothing we can do here to guarantee that + two areas with the same attributes will be linked adjacently in the + resulting executable, so we have to be careful not to do pc-relative + addressing across such boundaries. */ + +static void +aof_asm_init_sections (void) +{ + text_section = get_unnamed_section (SECTION_CODE, + aof_output_text_section_asm_op, NULL); + data_section = get_unnamed_section (SECTION_WRITE, + aof_output_data_section_asm_op, NULL); + readonly_data_section = text_section; +} + +void +zero_init_section (void) +{ + static int zero_init_count = 1; + + fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++); + in_section = NULL; } /* The AOF assembler is religiously strict about declarations of @@ -13074,7 +14646,7 @@ aof_dump_imports (FILE *f) automagically. */ if (arm_main_function) { - text_section (); + switch_to_section (text_section); fputs ("\tIMPORT __main\n", f); fputs ("\tDCD __main\n", f); } @@ -13125,7 +14697,7 @@ aof_file_start (void) fputs ("__f5\tFN\t5\n", asm_out_file); fputs ("__f6\tFN\t6\n", asm_out_file); fputs ("__f7\tFN\t7\n", asm_out_file); - text_section (); + switch_to_section (text_section); } static void @@ -13133,67 +14705,12 @@ aof_file_end (void) { if (flag_pic) aof_dump_pic_table (asm_out_file); + arm_file_end (); aof_dump_imports (asm_out_file); fputs ("\tEND\n", asm_out_file); } #endif /* AOF_ASSEMBLER */ -#ifdef OBJECT_FORMAT_ELF -/* Switch to an arbitrary section NAME with attributes as specified - by FLAGS. ALIGN specifies any known alignment requirements for - the section; 0 if the default should be used. - - Differs from the default elf version only in the prefix character - used before the section type. */ - -static void -arm_elf_asm_named_section (const char *name, unsigned int flags) -{ - char flagchars[10], *f = flagchars; - - if (! named_section_first_declaration (name)) - { - fprintf (asm_out_file, "\t.section\t%s\n", name); - return; - } - - if (!(flags & SECTION_DEBUG)) - *f++ = 'a'; - if (flags & SECTION_WRITE) - *f++ = 'w'; - if (flags & SECTION_CODE) - *f++ = 'x'; - if (flags & SECTION_SMALL) - *f++ = 's'; - if (flags & SECTION_MERGE) - *f++ = 'M'; - if (flags & SECTION_STRINGS) - *f++ = 'S'; - if (flags & SECTION_TLS) - *f++ = 'T'; - *f = '\0'; - - fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars); - - if (!(flags & SECTION_NOTYPE)) - { - const char *type; - - if (flags & SECTION_BSS) - type = "nobits"; - else - type = "progbits"; - - fprintf (asm_out_file, ",%%%s", type); - - if (flags & SECTION_ENTSIZE) - fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE); - } - - putc ('\n', asm_out_file); -} -#endif - #ifndef ARM_PE /* Symbols in the text segment can be accessed without indirecting via the constant pool; it may take an extra binary operation, but this is still @@ -13207,21 +14724,22 @@ arm_encode_section_info (tree decl, rtx rtl, int first) /* This doesn't work with AOF syntax, since the string table may be in a different AREA. */ #ifndef AOF_ASSEMBLER - if (optimize > 0 && TREE_CONSTANT (decl) - && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) + if (optimize > 0 && TREE_CONSTANT (decl)) SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; #endif /* If we are referencing a function that is weak then encode a long call flag in the function name, otherwise if the function is static or or known to be defined in this file then encode a short call flag. */ - if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd') + if (first && DECL_P (decl)) { if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); else if (! TREE_PUBLIC (decl)) arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); } + + default_encode_section_info (decl, rtl, first); } #endif /* !ARM_PE */ @@ -13247,6 +14765,7 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, { static int thunk_label = 0; char label[256]; + char labelpc[256]; int mi_delta = delta; const char *const mi_op = mi_delta < 0 ? "sub" : "add"; int shift = 0; @@ -13261,6 +14780,23 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, fputs ("\tldr\tr12, ", file); assemble_name (file, label); fputc ('\n', file); + if (flag_pic) + { + /* If we are generating PIC, the ldr instruction below loads + "(target - 7) - .LTHUNKPCn" into r12. The pc reads as + the address of the add + 8, so we have: + + r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) + = target + 1. + + Note that we have "+ 1" because some versions of GNU ld + don't set the low bit of the result for R_ARM_REL32 + relocations against thumb function symbols. */ + ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); + assemble_name (file, labelpc); + fputs (":\n", file); + fputs ("\tadd\tr12, pc, r12\n", file); + } } while (mi_delta != 0) { @@ -13281,7 +14817,20 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, ASM_OUTPUT_ALIGN (file, 2); assemble_name (file, label); fputs (":\n", file); - assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); + if (flag_pic) + { + /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ + rtx tem = XEXP (DECL_RTL (function), 0); + tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); + tem = gen_rtx_MINUS (GET_MODE (tem), + tem, + gen_rtx_SYMBOL_REF (Pmode, + ggc_strdup (labelpc))); + assemble_integer (tem, 4, BITS_PER_WORD, 1); + } + else + /* Output ".word .LTHUNKn". */ + assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); } else { @@ -13299,15 +14848,14 @@ arm_emit_vector_const (FILE *file, rtx x) int i; const char * pattern; - if (GET_CODE (x) != CONST_VECTOR) - abort (); + gcc_assert (GET_CODE (x) == CONST_VECTOR); switch (GET_MODE (x)) { case V2SImode: pattern = "%08x"; break; case V4HImode: pattern = "%04x"; break; case V8QImode: pattern = "%02x"; break; - default: abort (); + default: gcc_unreachable (); } fprintf (file, "0x"); @@ -13329,15 +14877,15 @@ arm_output_load_gr (rtx *operands) rtx offset; rtx wcgr; rtx sum; - + if (GET_CODE (operands [1]) != MEM || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS || GET_CODE (reg = XEXP (sum, 0)) != REG || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) return "wldrw%?\t%0, %1"; - - /* Fix up an out-of-range load of a GR register. */ + + /* Fix up an out-of-range load of a GR register. */ output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); wcgr = operands[0]; operands[0] = reg; @@ -13350,3 +14898,740 @@ arm_output_load_gr (rtx *operands) return ""; } + +/* Worker function for TARGET_SETUP_INCOMING_VARARGS. + + On the ARM, PRETEND_SIZE is set in order to have the prologue push the last + named arg and all anonymous args onto the stack. + XXX I know the prologue shouldn't be pushing registers, but it is faster + that way. */ + +static void +arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type ATTRIBUTE_UNUSED, + int *pretend_size, + int second_time ATTRIBUTE_UNUSED) +{ + cfun->machine->uses_anonymous_args = 1; + if (cum->nregs < NUM_ARG_REGS) + *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD; +} + +/* Return nonzero if the CONSUMER instruction (a store) does not need + PRODUCER's value to calculate the address. */ + +int +arm_no_early_store_addr_dep (rtx producer, rtx consumer) +{ + rtx value = PATTERN (producer); + rtx addr = PATTERN (consumer); + + if (GET_CODE (value) == COND_EXEC) + value = COND_EXEC_CODE (value); + if (GET_CODE (value) == PARALLEL) + value = XVECEXP (value, 0, 0); + value = XEXP (value, 0); + if (GET_CODE (addr) == COND_EXEC) + addr = COND_EXEC_CODE (addr); + if (GET_CODE (addr) == PARALLEL) + addr = XVECEXP (addr, 0, 0); + addr = XEXP (addr, 0); + + return !reg_overlap_mentioned_p (value, addr); +} + +/* Return nonzero if the CONSUMER instruction (an ALU op) does not + have an early register shift value or amount dependency on the + result of PRODUCER. */ + +int +arm_no_early_alu_shift_dep (rtx producer, rtx consumer) +{ + rtx value = PATTERN (producer); + rtx op = PATTERN (consumer); + rtx early_op; + + if (GET_CODE (value) == COND_EXEC) + value = COND_EXEC_CODE (value); + if (GET_CODE (value) == PARALLEL) + value = XVECEXP (value, 0, 0); + value = XEXP (value, 0); + if (GET_CODE (op) == COND_EXEC) + op = COND_EXEC_CODE (op); + if (GET_CODE (op) == PARALLEL) + op = XVECEXP (op, 0, 0); + op = XEXP (op, 1); + + early_op = XEXP (op, 0); + /* This is either an actual independent shift, or a shift applied to + the first operand of another operation. We want the whole shift + operation. */ + if (GET_CODE (early_op) == REG) + early_op = op; + + return !reg_overlap_mentioned_p (value, early_op); +} + +/* Return nonzero if the CONSUMER instruction (an ALU op) does not + have an early register shift value dependency on the result of + PRODUCER. */ + +int +arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) +{ + rtx value = PATTERN (producer); + rtx op = PATTERN (consumer); + rtx early_op; + + if (GET_CODE (value) == COND_EXEC) + value = COND_EXEC_CODE (value); + if (GET_CODE (value) == PARALLEL) + value = XVECEXP (value, 0, 0); + value = XEXP (value, 0); + if (GET_CODE (op) == COND_EXEC) + op = COND_EXEC_CODE (op); + if (GET_CODE (op) == PARALLEL) + op = XVECEXP (op, 0, 0); + op = XEXP (op, 1); + + early_op = XEXP (op, 0); + + /* This is either an actual independent shift, or a shift applied to + the first operand of another operation. We want the value being + shifted, in either case. */ + if (GET_CODE (early_op) != REG) + early_op = XEXP (early_op, 0); + + return !reg_overlap_mentioned_p (value, early_op); +} + +/* Return nonzero if the CONSUMER (a mul or mac op) does not + have an early register mult dependency on the result of + PRODUCER. */ + +int +arm_no_early_mul_dep (rtx producer, rtx consumer) +{ + rtx value = PATTERN (producer); + rtx op = PATTERN (consumer); + + if (GET_CODE (value) == COND_EXEC) + value = COND_EXEC_CODE (value); + if (GET_CODE (value) == PARALLEL) + value = XVECEXP (value, 0, 0); + value = XEXP (value, 0); + if (GET_CODE (op) == COND_EXEC) + op = COND_EXEC_CODE (op); + if (GET_CODE (op) == PARALLEL) + op = XVECEXP (op, 0, 0); + op = XEXP (op, 1); + + return (GET_CODE (op) == PLUS + && !reg_overlap_mentioned_p (value, XEXP (op, 0))); +} + + +/* We can't rely on the caller doing the proper promotion when + using APCS or ATPCS. */ + +static bool +arm_promote_prototypes (tree t ATTRIBUTE_UNUSED) +{ + return !TARGET_AAPCS_BASED; +} + + +/* AAPCS based ABIs use short enums by default. */ + +static bool +arm_default_short_enums (void) +{ + return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; +} + + +/* AAPCS requires that anonymous bitfields affect structure alignment. */ + +static bool +arm_align_anon_bitfield (void) +{ + return TARGET_AAPCS_BASED; +} + + +/* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ + +static tree +arm_cxx_guard_type (void) +{ + return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; +} + + +/* The EABI says test the least significant bit of a guard variable. */ + +static bool +arm_cxx_guard_mask_bit (void) +{ + return TARGET_AAPCS_BASED; +} + + +/* The EABI specifies that all array cookies are 8 bytes long. */ + +static tree +arm_get_cookie_size (tree type) +{ + tree size; + + if (!TARGET_AAPCS_BASED) + return default_cxx_get_cookie_size (type); + + size = build_int_cst (sizetype, 8); + return size; +} + + +/* The EABI says that array cookies should also contain the element size. */ + +static bool +arm_cookie_has_size (void) +{ + return TARGET_AAPCS_BASED; +} + + +/* The EABI says constructors and destructors should return a pointer to + the object constructed/destroyed. */ + +static bool +arm_cxx_cdtor_returns_this (void) +{ + return TARGET_AAPCS_BASED; +} + +/* The EABI says that an inline function may never be the key + method. */ + +static bool +arm_cxx_key_method_may_be_inline (void) +{ + return !TARGET_AAPCS_BASED; +} + +static void +arm_cxx_determine_class_data_visibility (tree decl) +{ + if (!TARGET_AAPCS_BASED) + return; + + /* In general, \S 3.2.5.5 of the ARM EABI requires that class data + is exported. However, on systems without dynamic vague linkage, + \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ + if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) + DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; + else + DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; + DECL_VISIBILITY_SPECIFIED (decl) = 1; +} + +static bool +arm_cxx_class_data_always_comdat (void) +{ + /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have + vague linkage if the class has no key function. */ + return !TARGET_AAPCS_BASED; +} + + +/* The EABI says __aeabi_atexit should be used to register static + destructors. */ + +static bool +arm_cxx_use_aeabi_atexit (void) +{ + return TARGET_AAPCS_BASED; +} + + +void +arm_set_return_address (rtx source, rtx scratch) +{ + arm_stack_offsets *offsets; + HOST_WIDE_INT delta; + rtx addr; + unsigned long saved_regs; + + saved_regs = arm_compute_save_reg_mask (); + + if ((saved_regs & (1 << LR_REGNUM)) == 0) + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); + else + { + if (frame_pointer_needed) + addr = plus_constant(hard_frame_pointer_rtx, -4); + else + { + /* LR will be the first saved register. */ + offsets = arm_get_frame_offsets (); + delta = offsets->outgoing_args - (offsets->frame + 4); + + + if (delta >= 4096) + { + emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, + GEN_INT (delta & ~4095))); + addr = scratch; + delta &= 4095; + } + else + addr = stack_pointer_rtx; + + addr = plus_constant (addr, delta); + } + emit_move_insn (gen_frame_mem (Pmode, addr), source); + } +} + + +void +thumb_set_return_address (rtx source, rtx scratch) +{ + arm_stack_offsets *offsets; + HOST_WIDE_INT delta; + int reg; + rtx addr; + unsigned long mask; + + emit_insn (gen_rtx_USE (VOIDmode, source)); + + mask = thumb_compute_save_reg_mask (); + if (mask & (1 << LR_REGNUM)) + { + offsets = arm_get_frame_offsets (); + + /* Find the saved regs. */ + if (frame_pointer_needed) + { + delta = offsets->soft_frame - offsets->saved_args; + reg = THUMB_HARD_FRAME_POINTER_REGNUM; + } + else + { + delta = offsets->outgoing_args - offsets->saved_args; + reg = SP_REGNUM; + } + /* Allow for the stack frame. */ + if (TARGET_BACKTRACE) + delta -= 16; + /* The link register is always the first saved register. */ + delta -= 4; + + /* Construct the address. */ + addr = gen_rtx_REG (SImode, reg); + if ((reg != SP_REGNUM && delta >= 128) + || delta >= 1024) + { + emit_insn (gen_movsi (scratch, GEN_INT (delta))); + emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); + addr = scratch; + } + else + addr = plus_constant (addr, delta); + + emit_move_insn (gen_frame_mem (Pmode, addr), source); + } + else + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); +} + +/* Implements target hook vector_mode_supported_p. */ +bool +arm_vector_mode_supported_p (enum machine_mode mode) +{ + if ((mode == V2SImode) + || (mode == V4HImode) + || (mode == V8QImode)) + return true; + + return false; +} + +/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal + ARM insns and therefore guarantee that the shift count is modulo 256. + DImode shifts (those implemented by lib1funcs.asm or by optabs.c) + guarantee no particular behavior for out-of-range counts. */ + +static unsigned HOST_WIDE_INT +arm_shift_truncation_mask (enum machine_mode mode) +{ + return mode == SImode ? 255 : 0; +} + + +/* Map internal gcc register numbers to DWARF2 register numbers. */ + +unsigned int +arm_dbx_register_number (unsigned int regno) +{ + if (regno < 16) + return regno; + + /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards + compatibility. The EABI defines them as registers 96-103. */ + if (IS_FPA_REGNUM (regno)) + return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; + + if (IS_VFP_REGNUM (regno)) + return 64 + regno - FIRST_VFP_REGNUM; + + if (IS_IWMMXT_GR_REGNUM (regno)) + return 104 + regno - FIRST_IWMMXT_GR_REGNUM; + + if (IS_IWMMXT_REGNUM (regno)) + return 112 + regno - FIRST_IWMMXT_REGNUM; + + gcc_unreachable (); +} + + +#ifdef TARGET_UNWIND_INFO +/* Emit unwind directives for a store-multiple instruction. This should + only ever be generated by the function prologue code, so we expect it + to have a particular form. */ + +static void +arm_unwind_emit_stm (FILE * asm_out_file, rtx p) +{ + int i; + HOST_WIDE_INT offset; + HOST_WIDE_INT nregs; + int reg_size; + unsigned reg; + unsigned lastreg; + rtx e; + + /* First insn will adjust the stack pointer. */ + e = XVECEXP (p, 0, 0); + if (GET_CODE (e) != SET + || GET_CODE (XEXP (e, 0)) != REG + || REGNO (XEXP (e, 0)) != SP_REGNUM + || GET_CODE (XEXP (e, 1)) != PLUS) + abort (); + + offset = -INTVAL (XEXP (XEXP (e, 1), 1)); + nregs = XVECLEN (p, 0) - 1; + + reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); + if (reg < 16) + { + /* The function prologue may also push pc, but not annotate it as it is + never restored. We turn this into a stack pointer adjustment. */ + if (nregs * 4 == offset - 4) + { + fprintf (asm_out_file, "\t.pad #4\n"); + offset -= 4; + } + reg_size = 4; + } + else if (IS_VFP_REGNUM (reg)) + { + /* FPA register saves use an additional word. */ + offset -= 4; + reg_size = 8; + } + else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) + { + /* FPA registers are done differently. */ + asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); + return; + } + else + /* Unknown register type. */ + abort (); + + /* If the stack increment doesn't match the size of the saved registers, + something has gone horribly wrong. */ + if (offset != nregs * reg_size) + abort (); + + fprintf (asm_out_file, "\t.save {"); + + offset = 0; + lastreg = 0; + /* The remaining insns will describe the stores. */ + for (i = 1; i <= nregs; i++) + { + /* Expect (set (mem <addr>) (reg)). + Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ + e = XVECEXP (p, 0, i); + if (GET_CODE (e) != SET + || GET_CODE (XEXP (e, 0)) != MEM + || GET_CODE (XEXP (e, 1)) != REG) + abort (); + + reg = REGNO (XEXP (e, 1)); + if (reg < lastreg) + abort (); + + if (i != 1) + fprintf (asm_out_file, ", "); + /* We can't use %r for vfp because we need to use the + double precision register names. */ + if (IS_VFP_REGNUM (reg)) + asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); + else + asm_fprintf (asm_out_file, "%r", reg); + +#ifdef ENABLE_CHECKING + /* Check that the addresses are consecutive. */ + e = XEXP (XEXP (e, 0), 0); + if (GET_CODE (e) == PLUS) + { + offset += reg_size; + if (GET_CODE (XEXP (e, 0)) != REG + || REGNO (XEXP (e, 0)) != SP_REGNUM + || GET_CODE (XEXP (e, 1)) != CONST_INT + || offset != INTVAL (XEXP (e, 1))) + abort (); + } + else if (i != 1 + || GET_CODE (e) != REG + || REGNO (e) != SP_REGNUM) + abort (); +#endif + } + fprintf (asm_out_file, "}\n"); +} + +/* Emit unwind directives for a SET. */ + +static void +arm_unwind_emit_set (FILE * asm_out_file, rtx p) +{ + rtx e0; + rtx e1; + + e0 = XEXP (p, 0); + e1 = XEXP (p, 1); + switch (GET_CODE (e0)) + { + case MEM: + /* Pushing a single register. */ + if (GET_CODE (XEXP (e0, 0)) != PRE_DEC + || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG + || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) + abort (); + + asm_fprintf (asm_out_file, "\t.save "); + if (IS_VFP_REGNUM (REGNO (e1))) + asm_fprintf(asm_out_file, "{d%d}\n", + (REGNO (e1) - FIRST_VFP_REGNUM) / 2); + else + asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); + break; + + case REG: + if (REGNO (e0) == SP_REGNUM) + { + /* A stack increment. */ + if (GET_CODE (e1) != PLUS + || GET_CODE (XEXP (e1, 0)) != REG + || REGNO (XEXP (e1, 0)) != SP_REGNUM + || GET_CODE (XEXP (e1, 1)) != CONST_INT) + abort (); + + asm_fprintf (asm_out_file, "\t.pad #%wd\n", + -INTVAL (XEXP (e1, 1))); + } + else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) + { + HOST_WIDE_INT offset; + unsigned reg; + + if (GET_CODE (e1) == PLUS) + { + if (GET_CODE (XEXP (e1, 0)) != REG + || GET_CODE (XEXP (e1, 1)) != CONST_INT) + abort (); + reg = REGNO (XEXP (e1, 0)); + offset = INTVAL (XEXP (e1, 1)); + asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", + HARD_FRAME_POINTER_REGNUM, reg, + INTVAL (XEXP (e1, 1))); + } + else if (GET_CODE (e1) == REG) + { + reg = REGNO (e1); + asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", + HARD_FRAME_POINTER_REGNUM, reg); + } + else + abort (); + } + else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) + { + /* Move from sp to reg. */ + asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); + } + else if (GET_CODE (e1) == PLUS + && GET_CODE (XEXP (e1, 0)) == REG + && REGNO (XEXP (e1, 0)) == SP_REGNUM + && GET_CODE (XEXP (e1, 1)) == CONST_INT) + { + /* Set reg to offset from sp. */ + asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", + REGNO (e0), (int)INTVAL(XEXP (e1, 1))); + } + else + abort (); + break; + + default: + abort (); + } +} + + +/* Emit unwind directives for the given insn. */ + +static void +arm_unwind_emit (FILE * asm_out_file, rtx insn) +{ + rtx pat; + + if (!ARM_EABI_UNWIND_TABLES) + return; + + if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) + return; + + pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); + if (pat) + pat = XEXP (pat, 0); + else + pat = PATTERN (insn); + + switch (GET_CODE (pat)) + { + case SET: + arm_unwind_emit_set (asm_out_file, pat); + break; + + case SEQUENCE: + /* Store multiple. */ + arm_unwind_emit_stm (asm_out_file, pat); + break; + + default: + abort(); + } +} + + +/* Output a reference from a function exception table to the type_info + object X. The EABI specifies that the symbol should be relocated by + an R_ARM_TARGET2 relocation. */ + +static bool +arm_output_ttype (rtx x) +{ + fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (GET_CODE (x) != CONST_INT) + fputs ("(TARGET2)", asm_out_file); + fputc ('\n', asm_out_file); + + return TRUE; +} +#endif /* TARGET_UNWIND_INFO */ + + +/* Output unwind directives for the start/end of a function. */ + +void +arm_output_fn_unwind (FILE * f, bool prologue) +{ + if (!ARM_EABI_UNWIND_TABLES) + return; + + if (prologue) + fputs ("\t.fnstart\n", f); + else + fputs ("\t.fnend\n", f); +} + +static bool +arm_emit_tls_decoration (FILE *fp, rtx x) +{ + enum tls_reloc reloc; + rtx val; + + val = XVECEXP (x, 0, 0); + reloc = INTVAL (XVECEXP (x, 0, 1)); + + output_addr_const (fp, val); + + switch (reloc) + { + case TLS_GD32: + fputs ("(tlsgd)", fp); + break; + case TLS_LDM32: + fputs ("(tlsldm)", fp); + break; + case TLS_LDO32: + fputs ("(tlsldo)", fp); + break; + case TLS_IE32: + fputs ("(gottpoff)", fp); + break; + case TLS_LE32: + fputs ("(tpoff)", fp); + break; + default: + gcc_unreachable (); + } + + switch (reloc) + { + case TLS_GD32: + case TLS_LDM32: + case TLS_IE32: + fputs (" + (. - ", fp); + output_addr_const (fp, XVECEXP (x, 0, 2)); + fputs (" - ", fp); + output_addr_const (fp, XVECEXP (x, 0, 3)); + fputc (')', fp); + break; + default: + break; + } + + return TRUE; +} + +bool +arm_output_addr_const_extra (FILE *fp, rtx x) +{ + if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) + return arm_emit_tls_decoration (fp, x); + else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) + { + char label[256]; + int labelno = INTVAL (XVECEXP (x, 0, 0)); + + ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); + assemble_name_raw (fp, label); + + return TRUE; + } + else if (GET_CODE (x) == CONST_VECTOR) + return arm_emit_vector_const (fp, x); + + return FALSE; +} + +#include "gt-arm.h" |