diff options
Diffstat (limited to 'contrib/gcc/config/s390/2084.md')
| -rw-r--r-- | contrib/gcc/config/s390/2084.md | 214 |
1 files changed, 131 insertions, 83 deletions
diff --git a/contrib/gcc/config/s390/2084.md b/contrib/gcc/config/s390/2084.md index a74ffbfdd468e..3a4479a293745 100644 --- a/contrib/gcc/config/s390/2084.md +++ b/contrib/gcc/config/s390/2084.md @@ -1,5 +1,5 @@ ;; Scheduling description for z990 (cpu 2084). -;; Copyright (C) 2003 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). @@ -17,8 +17,8 @@ ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING. If not, write to the Free -;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA -;; 02111-1307, USA. +;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +;; 02110-1301, USA. (define_automaton "x_ipu") @@ -61,151 +61,199 @@ ;; Simple insns ;; +(define_insn_reservation "x_int" 1 + (and (eq_attr "cpu" "z990,z9_109") + (and (eq_attr "type" "integer") + (eq_attr "atype" "reg"))) + "x-e1-st,x-wr-st") + +(define_insn_reservation "x_agen" 1 + (and (eq_attr "cpu" "z990,z9_109") + (and (eq_attr "type" "integer") + (eq_attr "atype" "agen"))) + "x-e1-st,x-wr-st") + (define_insn_reservation "x_lr" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "lr")) "x-e1-st,x-wr-st") (define_insn_reservation "x_la" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "la")) "x-e1-st,x-wr-st") (define_insn_reservation "x_larl" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "larl")) "x-e1-st,x-wr-st") (define_insn_reservation "x_load" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "load")) "x-e1-st+x-mem,x-wr-st") (define_insn_reservation "x_store" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "store")) "x-e1-st+x_store_tok,x-wr-st") (define_insn_reservation "x_branch" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "branch")) "x_e1_r,x_wr_r") (define_insn_reservation "x_call" 5 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "jsr")) - "x-e1-np*5,x-wr-np") + "x-e1-np*5,x-wr-np") + +(define_insn_reservation "x_mul_hi" 2 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "imulhi")) + "x-e1-np*2,x-wr-np") + +(define_insn_reservation "x_mul_sidi" 4 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "imulsi,imuldi")) + "x-e1-np*4,x-wr-np") + +(define_insn_reservation "x_div" 10 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "idiv")) + "x-e1-np*10,x-wr-np") + +(define_insn_reservation "x_sem" 17 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "sem")) + "x-e1-np+x-mem,x-e1-np*16,x-wr-st") ;; ;; Multicycle insns ;; -(define_insn_reservation "x_ss" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "op_type" "SS")) +(define_insn_reservation "x_cs" 1 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "cs")) "x-e1-np,x-wr-np") +(define_insn_reservation "x_vs" 1 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "vs")) + "x-e1-np*10,x-wr-np") + (define_insn_reservation "x_stm" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "stm")) "(x-e1-np+x_store_tok)*10,x-wr-np") (define_insn_reservation "x_lm" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "lm")) "x-e1-np*10,x-wr-np") -(define_insn_reservation "x_nn" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "op_type" "NN")) +(define_insn_reservation "x_other" 1 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "other")) "x-e1-np,x-wr-np") -(define_insn_reservation "x_o2" 2 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "o2")) - "x-e1-np*2,x-wr-np") - -(define_insn_reservation "x_o3" 3 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "o3")) - "x-e1-np*3,x-wr-np") - ;; ;; Floating point insns ;; -(define_insn_reservation "x_fsimpd" 6 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fsimpd,fmuld")) +(define_insn_reservation "x_fsimptf" 7 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fsimptf")) + "x_e1_t*2,x-wr-fp") + +(define_insn_reservation "x_fsimpdf" 6 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fsimpdf,fmuldf")) "x_e1_t,x-wr-fp") -(define_insn_reservation "x_fsimps" 6 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fsimps,fmuls")) +(define_insn_reservation "x_fsimpsf" 6 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fsimpsf,fmulsf")) "x_e1_t,x-wr-fp") -(define_insn_reservation "x_fdivd" 36 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fdivd")) + +(define_insn_reservation "x_fmultf" 33 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fmultf")) + "x_e1_t*27,x-wr-fp") + + +(define_insn_reservation "x_fdivtf" 82 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fdivtf,fsqrttf")) + "x_e1_t*76,x-wr-fp") + +(define_insn_reservation "x_fdivdf" 36 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fdivdf,fsqrtdf")) "x_e1_t*30,x-wr-fp") -(define_insn_reservation "x_fdivs" 36 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fdivs")) +(define_insn_reservation "x_fdivsf" 36 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fdivsf,fsqrtsf")) "x_e1_t*30,x-wr-fp") -(define_insn_reservation "x_floadd" 6 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "floadd")) + +(define_insn_reservation "x_floadtf" 6 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "floadtf")) + "x_e1_t,x-wr-fp") + +(define_insn_reservation "x_floaddf" 6 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "floaddf")) "x_e1_t,x-wr-fp") -(define_insn_reservation "x_floads" 6 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "floads")) +(define_insn_reservation "x_floadsf" 6 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "floadsf")) "x_e1_t,x-wr-fp") -(define_insn_reservation "x_fstored" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fstored")) + +(define_insn_reservation "x_fstoredf" 1 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fstoredf")) "x_e1_t,x-wr-fp") -(define_insn_reservation "x_fstores" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "type" "fstores")) +(define_insn_reservation "x_fstoresf" 1 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "fstoresf")) "x_e1_t,x-wr-fp") + +(define_insn_reservation "x_ftrunctf" 16 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "ftrunctf")) + "x_e1_t*10,x-wr-fp") + +(define_insn_reservation "x_ftruncdf" 11 + (and (eq_attr "cpu" "z990,z9_109") + (eq_attr "type" "ftruncdf")) + "x_e1_t*5,x-wr-fp") + + (define_insn_reservation "x_ftoi" 1 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "ftoi")) "x_e1_t*3,x-wr-fp") (define_insn_reservation "x_itof" 7 - (and (eq_attr "cpu" "z990") + (and (eq_attr "cpu" "z990,z9_109") (eq_attr "type" "itof")) "x_e1_t*3,x-wr-fp") -(define_bypass 1 "x_fsimpd" "x_fstored") +(define_bypass 1 "x_fsimpdf" "x_fstoredf") -(define_bypass 1 "x_fsimps" "x_fstores") +(define_bypass 1 "x_fsimpsf" "x_fstoresf") -(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd") +(define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") -(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads") - -;; -;; Insns still not mentioned are checked for -;; the usage of the agen unit -;; - -(define_insn_reservation "x_int" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "atype" "reg")) - "x-e1-st,x-wr-st") - -(define_insn_reservation "x_agen" 1 - (and (eq_attr "cpu" "z990") - (eq_attr "atype" "agen")) - "x-e1-st+x-mem,x-wr-st") +(define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") ;; ;; s390_agen_dep_p returns 1, if a register is set in the @@ -218,12 +266,12 @@ ;; (define_bypass 5 "x_int,x_agen,x_lr" - "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm" + "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" "s390_agen_dep_p") (define_bypass 9 "x_int,x_agen,x_lr" - "x_floadd, x_floads, x_fstored, x_fstores,\ - x_fsimpd, x_fsimps, x_fdivd, x_fdivs" + "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ + x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" "s390_agen_dep_p") ;; ;; A load type instruction uses a bypass to feed the result back @@ -231,12 +279,12 @@ ;; (define_bypass 4 "x_load" - "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm" + "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" "s390_agen_dep_p") (define_bypass 5 "x_load" - "x_floadd, x_floads, x_fstored, x_fstores,\ - x_fsimpd, x_fsimps, x_fdivd, x_fdivs" + "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ + x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" "s390_agen_dep_p") ;; @@ -245,12 +293,12 @@ ;; (define_bypass 3 "x_larl,x_la" - "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm" + "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" "s390_agen_dep_p") (define_bypass 5 "x_larl, x_la" - "x_floadd, x_floads, x_fstored, x_fstores,\ - x_fsimpd, x_fsimps, x_fdivd, x_fdivs" + "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ + x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" "s390_agen_dep_p") ;; |