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| -rw-r--r-- | docs/CodeGenerator.rst | 59 |
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diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index 106fc8456f616..bcdc722835665 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -2642,59 +2642,6 @@ to ensure valid register usage and operand types. The AMDGPU backend ------------------ -The AMDGPU code generator lives in the lib/Target/AMDGPU directory, and is an -open source native AMD GCN ISA code generator. - -Target triples supported -^^^^^^^^^^^^^^^^^^^^^^^^ - -The following are the known target triples that are supported by the AMDGPU -backend. - -* **amdgcn--** --- AMD GCN GPUs (AMDGPU.7.0.0+) -* **amdgcn--amdhsa** --- AMD GCN GPUs (AMDGPU.7.0.0+) with HSA support -* **r600--** --- AMD GPUs HD2XXX-HD6XXX - -Relocations -^^^^^^^^^^^ - -Supported relocatable fields are: - -* **word32** --- This specifies a 32-bit field occupying 4 bytes with arbitrary - byte alignment. These values use the same byte order as other word values in - the AMD GPU architecture -* **word64** --- This specifies a 64-bit field occupying 8 bytes with arbitrary - byte alignment. These values use the same byte order as other word values in - the AMD GPU architecture - -Following notations are used for specifying relocation calculations: - -* **A** --- Represents the addend used to compute the value of the relocatable - field -* **G** --- Represents the offset into the global offset table at which the - relocation entry’s symbol will reside during execution. -* **GOT** --- Represents the address of the global offset table. -* **P** --- Represents the place (section offset or address) of the storage unit - being relocated (computed using ``r_offset``) -* **S** --- Represents the value of the symbol whose index resides in the - relocation entry - -AMDGPU Backend generates *Elf64_Rela* relocation records with the following -supported relocation types: - - ========================== ===== ========== ============================== - Relocation type Value Field Calculation - ========================== ===== ========== ============================== - ``R_AMDGPU_NONE`` 0 ``none`` ``none`` - ``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF - ``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32 - ``R_AMDGPU_ABS64`` 3 ``word64`` S + A - ``R_AMDGPU_REL32`` 4 ``word32`` S + A - P - ``R_AMDGPU_REL64`` 5 ``word64`` S + A - P - ``R_AMDGPU_ABS32`` 6 ``word32`` S + A - ``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P - ``R_AMDGPU_GOTPCREL32_LO`` 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF - ``R_AMDGPU_GOTPCREL32_HI`` 9 ``word32`` (G + GOT + A - P) >> 32 - ``R_AMDGPU_REL32_LO`` 10 ``word32`` (S + A - P) & 0xFFFFFFFF - ``R_AMDGPU_REL32_HI`` 11 ``word32`` (S + A - P) >> 32 - ========================== ===== ========== ============================== +The AMDGPU code generator lives in the ``lib/Target/AMDGPU`` +directory. This code generator is capable of targeting a variety of +AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information. |