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-rw-r--r--include/llvm/CodeGen/DIE.h6
-rw-r--r--include/llvm/CodeGen/GlobalISel/InstructionSelector.h11
-rw-r--r--include/llvm/CodeGen/GlobalISel/Legalizer.h2
-rw-r--r--include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h33
-rw-r--r--include/llvm/CodeGen/GlobalISel/Utils.h15
-rw-r--r--include/llvm/CodeGen/LexicalScopes.h2
-rw-r--r--include/llvm/CodeGen/MachineBasicBlock.h3
-rw-r--r--include/llvm/CodeGen/MachineMemOperand.h5
-rw-r--r--include/llvm/CodeGen/MachineModuleInfoImpls.h27
-rw-r--r--include/llvm/CodeGen/MachineScheduler.h8
-rw-r--r--include/llvm/CodeGen/MacroFusion.h41
-rw-r--r--include/llvm/CodeGen/RegisterScavenging.h18
-rw-r--r--include/llvm/CodeGen/SelectionDAGAddressAnalysis.h64
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h2
14 files changed, 173 insertions, 64 deletions
diff --git a/include/llvm/CodeGen/DIE.h b/include/llvm/CodeGen/DIE.h
index 5ed5faa2c4150..f809fc97fe593 100644
--- a/include/llvm/CodeGen/DIE.h
+++ b/include/llvm/CodeGen/DIE.h
@@ -121,8 +121,8 @@ public:
/// Print the abbreviation using the specified asm printer.
void Emit(const AsmPrinter *AP) const;
- void print(raw_ostream &O);
- void dump();
+ void print(raw_ostream &O) const;
+ void dump() const;
};
//===--------------------------------------------------------------------===//
@@ -780,7 +780,7 @@ public:
DIEValue findAttribute(dwarf::Attribute Attribute) const;
void print(raw_ostream &O, unsigned IndentCount = 0) const;
- void dump();
+ void dump() const;
};
//===--------------------------------------------------------------------===//
diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
index 1a865c3f0dce7..b3ef7c2dc1859 100644
--- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
+++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
@@ -29,6 +29,7 @@ class MachineOperand;
class MachineRegisterInfo;
class RegisterBankInfo;
class TargetInstrInfo;
+class TargetRegisterClass;
class TargetRegisterInfo;
/// Container class for CodeGen predicate results.
@@ -79,6 +80,16 @@ protected:
InstructionSelector();
+ /// Constrain a register operand of an instruction \p I to a specified
+ /// register class. This could involve inserting COPYs before (for uses) or
+ /// after (for defs) and may replace the operand of \p I.
+ /// \returns whether operand regclass constraining succeeded.
+ bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
+ const TargetRegisterClass &RC,
+ const TargetInstrInfo &TII,
+ const TargetRegisterInfo &TRI,
+ const RegisterBankInfo &RBI) const;
+
/// Mutate the newly-selected instruction \p I to constrain its (possibly
/// generic) virtual register operands to the instruction's register class.
/// This could involve inserting COPYs before (for uses) or after (for defs).
diff --git a/include/llvm/CodeGen/GlobalISel/Legalizer.h b/include/llvm/CodeGen/GlobalISel/Legalizer.h
index bed7230cc013b..9b9b8b563a30e 100644
--- a/include/llvm/CodeGen/GlobalISel/Legalizer.h
+++ b/include/llvm/CodeGen/GlobalISel/Legalizer.h
@@ -59,7 +59,7 @@ public:
const TargetInstrInfo &TII);
bool combineMerges(MachineInstr &MI, MachineRegisterInfo &MRI,
- const TargetInstrInfo &TII);
+ const TargetInstrInfo &TII, MachineIRBuilder &MIRBuilder);
bool runOnMachineFunction(MachineFunction &MF) override;
};
diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 4e7b8350038b8..c9327d50432e1 100644
--- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -471,10 +471,12 @@ public:
/// Build and insert \p Res = IMPLICIT_DEF.
MachineInstrBuilder buildUndef(unsigned Dst);
- /// Build and insert \p Res<def> = G_SEQUENCE \p Op0, \p Idx0...
+ /// Build and insert instructions to put \p Ops together at the specified p
+ /// Indices to form a larger register.
///
- /// G_SEQUENCE inserts each element of Ops into an IMPLICIT_DEF register,
- /// where each entry starts at the bit-index specified by \p Indices.
+ /// If the types of the input registers are uniform and cover the entirity of
+ /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
+ /// followed by a sequence of G_INSERT instructions.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre The final element of the sequence must not extend past the end of the
@@ -482,11 +484,8 @@ public:
/// \pre The bits defined by each Op (derived from index and scalar size) must
/// not overlap.
/// \pre \p Indices must be in ascending order of bit position.
- ///
- /// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildSequence(unsigned Res,
- ArrayRef<unsigned> Ops,
- ArrayRef<uint64_t> Indices);
+ void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
+ ArrayRef<uint64_t> Indices);
/// Build and insert \p Res<def> = G_MERGE_VALUES \p Op0, ...
///
@@ -513,24 +512,6 @@ public:
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op);
- void addUsesWithIndices(MachineInstrBuilder MIB) {}
-
- template <typename... ArgTys>
- void addUsesWithIndices(MachineInstrBuilder MIB, unsigned Reg,
- unsigned BitIndex, ArgTys... Args) {
- MIB.addUse(Reg).addImm(BitIndex);
- addUsesWithIndices(MIB, Args...);
- }
-
- template <typename... ArgTys>
- MachineInstrBuilder buildSequence(unsigned Res, unsigned Op,
- unsigned Index, ArgTys... Args) {
- MachineInstrBuilder MIB =
- buildInstr(TargetOpcode::G_SEQUENCE).addDef(Res);
- addUsesWithIndices(MIB, Op, Index, Args...);
- return MIB;
- }
-
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
unsigned Op, unsigned Index);
diff --git a/include/llvm/CodeGen/GlobalISel/Utils.h b/include/llvm/CodeGen/GlobalISel/Utils.h
index 69d5070698082..50ddbeb9432a3 100644
--- a/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -29,13 +29,26 @@ class RegisterBankInfo;
class TargetInstrInfo;
class TargetPassConfig;
class TargetRegisterInfo;
+class TargetRegisterClass;
class Twine;
class ConstantFP;
+/// Try to constrain Reg to the specified register class. If this fails,
+/// create a new virtual register in the correct class and insert a COPY before
+/// \p InsertPt. The debug location of \p InsertPt is used for the new copy.
+///
+/// \return The virtual register constrained to the right register class.
+unsigned constrainRegToClass(MachineRegisterInfo &MRI,
+ const TargetInstrInfo &TII,
+ const RegisterBankInfo &RBI,
+ MachineInstr &InsertPt, unsigned Reg,
+ const TargetRegisterClass &RegClass);
+
/// Try to constrain Reg so that it is usable by argument OpIdx of the
/// provided MCInstrDesc \p II. If this fails, create a new virtual
/// register in the correct class and insert a COPY before \p InsertPt.
-/// The debug location of \p InsertPt is used for the new copy.
+/// This is equivalent to constrainRegToClass() with RegClass obtained from the
+/// MCInstrDesc. The debug location of \p InsertPt is used for the new copy.
///
/// \return The virtual register constrained to the right register class.
unsigned constrainOperandRegClass(const MachineFunction &MF,
diff --git a/include/llvm/CodeGen/LexicalScopes.h b/include/llvm/CodeGen/LexicalScopes.h
index 79fa12ec2fbbb..3ba503487823d 100644
--- a/include/llvm/CodeGen/LexicalScopes.h
+++ b/include/llvm/CodeGen/LexicalScopes.h
@@ -196,7 +196,7 @@ public:
}
/// dump - Print data structures to dbgs().
- void dump();
+ void dump() const;
/// getOrCreateAbstractScope - Find or create an abstract lexical scope.
LexicalScope *getOrCreateAbstractScope(const DILocalScope *Scope);
diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h
index 051908c40df71..97a49ce4dc4fa 100644
--- a/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/include/llvm/CodeGen/MachineBasicBlock.h
@@ -376,6 +376,9 @@ public:
/// Indicates if this is the entry block of a cleanup funclet.
void setIsCleanupFuncletEntry(bool V = true) { IsCleanupFuncletEntry = V; }
+ /// Returns true if it is legal to hoist instructions into this block.
+ bool isLegalToHoistInto() const;
+
// Code Layout methods.
/// Move 'this' block before or after the specified block. This only moves
diff --git a/include/llvm/CodeGen/MachineMemOperand.h b/include/llvm/CodeGen/MachineMemOperand.h
index 4d83f27eac3c3..78adce507b8cd 100644
--- a/include/llvm/CodeGen/MachineMemOperand.h
+++ b/include/llvm/CodeGen/MachineMemOperand.h
@@ -59,6 +59,11 @@ struct MachinePointerInfo {
return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O);
}
+ /// Return true if memory region [V, V+Offset+Size) is known to be
+ /// dereferenceable.
+ bool isDereferenceable(unsigned Size, LLVMContext &C,
+ const DataLayout &DL) const;
+
/// Return the LLVM IR address space number that this pointer points into.
unsigned getAddrSpace() const;
diff --git a/include/llvm/CodeGen/MachineModuleInfoImpls.h b/include/llvm/CodeGen/MachineModuleInfoImpls.h
index 61cff3890b75f..34b21ceddd434 100644
--- a/include/llvm/CodeGen/MachineModuleInfoImpls.h
+++ b/include/llvm/CodeGen/MachineModuleInfoImpls.h
@@ -77,33 +77,6 @@ public:
SymbolListTy GetGVStubList() { return getSortedStubs(GVStubs); }
};
-/// MachineModuleInfoWasm - This is a MachineModuleInfoImpl implementation
-/// for Wasm targets.
-class MachineModuleInfoWasm : public MachineModuleInfoImpl {
- /// WebAssembly global variables defined by CodeGen.
- std::vector<wasm::Global> Globals;
-
- /// The WebAssembly global variable which is the stack pointer.
- unsigned StackPointerGlobal;
-
- virtual void anchor(); // Out of line virtual method.
-public:
- MachineModuleInfoWasm(const MachineModuleInfo &)
- : StackPointerGlobal(-1U) {}
-
- void addGlobal(const wasm::Global &G) { Globals.push_back(G); }
- const std::vector<wasm::Global> &getGlobals() const { return Globals; }
-
- bool hasStackPointerGlobal() const {
- return StackPointerGlobal != -1U;
- }
- unsigned getStackPointerGlobal() const {
- assert(hasStackPointerGlobal() && "Stack ptr global hasn't been set");
- return StackPointerGlobal;
- }
- void setStackPointerGlobal(unsigned Global) { StackPointerGlobal = Global; }
-};
-
} // end namespace llvm
#endif
diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h
index 3b02ec400abac..34cbffa78203a 100644
--- a/include/llvm/CodeGen/MachineScheduler.h
+++ b/include/llvm/CodeGen/MachineScheduler.h
@@ -203,7 +203,7 @@ public:
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) {}
- virtual void dumpPolicy() {}
+ virtual void dumpPolicy() const {}
/// Check if pressure tracking is needed before building the DAG and
/// initializing this strategy. Called after initPolicy.
@@ -555,7 +555,7 @@ public:
return Queue.begin() + idx;
}
- void dump();
+ void dump() const;
};
/// Summarize the unscheduled region.
@@ -756,7 +756,7 @@ public:
SUnit *pickOnlyChoice();
#ifndef NDEBUG
- void dumpScheduledState();
+ void dumpScheduledState() const;
#endif
};
@@ -890,7 +890,7 @@ public:
MachineBasicBlock::iterator End,
unsigned NumRegionInstrs) override;
- void dumpPolicy() override;
+ void dumpPolicy() const override;
bool shouldTrackPressure() const override {
return RegionPolicy.ShouldTrackPressure;
diff --git a/include/llvm/CodeGen/MacroFusion.h b/include/llvm/CodeGen/MacroFusion.h
new file mode 100644
index 0000000000000..473784bc58412
--- /dev/null
+++ b/include/llvm/CodeGen/MacroFusion.h
@@ -0,0 +1,41 @@
+//===- MacroFusion.h - Macro Fusion ------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file contains the definition of the DAG scheduling mutation to
+/// pair instructions back to back.
+//
+//===----------------------------------------------------------------------===//
+
+#include <functional>
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineScheduler.h"
+
+namespace llvm {
+
+/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
+/// together. Given SecondMI, when FirstMI is unspecified, then check if
+/// SecondMI may be part of a fused pair at all.
+typedef std::function<bool(const TargetInstrInfo &TII,
+ const TargetSubtargetInfo &TSI,
+ const MachineInstr *FirstMI,
+ const MachineInstr &SecondMI)> ShouldSchedulePredTy;
+
+/// \brief Create a DAG scheduling mutation to pair instructions back to back
+/// for instructions that benefit according to the target-specific
+/// shouldScheduleAdjacent predicate function.
+std::unique_ptr<ScheduleDAGMutation>
+createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+
+/// \brief Create a DAG scheduling mutation to pair branch instructions with one
+/// of their predecessors back to back for instructions that benefit according
+/// to the target-specific shouldScheduleAdjacent predicate function.
+std::unique_ptr<ScheduleDAGMutation>
+createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
+
+} // end namespace llvm
diff --git a/include/llvm/CodeGen/RegisterScavenging.h b/include/llvm/CodeGen/RegisterScavenging.h
index ad1efe18c72d3..489c72b81a985 100644
--- a/include/llvm/CodeGen/RegisterScavenging.h
+++ b/include/llvm/CodeGen/RegisterScavenging.h
@@ -156,12 +156,24 @@ public:
/// available and do the appropriate bookkeeping. SPAdj is the stack
/// adjustment due to call frame, it's passed along to eliminateFrameIndex().
/// Returns the scavenged register.
+ /// This is deprecated as it depends on the quality of the kill flags being
+ /// present; Use scavengeRegisterBackwards() instead!
unsigned scavengeRegister(const TargetRegisterClass *RegClass,
MachineBasicBlock::iterator I, int SPAdj);
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
return scavengeRegister(RegClass, MBBI, SPAdj);
}
+ /// Make a register of the specific register class available from the current
+ /// position backwards to the place before \p To. If \p RestoreAfter is true
+ /// this includes the instruction following the current position.
+ /// SPAdj is the stack adjustment due to call frame, it's passed along to
+ /// eliminateFrameIndex().
+ /// Returns the scavenged register.
+ unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,
+ MachineBasicBlock::iterator To,
+ bool RestoreAfter, int SPAdj);
+
/// Tell the scavenger a register is used.
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
@@ -202,6 +214,12 @@ private:
/// Mark live-in registers of basic block as used.
void setLiveInsUsed(const MachineBasicBlock &MBB);
+
+ /// Spill a register after position \p After and reload it before position
+ /// \p UseMI.
+ ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
+ MachineBasicBlock::iterator After,
+ MachineBasicBlock::iterator &UseMI);
};
/// Replaces all frame index virtual registers with physical registers. Uses the
diff --git a/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h b/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
new file mode 100644
index 0000000000000..d82ab7d647e75
--- /dev/null
+++ b/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
@@ -0,0 +1,64 @@
+//===-- llvm/CodeGen/SelectionDAGAddressAnalysis.h ------- DAG Address Analysis
+//---*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+
+#ifndef LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
+#define LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
+
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+
+namespace llvm {
+/// Helper struct to parse and store a memory address as base + index + offset.
+/// We ignore sign extensions when it is safe to do so.
+/// The following two expressions are not equivalent. To differentiate we need
+/// to store whether there was a sign extension involved in the index
+/// computation.
+/// (load (i64 add (i64 copyfromreg %c)
+/// (i64 signextend (add (i8 load %index)
+/// (i8 1))))
+/// vs
+///
+/// (load (i64 add (i64 copyfromreg %c)
+/// (i64 signextend (i32 add (i32 signextend (i8 load %index))
+/// (i32 1)))))
+class BaseIndexOffset {
+private:
+ SDValue Base;
+ SDValue Index;
+ int64_t Offset;
+ bool IsIndexSignExt;
+
+public:
+ BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
+
+ BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
+ bool IsIndexSignExt)
+ : Base(Base), Index(Index), Offset(Offset),
+ IsIndexSignExt(IsIndexSignExt) {}
+
+ SDValue getBase() { return Base; }
+ SDValue getIndex() { return Index; }
+
+ bool equalBaseIndex(BaseIndexOffset &Other, const SelectionDAG &DAG) {
+ int64_t Off;
+ return equalBaseIndex(Other, DAG, Off);
+ }
+
+ bool equalBaseIndex(BaseIndexOffset &Other, const SelectionDAG &DAG,
+ int64_t &Off);
+
+ /// Parses tree in Ptr for base, index, offset addresses.
+ static BaseIndexOffset match(SDValue Ptr);
+};
+} // namespace llvm
+
+#endif
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 0cd26d35a4829..af418d3050e45 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -2107,7 +2107,7 @@ class MaskedGatherScatterSDNode : public MemSDNode {
public:
friend class SelectionDAG;
- MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
+ MaskedGatherScatterSDNode(unsigned NodeTy, unsigned Order,
const DebugLoc &dl, SDVTList VTs, EVT MemVT,
MachineMemOperand *MMO)
: MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-30 08:22:56 +0000