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-rw-r--r--include/llvm/CodeGen/ExpandReductions.h24
-rw-r--r--include/llvm/CodeGen/GlobalISel/LegalizerInfo.h17
-rw-r--r--include/llvm/CodeGen/GlobalISel/Utils.h3
-rw-r--r--include/llvm/CodeGen/ISDOpcodes.h21
-rw-r--r--include/llvm/CodeGen/MachineCombinerPattern.h2
-rw-r--r--include/llvm/CodeGen/Passes.h12
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h14
7 files changed, 83 insertions, 10 deletions
diff --git a/include/llvm/CodeGen/ExpandReductions.h b/include/llvm/CodeGen/ExpandReductions.h
new file mode 100644
index 0000000000000..c6aaaad967b38
--- /dev/null
+++ b/include/llvm/CodeGen/ExpandReductions.h
@@ -0,0 +1,24 @@
+//===----- ExpandReductions.h - Expand experimental reduction intrinsics --===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_EXPANDREDUCTIONS_H
+#define LLVM_CODEGEN_EXPANDREDUCTIONS_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class ExpandReductionsPass
+ : public PassInfoMixin<ExpandReductionsPass> {
+public:
+ PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_EXPANDREDUCTIONS_H
diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index 30d67eb499233..21354ae20ed14 100644
--- a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -145,7 +145,7 @@ public:
/// Iterate the given function (typically something like doubling the width)
/// on Ty until we find a legal type for this operation.
- LLT findLegalType(const InstrAspect &Aspect,
+ Optional<LLT> findLegalType(const InstrAspect &Aspect,
function_ref<LLT(LLT)> NextType) const {
LegalizeAction Action;
const TypeMap &Map = Actions[Aspect.Opcode - FirstOp][Aspect.Idx];
@@ -153,8 +153,12 @@ public:
do {
Ty = NextType(Ty);
auto ActionIt = Map.find(Ty);
- if (ActionIt == Map.end())
- Action = DefaultActions.find(Aspect.Opcode)->second;
+ if (ActionIt == Map.end()) {
+ auto DefaultIt = DefaultActions.find(Aspect.Opcode);
+ if (DefaultIt == DefaultActions.end())
+ return None;
+ Action = DefaultIt->second;
+ }
else
Action = ActionIt->second;
} while(Action != Legal);
@@ -163,11 +167,14 @@ public:
/// Find what type it's actually OK to perform the given operation on, given
/// the general approach we've decided to take.
- LLT findLegalType(const InstrAspect &Aspect, LegalizeAction Action) const;
+ Optional<LLT> findLegalType(const InstrAspect &Aspect, LegalizeAction Action) const;
std::pair<LegalizeAction, LLT> findLegalAction(const InstrAspect &Aspect,
LegalizeAction Action) const {
- return std::make_pair(Action, findLegalType(Aspect, Action));
+ auto LegalType = findLegalType(Aspect, Action);
+ if (!LegalType)
+ return std::make_pair(LegalizeAction::Unsupported, LLT());
+ return std::make_pair(Action, *LegalType);
}
/// Find the specified \p Aspect in the primary (explicitly set) Actions
diff --git a/include/llvm/CodeGen/GlobalISel/Utils.h b/include/llvm/CodeGen/GlobalISel/Utils.h
index 92bc9736141a1..69d5070698082 100644
--- a/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -30,6 +30,7 @@ class TargetInstrInfo;
class TargetPassConfig;
class TargetRegisterInfo;
class Twine;
+class ConstantFP;
/// Try to constrain Reg so that it is usable by argument OpIdx of the
/// provided MCInstrDesc \p II. If this fails, create a new virtual
@@ -62,6 +63,8 @@ void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
Optional<int64_t> getConstantVRegVal(unsigned VReg,
const MachineRegisterInfo &MRI);
+const ConstantFP* getConstantFPVRegVal(unsigned VReg,
+ const MachineRegisterInfo &MRI);
} // End namespace llvm.
#endif
diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h
index ca0f3fbad892a..f2a9a9f73ca6a 100644
--- a/include/llvm/CodeGen/ISDOpcodes.h
+++ b/include/llvm/CodeGen/ISDOpcodes.h
@@ -644,6 +644,13 @@ namespace ISD {
/// of a call sequence, and carry arbitrary information that target might
/// want to know. The first operand is a chain, the rest are specified by
/// the target and not touched by the DAG optimizers.
+ /// Targets that may use stack to pass call arguments define additional
+ /// operands:
+ /// - size of the call frame part that must be set up within the
+ /// CALLSEQ_START..CALLSEQ_END pair,
+ /// - part of the call frame prepared prior to CALLSEQ_START.
+ /// Both these parameters must be constants, their sum is the total call
+ /// frame size.
/// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
CALLSEQ_START, // Beginning of a call sequence
CALLSEQ_END, // End of a call sequence
@@ -783,6 +790,20 @@ namespace ISD {
/// known nonzero constant. The only operand here is the chain.
GET_DYNAMIC_AREA_OFFSET,
+ /// Generic reduction nodes. These nodes represent horizontal vector
+ /// reduction operations, producing a scalar result.
+ /// The STRICT variants perform reductions in sequential order. The first
+ /// operand is an initial scalar accumulator value, and the second operand
+ /// is the vector to reduce.
+ VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
+ /// These reductions are non-strict, and have a single vector operand.
+ VECREDUCE_FADD, VECREDUCE_FMUL,
+ VECREDUCE_ADD, VECREDUCE_MUL,
+ VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
+ VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
+ /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
+ VECREDUCE_FMAX, VECREDUCE_FMIN,
+
/// BUILTIN_OP_END - This must be the last enum value in this list.
/// The target-specific pre-isel opcode values start here.
BUILTIN_OP_END
diff --git a/include/llvm/CodeGen/MachineCombinerPattern.h b/include/llvm/CodeGen/MachineCombinerPattern.h
index 11238016d447b..8c54ae9254708 100644
--- a/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -48,6 +48,8 @@ enum class MachineCombinerPattern {
FMULADDD_OP2,
FMULSUBD_OP1,
FMULSUBD_OP2,
+ FNMULSUBS_OP1,
+ FNMULSUBD_OP1,
FMLAv1i32_indexed_OP1,
FMLAv1i32_indexed_OP2,
FMLAv1i64_indexed_OP1,
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 42299b5294108..8a5a1997386f2 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -68,6 +68,10 @@ namespace llvm {
/// matching during instruction selection.
FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
+ /// createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather
+ /// and scatter intrinsics with scalar code when target doesn't support them.
+ FunctionPass *createScalarizeMaskedMemIntrinPass();
+
/// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
/// load-linked/store-conditional loops.
extern char &AtomicExpandID;
@@ -129,6 +133,10 @@ namespace llvm {
// instruction and update the MachineFunctionInfo with that information.
extern char &ShrinkWrapID;
+ /// LiveRangeShrink pass. Move instruction close to its definition to shrink
+ /// the definition's live range.
+ extern char &LiveRangeShrinkID;
+
/// Greedy register allocator.
extern char &RAGreedyID;
@@ -405,6 +413,10 @@ namespace llvm {
/// printing assembly.
ModulePass *createMachineOutlinerPass();
+ /// This pass expands the experimental reduction intrinsics into sequences of
+ /// shuffles.
+ FunctionPass *createExpandReductionsPass();
+
} // End llvm namespace
/// Target machine pass initializer for passes with dependencies. Use with
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 9e1d148c7ce50..d761661f763ea 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -406,7 +406,7 @@ public:
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
- void Combine(CombineLevel Level, AliasAnalysis &AA,
+ void Combine(CombineLevel Level, AliasAnalysis *AA,
CodeGenOpt::Level OptLevel);
/// This transforms the SelectionDAG into a SelectionDAG that
@@ -737,11 +737,15 @@ public:
/// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
- /// Return a new CALLSEQ_START node, which always must have a glue result
- /// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful SDLoc.
- SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {
+ /// Return a new CALLSEQ_START node, that starts new call frame, in which
+ /// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and
+ /// OutSize specifies part of the frame set up prior to the sequence.
+ SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize,
+ const SDLoc &DL) {
SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
- SDValue Ops[] = { Chain, Op };
+ SDValue Ops[] = { Chain,
+ getIntPtrConstant(InSize, DL, true),
+ getIntPtrConstant(OutSize, DL, true) };
return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-25 06:00:07 +0000