diff options
Diffstat (limited to 'include/llvm/CodeGen')
18 files changed, 244 insertions, 169 deletions
diff --git a/include/llvm/CodeGen/BasicTTIImpl.h b/include/llvm/CodeGen/BasicTTIImpl.h index 5eb7a0f61eec4..a740df96899df 100644 --- a/include/llvm/CodeGen/BasicTTIImpl.h +++ b/include/llvm/CodeGen/BasicTTIImpl.h @@ -277,7 +277,8 @@ public: unsigned getInliningThresholdMultiplier() { return 1; } - void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP) { + void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, + TTI::UnrollingPreferences &UP) { // This unrolling functionality is target independent, but to provide some // motivation for its intended use, for x86: diff --git a/include/llvm/CodeGen/GlobalISel/CallLowering.h b/include/llvm/CodeGen/GlobalISel/CallLowering.h index 3e9a9d514cb87..e7ce1946889e3 100644 --- a/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering --*- C++ -*-===// +//===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -15,21 +15,31 @@ #ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H #define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H -#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/ValueTypes.h" -#include "llvm/IR/Function.h" +#include "llvm/CodeGen/MachineValueType.h" +#include "llvm/IR/CallSite.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetCallingConv.h" +#include <cstdint> +#include <functional> namespace llvm { -// Forward declarations. + +class DataLayout; +class Function; class MachineIRBuilder; class MachineOperand; +struct MachinePointerInfo; +class MachineRegisterInfo; class TargetLowering; +class Type; class Value; class CallLowering { const TargetLowering *TLI; + public: struct ArgInfo { unsigned Reg; @@ -49,6 +59,12 @@ public: /// arugment should go, exactly what happens can vary slightly. This /// class abstracts the differences. struct ValueHandler { + ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, + CCAssignFn *AssignFn) + : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {} + + virtual ~ValueHandler() = default; + /// Materialize a VReg containing the address of the specified /// stack-based object. This is either based on a FrameIndex or /// direct SP manipulation, depending on the context. \p MPO @@ -89,12 +105,6 @@ public: return AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); } - ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - CCAssignFn *AssignFn) - : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {} - - virtual ~ValueHandler() {} - MachineIRBuilder &MIRBuilder; MachineRegisterInfo &MRI; CCAssignFn *AssignFn; @@ -112,7 +122,6 @@ protected: return static_cast<const XXXTargetLowering *>(TLI); } - template <typename FuncInfoTy> void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL, const FuncInfoTy &FuncInfo) const; @@ -126,7 +135,7 @@ protected: public: CallLowering(const TargetLowering *TLI) : TLI(TLI) {} - virtual ~CallLowering() {} + virtual ~CallLowering() = default; /// This hook must be implemented to lower outgoing return values, described /// by \p Val, into the specified virtual register \p VReg. @@ -200,6 +209,7 @@ public: unsigned ResReg, ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const; }; -} // End namespace llvm. -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h index e292e8913db06..7061c014d9b7f 100644 --- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ---*- C++ -*-===// +//===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -19,24 +19,33 @@ #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H -#include "Types.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Types.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/IR/Intrinsics.h" +#include <memory> +#include <utility> namespace llvm { -// Forward declarations. + +class AllocaInst; class BasicBlock; +class CallInst; class CallLowering; class Constant; +class DataLayout; class Instruction; class MachineBasicBlock; class MachineFunction; class MachineInstr; -class OptimizationRemarkEmitter; class MachineRegisterInfo; +class OptimizationRemarkEmitter; +class PHINode; class TargetPassConfig; +class User; +class Value; // Technically the pass should run on an hypothetical MachineModule, // since it should translate Global into some sort of MachineGlobal. @@ -53,6 +62,7 @@ public: private: /// Interface used to lower the everything related to calls. const CallLowering *CLI; + /// Mapping of the values of the current LLVM IR function /// to the related virtual registers. ValueToVReg ValToVReg; @@ -67,7 +77,7 @@ private: // a mapping between the edges arriving at the BasicBlock to the corresponding // created MachineBasicBlocks. Some BasicBlocks that get translated to a // single MachineBasicBlock may also end up in this Map. - typedef std::pair<const BasicBlock *, const BasicBlock *> CFGEdge; + using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>; DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds; // List of stubbed PHI instructions, for values and basic blocks to be filled @@ -165,7 +175,6 @@ private: return translateCompare(U, MIRBuilder); } - /// Add remaining operands onto phis we've translated. Executed after all /// MachineBasicBlocks for the function have been created. void finishPendingPhis(); @@ -356,7 +365,7 @@ private: MachineFunction *MF; /// MachineRegisterInfo used to create virtual registers. - MachineRegisterInfo *MRI; + MachineRegisterInfo *MRI = nullptr; const DataLayout *DL; @@ -430,5 +439,6 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; }; -} // End namespace llvm. -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index b3ef7c2dc1859..ec60123e54b15 100644 --- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -1,4 +1,4 @@ -//==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==// +//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -16,15 +16,16 @@ #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H -#include "llvm/ADT/Optional.h" #include <bitset> +#include <cstddef> #include <cstdint> #include <functional> +#include <initializer_list> namespace llvm { + class MachineInstr; class MachineInstrBuilder; -class MachineFunction; class MachineOperand; class MachineRegisterInfo; class RegisterBankInfo; @@ -60,7 +61,7 @@ public: /// Provides the logic to select generic machine instructions. class InstructionSelector { public: - virtual ~InstructionSelector() {} + virtual ~InstructionSelector() = default; /// Select the (possibly generic) instruction \p I to only use target-specific /// opcodes. It is OK to insert multiple instructions, but they cannot be @@ -76,7 +77,7 @@ public: virtual bool select(MachineInstr &I) const = 0; protected: - typedef std::function<void(MachineInstrBuilder &)> ComplexRendererFn; + using ComplexRendererFn = std::function<void(MachineInstrBuilder &)>; InstructionSelector(); @@ -110,6 +111,6 @@ protected: bool isObviouslySafeToFold(MachineInstr &MI) const; }; -} // End namespace llvm. +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h index 21354ae20ed14..c259e93fdd366 100644 --- a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h +++ b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h @@ -1,4 +1,4 @@ -//==-- llvm/CodeGen/GlobalISel/LegalizerInfo.h -------------------*- C++ -*-==// +//===- llvm/CodeGen/GlobalISel/LegalizerInfo.h ------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -12,33 +12,36 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H -#define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZER_H +#ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H +#define LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H #include "llvm/ADT/DenseMap.h" -#include "llvm/CodeGen/LowLevelType.h" +#include "llvm/ADT/None.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/Support/LowLevelTypeImpl.h" #include "llvm/Target/TargetOpcodes.h" - #include <cstdint> -#include <functional> +#include <cassert> +#include <tuple> +#include <utility> namespace llvm { -class LLVMContext; + class MachineInstr; class MachineIRBuilder; class MachineRegisterInfo; -class Type; -class VectorType; /// Legalization is decided based on an instruction's opcode, which type slot /// we're considering, and what the existing type is. These aspects are gathered /// together for convenience in the InstrAspect class. struct InstrAspect { unsigned Opcode; - unsigned Idx; + unsigned Idx = 0; LLT Type; - InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Idx(0), Type(Type) {} + InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) : Opcode(Opcode), Idx(Idx), Type(Type) {} @@ -104,6 +107,19 @@ public: /// before any query is made or incorrect results may be returned. void computeTables(); + static bool needsLegalizingToDifferentSize(const LegalizeAction Action) { + switch (Action) { + case NarrowScalar: + case WidenScalar: + case FewerElements: + case MoreElements: + case Unsupported: + return true; + default: + return false; + } + } + /// More friendly way to set an action for common types that have an LLT /// representation. void setAction(const InstrAspect &Aspect, LegalizeAction Action) { @@ -125,7 +141,6 @@ public: ScalarInVectorActions[std::make_pair(Opcode, ScalarTy)] = Action; } - /// Determine what action should be taken to legalize the given generic /// instruction opcode, type-index and type. Requires computeTables to have /// been called. @@ -145,8 +160,8 @@ public: /// Iterate the given function (typically something like doubling the width) /// on Ty until we find a legal type for this operation. - Optional<LLT> findLegalType(const InstrAspect &Aspect, - function_ref<LLT(LLT)> NextType) const { + Optional<LLT> findLegalizableSize(const InstrAspect &Aspect, + function_ref<LLT(LLT)> NextType) const { LegalizeAction Action; const TypeMap &Map = Actions[Aspect.Opcode - FirstOp][Aspect.Idx]; LLT Ty = Aspect.Type; @@ -158,10 +173,9 @@ public: if (DefaultIt == DefaultActions.end()) return None; Action = DefaultIt->second; - } - else + } else Action = ActionIt->second; - } while(Action != Legal); + } while (needsLegalizingToDifferentSize(Action)); return Ty; } @@ -203,18 +217,17 @@ private: static const int FirstOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START; static const int LastOp = TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; - typedef DenseMap<LLT, LegalizeAction> TypeMap; - typedef DenseMap<std::pair<unsigned, LLT>, LegalizeAction> SIVActionMap; + using TypeMap = DenseMap<LLT, LegalizeAction>; + using SIVActionMap = DenseMap<std::pair<unsigned, LLT>, LegalizeAction>; SmallVector<TypeMap, 1> Actions[LastOp - FirstOp + 1]; SIVActionMap ScalarInVectorActions; DenseMap<std::pair<unsigned, LLT>, uint16_t> MaxLegalVectorElts; DenseMap<unsigned, LegalizeAction> DefaultActions; - bool TablesInitialized; + bool TablesInitialized = false; }; +} // end namespace llvm -} // End namespace llvm. - -#endif +#endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H diff --git a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h index f610bc02b6f26..676955c33fe9c 100644 --- a/include/llvm/CodeGen/GlobalISel/RegBankSelect.h +++ b/include/llvm/CodeGen/GlobalISel/RegBankSelect.h @@ -1,4 +1,4 @@ -//== llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector -*- C++ -*-==// +//=- llvm/CodeGen/GlobalISel/RegBankSelect.h - Reg Bank Selector --*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -64,20 +64,27 @@ #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H #define LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" +#include <cassert> +#include <cstdint> +#include <memory> namespace llvm { -// Forward declarations. + class BlockFrequency; -class MachineBranchProbabilityInfo; class MachineBlockFrequencyInfo; +class MachineBranchProbabilityInfo; +class MachineOperand; class MachineRegisterInfo; +class Pass; +class raw_ostream; class TargetPassConfig; class TargetRegisterInfo; -class raw_ostream; /// This pass implements the reg bank selector pass used in the GlobalISel /// pipeline. At the end of this pass, all register operands have been assigned @@ -105,6 +112,7 @@ public: protected: /// Tell if the insert point has already been materialized. bool WasMaterialized = false; + /// Materialize the insertion point. /// /// If isSplit() is true, this involves actually splitting @@ -128,7 +136,7 @@ public: virtual MachineBasicBlock::iterator getPointImpl() = 0; public: - virtual ~InsertPoint() {} + virtual ~InsertPoint() = default; /// The first call to this method will cause the splitting to /// happen if need be, then sub sequent calls just return @@ -197,6 +205,7 @@ public: private: /// Insertion point. MachineInstr &Instr; + /// Does the insertion point is before or after Instr. bool Before; @@ -216,6 +225,7 @@ public: public: /// Create an insertion point before (\p Before=true) or after \p Instr. InstrInsertPoint(MachineInstr &Instr, bool Before = true); + bool isSplit() const override; uint64_t frequency(const Pass &P) const override; @@ -228,6 +238,7 @@ public: private: /// Insertion point. MachineBasicBlock &MBB; + /// Does the insertion point is at the beginning or end of MBB. bool Beginning; @@ -252,6 +263,7 @@ public: assert((Beginning || MBB.getFirstTerminator() == MBB.end()) && "Invalid end point"); } + bool isSplit() const override { return false; } uint64_t frequency(const Pass &P) const override; bool canMaterialize() const override { return true; }; @@ -262,10 +274,12 @@ public: private: /// Source of the edge. MachineBasicBlock &Src; + /// Destination of the edge. /// After the materialization is done, this hold the basic block /// that resulted from the splitting. MachineBasicBlock *DstOrSplit; + /// P is used to update the analysis passes as applicable. Pass &P; @@ -286,9 +300,11 @@ public: public: EdgeInsertPoint(MachineBasicBlock &Src, MachineBasicBlock &Dst, Pass &P) : InsertPoint(), Src(Src), DstOrSplit(&Dst), P(P) {} + bool isSplit() const override { return Src.succ_size() > 1 && DstOrSplit->pred_size() > 1; } + uint64_t frequency(const Pass &P) const override; bool canMaterialize() const override; }; @@ -311,9 +327,9 @@ public: /// \name Convenient types for a list of insertion points. /// @{ - typedef SmallVector<std::unique_ptr<InsertPoint>, 2> InsertionPoints; - typedef InsertionPoints::iterator insertpt_iterator; - typedef InsertionPoints::const_iterator const_insertpt_iterator; + using InsertionPoints = SmallVector<std::unique_ptr<InsertPoint>, 2>; + using insertpt_iterator = InsertionPoints::iterator; + using const_insertpt_iterator = InsertionPoints::const_iterator; /// @} private: @@ -324,7 +340,7 @@ public: /// Are all the insert points materializeable? bool CanMaterialize; /// Is there any of the insert points needing splitting? - bool HasSplit; + bool HasSplit = false; /// Insertion point for the repair code. /// The repairing code needs to happen just before these points. InsertionPoints InsertPoints; @@ -407,10 +423,10 @@ private: private: /// Cost of the local instructions. /// This cost is free of basic block frequency. - uint64_t LocalCost; + uint64_t LocalCost = 0; /// Cost of the non-local instructions. /// This cost should include the frequency of the related blocks. - uint64_t NonLocalCost; + uint64_t NonLocalCost = 0; /// Frequency of the block where the local instructions live. uint64_t LocalFreq; @@ -468,22 +484,22 @@ private: /// Interface to the target lowering info related /// to register banks. - const RegisterBankInfo *RBI; + const RegisterBankInfo *RBI = nullptr; /// MRI contains all the register class/bank information that this /// pass uses and updates. - MachineRegisterInfo *MRI; + MachineRegisterInfo *MRI = nullptr; /// Information on the register classes for the current function. - const TargetRegisterInfo *TRI; + const TargetRegisterInfo *TRI = nullptr; /// Get the frequency of blocks. /// This is required for non-fast mode. - MachineBlockFrequencyInfo *MBFI; + MachineBlockFrequencyInfo *MBFI = nullptr; /// Get the frequency of the edges. /// This is required for non-fast mode. - MachineBranchProbabilityInfo *MBPI; + MachineBranchProbabilityInfo *MBPI = nullptr; /// Current optimization remark emitter. Used to report failures. std::unique_ptr<MachineOptimizationRemarkEmitter> MORE; @@ -644,6 +660,6 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; }; -} // End namespace llvm. +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H diff --git a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index e3549d8988cda..60905c7ec226d 100644 --- a/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -1,4 +1,4 @@ -//==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==// +//===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -12,26 +12,27 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H -#define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H +#ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H +#define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H -#include "llvm/ADT/APInt.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Hashing.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/GlobalISel/RegisterBank.h" -#include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType. +#include "llvm/ADT/iterator_range.h" #include "llvm/Support/ErrorHandling.h" - #include <cassert> -#include <memory> // For unique_ptr. +#include <initializer_list> +#include <memory> namespace llvm { + class MachineInstr; class MachineRegisterInfo; +class raw_ostream; +class RegisterBank; class TargetInstrInfo; +class TargetRegisterClass; class TargetRegisterInfo; -class raw_ostream; /// Holds all the information related to register banks. class RegisterBankInfo { @@ -48,10 +49,12 @@ public: /// original value. The bits are counted from less significant /// bits to most significant bits. unsigned StartIdx; + /// Length of this mapping in bits. This is how many bits this /// partial mapping covers in the original value: /// from StartIdx to StartIdx + Length -1. unsigned Length; + /// Register bank where the partial value lives. const RegisterBank *RegBank; @@ -180,13 +183,16 @@ public: /// Identifier of the mapping. /// This is used to communicate between the target and the optimizers /// which mapping should be realized. - unsigned ID; + unsigned ID = InvalidMappingID; + /// Cost of this mapping. - unsigned Cost; + unsigned Cost = 0; + /// Mapping of all the operands. const ValueMapping *OperandsMapping; + /// Number of operands. - unsigned NumOperands; + unsigned NumOperands = 0; const ValueMapping &getOperandMapping(unsigned i) { assert(i < getNumOperands() && "Out of bound operand"); @@ -213,7 +219,7 @@ public: /// Default constructor. /// Use this constructor to express that the mapping is invalid. - InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {} + InstructionMapping() = default; /// Get the cost. unsigned getCost() const { return Cost; } @@ -264,7 +270,7 @@ public: /// Convenient type to represent the alternatives for mapping an /// instruction. /// \todo When we move to TableGen this should be an array ref. - typedef SmallVector<const InstructionMapping *, 4> InstructionMappings; + using InstructionMappings = SmallVector<const InstructionMapping *, 4>; /// Helper class used to get/create the virtual registers that will be used /// to replace the MachineOperand when applying a mapping. @@ -273,12 +279,16 @@ public: /// OpIdx-th operand starts. -1 means we do not have such mapping yet. /// Note: We use a SmallVector to avoid heap allocation for most cases. SmallVector<int, 8> OpToNewVRegIdx; + /// Hold the registers that will be used to map MI with InstrMapping. SmallVector<unsigned, 8> NewVRegs; + /// Current MachineRegisterInfo, used to create new virtual registers. MachineRegisterInfo &MRI; + /// Instruction being remapped. MachineInstr &MI; + /// New mapping of the instruction. const InstructionMapping &InstrMapping; @@ -373,6 +383,7 @@ public: protected: /// Hold the set of supported register banks. RegisterBank **RegBanks; + /// Total number of register banks. unsigned NumRegBanks; @@ -729,6 +740,7 @@ operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) { /// Hashing function for PartialMapping. /// It is required for the hashing of ValueMapping. hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping); -} // End namespace llvm. -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H diff --git a/include/llvm/CodeGen/GlobalISel/Types.h b/include/llvm/CodeGen/GlobalISel/Types.h index 7d974878d3b9f..7b22e343a7f86 100644 --- a/include/llvm/CodeGen/GlobalISel/Types.h +++ b/include/llvm/CodeGen/GlobalISel/Types.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===// +//===- llvm/CodeGen/GlobalISel/Types.h - Types used by GISel ----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -16,17 +16,19 @@ #define LLVM_CODEGEN_GLOBALISEL_TYPES_H #include "llvm/ADT/DenseMap.h" -#include "llvm/IR/Value.h" namespace llvm { +class Value; + /// Map a value to a virtual register. /// For now, we chose to map aggregate types to on single virtual /// register. This might be revisited if it turns out to be inefficient. /// PR26161 tracks that. /// Note: We need to expose this type to the target hooks for thing like /// ABI lowering that would be used during IRTranslation. -typedef DenseMap<const Value *, unsigned> ValueToVReg; +using ValueToVReg = DenseMap<const Value *, unsigned>; + +} // end namespace llvm -} // End namespace llvm. -#endif +#endif // LLVM_CODEGEN_GLOBALISEL_TYPES_H diff --git a/include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h b/include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h index da8fdcdf5a33d..6ad5de533d13d 100644 --- a/include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h +++ b/include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h @@ -134,7 +134,7 @@ using MNV = DiagnosticInfoMIROptimization::MachineArgument; /// /// It allows reporting when optimizations are performed and when they are not /// along with the reasons for it. Hotness information of the corresponding -/// code region can be included in the remark if DiagnosticHotnessRequested is +/// code region can be included in the remark if DiagnosticsHotnessRequested is /// enabled in the LLVM context. class MachineOptimizationRemarkEmitter { public: diff --git a/include/llvm/CodeGen/MachinePassRegistry.h b/include/llvm/CodeGen/MachinePassRegistry.h index db914b1f8bc71..3aba0bba7d1a3 100644 --- a/include/llvm/CodeGen/MachinePassRegistry.h +++ b/include/llvm/CodeGen/MachinePassRegistry.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/MachinePassRegistry.h ----------------------*- C++ -*-===// +//===- llvm/CodeGen/MachinePassRegistry.h -----------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -18,13 +18,13 @@ #ifndef LLVM_CODEGEN_MACHINEPASSREGISTRY_H #define LLVM_CODEGEN_MACHINEPASSREGISTRY_H +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/CommandLine.h" namespace llvm { -typedef void *(*MachinePassCtor)(); - +using MachinePassCtor = void *(*)(); //===----------------------------------------------------------------------===// /// @@ -34,36 +34,30 @@ typedef void *(*MachinePassCtor)(); //===----------------------------------------------------------------------===// class MachinePassRegistryListener { virtual void anchor(); + public: - MachinePassRegistryListener() {} - virtual ~MachinePassRegistryListener() {} + MachinePassRegistryListener() = default; + virtual ~MachinePassRegistryListener() = default; + virtual void NotifyAdd(StringRef N, MachinePassCtor C, StringRef D) = 0; virtual void NotifyRemove(StringRef N) = 0; }; - //===----------------------------------------------------------------------===// /// /// MachinePassRegistryNode - Machine pass node stored in registration list. /// //===----------------------------------------------------------------------===// class MachinePassRegistryNode { - private: - - MachinePassRegistryNode *Next; // Next function pass in list. + MachinePassRegistryNode *Next = nullptr; // Next function pass in list. StringRef Name; // Name of function pass. StringRef Description; // Description string. MachinePassCtor Ctor; // Function pass creator. public: - MachinePassRegistryNode(const char *N, const char *D, MachinePassCtor C) - : Next(nullptr) - , Name(N) - , Description(D) - , Ctor(C) - {} + : Name(N), Description(D), Ctor(C) {} // Accessors MachinePassRegistryNode *getNext() const { return Next; } @@ -72,25 +66,20 @@ public: StringRef getDescription() const { return Description; } MachinePassCtor getCtor() const { return Ctor; } void setNext(MachinePassRegistryNode *N) { Next = N; } - }; - //===----------------------------------------------------------------------===// /// /// MachinePassRegistry - Track the registration of machine passes. /// //===----------------------------------------------------------------------===// class MachinePassRegistry { - private: - MachinePassRegistryNode *List; // List of registry nodes. MachinePassCtor Default; // Default function pass creator. - MachinePassRegistryListener* Listener;// Listener for list adds are removes. + MachinePassRegistryListener *Listener; // Listener for list adds are removes. public: - // NO CONSTRUCTOR - we don't want static constructor ordering to mess // with the registry. @@ -109,10 +98,8 @@ public: /// Remove - Removes a function pass from the registration list. /// void Remove(MachinePassRegistryNode *Node); - }; - //===----------------------------------------------------------------------===// /// /// RegisterPassParser class - Handle the addition of new machine passes. @@ -142,7 +129,6 @@ public: } // Implement the MachinePassRegistryListener callbacks. - // void NotifyAdd(StringRef N, MachinePassCtor C, StringRef D) override { this->addLiteralOption(N, (typename RegistryClass::FunctionPassCtor)C, D); } @@ -151,7 +137,6 @@ public: } }; - } // end namespace llvm -#endif +#endif // LLVM_CODEGEN_MACHINEPASSREGISTRY_H diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index 34cbffa78203a..8590b7a348cfc 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -32,7 +32,7 @@ // // ScheduleDAGInstrs *<Target>PassConfig:: // createMachineScheduler(MachineSchedContext *C) { -// return new ScheduleDAGMI(C, CustomStrategy(C)); +// return new ScheduleDAGMILive(C, CustomStrategy(C)); // } // // The DAG builder can also be customized in a sense by adding DAG mutations diff --git a/include/llvm/CodeGen/MachineValueType.h b/include/llvm/CodeGen/MachineValueType.h index d991e4c216d95..0bdb38bfcbec8 100644 --- a/include/llvm/CodeGen/MachineValueType.h +++ b/include/llvm/CodeGen/MachineValueType.h @@ -18,6 +18,7 @@ #include "llvm/ADT/iterator_range.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include <cassert> namespace llvm { @@ -232,8 +233,7 @@ namespace llvm { Any = 255 }; - SimpleValueType SimpleTy; - + SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE; // A class to represent the number of elements in a vector // @@ -270,7 +270,7 @@ namespace llvm { } }; - constexpr MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} + constexpr MVT() = default; constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; } @@ -780,7 +780,6 @@ namespace llvm { return getSizeInBits() <= VT.getSizeInBits(); } - static MVT getFloatingPointVT(unsigned BitWidth) { switch (BitWidth) { default: @@ -982,9 +981,12 @@ namespace llvm { /// A simple iterator over the MVT::SimpleValueType enum. struct mvt_iterator { SimpleValueType VT; + mvt_iterator(SimpleValueType VT) : VT(VT) {} + MVT operator*() const { return VT; } bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; } + mvt_iterator& operator++() { VT = (MVT::SimpleValueType)((int)VT + 1); assert((int)VT <= MVT::MAX_ALLOWED_VALUETYPE && @@ -992,8 +994,9 @@ namespace llvm { return *this; } }; + /// A range of the MVT::SimpleValueType enum. - typedef iterator_range<mvt_iterator> mvt_range; + using mvt_range = iterator_range<mvt_iterator>; public: /// SimpleValueType Iteration @@ -1001,32 +1004,39 @@ namespace llvm { static mvt_range all_valuetypes() { return mvt_range(MVT::FIRST_VALUETYPE, MVT::LAST_VALUETYPE); } + static mvt_range integer_valuetypes() { return mvt_range(MVT::FIRST_INTEGER_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_INTEGER_VALUETYPE + 1)); } + static mvt_range fp_valuetypes() { return mvt_range(MVT::FIRST_FP_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_FP_VALUETYPE + 1)); } + static mvt_range vector_valuetypes() { return mvt_range(MVT::FIRST_VECTOR_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_VECTOR_VALUETYPE + 1)); } + static mvt_range integer_vector_valuetypes() { return mvt_range( MVT::FIRST_INTEGER_VECTOR_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_INTEGER_VECTOR_VALUETYPE + 1)); } + static mvt_range fp_vector_valuetypes() { return mvt_range( MVT::FIRST_FP_VECTOR_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_FP_VECTOR_VALUETYPE + 1)); } + static mvt_range integer_scalable_vector_valuetypes() { return mvt_range(MVT::FIRST_INTEGER_SCALABLE_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_INTEGER_SCALABLE_VALUETYPE + 1)); } + static mvt_range fp_scalable_vector_valuetypes() { return mvt_range(MVT::FIRST_FP_SCALABLE_VALUETYPE, (MVT::SimpleValueType)(MVT::LAST_FP_SCALABLE_VALUETYPE + 1)); @@ -1034,6 +1044,6 @@ namespace llvm { /// @} }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_MACHINEVALUETYPE_H diff --git a/include/llvm/CodeGen/MacroFusion.h b/include/llvm/CodeGen/MacroFusion.h index 473784bc58412..dc105fdc68fd8 100644 --- a/include/llvm/CodeGen/MacroFusion.h +++ b/include/llvm/CodeGen/MacroFusion.h @@ -1,4 +1,4 @@ -//===- MacroFusion.h - Macro Fusion ------------------------===// +//===- MacroFusion.h - Macro Fusion -----------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -12,19 +12,26 @@ // //===----------------------------------------------------------------------===// +#ifndef LLVM_CODEGEN_MACROFUSION_H +#define LLVM_CODEGEN_MACROFUSION_H + #include <functional> -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/CodeGen/MachineScheduler.h" +#include <memory> namespace llvm { +class MachineInstr; +class ScheduleDAGMutation; +class TargetInstrInfo; +class TargetSubtargetInfo; + /// \brief Check if the instr pair, FirstMI and SecondMI, should be fused /// together. Given SecondMI, when FirstMI is unspecified, then check if /// SecondMI may be part of a fused pair at all. -typedef std::function<bool(const TargetInstrInfo &TII, - const TargetSubtargetInfo &TSI, - const MachineInstr *FirstMI, - const MachineInstr &SecondMI)> ShouldSchedulePredTy; +using ShouldSchedulePredTy = std::function<bool(const TargetInstrInfo &TII, + const TargetSubtargetInfo &TSI, + const MachineInstr *FirstMI, + const MachineInstr &SecondMI)>; /// \brief Create a DAG scheduling mutation to pair instructions back to back /// for instructions that benefit according to the target-specific @@ -39,3 +46,5 @@ std::unique_ptr<ScheduleDAGMutation> createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent); } // end namespace llvm + +#endif // LLVM_CODEGEN_MACROFUSION_H diff --git a/include/llvm/CodeGen/PseudoSourceValue.h b/include/llvm/CodeGen/PseudoSourceValue.h index 681ccb4b997cb..f5aedb07e4d2b 100644 --- a/include/llvm/CodeGen/PseudoSourceValue.h +++ b/include/llvm/CodeGen/PseudoSourceValue.h @@ -94,7 +94,7 @@ public: explicit FixedStackPseudoSourceValue(int FI) : PseudoSourceValue(FixedStack), FI(FI) {} - static inline bool classof(const PseudoSourceValue *V) { + static bool classof(const PseudoSourceValue *V) { return V->kind() == FixedStack; } @@ -126,7 +126,7 @@ class GlobalValuePseudoSourceValue : public CallEntryPseudoSourceValue { public: GlobalValuePseudoSourceValue(const GlobalValue *GV); - static inline bool classof(const PseudoSourceValue *V) { + static bool classof(const PseudoSourceValue *V) { return V->kind() == GlobalValueCallEntry; } @@ -140,7 +140,7 @@ class ExternalSymbolPseudoSourceValue : public CallEntryPseudoSourceValue { public: ExternalSymbolPseudoSourceValue(const char *ES); - static inline bool classof(const PseudoSourceValue *V) { + static bool classof(const PseudoSourceValue *V) { return V->kind() == ExternalSymbolCallEntry; } diff --git a/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h b/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h index d82ab7d647e75..2107e5a313819 100644 --- a/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h +++ b/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h @@ -57,7 +57,7 @@ public: int64_t &Off); /// Parses tree in Ptr for base, index, offset addresses. - static BaseIndexOffset match(SDValue Ptr); + static BaseIndexOffset match(SDValue Ptr, const SelectionDAG &DAG); }; } // namespace llvm diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index af418d3050e45..d9f8af0e21d16 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1743,7 +1743,7 @@ public: bool isConstant() const; - static inline bool classof(const SDNode *N) { + static bool classof(const SDNode *N) { return N->getOpcode() == ISD::BUILD_VECTOR; } }; diff --git a/include/llvm/CodeGen/TargetPassConfig.h b/include/llvm/CodeGen/TargetPassConfig.h index c109b7489ccad..aaf0ab5d5481d 100644 --- a/include/llvm/CodeGen/TargetPassConfig.h +++ b/include/llvm/CodeGen/TargetPassConfig.h @@ -1,4 +1,4 @@ -//===-- TargetPassConfig.h - Code Generation pass options -------*- C++ -*-===// +//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -16,19 +16,23 @@ #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" +#include <cassert> #include <string> namespace llvm { -class PassConfigImpl; -class ScheduleDAGInstrs; class LLVMTargetMachine; struct MachineSchedContext; +class PassConfigImpl; +class ScheduleDAGInstrs; // The old pass manager infrastructure is hidden in a legacy namespace now. namespace legacy { + class PassManagerBase; -} + +} // end namespace legacy + using legacy::PassManagerBase; /// Discriminated union of Pass ID types. @@ -50,10 +54,11 @@ class IdentifyingPassPtr { AnalysisID ID; Pass *P; }; - bool IsInstance; + bool IsInstance = false; + public: - IdentifyingPassPtr() : P(nullptr), IsInstance(false) {} - IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {} + IdentifyingPassPtr() : P(nullptr) {} + IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {} IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} bool isValid() const { return P; } @@ -63,6 +68,7 @@ public: assert(!IsInstance && "Not a Pass ID"); return ID; } + Pass *getInstance() const { assert(IsInstance && "Not a Pass Instance"); return P; @@ -93,31 +99,30 @@ public: static char PostRAMachineLICMID; private: - PassManagerBase *PM; + PassManagerBase *PM = nullptr; AnalysisID StartBefore = nullptr; AnalysisID StartAfter = nullptr; AnalysisID StopBefore = nullptr; AnalysisID StopAfter = nullptr; - bool Started; - bool Stopped; - bool AddingMachinePasses; + bool Started = true; + bool Stopped = false; + bool AddingMachinePasses = false; protected: LLVMTargetMachine *TM; - PassConfigImpl *Impl; // Internal data structures - bool Initialized; // Flagged after all passes are configured. + PassConfigImpl *Impl = nullptr; // Internal data structures + bool Initialized = false; // Flagged after all passes are configured. // Target Pass Options // Targets provide a default setting, user flags override. - // - bool DisableVerify; + bool DisableVerify = false; /// Default setting for -enable-tail-merge on this target. - bool EnableTailMerge; + bool EnableTailMerge = true; /// Require processing of functions such that callees are generated before /// callers. - bool RequireCodeGenSCCOrder; + bool RequireCodeGenSCCOrder = false; /// Add the actual instruction selection passes. This does not include /// preparation passes on IR. @@ -296,7 +301,6 @@ public: /// printAndVerify - Add a pass to dump then verify the machine function, if /// those steps are enabled. - /// void printAndVerify(const std::string &Banner); /// Add a pass to print the machine function if printing is enabled. @@ -430,4 +434,4 @@ protected: } // end namespace llvm -#endif +#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index b404b4ca701f9..40d501edde10b 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -17,7 +17,10 @@ #define LLVM_CODEGEN_VALUETYPES_H #include "llvm/CodeGen/MachineValueType.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/MathExtras.h" #include <cassert> +#include <cstdint> #include <string> namespace llvm { @@ -30,13 +33,13 @@ namespace llvm { /// can represent. struct EVT { private: - MVT V; - Type *LLVMTy; + MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE; + Type *LLVMTy = nullptr; public: - constexpr EVT() : V(MVT::INVALID_SIMPLE_VALUE_TYPE), LLVMTy(nullptr) {} - constexpr EVT(MVT::SimpleValueType SVT) : V(SVT), LLVMTy(nullptr) {} - constexpr EVT(MVT S) : V(S), LLVMTy(nullptr) {} + constexpr EVT() = default; + constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} + constexpr EVT(MVT S) : V(S) {} bool operator==(EVT VT) const { return !(*this != VT); @@ -246,7 +249,6 @@ namespace llvm { return getSizeInBits() <= VT.getSizeInBits(); } - /// Return the SimpleValueType held in the specified simple EVT. MVT getSimpleVT() const { assert(isSimple() && "Expected a SimpleValueType!"); @@ -430,6 +432,6 @@ namespace llvm { unsigned getExtendedSizeInBits() const LLVM_READONLY; }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_VALUETYPES_H |