diff options
Diffstat (limited to 'include/llvm/Target/TargetSubtargetInfo.h')
-rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index 9cb07a5c6daea..9440c56dcf17e 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -1,4 +1,4 @@ -//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// +//===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -20,21 +20,29 @@ #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/CodeGen.h" #include <memory> #include <vector> + namespace llvm { class CallLowering; +class InstrItineraryData; +struct InstrStage; class InstructionSelector; class LegalizerInfo; class MachineInstr; +struct MachineSchedPolicy; +struct MCReadAdvanceEntry; +struct MCWriteLatencyEntry; +struct MCWriteProcResEntry; class RegisterBankInfo; class SDep; class SelectionDAGTargetInfo; +struct SubtargetFeatureKV; +struct SubtargetInfoKV; class SUnit; class TargetFrameLowering; class TargetInstrInfo; @@ -42,7 +50,7 @@ class TargetLowering; class TargetRegisterClass; class TargetRegisterInfo; class TargetSchedModel; -struct MachineSchedPolicy; +class Triple; //===----------------------------------------------------------------------===// /// @@ -64,13 +72,13 @@ protected: // Can only create subclasses... public: // AntiDepBreakMode - Type of anti-dependence breaking that should // be performed before post-RA scheduling. - typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; - typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector; + using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }; + using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>; TargetSubtargetInfo() = delete; TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; - void operator=(const TargetSubtargetInfo &) = delete; - virtual ~TargetSubtargetInfo(); + TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete; + ~TargetSubtargetInfo() override; virtual bool isXRaySupported() const { return false; } @@ -112,7 +120,6 @@ public: /// getRegisterInfo - If register information is available, return it. If /// not, return null. - /// virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } /// If the information for the register banks is available, return it. @@ -121,7 +128,6 @@ public: /// getInstrItineraryData - Returns instruction itinerary data for the target /// or specific subtarget. - /// virtual const InstrItineraryData *getInstrItineraryData() const { return nullptr; } |