diff options
Diffstat (limited to 'include/llvm/Target/TargetSubtargetInfo.h')
| -rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index b2d405de8464c..1b2e06acc2b01 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -25,6 +25,7 @@ class SDep; class SUnit; class TargetRegisterClass; class TargetSchedModel; +struct MachineSchedPolicy; template <typename T> class SmallVectorImpl; //===----------------------------------------------------------------------===// @@ -55,6 +56,9 @@ public: return 0; } + /// \brief Temporary API to test migration to MI scheduler. + bool useMachineScheduler() const; + /// \brief True if the subtarget should run MachineScheduler after aggressive /// coalescing. /// @@ -62,6 +66,16 @@ public: /// scheduler. It does not yet disable the postRA scheduler. virtual bool enableMachineScheduler() const; + /// \brief Override generic scheduling policy within a region. + /// + /// This is a convenient way for targets that don't provide any custom + /// scheduling heuristics (no custom MachineSchedStrategy) to make + /// changes to the generic scheduling policy. + virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, + MachineInstr *begin, + MachineInstr *end, + unsigned NumRegionInstrs) const {} + // enablePostRAScheduler - If the target can benefit from post-regalloc // scheduling and the specified optimization level meets the requirement // return true to enable post-register-allocation scheduling. In @@ -75,6 +89,10 @@ public: virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const { } + /// \brief Enable use of alias analysis during code generation (during MI + /// scheduling, DAGCombine, etc.). + virtual bool useAA() const; + /// \brief Reset the features for the subtarget. virtual void resetSubtargetFeatures(const MachineFunction *MF) { } }; |