diff options
Diffstat (limited to 'include/llvm/Target/TargetSubtargetInfo.h')
-rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index d50aa4932f8f3..b929070484f90 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -16,14 +16,18 @@ #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/SchedulerRegistry.h" +#include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/CodeGen.h" +#include <vector> namespace llvm { +class CallLowering; class DataLayout; class MachineFunction; class MachineInstr; +class RegisterBankInfo; class SDep; class SUnit; class TargetFrameLowering; @@ -32,7 +36,7 @@ class TargetLowering; class TargetRegisterClass; class TargetRegisterInfo; class TargetSchedModel; -class TargetSelectionDAGInfo; +class SelectionDAGTargetInfo; struct MachineSchedPolicy; template <typename T> class SmallVectorImpl; @@ -71,6 +75,7 @@ public: // -- Pipelines and scheduling information // -- Stack frame information // -- Selection DAG lowering information + // -- Call lowering information // // N.B. These objects may change during compilation. It's not safe to cache // them between functions. @@ -79,9 +84,10 @@ public: return nullptr; } virtual const TargetLowering *getTargetLowering() const { return nullptr; } - virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const { + virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const { return nullptr; } + virtual const CallLowering *getCallLowering() const { return nullptr; } /// Target can subclass this hook to select a different DAG scheduler. virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const { @@ -89,11 +95,14 @@ public: } /// getRegisterInfo - If register information is available, return it. If - /// not, return null. This is kept separate from RegInfo until RegInfo has - /// details of graph coloring register allocation removed from it. + /// not, return null. /// virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } + /// If the information for the register banks is available, return it. + /// Otherwise return nullptr. + virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; } + /// getInstrItineraryData - Returns instruction itinerary data for the target /// or specific subtarget. /// @@ -144,7 +153,6 @@ public: /// scheduling heuristics (no custom MachineSchedStrategy) to make /// changes to the generic scheduling policy. virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, - MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const {} // \brief Perform target specific adjustments to the latency of a schedule @@ -162,6 +170,12 @@ public: return CriticalPathRCs.clear(); } + // \brief Provide an ordered list of schedule DAG mutations for the post-RA + // scheduler. + virtual void getPostRAMutations( + std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { + } + // For use with PostRAScheduling: get the minimum optimization level needed // to enable post-RA scheduling. virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const { |