diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/CostTable.h | 35 | ||||
| -rw-r--r-- | include/llvm/Target/Mangler.h | 23 | ||||
| -rw-r--r-- | include/llvm/Target/Target.td | 63 | ||||
| -rw-r--r-- | include/llvm/Target/TargetCallingConv.h | 8 | ||||
| -rw-r--r-- | include/llvm/Target/TargetCallingConv.td | 6 | ||||
| -rw-r--r-- | include/llvm/Target/TargetFrameLowering.h | 5 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 73 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLibraryInfo.h | 31 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 1500 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLoweringObjectFile.h | 8 | ||||
| -rw-r--r-- | include/llvm/Target/TargetMachine.h | 21 | ||||
| -rw-r--r-- | include/llvm/Target/TargetOpcodes.h | 19 | ||||
| -rw-r--r-- | include/llvm/Target/TargetOptions.h | 60 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 45 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSchedule.td | 20 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 4 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAGInfo.h | 74 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 18 |
18 files changed, 1189 insertions, 824 deletions
diff --git a/include/llvm/Target/CostTable.h b/include/llvm/Target/CostTable.h index a974b56094560..34f6041137c12 100644 --- a/include/llvm/Target/CostTable.h +++ b/include/llvm/Target/CostTable.h @@ -25,18 +25,25 @@ struct CostTblEntry { unsigned Cost; }; -/// Find in cost table, TypeTy must be comparable by == -template <class TypeTy> -int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, - unsigned len, int ISD, TypeTy Ty) { +/// Find in cost table, TypeTy must be comparable to CompareTy by == +template <class TypeTy, class CompareTy> +int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, + CompareTy Ty) { for (unsigned int i = 0; i < len; ++i) - if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty) + if (ISD == Tbl[i].ISD && Ty == Tbl[i].Type) return i; // Could not find an entry. return -1; } +/// Find in cost table, TypeTy must be comparable to CompareTy by == +template <class TypeTy, class CompareTy, unsigned N> +int CostTableLookup(const CostTblEntry<TypeTy>(&Tbl)[N], int ISD, + CompareTy Ty) { + return CostTableLookup(Tbl, N, ISD, Ty); +} + /// Type Conversion Cost Table template <class TypeTy> struct TypeConversionCostTblEntry { @@ -46,18 +53,28 @@ struct TypeConversionCostTblEntry { unsigned Cost; }; -/// Find in type conversion cost table, TypeTy must be comparable by == -template <class TypeTy> +/// Find in type conversion cost table, TypeTy must be comparable to CompareTy +/// by == +template <class TypeTy, class CompareTy> int ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, - unsigned len, int ISD, TypeTy Dst, TypeTy Src) { + unsigned len, int ISD, CompareTy Dst, + CompareTy Src) { for (unsigned int i = 0; i < len; ++i) - if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst) + if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst) return i; // Could not find an entry. return -1; } +/// Find in type conversion cost table, TypeTy must be comparable to CompareTy +/// by == +template <class TypeTy, class CompareTy, unsigned N> +int ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy>(&Tbl)[N], + int ISD, CompareTy Dst, CompareTy Src) { + return ConvertCostTableLookup(Tbl, N, ISD, Dst, Src); +} + } // namespace llvm diff --git a/include/llvm/Target/Mangler.h b/include/llvm/Target/Mangler.h index 9500f1cc8f48b..eee7bf6d6979e 100644 --- a/include/llvm/Target/Mangler.h +++ b/include/llvm/Target/Mangler.h @@ -17,12 +17,12 @@ #include "llvm/ADT/DenseMap.h" namespace llvm { -class Twine; + class GlobalValue; -template <typename T> class SmallVectorImpl; class MCContext; -class MCSymbol; -class DataLayout; +template <typename T> class SmallVectorImpl; +class TargetMachine; +class Twine; class Mangler { public: @@ -33,8 +33,7 @@ public: }; private: - MCContext &Context; - const DataLayout &TD; + const TargetMachine *TM; /// AnonGlobalIDs - We need to give global values the same name every time /// they are mangled. This keeps track of the number we give to anonymous @@ -47,24 +46,20 @@ private: unsigned NextAnonGlobalID; public: - Mangler(MCContext &context, const DataLayout &td) - : Context(context), TD(td), NextAnonGlobalID(1) {} - - /// getSymbol - Return the MCSymbol for the specified global value. This - /// symbol is the main label that is the address of the global. - MCSymbol *getSymbol(const GlobalValue *GV); + Mangler(const TargetMachine *TM) : TM(TM), NextAnonGlobalID(1) {} /// getNameWithPrefix - Fill OutName with the name of the appropriate prefix /// and the specified global variable's name. If the global variable doesn't /// have a name, this fills in a unique name for the global. void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV, - bool isImplicitlyPrivate); + bool isImplicitlyPrivate, bool UseGlobalPrefix = true); /// getNameWithPrefix - Fill OutName with the name of the appropriate prefix /// and the specified name as the global variable name. GVName must not be /// empty. void getNameWithPrefix(SmallVectorImpl<char> &OutName, const Twine &GVName, - ManglerPrefixTy PrefixTy = Mangler::Default); + ManglerPrefixTy PrefixTy = Mangler::Default, + bool UseGlobalPrefix = true); }; } // End llvm namespace diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 7de8b384c3534..3f6eae6bb20a4 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -22,12 +22,22 @@ include "llvm/IR/Intrinsics.td" class RegisterClass; // Forward def // SubRegIndex - Use instances of SubRegIndex to identify subregisters. -class SubRegIndex<list<SubRegIndex> comps = []> { +class SubRegIndex<int size, int offset = 0> { string Namespace = ""; + // Size - Size (in bits) of the sub-registers represented by this index. + int Size = size; + + // Offset - Offset of the first bit that is part of this sub-register index. + // Set it to -1 if the same index is used to represent sub-registers that can + // be at different offsets (for example when using an index to access an + // element in a register tuple). + int Offset = offset; + // ComposedOf - A list of two SubRegIndex instances, [A, B]. // This indicates that this SubRegIndex is the result of composing A and B. - list<SubRegIndex> ComposedOf = comps; + // See ComposedSubRegIndex. + list<SubRegIndex> ComposedOf = []; // CoveringSubRegIndices - A list of two or more sub-register indexes that // cover this sub-register. @@ -48,6 +58,16 @@ class SubRegIndex<list<SubRegIndex> comps = []> { list<SubRegIndex> CoveringSubRegIndices = []; } +// ComposedSubRegIndex - A sub-register that is the result of composing A and B. +// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. +class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> + : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, + !if(!eq(B.Offset, -1), -1, + !add(A.Offset, B.Offset)))> { + // See SubRegIndex. + let ComposedOf = [A, B]; +} + // RegAltNameIndex - The alternate name set to use for register operands of // this register class when printing. class RegAltNameIndex { @@ -425,6 +445,11 @@ class Instruction { string TwoOperandAliasConstraint = ""; ///@} + + /// UseNamedOperandTable - If set, the operand indices of this instruction + /// can be queried via the getNamedOperandIdx() function which is generated + /// by TableGen. + bit UseNamedOperandTable = 0; } /// PseudoInstExpansion - Expansion information for a pseudo-instruction. @@ -607,6 +632,11 @@ def f64imm : Operand<f64>; /// def zero_reg; +/// All operands which the MC layer classifies as predicates should inherit from +/// this class in some manner. This is already handled for the most commonly +/// used PredicateOperand, but may be useful in other circumstances. +class PredicateOp; + /// OperandWithDefaultOps - This Operand class can be used as the parent class /// for an Operand that needs to be initialized with a default value if /// no value is supplied in a pattern. This class can be used to simplify the @@ -622,7 +652,7 @@ class OperandWithDefaultOps<ValueType ty, dag defaultops> /// AlwaysVal specifies the value of this predicate when set to "always /// execute". class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> - : OperandWithDefaultOps<ty, AlwaysVal> { + : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { let MIOperandInfo = OpTypes; } @@ -770,6 +800,19 @@ def LIFETIME_END : Instruction { let AsmString = "LIFETIME_END"; let neverHasSideEffects = 1; } +def STACKMAP : Instruction { + let OutOperandList = (outs); + let InOperandList = (ins i32imm:$id, i32imm:$nbytes, variable_ops); + let isCall = 1; + let mayLoad = 1; +} +def PATCHPOINT : Instruction { + let OutOperandList = (outs unknown:$dst); + let InOperandList = (ins i32imm:$id, i32imm:$nbytes, unknown:$callee, + i32imm:$nargs, i32imm:$cc, variable_ops); + let isCall = 1; + let mayLoad = 1; +} } //===----------------------------------------------------------------------===// @@ -793,6 +836,9 @@ class AsmParser { // ShouldEmitMatchRegisterName - Set to false if the target needs a hand // written register name matcher bit ShouldEmitMatchRegisterName = 1; + + /// Does the instruction mnemonic allow '.' + bit MnemonicContainsDot = 0; } def DefaultAsmParser : AsmParser; @@ -977,6 +1023,17 @@ class SubtargetFeature<string n, string a, string v, string d, list<SubtargetFeature> Implies = i; } +/// Specifies a Subtarget feature that this instruction is deprecated on. +class Deprecated<SubtargetFeature dep> { + SubtargetFeature DeprecatedFeatureMask = dep; +} + +/// A custom predicate used to determine if an instruction is +/// deprecated or not. +class ComplexDeprecationPredicate<string dep> { + string ComplexDeprecationPredicate = dep; +} + //===----------------------------------------------------------------------===// // Processor chip sets - These values represent each of the chip sets supported // by the scheduler. Each Processor definition requires corresponding diff --git a/include/llvm/Target/TargetCallingConv.h b/include/llvm/Target/TargetCallingConv.h index 1fd0bd98b6fae..9cc52a591b36c 100644 --- a/include/llvm/Target/TargetCallingConv.h +++ b/include/llvm/Target/TargetCallingConv.h @@ -113,6 +113,7 @@ namespace ISD { struct InputArg { ArgFlagsTy Flags; MVT VT; + EVT ArgVT; bool Used; /// Index original Function's argument. @@ -124,10 +125,11 @@ namespace ISD { unsigned PartOffset; InputArg() : VT(MVT::Other), Used(false) {} - InputArg(ArgFlagsTy flags, EVT vt, bool used, + InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used, unsigned origIdx, unsigned partOffs) : Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOffs) { VT = vt.getSimpleVT(); + ArgVT = argvt; } }; @@ -138,6 +140,7 @@ namespace ISD { struct OutputArg { ArgFlagsTy Flags; MVT VT; + EVT ArgVT; /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...". bool IsFixed; @@ -151,11 +154,12 @@ namespace ISD { unsigned PartOffset; OutputArg() : IsFixed(false) {} - OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed, + OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed, unsigned origIdx, unsigned partOffs) : Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx), PartOffset(partOffs) { VT = vt.getSimpleVT(); + ArgVT = argvt; } }; } diff --git a/include/llvm/Target/TargetCallingConv.td b/include/llvm/Target/TargetCallingConv.td index a53ed29f1ec15..c1bef28652e9a 100644 --- a/include/llvm/Target/TargetCallingConv.td +++ b/include/llvm/Target/TargetCallingConv.td @@ -143,4 +143,10 @@ class CallingConv<list<CCAction> actions> { /// returning from getCallPreservedMask(). class CalleeSavedRegs<dag saves> { dag SaveList = saves; + + // Registers that are also preserved across function calls, but should not be + // included in the generated FOO_SaveList array. These registers will be + // included in the FOO_RegMask bit mask. This can be used for registers that + // are saved automatically, like the SPARC register windows. + dag OtherPreserved; } diff --git a/include/llvm/Target/TargetFrameLowering.h b/include/llvm/Target/TargetFrameLowering.h index d5f30f40addbe..a60147f5c092a 100644 --- a/include/llvm/Target/TargetFrameLowering.h +++ b/include/llvm/Target/TargetFrameLowering.h @@ -88,6 +88,11 @@ public: /// int getOffsetOfLocalArea() const { return LocalAreaOffset; } + /// isFPCloseToIncomingSP - Return true if the frame pointer is close to + /// the incoming stack pointer, false if it is close to the post-prologue + /// stack pointer. + virtual bool isFPCloseToIncomingSP() const { return true; } + /// getCalleeSavedSpillSlots - This method returns a pointer to an array of /// pairs, that contains an entry for each callee saved register that must be /// spilled to a particular stack location if it is spilled. diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index d49ce1ce7f46e..d4e14f60f237b 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -173,6 +173,31 @@ public: const MachineMemOperand *&MMO, int &FrameIndex) const; + /// isStackSlotCopy - Return true if the specified machine instruction + /// is a copy of one stack slot to another and has no other effect. + /// Provide the identity of the two frame indices. + virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, + int &SrcFrameIndex) const { + return false; + } + + /// Compute the size in bytes and offset within a stack slot of a spilled + /// register or subregister. + /// + /// \param [out] Size in bytes of the spilled value. + /// \param [out] Offset in bytes within the stack slot. + /// \returns true if both Size and Offset are successfully computed. + /// + /// Not all subregisters have computable spill slots. For example, + /// subregisters registers may not be byte-sized, and a pair of discontiguous + /// subregisters has no single offset. + /// + /// Targets with nontrivial bigendian implementations may need to override + /// this, particularly to support spilled vector registers. + virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, + unsigned &Size, unsigned &Offset, + const TargetMachine *TM) const; + /// reMaterialize - Re-issue the specified 'original' instruction at the /// specific location targeting a new destination register. /// The register in Orig->getOperand(0).getReg() will be substituted by @@ -505,22 +530,6 @@ public: return false; } - /// emitFrameIndexDebugValue - Emit a target-dependent form of - /// DBG_VALUE encoding the address of a frame index. Addresses would - /// normally be lowered the same way as other addresses on the target, - /// e.g. in load instructions. For targets that do not support this - /// the debug info is simply lost. - /// If you add this for a target you should handle this DBG_VALUE in the - /// target-specific AsmPrinter code as well; you will probably get invalid - /// assembly output if you don't. - virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, - int FrameIx, - uint64_t Offset, - const MDNode *MDPtr, - DebugLoc dl) const { - return 0; - } - /// foldMemoryOperand - Attempt to fold a load or store of the specified stack /// slot into the specified machine instruction for the specified operand(s). /// If this is possible, a new instruction is returned with the specified @@ -623,6 +632,8 @@ public: return false; } + virtual bool enableClusterLoads() const { return false; } + virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const { @@ -817,12 +828,10 @@ public: /// computeOperandLatency - Compute and return the latency of the given data /// dependent def and use when the operand indices are already known. - /// - /// FindMin may be set to get the minimum vs. expected latency. unsigned computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx, - bool FindMin = false) const; + const MachineInstr *UseMI, unsigned UseIdx) + const; /// getInstrLatency - Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via @@ -831,6 +840,8 @@ public: const MachineInstr *MI, unsigned *PredCost = 0) const; + virtual unsigned getPredicationCost(const MachineInstr *MI) const; + virtual int getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const; @@ -839,7 +850,7 @@ public: const MachineInstr *DefMI) const; int computeDefOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr *DefMI, bool FindMin) const; + const MachineInstr *DefMI) const; /// isHighLatencyDef - Return true if this opcode has high latency to its /// result. @@ -948,6 +959,26 @@ public: return 0; } + /// \brief Return the minimum clearance before an instruction that reads an + /// unused register. + /// + /// For example, AVX instructions may copy part of an register operand into + /// the unused high bits of the destination register. + /// + /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 + /// + /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a + /// false dependence on any previous write to %xmm0. + /// + /// This hook works similarly to getPartialRegUpdateClearance, except that it + /// does not take an operand index. Instead sets \p OpNum to the index of the + /// unused register. + virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, + const TargetRegisterInfo *TRI) const { + // The default implementation returns 0 for no undef register dependency. + return 0; + } + /// breakPartialRegDependency - Insert a dependency-breaking instruction /// before MI to eliminate an unwanted dependency on OpNum. /// diff --git a/include/llvm/Target/TargetLibraryInfo.h b/include/llvm/Target/TargetLibraryInfo.h index 5f01c8d8351af..46eaef2871b1b 100644 --- a/include/llvm/Target/TargetLibraryInfo.h +++ b/include/llvm/Target/TargetLibraryInfo.h @@ -24,8 +24,12 @@ namespace llvm { under_IO_putc, /// void operator delete[](void*); ZdaPv, + /// void operator delete[](void*, nothrow); + ZdaPvRKSt9nothrow_t, /// void operator delete(void*); ZdlPv, + /// void operator delete(void*, nothrow); + ZdlPvRKSt9nothrow_t, /// void *new[](unsigned int); Znaj, /// void *new[](unsigned int, nothrow); @@ -42,6 +46,10 @@ namespace llvm { Znwm, /// void *new(unsigned long, nothrow); ZnwmRKSt9nothrow_t, + /// double __cospi(double x); + cospi, + /// float __cospif(float x); + cospif, /// int __cxa_atexit(void (*f)(void *), void *p, void *d); cxa_atexit, /// void __cxa_guard_abort(guard_t *guard); @@ -57,6 +65,20 @@ namespace llvm { dunder_isoc99_sscanf, /// void *__memcpy_chk(void *s1, const void *s2, size_t n, size_t s1size); memcpy_chk, + /// double __sincospi_stret(double x); + sincospi_stret, + /// float __sincospi_stretf(float x); + sincospi_stretf, + /// double __sinpi(double x); + sinpi, + /// float __sinpif(float x); + sinpif, + /// double __sqrt_finite(double x); + sqrt_finite, + /// float __sqrt_finite(float x); + sqrtf_finite, + /// long double __sqrt_finite(long double x); + sqrtl_finite, /// char * __strdup(const char *s); dunder_strdup, /// char *__strndup(const char *s, size_t n); @@ -302,6 +324,8 @@ namespace llvm { getpwnam, /// char *gets(char *s); gets, + /// int gettimeofday(struct timeval *tp, void *tzp); + gettimeofday, /// uint32_t htonl(uint32_t hostlong); htonl, /// uint16_t htons(uint16_t hostshort); @@ -677,14 +701,19 @@ public: case LibFunc::sin: case LibFunc::sinf: case LibFunc::sinl: case LibFunc::cos: case LibFunc::cosf: case LibFunc::cosl: case LibFunc::sqrt: case LibFunc::sqrtf: case LibFunc::sqrtl: + case LibFunc::sqrt_finite: case LibFunc::sqrtf_finite: + case LibFunc::sqrtl_finite: case LibFunc::floor: case LibFunc::floorf: case LibFunc::floorl: case LibFunc::nearbyint: case LibFunc::nearbyintf: case LibFunc::nearbyintl: case LibFunc::ceil: case LibFunc::ceilf: case LibFunc::ceill: case LibFunc::rint: case LibFunc::rintf: case LibFunc::rintl: + case LibFunc::round: case LibFunc::roundf: case LibFunc::roundl: case LibFunc::trunc: case LibFunc::truncf: case LibFunc::truncl: case LibFunc::log2: case LibFunc::log2f: case LibFunc::log2l: case LibFunc::exp2: case LibFunc::exp2f: case LibFunc::exp2l: - case LibFunc::memcmp: + case LibFunc::memcmp: case LibFunc::strcmp: case LibFunc::strcpy: + case LibFunc::stpcpy: case LibFunc::strlen: case LibFunc::strnlen: + case LibFunc::memchr: return true; } return false; diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index d5c9ebe0f2a9b..5ab04f794452e 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -6,17 +6,18 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// This file describes how to lower LLVM code to machine code. This has two -// main components: -// -// 1. Which ValueTypes are natively supported by the target. -// 2. Which operations are supported for supported ValueTypes. -// 3. Cost thresholds for alternative implementations of certain operations. -// -// In addition it has a few other components, like information about FP -// immediates. -// +/// +/// \file +/// This file describes how to lower LLVM code to machine code. This has two +/// main components: +/// +/// 1. Which ValueTypes are natively supported by the target. +/// 2. Which operations are supported for supported ValueTypes. +/// 3. Cost thresholds for alternative implementations of certain operations. +/// +/// In addition it has a few other components, like information about FP +/// immediates. +/// //===----------------------------------------------------------------------===// #ifndef LLVM_TARGET_TARGETLOWERING_H @@ -30,7 +31,6 @@ #include "llvm/IR/CallingConv.h" #include "llvm/IR/InlineAsm.h" #include "llvm/Support/CallSite.h" -#include "llvm/Support/DebugLoc.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetMachine.h" #include <climits> @@ -68,15 +68,15 @@ namespace llvm { }; } -/// TargetLoweringBase - This base class for TargetLowering contains the -/// SelectionDAG-independent parts that can be used from the rest of CodeGen. +/// This base class for TargetLowering contains the SelectionDAG-independent +/// parts that can be used from the rest of CodeGen. class TargetLoweringBase { TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; public: - /// LegalizeAction - This enum indicates whether operations are valid for a - /// target, and if not, what action should be used to make them valid. + /// This enum indicates whether operations are valid for a target, and if not, + /// what action should be used to make them valid. enum LegalizeAction { Legal, // The target natively supports this operation. Promote, // This operation should be executed in a larger type. @@ -84,8 +84,8 @@ public: Custom // Use the LowerOperation hook to implement custom lowering. }; - /// LegalizeTypeAction - This enum indicates whether a types are legal for a - /// target, and if not, what action should be used to make them valid. + /// This enum indicates whether a types are legal for a target, and if not, + /// what action should be used to make them valid. enum LegalizeTypeAction { TypeLegal, // The target natively supports this type. TypePromoteInteger, // Replace this integer with a larger one. @@ -101,12 +101,14 @@ public: /// in order to type-legalize it. typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; - enum BooleanContent { // How the target represents true/false values. + /// Enum that describes how the target represents true/false values. + enum BooleanContent { UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. ZeroOrOneBooleanContent, // All bits zero except for bit 0. ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. }; + /// Enum that describes what type of support for selects the target has. enum SelectSupportKind { ScalarValSelect, // The target supports scalar selects (ex: cmov). ScalarCondVectorVal, // The target supports selects with a scalar condition @@ -146,118 +148,140 @@ public: bool isBigEndian() const { return !IsLittleEndian; } bool isLittleEndian() const { return IsLittleEndian; } - // Return the pointer type for the given address space, defaults to - // the pointer type from the data layout. - // FIXME: The default needs to be removed once all the code is updated. - virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; } + + /// Return the pointer type for the given address space, defaults to + /// the pointer type from the data layout. + /// FIXME: The default needs to be removed once all the code is updated. + virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const; + unsigned getPointerSizeInBits(uint32_t AS = 0) const; + unsigned getPointerTypeSizeInBits(Type *Ty) const; virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; EVT getShiftAmountTy(EVT LHSTy) const; - /// isSelectExpensive - Return true if the select operation is expensive for - /// this target. + /// Returns the type to be used for the index operand of: + /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, + /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR + virtual MVT getVectorIdxTy() const { + return getPointerTy(); + } + + /// Return true if the select operation is expensive for this target. bool isSelectExpensive() const { return SelectIsExpensive; } - virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } + virtual bool isSelectSupported(SelectSupportKind /*kind*/) const { + return true; + } - /// shouldSplitVectorElementType - Return true if a vector of the given type - /// should be split (TypeSplitVector) instead of promoted - /// (TypePromoteInteger) during type legalization. - virtual bool shouldSplitVectorElementType(EVT VT) const { return false; } + /// Return true if a vector of the given type should be split + /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type + /// legalization. + virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; } - /// isIntDivCheap() - Return true if integer divide is usually cheaper than - /// a sequence of several shifts, adds, and multiplies for this target. + /// Return true if integer divide is usually cheaper than a sequence of + /// several shifts, adds, and multiplies for this target. bool isIntDivCheap() const { return IntDivIsCheap; } - /// isSlowDivBypassed - Returns true if target has indicated at least one - /// type should be bypassed. + /// Returns true if target has indicated at least one type should be bypassed. bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } - /// getBypassSlowDivTypes - Returns map of slow types for division or - /// remainder with corresponding fast types + /// Returns map of slow types for division or remainder with corresponding + /// fast types const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { return BypassSlowDivWidths; } - /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of - /// srl/add/sra. + /// Return true if pow2 div is cheaper than a chain of srl/add/sra. bool isPow2DivCheap() const { return Pow2DivIsCheap; } - /// isJumpExpensive() - Return true if Flow Control is an expensive operation - /// that should be avoided. + /// Return true if Flow Control is an expensive operation that should be + /// avoided. bool isJumpExpensive() const { return JumpIsExpensive; } - /// isPredictableSelectExpensive - Return true if selects are only cheaper - /// than branches if the branch is unlikely to be predicted right. + /// Return true if selects are only cheaper than branches if the branch is + /// unlikely to be predicted right. bool isPredictableSelectExpensive() const { return PredictableSelectIsExpensive; } - /// getSetCCResultType - Return the ValueType of the result of SETCC - /// operations. Also used to obtain the target's preferred type for - /// the condition operand of SELECT and BRCOND nodes. In the case of - /// BRCOND the argument passed is MVT::Other since there are no other - /// operands to get a type hint from. - virtual EVT getSetCCResultType(EVT VT) const; + /// isLoadBitCastBeneficial() - Return true if the following transform + /// is beneficial. + /// fold (conv (load x)) -> (load (conv*)x) + /// On architectures that don't natively support some vector loads efficiently, + /// casting the load to a smaller vector of larger types and loading + /// is more efficient, however, this can be undone by optimizations in + /// dag combiner. + virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const { + return true; + } - /// getCmpLibcallReturnType - Return the ValueType for comparison - /// libcalls. Comparions libcalls include floating point comparion calls, - /// and Ordered/Unordered check calls on floating point numbers. + /// Return the ValueType of the result of SETCC operations. Also used to + /// obtain the target's preferred type for the condition operand of SELECT and + /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other + /// since there are no other operands to get a type hint from. + virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; + + /// Return the ValueType for comparison libcalls. Comparions libcalls include + /// floating point comparion calls, and Ordered/Unordered check calls on + /// floating point numbers. virtual MVT::SimpleValueType getCmpLibcallReturnType() const; - /// getBooleanContents - For targets without i1 registers, this gives the - /// nature of the high-bits of boolean values held in types wider than i1. + /// For targets without i1 registers, this gives the nature of the high-bits + /// of boolean values held in types wider than i1. + /// /// "Boolean values" are special true/false values produced by nodes like /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. - /// Not to be confused with general values promoted from i1. - /// Some cpus distinguish between vectors of boolean and scalars; the isVec - /// parameter selects between the two kinds. For example on X86 a scalar - /// boolean should be zero extended from i1, while the elements of a vector - /// of booleans should be sign extended from i1. + /// Not to be confused with general values promoted from i1. Some cpus + /// distinguish between vectors of boolean and scalars; the isVec parameter + /// selects between the two kinds. For example on X86 a scalar boolean should + /// be zero extended from i1, while the elements of a vector of booleans + /// should be sign extended from i1. BooleanContent getBooleanContents(bool isVec) const { return isVec ? BooleanVectorContents : BooleanContents; } - /// getSchedulingPreference - Return target scheduling preference. + /// Return target scheduling preference. Sched::Preference getSchedulingPreference() const { return SchedPreferenceInfo; } - /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to - /// different scheduling heuristics for different nodes. This function returns - /// the preference (or none) for the given node. + /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics + /// for different nodes. This function returns the preference (or none) for + /// the given node. virtual Sched::Preference getSchedulingPreference(SDNode *) const { return Sched::None; } - /// getRegClassFor - Return the register class that should be used for the - /// specified value type. + /// Return the register class that should be used for the specified value + /// type. virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; assert(RC && "This value type is not natively supported!"); return RC; } - /// getRepRegClassFor - Return the 'representative' register class for the - /// specified value type. The 'representative' register class is the largest - /// legal super-reg register class for the register class of the value type. - /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; - /// while the rep register class is GR64 on x86_64. + /// Return the 'representative' register class for the specified value + /// type. + /// + /// The 'representative' register class is the largest legal super-reg + /// register class for the register class of the value type. For example, on + /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep + /// register class is GR64 on x86_64. virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; return RC; } - /// getRepRegClassCostFor - Return the cost of the 'representative' register - /// class for the specified value type. + /// Return the cost of the 'representative' register class for the specified + /// value type. virtual uint8_t getRepRegClassCostFor(MVT VT) const { return RepRegClassCostForVT[VT.SimpleTy]; } - /// isTypeLegal - Return true if the target has native support for the - /// specified value type. This means that it has a register that directly - /// holds it without promotions or expansions. + /// Return true if the target has native support for the specified value type. + /// This means that it has a register that directly holds it without + /// promotions or expansions. bool isTypeLegal(EVT VT) const { assert(!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); @@ -288,10 +312,10 @@ public: return ValueTypeActions; } - /// getTypeAction - Return how we should legalize values of this type, either - /// it is already legal (return 'Legal') or we need to promote it to a larger - /// type (return 'Promote'), or we need to expand it into multiple registers - /// of smaller integer type (return 'Expand'). 'Custom' is not an option. + /// Return how we should legalize values of this type, either it is already + /// legal (return 'Legal') or we need to promote it to a larger type (return + /// 'Promote'), or we need to expand it into multiple registers of smaller + /// integer type (return 'Expand'). 'Custom' is not an option. LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { return getTypeConversion(Context, VT).first; } @@ -299,20 +323,20 @@ public: return ValueTypeActions.getTypeAction(VT); } - /// getTypeToTransformTo - For types supported by the target, this is an - /// identity function. For types that must be promoted to larger types, this - /// returns the larger type to promote to. For integer types that are larger - /// than the largest integer register, this contains one step in the expansion - /// to get to the smaller register. For illegal floating point types, this - /// returns the integer type to transform to. + /// For types supported by the target, this is an identity function. For + /// types that must be promoted to larger types, this returns the larger type + /// to promote to. For integer types that are larger than the largest integer + /// register, this contains one step in the expansion to get to the smaller + /// register. For illegal floating point types, this returns the integer type + /// to transform to. EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { return getTypeConversion(Context, VT).second; } - /// getTypeToExpandTo - For types supported by the target, this is an - /// identity function. For types that must be expanded (i.e. integer types - /// that are larger than the largest integer register or illegal floating - /// point types), this returns the largest legal type it will be expanded to. + /// For types supported by the target, this is an identity function. For + /// types that must be expanded (i.e. integer types that are larger than the + /// largest integer register or illegal floating point types), this returns + /// the largest legal type it will be expanded to. EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { assert(!VT.isVector()); while (true) { @@ -328,24 +352,19 @@ public: } } - /// getVectorTypeBreakdown - Vector types are broken down into some number of - /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 - /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. - /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. + /// Vector types are broken down into some number of legal first class types. + /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 + /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 + /// turns into 4 EVT::i32 values with both PPC and X86. /// /// This method returns the number of registers needed, and the VT for each /// register. It also returns the VT and quantity of the intermediate values /// before they are promoted/expanded. - /// unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const; - /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the - /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If - /// this is the case, it returns true and store the intrinsic - /// information into the IntrinsicInfo that was passed to the function. struct IntrinsicInfo { unsigned opc; // target opcode EVT memVT; // memory VT @@ -357,45 +376,48 @@ public: bool writeMem; // writes memory? }; + /// Given an intrinsic, checks if on the target the intrinsic will need to map + /// to a MemIntrinsicNode (touches memory). If this is the case, it returns + /// true and store the intrinsic information into the IntrinsicInfo that was + /// passed to the function. virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned /*Intrinsic*/) const { return false; } - /// isFPImmLegal - Returns true if the target can instruction select the - /// specified FP immediate natively. If false, the legalizer will materialize - /// the FP immediate as a load from a constant pool. + /// Returns true if the target can instruction select the specified FP + /// immediate natively. If false, the legalizer will materialize the FP + /// immediate as a load from a constant pool. virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { return false; } - /// isShuffleMaskLegal - Targets can use this to indicate that they only - /// support *some* VECTOR_SHUFFLE operations, those with specific masks. - /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values - /// are assumed to be legal. + /// Targets can use this to indicate that they only support *some* + /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a + /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be + /// legal. virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, EVT /*VT*/) const { return true; } - /// canOpTrap - Returns true if the operation can trap for the value type. + /// Returns true if the operation can trap for the value type. + /// /// VT must be a legal type. By default, we optimistically assume most /// operations don't trap except for divide and remainder. virtual bool canOpTrap(unsigned Op, EVT VT) const; - /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is - /// used by Targets can use this to indicate if there is a suitable - /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant - /// pool entry. + /// Similar to isShuffleMaskLegal. This is used by Targets can use this to + /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace + /// a VAND with a constant pool entry. virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, EVT /*VT*/) const { return false; } - /// getOperationAction - Return how this operation should be treated: either - /// it is legal, needs to be promoted to a larger size, needs to be - /// expanded to some other code sequence, or the target has a custom expander - /// for it. + /// Return how this operation should be treated: either it is legal, needs to + /// be promoted to a larger size, needs to be expanded to some other code + /// sequence, or the target has a custom expander for it. LegalizeAction getOperationAction(unsigned Op, EVT VT) const { if (VT.isExtended()) return Expand; // If a target-specific SDNode requires legalization, require the target @@ -405,59 +427,55 @@ public: return (LegalizeAction)OpActions[I][Op]; } - /// isOperationLegalOrCustom - Return true if the specified operation is - /// legal on this target or can be made legal with custom lowering. This - /// is used to help guide high-level lowering decisions. + /// Return true if the specified operation is legal on this target or can be + /// made legal with custom lowering. This is used to help guide high-level + /// lowering decisions. bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { return (VT == MVT::Other || isTypeLegal(VT)) && (getOperationAction(Op, VT) == Legal || getOperationAction(Op, VT) == Custom); } - /// isOperationLegalOrPromote - Return true if the specified operation is - /// legal on this target or can be made legal using promotion. This - /// is used to help guide high-level lowering decisions. + /// Return true if the specified operation is legal on this target or can be + /// made legal using promotion. This is used to help guide high-level lowering + /// decisions. bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { return (VT == MVT::Other || isTypeLegal(VT)) && (getOperationAction(Op, VT) == Legal || getOperationAction(Op, VT) == Promote); } - /// isOperationExpand - Return true if the specified operation is illegal on - /// this target or unlikely to be made legal with custom lowering. This is - /// used to help guide high-level lowering decisions. + /// Return true if the specified operation is illegal on this target or + /// unlikely to be made legal with custom lowering. This is used to help guide + /// high-level lowering decisions. bool isOperationExpand(unsigned Op, EVT VT) const { return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); } - /// isOperationLegal - Return true if the specified operation is legal on this - /// target. + /// Return true if the specified operation is legal on this target. bool isOperationLegal(unsigned Op, EVT VT) const { return (VT == MVT::Other || isTypeLegal(VT)) && getOperationAction(Op, VT) == Legal; } - /// getLoadExtAction - Return how this load with extension should be treated: - /// either it is legal, needs to be promoted to a larger size, needs to be - /// expanded to some other code sequence, or the target has a custom expander - /// for it. + /// Return how this load with extension should be treated: either it is legal, + /// needs to be promoted to a larger size, needs to be expanded to some other + /// code sequence, or the target has a custom expander for it. LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && "Table isn't big enough!"); return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; } - /// isLoadExtLegal - Return true if the specified load with extension is legal - /// on this target. + /// Return true if the specified load with extension is legal on this target. bool isLoadExtLegal(unsigned ExtType, EVT VT) const { return VT.isSimple() && getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; } - /// getTruncStoreAction - Return how this store with truncation should be - /// treated: either it is legal, needs to be promoted to a larger size, needs - /// to be expanded to some other code sequence, or the target has a custom - /// expander for it. + /// Return how this store with truncation should be treated: either it is + /// legal, needs to be promoted to a larger size, needs to be expanded to some + /// other code sequence, or the target has a custom expander for it. LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && "Table isn't big enough!"); @@ -465,17 +483,16 @@ public: [MemVT.SimpleTy]; } - /// isTruncStoreLegal - Return true if the specified store with truncation is - /// legal on this target. + /// Return true if the specified store with truncation is legal on this + /// target. bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { return isTypeLegal(ValVT) && MemVT.isSimple() && getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; } - /// getIndexedLoadAction - Return how the indexed load should be treated: - /// either it is legal, needs to be promoted to a larger size, needs to be - /// expanded to some other code sequence, or the target has a custom expander - /// for it. + /// Return how the indexed load should be treated: either it is legal, needs + /// to be promoted to a larger size, needs to be expanded to some other code + /// sequence, or the target has a custom expander for it. LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const { assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && @@ -484,18 +501,16 @@ public: return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); } - /// isIndexedLoadLegal - Return true if the specified indexed load is legal - /// on this target. + /// Return true if the specified indexed load is legal on this target. bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { return VT.isSimple() && (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); } - /// getIndexedStoreAction - Return how the indexed store should be treated: - /// either it is legal, needs to be promoted to a larger size, needs to be - /// expanded to some other code sequence, or the target has a custom expander - /// for it. + /// Return how the indexed store should be treated: either it is legal, needs + /// to be promoted to a larger size, needs to be expanded to some other code + /// sequence, or the target has a custom expander for it. LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const { assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && @@ -504,33 +519,30 @@ public: return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); } - /// isIndexedStoreLegal - Return true if the specified indexed load is legal - /// on this target. + /// Return true if the specified indexed load is legal on this target. bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { return VT.isSimple() && (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); } - /// getCondCodeAction - Return how the condition code should be treated: - /// either it is legal, needs to be expanded to some other code sequence, - /// or the target has a custom expander for it. + /// Return how the condition code should be treated: either it is legal, needs + /// to be expanded to some other code sequence, or the target has a custom + /// expander for it. LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const { assert((unsigned)CC < array_lengthof(CondCodeActions) && - (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && + ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) && "Table isn't big enough!"); - /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit - /// value and the upper 27 bits index into the second dimension of the - /// array to select what 64bit value to use. - LegalizeAction Action = (LegalizeAction) - ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3); + // See setCondCodeAction for how this is encoded. + uint32_t Shift = 2 * (VT.SimpleTy & 0xF); + uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4]; + LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3); assert(Action != Promote && "Can't promote condition code!"); return Action; } - /// isCondCodeLegal - Return true if the specified condition code is legal - /// on this target. + /// Return true if the specified condition code is legal on this target. bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { return getCondCodeAction(CC, VT) == Legal || @@ -538,8 +550,8 @@ public: } - /// getTypeToPromoteTo - If the action for this operation is to promote, this - /// method returns the ValueType to promote to. + /// If the action for this operation is to promote, this method returns the + /// ValueType to promote to. MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { assert(getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"); @@ -563,20 +575,24 @@ public: return NVT; } - /// getValueType - Return the EVT corresponding to this LLVM type. - /// This is fixed by the LLVM operations except for the pointer size. If - /// AllowUnknown is true, this will return MVT::Other for types with no EVT - /// counterpart (e.g. structs), otherwise it will assert. + /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM + /// operations except for the pointer size. If AllowUnknown is true, this + /// will return MVT::Other for types with no EVT counterpart (e.g. structs), + /// otherwise it will assert. EVT getValueType(Type *Ty, bool AllowUnknown = false) const { // Lower scalar pointers to native pointer types. - if (Ty->isPointerTy()) return PointerTy; + if (PointerType *PTy = dyn_cast<PointerType>(Ty)) + return getPointerTy(PTy->getAddressSpace()); if (Ty->isVectorTy()) { VectorType *VTy = cast<VectorType>(Ty); Type *Elm = VTy->getElementType(); // Lower vectors of pointers to native pointer types. - if (Elm->isPointerTy()) - Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); + if (PointerType *PT = dyn_cast<PointerType>(Elm)) { + EVT PointerTy(getPointerTy(PT->getAddressSpace())); + Elm = PointerTy.getTypeForEVT(Ty->getContext()); + } + return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), VTy->getNumElements()); } @@ -588,20 +604,17 @@ public: return getValueType(Ty, AllowUnknown).getSimpleVT(); } - /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate - /// function arguments in the caller parameter area. This is the actual - /// alignment, not its logarithm. + /// Return the desired alignment for ByVal aggregate function arguments in the + /// caller parameter area. This is the actual alignment, not its logarithm. virtual unsigned getByValTypeAlignment(Type *Ty) const; - /// getRegisterType - Return the type of registers that this ValueType will - /// eventually require. + /// Return the type of registers that this ValueType will eventually require. MVT getRegisterType(MVT VT) const { assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); return RegisterTypeForVT[VT.SimpleTy]; } - /// getRegisterType - Return the type of registers that this ValueType will - /// eventually require. + /// Return the type of registers that this ValueType will eventually require. MVT getRegisterType(LLVMContext &Context, EVT VT) const { if (VT.isSimple()) { assert((unsigned)VT.getSimpleVT().SimpleTy < @@ -622,12 +635,14 @@ public: llvm_unreachable("Unsupported extended type!"); } - /// getNumRegisters - Return the number of registers that this ValueType will - /// eventually require. This is one for any types promoted to live in larger - /// registers, but may be more than one for types (like i64) that are split - /// into pieces. For types like i140, which are first promoted then expanded, - /// it is the number of registers needed to hold all the bits of the original - /// type. For an i140 on a 32 bit machine this means 5 registers. + /// Return the number of registers that this ValueType will eventually + /// require. + /// + /// This is one for any types promoted to live in larger registers, but may be + /// more than one for types (like i64) that are split into pieces. For types + /// like i140, which are first promoted then expanded, it is the number of + /// registers needed to hold all the bits of the original type. For an i140 + /// on a 32 bit machine this means 5 registers. unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { if (VT.isSimple()) { assert((unsigned)VT.getSimpleVT().SimpleTy < @@ -648,68 +663,72 @@ public: llvm_unreachable("Unsupported extended type!"); } - /// ShouldShrinkFPConstant - If true, then instruction selection should - /// seek to shrink the FP constant of the specified type to a smaller type - /// in order to save space and / or reduce runtime. + /// If true, then instruction selection should seek to shrink the FP constant + /// of the specified type to a smaller type in order to save space and / or + /// reduce runtime. virtual bool ShouldShrinkFPConstant(EVT) const { return true; } - /// hasTargetDAGCombine - If true, the target has custom DAG combine - /// transformations that it can perform for the specified node. + /// If true, the target has custom DAG combine transformations that it can + /// perform for the specified node. bool hasTargetDAGCombine(ISD::NodeType NT) const { assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); } + /// \brief Get maximum # of store operations permitted for llvm.memset + /// /// This function returns the maximum number of store operations permitted /// to replace a call to llvm.memset. The value is set by the target at the /// performance threshold for such a replacement. If OptSize is true, /// return the limit for functions that have OptSize attribute. - /// @brief Get maximum # of store operations permitted for llvm.memset unsigned getMaxStoresPerMemset(bool OptSize) const { return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; } + /// \brief Get maximum # of store operations permitted for llvm.memcpy + /// /// This function returns the maximum number of store operations permitted /// to replace a call to llvm.memcpy. The value is set by the target at the /// performance threshold for such a replacement. If OptSize is true, /// return the limit for functions that have OptSize attribute. - /// @brief Get maximum # of store operations permitted for llvm.memcpy unsigned getMaxStoresPerMemcpy(bool OptSize) const { return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; } + /// \brief Get maximum # of store operations permitted for llvm.memmove + /// /// This function returns the maximum number of store operations permitted /// to replace a call to llvm.memmove. The value is set by the target at the /// performance threshold for such a replacement. If OptSize is true, /// return the limit for functions that have OptSize attribute. - /// @brief Get maximum # of store operations permitted for llvm.memmove unsigned getMaxStoresPerMemmove(bool OptSize) const { return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; } + /// \brief Determine if the target supports unaligned memory accesses. + /// /// This function returns true if the target allows unaligned memory accesses. /// of the specified type. If true, it also returns whether the unaligned /// memory access is "fast" in the second argument by reference. This is used, - /// for example, in situations where an array copy/move/set is converted to a + /// for example, in situations where an array copy/move/set is converted to a /// sequence of store operations. It's use helps to ensure that such - /// replacements don't generate code that causes an alignment error (trap) on + /// replacements don't generate code that causes an alignment error (trap) on /// the target machine. - /// @brief Determine if the target supports unaligned memory accesses. - virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const { + virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) const { return false; } - /// getOptimalMemOpType - Returns the target specific optimal type for load - /// and store operations as a result of memset, memcpy, and memmove - /// lowering. If DstAlign is zero that means it's safe to destination - /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it - /// means there isn't a need to check it against alignment requirement, - /// probably because the source does not need to be loaded. If 'IsMemset' is - /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that - /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy - /// source is constant so it does not need to be loaded. - /// It returns EVT::Other if the type should be determined using generic - /// target-independent logic. + /// Returns the target specific optimal type for load and store operations as + /// a result of memset, memcpy, and memmove lowering. + /// + /// If DstAlign is zero that means it's safe to destination alignment can + /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't + /// a need to check it against alignment requirement, probably because the + /// source does not need to be loaded. If 'IsMemset' is true, that means it's + /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of + /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it + /// does not need to be loaded. It returns EVT::Other if the type should be + /// determined using generic target-independent logic. virtual EVT getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/, unsigned /*SrcAlign*/, bool /*IsMemset*/, @@ -719,119 +738,111 @@ public: return MVT::Other; } - /// isSafeMemOpType - Returns true if it's safe to use load / store of the - /// specified type to expand memcpy / memset inline. This is mostly true - /// for all types except for some special cases. For example, on X86 - /// targets without SSE2 f64 load / store are done with fldl / fstpl which - /// also does type conversion. Note the specified type doesn't have to be - /// legal as the hook is used before type legalization. - virtual bool isSafeMemOpType(MVT VT) const { - return true; - } + /// Returns true if it's safe to use load / store of the specified type to + /// expand memcpy / memset inline. + /// + /// This is mostly true for all types except for some special cases. For + /// example, on X86 targets without SSE2 f64 load / store are done with fldl / + /// fstpl which also does type conversion. Note the specified type doesn't + /// have to be legal as the hook is used before type legalization. + virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; } - /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp - /// to implement llvm.setjmp. + /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp. bool usesUnderscoreSetJmp() const { return UseUnderscoreSetJmp; } - /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp - /// to implement llvm.longjmp. + /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp. bool usesUnderscoreLongJmp() const { return UseUnderscoreLongJmp; } - /// supportJumpTables - return whether the target can generate code for - /// jump tables. + /// Return whether the target can generate code for jump tables. bool supportJumpTables() const { return SupportJumpTables; } - /// getMinimumJumpTableEntries - return integer threshold on number of - /// blocks to use jump tables rather than if sequence. + /// Return integer threshold on number of blocks to use jump tables rather + /// than if sequence. int getMinimumJumpTableEntries() const { return MinimumJumpTableEntries; } - /// getStackPointerRegisterToSaveRestore - If a physical register, this - /// specifies the register that llvm.savestack/llvm.restorestack should save - /// and restore. + /// If a physical register, this specifies the register that + /// llvm.savestack/llvm.restorestack should save and restore. unsigned getStackPointerRegisterToSaveRestore() const { return StackPointerRegisterToSaveRestore; } - /// getExceptionPointerRegister - If a physical register, this returns - /// the register that receives the exception address on entry to a landing - /// pad. + /// If a physical register, this returns the register that receives the + /// exception address on entry to a landing pad. unsigned getExceptionPointerRegister() const { return ExceptionPointerRegister; } - /// getExceptionSelectorRegister - If a physical register, this returns - /// the register that receives the exception typeid on entry to a landing - /// pad. + /// If a physical register, this returns the register that receives the + /// exception typeid on entry to a landing pad. unsigned getExceptionSelectorRegister() const { return ExceptionSelectorRegister; } - /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never - /// set, the default is 200) + /// Returns the target's jmp_buf size in bytes (if never set, the default is + /// 200) unsigned getJumpBufSize() const { return JumpBufSize; } - /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes - /// (if never set, the default is 0) + /// Returns the target's jmp_buf alignment in bytes (if never set, the default + /// is 0) unsigned getJumpBufAlignment() const { return JumpBufAlignment; } - /// getMinStackArgumentAlignment - return the minimum stack alignment of an - /// argument. + /// Return the minimum stack alignment of an argument. unsigned getMinStackArgumentAlignment() const { return MinStackArgumentAlignment; } - /// getMinFunctionAlignment - return the minimum function alignment. - /// + /// Return the minimum function alignment. unsigned getMinFunctionAlignment() const { return MinFunctionAlignment; } - /// getPrefFunctionAlignment - return the preferred function alignment. - /// + /// Return the preferred function alignment. unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; } - /// getPrefLoopAlignment - return the preferred loop alignment. - /// + /// Return the preferred loop alignment. unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; } - /// getInsertFencesFor - return whether the DAG builder should automatically - /// insert fences and reduce ordering for atomics. - /// + /// Return whether the DAG builder should automatically insert fences and + /// reduce ordering for atomics. bool getInsertFencesForAtomic() const { return InsertFencesForAtomic; } - /// getStackCookieLocation - Return true if the target stores stack - /// protector cookies at a fixed offset in some non-standard address - /// space, and populates the address space and offset as - /// appropriate. + /// Return true if the target stores stack protector cookies at a fixed offset + /// in some non-standard address space, and populates the address space and + /// offset as appropriate. virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, unsigned &/*Offset*/) const { return false; } - /// getMaximalGlobalOffset - Returns the maximal possible offset which can be - /// used for loads / stores from the global. + /// Returns the maximal possible offset which can be used for loads / stores + /// from the global. virtual unsigned getMaximalGlobalOffset() const { return 0; } + /// Returns true if a cast between SrcAS and DestAS is a noop. + virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const { + return false; + } + //===--------------------------------------------------------------------===// /// \name Helpers for TargetTransformInfo implementations /// @{ @@ -853,106 +864,98 @@ public: virtual void resetOperationActions() {} protected: - /// setBooleanContents - Specify how the target extends the result of a - /// boolean value from i1 to a wider type. See getBooleanContents. + /// Specify how the target extends the result of a boolean value from i1 to a + /// wider type. See getBooleanContents. void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } - /// setBooleanVectorContents - Specify how the target extends the result - /// of a vector boolean value from a vector of i1 to a wider type. See - /// getBooleanContents. + + /// Specify how the target extends the result of a vector boolean value from a + /// vector of i1 to a wider type. See getBooleanContents. void setBooleanVectorContents(BooleanContent Ty) { BooleanVectorContents = Ty; } - /// setSchedulingPreference - Specify the target scheduling preference. + /// Specify the target scheduling preference. void setSchedulingPreference(Sched::Preference Pref) { SchedPreferenceInfo = Pref; } - /// setUseUnderscoreSetJmp - Indicate whether this target prefers to - /// use _setjmp to implement llvm.setjmp or the non _ version. - /// Defaults to false. + /// Indicate whether this target prefers to use _setjmp to implement + /// llvm.setjmp or the non _ version. Defaults to false. void setUseUnderscoreSetJmp(bool Val) { UseUnderscoreSetJmp = Val; } - /// setUseUnderscoreLongJmp - Indicate whether this target prefers to - /// use _longjmp to implement llvm.longjmp or the non _ version. - /// Defaults to false. + /// Indicate whether this target prefers to use _longjmp to implement + /// llvm.longjmp or the non _ version. Defaults to false. void setUseUnderscoreLongJmp(bool Val) { UseUnderscoreLongJmp = Val; } - /// setSupportJumpTables - Indicate whether the target can generate code for - /// jump tables. + /// Indicate whether the target can generate code for jump tables. void setSupportJumpTables(bool Val) { SupportJumpTables = Val; } - /// setMinimumJumpTableEntries - Indicate the number of blocks to generate - /// jump tables rather than if sequence. + /// Indicate the number of blocks to generate jump tables rather than if + /// sequence. void setMinimumJumpTableEntries(int Val) { MinimumJumpTableEntries = Val; } - /// setStackPointerRegisterToSaveRestore - If set to a physical register, this - /// specifies the register that llvm.savestack/llvm.restorestack should save - /// and restore. + /// If set to a physical register, this specifies the register that + /// llvm.savestack/llvm.restorestack should save and restore. void setStackPointerRegisterToSaveRestore(unsigned R) { StackPointerRegisterToSaveRestore = R; } - /// setExceptionPointerRegister - If set to a physical register, this sets - /// the register that receives the exception address on entry to a landing - /// pad. + /// If set to a physical register, this sets the register that receives the + /// exception address on entry to a landing pad. void setExceptionPointerRegister(unsigned R) { ExceptionPointerRegister = R; } - /// setExceptionSelectorRegister - If set to a physical register, this sets - /// the register that receives the exception typeid on entry to a landing - /// pad. + /// If set to a physical register, this sets the register that receives the + /// exception typeid on entry to a landing pad. void setExceptionSelectorRegister(unsigned R) { ExceptionSelectorRegister = R; } - /// SelectIsExpensive - Tells the code generator not to expand operations - /// into sequences that use the select operations if possible. + /// Tells the code generator not to expand operations into sequences that use + /// the select operations if possible. void setSelectIsExpensive(bool isExpensive = true) { SelectIsExpensive = isExpensive; } - /// JumpIsExpensive - Tells the code generator not to expand sequence of - /// operations into a separate sequences that increases the amount of - /// flow control. + /// Tells the code generator not to expand sequence of operations into a + /// separate sequences that increases the amount of flow control. void setJumpIsExpensive(bool isExpensive = true) { JumpIsExpensive = isExpensive; } - /// setIntDivIsCheap - Tells the code generator that integer divide is - /// expensive, and if possible, should be replaced by an alternate sequence - /// of instructions not containing an integer divide. + /// Tells the code generator that integer divide is expensive, and if + /// possible, should be replaced by an alternate sequence of instructions not + /// containing an integer divide. void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } - /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. + /// Tells the code generator which bitwidths to bypass. void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; } - /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate - /// srl/add/sra for a signed divide by power of two, and let the target handle - /// it. + /// Tells the code generator that it shouldn't generate srl/add/sra for a + /// signed divide by power of two, and let the target handle it. void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } - /// addRegisterClass - Add the specified register class as an available - /// regclass for the specified value type. This indicates the selector can - /// handle values of that class natively. + /// Add the specified register class as an available regclass for the + /// specified value type. This indicates the selector can handle values of + /// that class natively. void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); AvailableRegClasses.push_back(std::make_pair(VT, RC)); RegClassForVT[VT.SimpleTy] = RC; } - /// clearRegisterClasses - Remove all register classes. + /// Remove all register classes. void clearRegisterClasses() { memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); @@ -963,25 +966,25 @@ protected: void clearOperationActions() { } - /// findRepresentativeClass - Return the largest legal super-reg register class - /// of the register class for the specified type and its associated "cost". + /// Return the largest legal super-reg register class of the register class + /// for the specified type and its associated "cost". virtual std::pair<const TargetRegisterClass*, uint8_t> findRepresentativeClass(MVT VT) const; - /// computeRegisterProperties - Once all of the register classes are added, - /// this allows us to compute derived properties we expose. + /// Once all of the register classes are added, this allows us to compute + /// derived properties we expose. void computeRegisterProperties(); - /// setOperationAction - Indicate that the specified operation does not work - /// with the specified type and indicate what to do about it. + /// Indicate that the specified operation does not work with the specified + /// type and indicate what to do about it. void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) { assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; } - /// setLoadExtAction - Indicate that the specified load with extension does - /// not work with the specified type and indicate what to do about it. + /// Indicate that the specified load with extension does not work with the + /// specified type and indicate what to do about it. void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action) { assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && @@ -989,8 +992,8 @@ protected: LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; } - /// setTruncStoreAction - Indicate that the specified truncating store does - /// not work with the specified type and indicate what to do about it. + /// Indicate that the specified truncating store does not work with the + /// specified type and indicate what to do about it. void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) { assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && @@ -998,9 +1001,10 @@ protected: TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; } - /// setIndexedLoadAction - Indicate that the specified indexed load does or - /// does not work with the specified type and indicate what to do abort - /// it. NOTE: All indexed mode loads are initialized to Expand in + /// Indicate that the specified indexed load does or does not work with the + /// specified type and indicate what to do abort it. + /// + /// NOTE: All indexed mode loads are initialized to Expand in /// TargetLowering.cpp void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { @@ -1011,9 +1015,10 @@ protected: IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; } - /// setIndexedStoreAction - Indicate that the specified indexed store does or - /// does not work with the specified type and indicate what to do about - /// it. NOTE: All indexed mode stores are initialized to Expand in + /// Indicate that the specified indexed store does or does not work with the + /// specified type and indicate what to do about it. + /// + /// NOTE: All indexed mode stores are initialized to Expand in /// TargetLowering.cpp void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { @@ -1024,79 +1029,74 @@ protected: IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); } - /// setCondCodeAction - Indicate that the specified condition code is or isn't - /// supported on the target and indicate what to do about it. + /// Indicate that the specified condition code is or isn't supported on the + /// target and indicate what to do about it. void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { assert(VT < MVT::LAST_VALUETYPE && (unsigned)CC < array_lengthof(CondCodeActions) && "Table isn't big enough!"); - /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit - /// value and the upper 27 bits index into the second dimension of the - /// array to select what 64bit value to use. - CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] - &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); - CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] - |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; - } - - /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the - /// promotion code defaults to trying a larger integer/fp until it can find - /// one that works. If that default is insufficient, this method can be used - /// by the target to override the default. + /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit + /// value and the upper 27 bits index into the second dimension of the array + /// to select what 32-bit value to use. + uint32_t Shift = 2 * (VT.SimpleTy & 0xF); + CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift); + CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift; + } + + /// If Opc/OrigVT is specified as being promoted, the promotion code defaults + /// to trying a larger integer/fp until it can find one that works. If that + /// default is insufficient, this method can be used by the target to override + /// the default. void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; } - /// setTargetDAGCombine - Targets should invoke this method for each target - /// independent node that they want to provide a custom DAG combiner for by - /// implementing the PerformDAGCombine virtual method. + /// Targets should invoke this method for each target independent node that + /// they want to provide a custom DAG combiner for by implementing the + /// PerformDAGCombine virtual method. void setTargetDAGCombine(ISD::NodeType NT) { assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); } - /// setJumpBufSize - Set the target's required jmp_buf buffer size (in - /// bytes); default is 200 + /// Set the target's required jmp_buf buffer size (in bytes); default is 200 void setJumpBufSize(unsigned Size) { JumpBufSize = Size; } - /// setJumpBufAlignment - Set the target's required jmp_buf buffer - /// alignment (in bytes); default is 0 + /// Set the target's required jmp_buf buffer alignment (in bytes); default is + /// 0 void setJumpBufAlignment(unsigned Align) { JumpBufAlignment = Align; } - /// setMinFunctionAlignment - Set the target's minimum function alignment (in - /// log2(bytes)) + /// Set the target's minimum function alignment (in log2(bytes)) void setMinFunctionAlignment(unsigned Align) { MinFunctionAlignment = Align; } - /// setPrefFunctionAlignment - Set the target's preferred function alignment. - /// This should be set if there is a performance benefit to - /// higher-than-minimum alignment (in log2(bytes)) + /// Set the target's preferred function alignment. This should be set if + /// there is a performance benefit to higher-than-minimum alignment (in + /// log2(bytes)) void setPrefFunctionAlignment(unsigned Align) { PrefFunctionAlignment = Align; } - /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default - /// alignment is zero, it means the target does not care about loop alignment. - /// The alignment is specified in log2(bytes). + /// Set the target's preferred loop alignment. Default alignment is zero, it + /// means the target does not care about loop alignment. The alignment is + /// specified in log2(bytes). void setPrefLoopAlignment(unsigned Align) { PrefLoopAlignment = Align; } - /// setMinStackArgumentAlignment - Set the minimum stack alignment of an - /// argument (in log2(bytes)). + /// Set the minimum stack alignment of an argument (in log2(bytes)). void setMinStackArgumentAlignment(unsigned Align) { MinStackArgumentAlignment = Align; } - /// setInsertFencesForAtomic - Set if the DAG builder should - /// automatically insert fences and reduce the order of atomic memory - /// operations to Monotonic. + /// Set if the DAG builder should automatically insert fences and reduce the + /// order of atomic memory operations to Monotonic. void setInsertFencesForAtomic(bool fence) { InsertFencesForAtomic = fence; } @@ -1106,25 +1106,24 @@ public: // Addressing mode description hooks (used by LSR etc). // - /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the - /// same BB as Load/Store instructions reading the address. This allows as - /// much computation as possible to be done in the address mode for that - /// operand. This hook lets targets also pass back when this should be done - /// on intrinsics which load/store. - virtual bool GetAddrModeArguments(IntrinsicInst *I, - SmallVectorImpl<Value*> &Ops, - Type *&AccessTy) const { + /// CodeGenPrepare sinks address calculations into the same BB as Load/Store + /// instructions reading the address. This allows as much computation as + /// possible to be done in the address mode for that operand. This hook lets + /// targets also pass back when this should be done on intrinsics which + /// load/store. + virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/, + SmallVectorImpl<Value*> &/*Ops*/, + Type *&/*AccessTy*/) const { return false; } - /// AddrMode - This represents an addressing mode of: + /// This represents an addressing mode of: /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg /// If BaseGV is null, there is no BaseGV. /// If BaseOffs is zero, there is no base offset. /// If HasBaseReg is false, there is no base register. /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with /// no scale. - /// struct AddrMode { GlobalValue *BaseGV; int64_t BaseOffs; @@ -1133,48 +1132,68 @@ public: AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} }; - /// isLegalAddressingMode - Return true if the addressing mode represented by - /// AM is legal for this target, for a load/store of the specified type. + /// Return true if the addressing mode represented by AM is legal for this + /// target, for a load/store of the specified type. + /// /// The type may be VoidTy, in which case only return true if the addressing - /// mode is legal for a load/store of any legal type. - /// TODO: Handle pre/postinc as well. + /// mode is legal for a load/store of any legal type. TODO: Handle + /// pre/postinc as well. virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; - /// isLegalICmpImmediate - Return true if the specified immediate is legal - /// icmp immediate, that is the target has icmp instructions which can compare - /// a register against the immediate without having to materialize the - /// immediate into a register. + /// \brief Return the cost of the scaling factor used in the addressing mode + /// represented by AM for this target, for a load/store of the specified type. + /// + /// If the AM is supported, the return value must be >= 0. + /// If the AM is not supported, it returns a negative value. + /// TODO: Handle pre/postinc as well. + virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const { + // Default: assume that any scaling factor used in a legal AM is free. + if (isLegalAddressingMode(AM, Ty)) return 0; + return -1; + } + + /// Return true if the specified immediate is legal icmp immediate, that is + /// the target has icmp instructions which can compare a register against the + /// immediate without having to materialize the immediate into a register. virtual bool isLegalICmpImmediate(int64_t) const { return true; } - /// isLegalAddImmediate - Return true if the specified immediate is legal - /// add immediate, that is the target has add instructions which can add - /// a register with the immediate without having to materialize the - /// immediate into a register. + /// Return true if the specified immediate is legal add immediate, that is the + /// target has add instructions which can add a register with the immediate + /// without having to materialize the immediate into a register. virtual bool isLegalAddImmediate(int64_t) const { return true; } - /// isTruncateFree - Return true if it's free to truncate a value of - /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in - /// register EAX to i16 by referencing its sub-register AX. + /// Return true if it's free to truncate a value of type Ty1 to type + /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 + /// by referencing its sub-register AX. virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { return false; } + /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding + /// whether a call is in tail position. Typically this means that both results + /// would be assigned to the same register or stack slot, but it could mean + /// the target performs adequate checks of its own before proceeding with the + /// tail call. + virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const { + return false; + } + virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { return false; } - /// isZExtFree - Return true if any actual instruction that defines a - /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result - /// register. This does not necessarily include registers defined in - /// unknown ways, such as incoming arguments, or copies from unknown - /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this - /// does not necessarily apply to truncate instructions. e.g. on x86-64, - /// all instructions that define 32-bit values implicit zero-extend the - /// result out to 64 bits. + /// Return true if any actual instruction that defines a value of type Ty1 + /// implicitly zero-extends the value to Ty2 in the result register. + /// + /// This does not necessarily include registers defined in unknown ways, such + /// as incoming arguments, or copies from unknown virtual registers. Also, if + /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to + /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit + /// values implicit zero-extend the result out to 64 bits. virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { return false; } @@ -1183,36 +1202,73 @@ public: return false; } - /// isZExtFree - Return true if zero-extending the specific node Val to type - /// VT2 is free (either because it's implicitly zero-extended such as ARM - /// ldrb / ldrh or because it's folded such as X86 zero-extending loads). + /// Return true if the target supplies and combines to a paired load + /// two loaded values of type LoadedType next to each other in memory. + /// RequiredAlignment gives the minimal alignment constraints that must be met + /// to be able to select this paired load. + /// + /// This information is *not* used to generate actual paired loads, but it is + /// used to generate a sequence of loads that is easier to combine into a + /// paired load. + /// For instance, something like this: + /// a = load i64* addr + /// b = trunc i64 a to i32 + /// c = lshr i64 a, 32 + /// d = trunc i64 c to i32 + /// will be optimized into: + /// b = load i32* addr1 + /// d = load i32* addr2 + /// Where addr1 = addr2 +/- sizeof(i32). + /// + /// In other words, unless the target performs a post-isel load combining, + /// this information should not be provided because it will generate more + /// loads. + virtual bool hasPairedLoad(Type * /*LoadedType*/, + unsigned & /*RequiredAligment*/) const { + return false; + } + + virtual bool hasPairedLoad(EVT /*LoadedType*/, + unsigned & /*RequiredAligment*/) const { + return false; + } + + /// Return true if zero-extending the specific node Val to type VT2 is free + /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or + /// because it's folded such as X86 zero-extending loads). virtual bool isZExtFree(SDValue Val, EVT VT2) const { return isZExtFree(Val.getValueType(), VT2); } - /// isFNegFree - Return true if an fneg operation is free to the point where - /// it is never worthwhile to replace it with a bitwise operation. - virtual bool isFNegFree(EVT) const { + /// Return true if an fneg operation is free to the point where it is never + /// worthwhile to replace it with a bitwise operation. + virtual bool isFNegFree(EVT VT) const { + assert(VT.isFloatingPoint()); return false; } - /// isFAbsFree - Return true if an fneg operation is free to the point where - /// it is never worthwhile to replace it with a bitwise operation. - virtual bool isFAbsFree(EVT) const { + /// Return true if an fabs operation is free to the point where it is never + /// worthwhile to replace it with a bitwise operation. + virtual bool isFAbsFree(EVT VT) const { + assert(VT.isFloatingPoint()); return false; } - /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than - /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to - /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd - /// is expanded to mul + add. - virtual bool isFMAFasterThanMulAndAdd(EVT) const { + /// Return true if an FMA operation is faster than a pair of fmul and fadd + /// instructions. fmuladd intrinsics will be expanded to FMAs when this method + /// returns true, otherwise fmuladd is expanded to fmul + fadd. + /// + /// NOTE: This may be called before legalization on types for which FMAs are + /// not legal, but should return true if those types will eventually legalize + /// to types that support FMAs. After legalization, it will only be called on + /// types that support FMAs (via Legal or Custom actions) + virtual bool isFMAFasterThanFMulAndFAdd(EVT) const { return false; } - /// isNarrowingProfitable - Return true if it's profitable to narrow - /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow - /// from i32 to i8 but not from i32 to i16. + /// Return true if it's profitable to narrow operations of type VT1 to + /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from + /// i32 to i16. virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { return false; } @@ -1221,38 +1277,34 @@ public: // Runtime Library hooks // - /// setLibcallName - Rename the default libcall routine name for the specified - /// libcall. + /// Rename the default libcall routine name for the specified libcall. void setLibcallName(RTLIB::Libcall Call, const char *Name) { LibcallRoutineNames[Call] = Name; } - /// getLibcallName - Get the libcall routine name for the specified libcall. - /// + /// Get the libcall routine name for the specified libcall. const char *getLibcallName(RTLIB::Libcall Call) const { return LibcallRoutineNames[Call]; } - /// setCmpLibcallCC - Override the default CondCode to be used to test the - /// result of the comparison libcall against zero. + /// Override the default CondCode to be used to test the result of the + /// comparison libcall against zero. void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { CmpLibcallCCs[Call] = CC; } - /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of - /// the comparison libcall against zero. + /// Get the CondCode that's to be used to test the result of the comparison + /// libcall against zero. ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { return CmpLibcallCCs[Call]; } - /// setLibcallCallingConv - Set the CallingConv that should be used for the - /// specified libcall. + /// Set the CallingConv that should be used for the specified libcall. void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { LibcallCallingConvs[Call] = CC; } - /// getLibcallCallingConv - Get the CallingConv that should be used for the - /// specified libcall. + /// Get the CallingConv that should be used for the specified libcall. CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { return LibcallCallingConvs[Call]; } @@ -1262,172 +1314,157 @@ private: const DataLayout *TD; const TargetLoweringObjectFile &TLOF; - /// PointerTy - The type to use for pointers for the default address space, - /// usually i32 or i64. - /// - MVT PointerTy; - - /// IsLittleEndian - True if this is a little endian target. - /// + /// True if this is a little endian target. bool IsLittleEndian; - /// SelectIsExpensive - Tells the code generator not to expand operations - /// into sequences that use the select operations if possible. + /// Tells the code generator not to expand operations into sequences that use + /// the select operations if possible. bool SelectIsExpensive; - /// IntDivIsCheap - Tells the code generator not to expand integer divides by - /// constants into a sequence of muls, adds, and shifts. This is a hack until - /// a real cost model is in place. If we ever optimize for size, this will be - /// set to true unconditionally. + /// Tells the code generator not to expand integer divides by constants into a + /// sequence of muls, adds, and shifts. This is a hack until a real cost + /// model is in place. If we ever optimize for size, this will be set to true + /// unconditionally. bool IntDivIsCheap; - /// BypassSlowDivMap - Tells the code generator to bypass slow divide or - /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the - /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned - /// integer div/rem when the operands are positive and less than 256. + /// Tells the code generator to bypass slow divide or remainder + /// instructions. For example, BypassSlowDivWidths[32,8] tells the code + /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer + /// div/rem when the operands are positive and less than 256. DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; - /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate - /// srl/add/sra for a signed divide by power of two, and let the target handle - /// it. + /// Tells the code generator that it shouldn't generate srl/add/sra for a + /// signed divide by power of two, and let the target handle it. bool Pow2DivIsCheap; - /// JumpIsExpensive - Tells the code generator that it shouldn't generate - /// extra flow control instructions and should attempt to combine flow - /// control instructions via predication. + /// Tells the code generator that it shouldn't generate extra flow control + /// instructions and should attempt to combine flow control instructions via + /// predication. bool JumpIsExpensive; - /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement - /// llvm.setjmp. Defaults to false. + /// This target prefers to use _setjmp to implement llvm.setjmp. + /// + /// Defaults to false. bool UseUnderscoreSetJmp; - /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement - /// llvm.longjmp. Defaults to false. + /// This target prefers to use _longjmp to implement llvm.longjmp. + /// + /// Defaults to false. bool UseUnderscoreLongJmp; - /// SupportJumpTables - Whether the target can generate code for jumptables. - /// If it's not true, then each jumptable must be lowered into if-then-else's. + /// Whether the target can generate code for jumptables. If it's not true, + /// then each jumptable must be lowered into if-then-else's. bool SupportJumpTables; - /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. + /// Number of blocks threshold to use jump tables. int MinimumJumpTableEntries; - /// BooleanContents - Information about the contents of the high-bits in - /// boolean values held in a type wider than i1. See getBooleanContents. + /// Information about the contents of the high-bits in boolean values held in + /// a type wider than i1. See getBooleanContents. BooleanContent BooleanContents; - /// BooleanVectorContents - Information about the contents of the high-bits - /// in boolean vector values when the element type is wider than i1. See - /// getBooleanContents. + + /// Information about the contents of the high-bits in boolean vector values + /// when the element type is wider than i1. See getBooleanContents. BooleanContent BooleanVectorContents; - /// SchedPreferenceInfo - The target scheduling preference: shortest possible - /// total cycles or lowest register usage. + /// The target scheduling preference: shortest possible total cycles or lowest + /// register usage. Sched::Preference SchedPreferenceInfo; - /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers + /// The size, in bytes, of the target's jmp_buf buffers unsigned JumpBufSize; - /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf - /// buffers + /// The alignment, in bytes, of the target's jmp_buf buffers unsigned JumpBufAlignment; - /// MinStackArgumentAlignment - The minimum alignment that any argument - /// on the stack needs to have. - /// + /// The minimum alignment that any argument on the stack needs to have. unsigned MinStackArgumentAlignment; - /// MinFunctionAlignment - The minimum function alignment (used when - /// optimizing for size, and to prevent explicitly provided alignment - /// from leading to incorrect code). - /// + /// The minimum function alignment (used when optimizing for size, and to + /// prevent explicitly provided alignment from leading to incorrect code). unsigned MinFunctionAlignment; - /// PrefFunctionAlignment - The preferred function alignment (used when - /// alignment unspecified and optimizing for speed). - /// + /// The preferred function alignment (used when alignment unspecified and + /// optimizing for speed). unsigned PrefFunctionAlignment; - /// PrefLoopAlignment - The preferred loop alignment. - /// + /// The preferred loop alignment. unsigned PrefLoopAlignment; - /// InsertFencesForAtomic - Whether the DAG builder should automatically - /// insert fences and reduce ordering for atomics. (This will be set for - /// for most architectures with weak memory ordering.) + /// Whether the DAG builder should automatically insert fences and reduce + /// ordering for atomics. (This will be set for for most architectures with + /// weak memory ordering.) bool InsertFencesForAtomic; - /// StackPointerRegisterToSaveRestore - If set to a physical register, this - /// specifies the register that llvm.savestack/llvm.restorestack should save - /// and restore. + /// If set to a physical register, this specifies the register that + /// llvm.savestack/llvm.restorestack should save and restore. unsigned StackPointerRegisterToSaveRestore; - /// ExceptionPointerRegister - If set to a physical register, this specifies - /// the register that receives the exception address on entry to a landing - /// pad. + /// If set to a physical register, this specifies the register that receives + /// the exception address on entry to a landing pad. unsigned ExceptionPointerRegister; - /// ExceptionSelectorRegister - If set to a physical register, this specifies - /// the register that receives the exception typeid on entry to a landing - /// pad. + /// If set to a physical register, this specifies the register that receives + /// the exception typeid on entry to a landing pad. unsigned ExceptionSelectorRegister; - /// RegClassForVT - This indicates the default register class to use for - /// each ValueType the target supports natively. + /// This indicates the default register class to use for each ValueType the + /// target supports natively. const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; - /// RepRegClassForVT - This indicates the "representative" register class to - /// use for each ValueType the target supports natively. This information is - /// used by the scheduler to track register pressure. By default, the - /// representative register class is the largest legal super-reg register - /// class of the register class of the specified type. e.g. On x86, i8, i16, - /// and i32's representative class would be GR32. + /// This indicates the "representative" register class to use for each + /// ValueType the target supports natively. This information is used by the + /// scheduler to track register pressure. By default, the representative + /// register class is the largest legal super-reg register class of the + /// register class of the specified type. e.g. On x86, i8, i16, and i32's + /// representative class would be GR32. const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; - /// RepRegClassCostForVT - This indicates the "cost" of the "representative" - /// register class for each ValueType. The cost is used by the scheduler to - /// approximate register pressure. + /// This indicates the "cost" of the "representative" register class for each + /// ValueType. The cost is used by the scheduler to approximate register + /// pressure. uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; - /// TransformToType - For any value types we are promoting or expanding, this - /// contains the value type that we are changing to. For Expanded types, this - /// contains one step of the expand (e.g. i64 -> i32), even if there are - /// multiple steps required (e.g. i64 -> i16). For types natively supported - /// by the system, this holds the same type (e.g. i32 -> i32). + /// For any value types we are promoting or expanding, this contains the value + /// type that we are changing to. For Expanded types, this contains one step + /// of the expand (e.g. i64 -> i32), even if there are multiple steps required + /// (e.g. i64 -> i16). For types natively supported by the system, this holds + /// the same type (e.g. i32 -> i32). MVT TransformToType[MVT::LAST_VALUETYPE]; - /// OpActions - For each operation and each value type, keep a LegalizeAction - /// that indicates how instruction selection should deal with the operation. - /// Most operations are Legal (aka, supported natively by the target), but + /// For each operation and each value type, keep a LegalizeAction that + /// indicates how instruction selection should deal with the operation. Most + /// operations are Legal (aka, supported natively by the target), but /// operations that are not should be described. Note that operations on /// non-legal value types are not described here. uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; - /// LoadExtActions - For each load extension type and each value type, - /// keep a LegalizeAction that indicates how instruction selection should deal - /// with a load of a specific value type and extension type. + /// For each load extension type and each value type, keep a LegalizeAction + /// that indicates how instruction selection should deal with a load of a + /// specific value type and extension type. uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; - /// TruncStoreActions - For each value type pair keep a LegalizeAction that - /// indicates whether a truncating store of a specific value type and - /// truncating type is legal. + /// For each value type pair keep a LegalizeAction that indicates whether a + /// truncating store of a specific value type and truncating type is legal. uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; - /// IndexedModeActions - For each indexed mode and each value type, - /// keep a pair of LegalizeAction that indicates how instruction - /// selection should deal with the load / store. The first dimension is the - /// value_type for the reference. The second dimension represents the various - /// modes for load store. + /// For each indexed mode and each value type, keep a pair of LegalizeAction + /// that indicates how instruction selection should deal with the load / + /// store. + /// + /// The first dimension is the value_type for the reference. The second + /// dimension represents the various modes for load store. uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; - /// CondCodeActions - For each condition code (ISD::CondCode) keep a - /// LegalizeAction that indicates how instruction selection should - /// deal with the condition code. - /// Because each CC action takes up 2 bits, we need to have the array size - /// be large enough to fit all of the value types. This can be done by - /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. - uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; + /// For each condition code (ISD::CondCode) keep a LegalizeAction that + /// indicates how instruction selection should deal with the condition code. + /// + /// Because each CC action takes up 2 bits, we need to have the array size be + /// large enough to fit all of the value types. This can be done by rounding + /// up the MVT::LAST_VALUETYPE value to the next multiple of 16. + uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16]; ValueTypeActionImpl ValueTypeActions; @@ -1482,10 +1519,12 @@ public: if (NumElts == 1) return LegalizeKind(TypeScalarizeVector, EltVT); - // Try to widen vector elements until a legal type is found. + // Try to widen vector elements until the element type is a power of two and + // promote it to a legal type later on, for example: + // <3 x i8> -> <4 x i8> -> <4 x i32> if (EltVT.isInteger()) { // Vectors with a number of elements that is not a power of two are always - // widened, for example <3 x float> -> <4 x float>. + // widened, for example <3 x i8> -> <4 x i8>. if (!VT.isPow2VectorType()) { NumElts = (unsigned)NextPowerOf2(NumElts); EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); @@ -1514,7 +1553,8 @@ public: // Stop trying when getting a non-simple element type. // Note that vector elements may be greater than legal vector element - // types. Example: X86 XMM registers hold 64bit element on 32bit systems. + // types. Example: X86 XMM registers hold 64bit element on 32bit + // systems. if (!EltVT.isSimple()) break; // Build a new vector type and check if it is legal. @@ -1562,34 +1602,34 @@ public: private: std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; - /// TargetDAGCombineArray - Targets can specify ISD nodes that they would - /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), - /// which sets a bit in this array. + /// Targets can specify ISD nodes that they would like PerformDAGCombine + /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this + /// array. unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; - /// PromoteToType - For operations that must be promoted to a specific type, - /// this holds the destination type. This map should be sparse, so don't hold - /// it as an array. + /// For operations that must be promoted to a specific type, this holds the + /// destination type. This map should be sparse, so don't hold it as an + /// array. /// /// Targets add entries to this map with AddPromotedToType(..), clients access /// this with getTypeToPromoteTo(..). std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> PromoteToType; - /// LibcallRoutineNames - Stores the name each libcall. - /// + /// Stores the name each libcall. const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; - /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result - /// of each of the comparison libcall against zero. + /// The ISD::CondCode that should be used to test the result of each of the + /// comparison libcall against zero. ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; - /// LibcallCallingConvs - Stores the CallingConv that should be used for each - /// libcall. + /// Stores the CallingConv that should be used for each libcall. CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; protected: + /// \brief Specify maximum number of store instructions per memset call. + /// /// When lowering \@llvm.memset this field specifies the maximum number of /// store operations that may be substituted for the call to memset. Targets /// must set this value based on the cost threshold for that target. Targets @@ -1598,13 +1638,14 @@ protected: /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine /// with 16-bit alignment would result in four 2-byte stores and one 1-byte /// store. This only applies to setting a constant array of a constant size. - /// @brief Specify maximum number of store instructions per memset call. unsigned MaxStoresPerMemset; /// Maximum number of stores operations that may be substituted for the call /// to memset, used for functions with OptSize attribute. unsigned MaxStoresPerMemsetOptSize; + /// \brief Specify maximum bytes of store instructions per memcpy call. + /// /// When lowering \@llvm.memcpy this field specifies the maximum number of /// store operations that may be substituted for a call to memcpy. Targets /// must set this value based on the cost threshold for that target. Targets @@ -1614,13 +1655,14 @@ protected: /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store /// and one 1-byte store. This only applies to copying a constant array of /// constant size. - /// @brief Specify maximum bytes of store instructions per memcpy call. unsigned MaxStoresPerMemcpy; - /// Maximum number of store operations that may be substituted for a call - /// to memcpy, used for functions with OptSize attribute. + /// Maximum number of store operations that may be substituted for a call to + /// memcpy, used for functions with OptSize attribute. unsigned MaxStoresPerMemcpyOptSize; + /// \brief Specify maximum bytes of store instructions per memmove call. + /// /// When lowering \@llvm.memmove this field specifies the maximum number of /// store instructions that may be substituted for a call to memmove. Targets /// must set this value based on the cost threshold for that target. Targets @@ -1629,31 +1671,27 @@ protected: /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine /// with 8-bit alignment would result in nine 1-byte stores. This only /// applies to copying a constant array of constant size. - /// @brief Specify maximum bytes of store instructions per memmove call. unsigned MaxStoresPerMemmove; - /// Maximum number of store instructions that may be substituted for a call - /// to memmove, used for functions with OpSize attribute. + /// Maximum number of store instructions that may be substituted for a call to + /// memmove, used for functions with OpSize attribute. unsigned MaxStoresPerMemmoveOptSize; - /// PredictableSelectIsExpensive - Tells the code generator that select is - /// more expensive than a branch if the branch is usually predicted right. + /// Tells the code generator that select is more expensive than a branch if + /// the branch is usually predicted right. bool PredictableSelectIsExpensive; protected: - /// isLegalRC - Return true if the value types that can be represented by the - /// specified register class are all legal. + /// Return true if the value types that can be represented by the specified + /// register class are all legal. bool isLegalRC(const TargetRegisterClass *RC) const; }; -//===----------------------------------------------------------------------===// -/// TargetLowering - This class defines information used to lower LLVM code to -/// legal SelectionDAG operators that the target instruction selector can accept -/// natively. +/// This class defines information used to lower LLVM code to legal SelectionDAG +/// operators that the target instruction selector can accept natively. /// /// This class also defines callbacks that targets must implement to lower /// target-specific constructs to SelectionDAG operators. -/// class TargetLowering : public TargetLoweringBase { TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; @@ -1663,9 +1701,9 @@ public: explicit TargetLowering(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF); - /// getPreIndexedAddressParts - returns true by value, base pointer and - /// offset pointer and addressing mode by reference if the node's address - /// can be legally represented as pre-indexed load / store address. + /// Returns true by value, base pointer and offset pointer and addressing mode + /// by reference if the node's address can be legally represented as + /// pre-indexed load / store address. virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, SDValue &/*Offset*/, ISD::MemIndexedMode &/*AM*/, @@ -1673,19 +1711,19 @@ public: return false; } - /// getPostIndexedAddressParts - returns true by value, base pointer and - /// offset pointer and addressing mode by reference if this node can be - /// combined with a load / store to form a post-indexed load / store. + /// Returns true by value, base pointer and offset pointer and addressing mode + /// by reference if this node can be combined with a load / store to form a + /// post-indexed load / store. virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, - SDValue &/*Base*/, SDValue &/*Offset*/, + SDValue &/*Base*/, + SDValue &/*Offset*/, ISD::MemIndexedMode &/*AM*/, SelectionDAG &/*DAG*/) const { return false; } - /// getJumpTableEncoding - Return the entry encoding for a jump table in the - /// current function. The returned value is a member of the - /// MachineJumpTableInfo::JTEntryKind enum. + /// Return the entry encoding for a jump table in the current function. The + /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. virtual unsigned getJumpTableEncoding() const; virtual const MCExpr * @@ -1695,21 +1733,18 @@ public: llvm_unreachable("Need to implement this hook if target has custom JTIs"); } - /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC - /// jumptable. + /// Returns relocation base for the given PIC jumptable. virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const; - /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the - /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an - /// MCExpr. + /// This returns the relocation base for the given PIC jumptable, the same as + /// getPICJumpTableRelocBase, but as an MCExpr. virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const; - /// isOffsetFoldingLegal - Return true if folding a constant offset - /// with the given GlobalAddress is legal. It is frequently not legal in - /// PIC relocation models. + /// Return true if folding a constant offset with the given GlobalAddress is + /// legal. It is frequently not legal in PIC relocation models. virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, @@ -1717,19 +1752,22 @@ public: void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode, DebugLoc DL) const; + ISD::CondCode &CCCode, SDLoc DL) const; - SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, - const SDValue *Ops, unsigned NumOps, - bool isSigned, DebugLoc dl) const; + /// Returns a pair of (return value, chain). + std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, + EVT RetVT, const SDValue *Ops, + unsigned NumOps, bool isSigned, + SDLoc dl, bool doesNotReturn = false, + bool isReturnValueUsed = true) const; //===--------------------------------------------------------------------===// // TargetLowering Optimization Methods // - /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two - /// SDValues for returning information from TargetLowering to its clients - /// that want to combine + /// A convenience struct that encapsulates a DAG, and two SDValues for + /// returning information from TargetLowering to its clients that want to + /// combine. struct TargetLoweringOpt { SelectionDAG &DAG; bool LegalTys; @@ -1750,44 +1788,40 @@ public: return true; } - /// ShrinkDemandedConstant - Check to see if the specified operand of the - /// specified instruction is a constant integer. If so, check to see if - /// there are any bits set in the constant that are not demanded. If so, - /// shrink the constant and return true. + /// Check to see if the specified operand of the specified instruction is a + /// constant integer. If so, check to see if there are any bits set in the + /// constant that are not demanded. If so, shrink the constant and return + /// true. bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); - /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the - /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening - /// cast, but it could be generalized for targets with other types of - /// implicit widening casts. + /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This + /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be + /// generalized for targets with other types of implicit widening casts. bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, - DebugLoc dl); + SDLoc dl); }; - /// SimplifyDemandedBits - Look at Op. At this point, we know that only the - /// DemandedMask bits of the result of Op are ever used downstream. If we can - /// use this information to simplify Op, create a new simplified DAG node and - /// return true, returning the original and new nodes in Old and New. - /// Otherwise, analyze the expression and return a mask of KnownOne and - /// KnownZero bits for the expression (used to simplify the caller). - /// The KnownZero/One bits may only be accurate for those bits in the - /// DemandedMask. + /// Look at Op. At this point, we know that only the DemandedMask bits of the + /// result of Op are ever used downstream. If we can use this information to + /// simplify Op, create a new simplified DAG node and return true, returning + /// the original and new nodes in Old and New. Otherwise, analyze the + /// expression and return a mask of KnownOne and KnownZero bits for the + /// expression (used to simplify the caller). The KnownZero/One bits may only + /// be accurate for those bits in the DemandedMask. bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth = 0) const; - /// computeMaskedBitsForTargetNode - Determine which of the bits specified in - /// Mask are known to be either zero or one and return them in the - /// KnownZero/KnownOne bitsets. + /// Determine which of the bits specified in Mask are known to be either zero + /// or one and return them in the KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth = 0) const; - /// ComputeNumSignBitsForTargetNode - This method can be implemented by - /// targets that want to expose additional information about sign bits to the - /// DAG Combiner. + /// This method can be implemented by targets that want to expose additional + /// information about sign bits to the DAG Combiner. virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth = 0) const; @@ -1819,20 +1853,20 @@ public: void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); }; - /// SimplifySetCC - Try to simplify a setcc built with the specified operands - /// and cc. If it is unable to simplify it, return a null SDValue. + /// Try to simplify a setcc built with the specified operands and cc. If it is + /// unable to simplify it, return a null SDValue. SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, - DAGCombinerInfo &DCI, DebugLoc dl) const; + DAGCombinerInfo &DCI, SDLoc dl) const; - /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the - /// node is a GlobalAddress + offset. + /// Returns true (and the GlobalValue and the offset) if the node is a + /// GlobalAddress + offset. virtual bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; - /// PerformDAGCombine - This method will be invoked for all target nodes and - /// for any target-independent nodes that the target has registered with - /// invoke it for. + /// This method will be invoked for all target nodes and for any + /// target-independent nodes that the target has registered with invoke it + /// for. /// /// The semantics are as follows: /// Return Value: @@ -1845,26 +1879,26 @@ public: /// virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; - /// isTypeDesirableForOp - Return true if the target has native support for - /// the specified value type and it is 'desirable' to use the type for the - /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 - /// instruction encodings are longer and some i16 instructions are slow. + /// Return true if the target has native support for the specified value type + /// and it is 'desirable' to use the type for the given node type. e.g. On x86 + /// i16 is legal, but undesirable since i16 instruction encodings are longer + /// and some i16 instructions are slow. virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { // By default, assume all legal types are desirable. return isTypeLegal(VT); } - /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner - /// to transform a floating point op of specified opcode to a equivalent op of - /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. + /// Return true if it is profitable for dag combiner to transform a floating + /// point op of specified opcode to a equivalent op of an integer + /// type. e.g. f32 load -> i32 load can be profitable on ARM. virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, EVT /*VT*/) const { return false; } - /// IsDesirableToPromoteOp - This method query the target whether it is - /// beneficial for dag combiner to promote the specified node. If true, it - /// should return the desired promotion type by reference. + /// This method query the target whether it is beneficial for dag combiner to + /// promote the specified node. If true, it should return the desired + /// promotion type by reference. virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { return false; } @@ -1874,17 +1908,16 @@ public: // the SelectionDAGBuilder code knows how to lower these. // - /// LowerFormalArguments - This hook must be implemented to lower the - /// incoming (formal) arguments, described by the Ins array, into the - /// specified DAG. The implementation should fill in the InVals array - /// with legal-type argument values, and return the resulting token - /// chain value. + /// This hook must be implemented to lower the incoming (formal) arguments, + /// described by the Ins array, into the specified DAG. The implementation + /// should fill in the InVals array with legal-type argument values, and + /// return the resulting token chain value. /// virtual SDValue LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/, const SmallVectorImpl<ISD::InputArg> &/*Ins*/, - DebugLoc /*dl*/, SelectionDAG &/*DAG*/, + SDLoc /*dl*/, SelectionDAG &/*DAG*/, SmallVectorImpl<SDValue> &/*InVals*/) const { llvm_unreachable("Not Implemented"); } @@ -1904,13 +1937,15 @@ public: ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), isSRet(false), isNest(false), isByVal(false), isReturned(false), Alignment(0) { } + + void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx); }; typedef std::vector<ArgListEntry> ArgListTy; - /// CallLoweringInfo - This structure contains all information that is - /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the - /// SelectionDAG builder needs to lower a call, and targets will see this - /// struct in their LowerCall implementation. + /// This structure contains all information that is necessary for lowering + /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder + /// needs to lower a call, and targets will see this struct in their LowerCall + /// implementation. struct CallLoweringInfo { SDValue Chain; Type *RetTy; @@ -1930,18 +1965,17 @@ public: SDValue Callee; ArgListTy &Args; SelectionDAG &DAG; - DebugLoc DL; + SDLoc DL; ImmutableCallSite *CS; SmallVector<ISD::OutputArg, 32> Outs; SmallVector<SDValue, 32> OutVals; SmallVector<ISD::InputArg, 32> Ins; - /// CallLoweringInfo - Constructs a call lowering context based on the - /// ImmutableCallSite \p cs. + /// Constructs a call lowering context based on the ImmutableCallSite \p cs. CallLoweringInfo(SDValue chain, Type *retTy, FunctionType *FTy, bool isTailCall, SDValue callee, - ArgListTy &args, SelectionDAG &dag, DebugLoc dl, + ArgListTy &args, SelectionDAG &dag, SDLoc dl, ImmutableCallSite &cs) : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), @@ -1952,13 +1986,13 @@ public: CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), DL(dl), CS(&cs) {} - /// CallLoweringInfo - Constructs a call lowering context based on the - /// provided call information. + /// Constructs a call lowering context based on the provided call + /// information. CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, bool isVarArg, bool isInReg, unsigned numFixedArgs, CallingConv::ID callConv, bool isTailCall, bool doesNotReturn, bool isReturnValueUsed, SDValue callee, - ArgListTy &args, SelectionDAG &dag, DebugLoc dl) + ArgListTy &args, SelectionDAG &dag, SDLoc dl) : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), @@ -1966,32 +2000,29 @@ public: Args(args), DAG(dag), DL(dl), CS(NULL) {} }; - /// LowerCallTo - This function lowers an abstract call to a function into an - /// actual call. This returns a pair of operands. The first element is the - /// return value for the function (if RetTy is not VoidTy). The second - /// element is the outgoing token chain. It calls LowerCall to do the actual - /// lowering. + /// This function lowers an abstract call to a function into an actual call. + /// This returns a pair of operands. The first element is the return value + /// for the function (if RetTy is not VoidTy). The second element is the + /// outgoing token chain. It calls LowerCall to do the actual lowering. std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; - /// LowerCall - This hook must be implemented to lower calls into the - /// the specified DAG. The outgoing arguments to the call are described - /// by the Outs array, and the values to be returned by the call are - /// described by the Ins array. The implementation should fill in the - /// InVals array with legal-type return values from the call, and return - /// the resulting token chain value. + /// This hook must be implemented to lower calls into the the specified + /// DAG. The outgoing arguments to the call are described by the Outs array, + /// and the values to be returned by the call are described by the Ins + /// array. The implementation should fill in the InVals array with legal-type + /// return values from the call, and return the resulting token chain value. virtual SDValue LowerCall(CallLoweringInfo &/*CLI*/, SmallVectorImpl<SDValue> &/*InVals*/) const { llvm_unreachable("Not Implemented"); } - /// HandleByVal - Target-specific cleanup for formal ByVal parameters. + /// Target-specific cleanup for formal ByVal parameters. virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} - /// CanLowerReturn - This hook should be implemented to check whether the - /// return values described by the Outs array can fit into the return - /// registers. If false is returned, an sret-demotion is performed. - /// + /// This hook should be implemented to check whether the return values + /// described by the Outs array can fit into the return registers. If false + /// is returned, an sret-demotion is performed. virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, MachineFunction &/*MF*/, bool /*isVarArg*/, const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, @@ -2001,56 +2032,60 @@ public: return true; } - /// LowerReturn - This hook must be implemented to lower outgoing - /// return values, described by the Outs array, into the specified - /// DAG. The implementation should return the resulting token chain - /// value. - /// + /// This hook must be implemented to lower outgoing return values, described + /// by the Outs array, into the specified DAG. The implementation should + /// return the resulting token chain value. virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/, const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, const SmallVectorImpl<SDValue> &/*OutVals*/, - DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { + SDLoc /*dl*/, SelectionDAG &/*DAG*/) const { llvm_unreachable("Not Implemented"); } - /// isUsedByReturnOnly - Return true if result of the specified node is used - /// by a return node only. It also compute and return the input chain for the - /// tail call. - /// This is used to determine whether it is possible - /// to codegen a libcall as tail call at legalization time. - virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { + /// Return true if result of the specified node is used by a return node + /// only. It also compute and return the input chain for the tail call. + /// + /// This is used to determine whether it is possible to codegen a libcall as + /// tail call at legalization time. + virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const { return false; } - /// mayBeEmittedAsTailCall - Return true if the target may be able emit the - /// call instruction as a tail call. This is used by optimization passes to - /// determine if it's profitable to duplicate return instructions to enable - /// tailcall optimization. + /// Return true if the target may be able emit the call instruction as a tail + /// call. This is used by optimization passes to determine if it's profitable + /// to duplicate return instructions to enable tailcall optimization. virtual bool mayBeEmittedAsTailCall(CallInst *) const { return false; } - /// getTypeForExtArgOrReturn - Return the type that should be used to zero or - /// sign extend a zeroext/signext integer argument or return value. - /// FIXME: Most C calling convention requires the return type to be promoted, - /// but this is not true all the time, e.g. i1 on x86-64. It is also not - /// necessary for non-C calling conventions. The frontend should handle this - /// and include all of the necessary information. + /// Return the type that should be used to zero or sign extend a + /// zeroext/signext integer argument or return value. FIXME: Most C calling + /// convention requires the return type to be promoted, but this is not true + /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C + /// calling conventions. The frontend should handle this and include all of + /// the necessary information. virtual MVT getTypeForExtArgOrReturn(MVT VT, ISD::NodeType /*ExtendKind*/) const { MVT MinVT = getRegisterType(MVT::i32); return VT.bitsLT(MinVT) ? MinVT : VT; } - /// LowerOperationWrapper - This callback is invoked by the type legalizer - /// to legalize nodes with an illegal operand type but legal result types. - /// It replaces the LowerOperation callback in the type Legalizer. - /// The reason we can not do away with LowerOperation entirely is that - /// LegalizeDAG isn't yet ready to use this callback. - /// TODO: Consider merging with ReplaceNodeResults. + /// Returns a 0 terminated array of registers that can be safely used as + /// scratch registers. + virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const { + return NULL; + } + /// This callback is invoked by the type legalizer to legalize nodes with an + /// illegal operand type but legal result types. It replaces the + /// LowerOperation callback in the type Legalizer. The reason we can not do + /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to + /// use this callback. + /// + /// TODO: Consider merging with ReplaceNodeResults. + /// /// The target places new result values for the node in Results (their number /// and types must exactly match those of the original return values of /// the node), or leaves Results empty, which indicates that the node is not @@ -2060,19 +2095,19 @@ public: SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const; - /// LowerOperation - This callback is invoked for operations that are - /// unsupported by the target, which are registered to use 'custom' lowering, - /// and whose defined values are all legal. - /// If the target has no operations that require custom lowering, it need not - /// implement this. The default implementation of this aborts. + /// This callback is invoked for operations that are unsupported by the + /// target, which are registered to use 'custom' lowering, and whose defined + /// values are all legal. If the target has no operations that require custom + /// lowering, it need not implement this. The default implementation of this + /// aborts. virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; - /// ReplaceNodeResults - This callback is invoked when a node result type is - /// illegal for the target, and the operation was registered to use 'custom' - /// lowering for that result type. The target places new result values for - /// the node in Results (their number and types must exactly match those of - /// the original return values of the node), or leaves Results empty, which - /// indicates that the node is not to be custom lowered after all. + /// This callback is invoked when a node result type is illegal for the + /// target, and the operation was registered to use 'custom' lowering for that + /// result type. The target places new result values for the node in Results + /// (their number and types must exactly match those of the original return + /// values of the node), or leaves Results empty, which indicates that the + /// node is not to be custom lowered after all. /// /// If the target has no operations that require custom lowering, it need not /// implement this. The default implementation aborts. @@ -2082,12 +2117,11 @@ public: llvm_unreachable("ReplaceNodeResults not implemented for this target!"); } - /// getTargetNodeName() - This method returns the name of a target specific - /// DAG node. + /// This method returns the name of a target specific DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; - /// createFastISel - This method returns a target specific FastISel object, - /// or null if the target does not support "fast" ISel. + /// This method returns a target specific FastISel object, or null if the + /// target does not support "fast" ISel. virtual FastISel *createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const { return 0; @@ -2097,10 +2131,10 @@ public: // Inline Asm Support hooks // - /// ExpandInlineAsm - This hook allows the target to expand an inline asm - /// call to be explicit llvm code if it wants to. This is useful for - /// turning simple inline asms into LLVM intrinsics, which gives the - /// compiler more information about the behavior of the code. + /// This hook allows the target to expand an inline asm call to be explicit + /// llvm code if it wants to. This is useful for turning simple inline asms + /// into LLVM intrinsics, which gives the compiler more information about the + /// behavior of the code. virtual bool ExpandInlineAsm(CallInst *) const { return false; } @@ -2129,32 +2163,31 @@ public: CW_Default = CW_Okay // Default or don't know type. }; - /// AsmOperandInfo - This contains information for each constraint that we are - /// lowering. + /// This contains information for each constraint that we are lowering. struct AsmOperandInfo : public InlineAsm::ConstraintInfo { - /// ConstraintCode - This contains the actual string for the code, like "m". - /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that - /// most closely matches the operand. + /// This contains the actual string for the code, like "m". TargetLowering + /// picks the 'best' code from ConstraintInfo::Codes that most closely + /// matches the operand. std::string ConstraintCode; - /// ConstraintType - Information about the constraint code, e.g. Register, - /// RegisterClass, Memory, Other, Unknown. + /// Information about the constraint code, e.g. Register, RegisterClass, + /// Memory, Other, Unknown. TargetLowering::ConstraintType ConstraintType; - /// CallOperandval - If this is the result output operand or a - /// clobber, this is null, otherwise it is the incoming operand to the - /// CallInst. This gets modified as the asm is processed. + /// If this is the result output operand or a clobber, this is null, + /// otherwise it is the incoming operand to the CallInst. This gets + /// modified as the asm is processed. Value *CallOperandVal; - /// ConstraintVT - The ValueType for the operand value. + /// The ValueType for the operand value. MVT ConstraintVT; - /// isMatchingInputConstraint - Return true of this is an input operand that - /// is a matching constraint like "4". + /// Return true of this is an input operand that is a matching constraint + /// like "4". bool isMatchingInputConstraint() const; - /// getMatchedOperand - If this is an input matching constraint, this method - /// returns the output operand it matches. + /// If this is an input matching constraint, this method returns the output + /// operand it matches. unsigned getMatchedOperand() const; /// Copy constructor for copying from an AsmOperandInfo. @@ -2176,11 +2209,10 @@ public: typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; - /// ParseConstraints - Split up the constraint string from the inline - /// assembly value into the specific constraints and their prefixes, - /// and also tie in the associated operand values. - /// If this returns an empty vector, and if the constraint string itself - /// isn't empty, there was an error parsing. + /// Split up the constraint string from the inline assembly value into the + /// specific constraints and their prefixes, and also tie in the associated + /// operand values. If this returns an empty vector, and if the constraint + /// string itself isn't empty, there was an error parsing. virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; /// Examine constraint type and operand type and determine a weight value. @@ -2193,41 +2225,37 @@ public: virtual ConstraintWeight getSingleConstraintMatchWeight( AsmOperandInfo &info, const char *constraint) const; - /// ComputeConstraintToUse - Determines the constraint code and constraint - /// type to use for the specific AsmOperandInfo, setting - /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand - /// being passed in is available, it can be passed in as Op, otherwise an - /// empty SDValue can be passed. + /// Determines the constraint code and constraint type to use for the specific + /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. + /// If the actual operand being passed in is available, it can be passed in as + /// Op, otherwise an empty SDValue can be passed. virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG = 0) const; - /// getConstraintType - Given a constraint, return the type of constraint it - /// is for this target. + /// Given a constraint, return the type of constraint it is for this target. virtual ConstraintType getConstraintType(const std::string &Constraint) const; - /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. - /// {edx}), return the register number and the register class for the - /// register. + /// Given a physical register constraint (e.g. {edx}), return the register + /// number and the register class for the register. /// /// Given a register class constraint, like 'r', if this corresponds directly /// to an LLVM register class, return a register of 0 and the register class /// pointer. /// - /// This should only be used for C_Register constraints. On error, - /// this returns a register number of 0 and a null register class pointer.. + /// This should only be used for C_Register constraints. On error, this + /// returns a register number of 0 and a null register class pointer.. virtual std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; + MVT VT) const; - /// LowerXConstraint - try to replace an X constraint, which matches anything, - /// with another that has more specific requirements based on the type of the - /// corresponding operand. This returns null if there is no replacement to - /// make. + /// Try to replace an X constraint, which matches anything, with another that + /// has more specific requirements based on the type of the corresponding + /// operand. This returns null if there is no replacement to make. virtual const char *LowerXConstraint(EVT ConstraintVT) const; - /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops - /// vector. If it is invalid, don't add anything to Ops. + /// Lower the specified operand into the Ops vector. If it is invalid, don't + /// add anything to Ops. virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const; @@ -2235,7 +2263,7 @@ public: //===--------------------------------------------------------------------===// // Div utility functions // - SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, + SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const; SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector<SDNode*> *Created) const; @@ -2246,26 +2274,26 @@ public: // Instruction Emitting Hooks // - // EmitInstrWithCustomInserter - This method should be implemented by targets - // that mark instructions with the 'usesCustomInserter' flag. These - // instructions are special in various ways, which require special support to - // insert. The specified MachineInstr is created but not inserted into any - // basic blocks, and this method is called to expand it into a sequence of - // instructions, potentially also creating new basic blocks and control flow. + /// This method should be implemented by targets that mark instructions with + /// the 'usesCustomInserter' flag. These instructions are special in various + /// ways, which require special support to insert. The specified MachineInstr + /// is created but not inserted into any basic blocks, and this method is + /// called to expand it into a sequence of instructions, potentially also + /// creating new basic blocks and control flow. virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; - /// AdjustInstrPostInstrSelection - This method should be implemented by - /// targets that mark instructions with the 'hasPostISelHook' flag. These - /// instructions must be adjusted after instruction selection by target hooks. - /// e.g. To fill in optional defs for ARM 's' setting instructions. + /// This method should be implemented by targets that mark instructions with + /// the 'hasPostISelHook' flag. These instructions must be adjusted after + /// instruction selection by target hooks. e.g. To fill in optional defs for + /// ARM 's' setting instructions. virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; }; -/// GetReturnInfo - Given an LLVM IR type and return type attributes, -/// compute the return value EVTs and flags, and optionally also -/// the offsets, if the return value is being lowered to memory. +/// Given an LLVM IR type and return type attributes, compute the return value +/// EVTs and flags, and optionally also the offsets, if the return value is +/// being lowered to memory. void GetReturnInfo(Type* ReturnType, AttributeSet attr, SmallVectorImpl<ISD::OutputArg> &Outs, const TargetLowering &TLI); diff --git a/include/llvm/Target/TargetLoweringObjectFile.h b/include/llvm/Target/TargetLoweringObjectFile.h index 9958755a66860..284b6bbdb897a 100644 --- a/include/llvm/Target/TargetLoweringObjectFile.h +++ b/include/llvm/Target/TargetLoweringObjectFile.h @@ -117,6 +117,10 @@ public: MachineModuleInfo *MMI, unsigned Encoding, MCStreamer &Streamer) const; + /// Return the MCSymbol for the specified global value. This symbol is the + /// main label that is the address of the global + MCSymbol *getSymbol(Mangler &M, const GlobalValue *GV) const; + // getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personality. virtual MCSymbol * getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, @@ -138,6 +142,10 @@ public: return StaticDtorSection; } + /// \brief Create a symbol reference to describe the given TLS variable when + /// emitting the address in debug info. + virtual const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const; + protected: virtual const MCSection * SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 37a79fe8526f4..11b0f5fb77fcd 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -29,7 +29,6 @@ class GlobalValue; class MCAsmInfo; class MCCodeGenInfo; class MCContext; -class PassManagerBase; class Target; class DataLayout; class TargetLibraryInfo; @@ -47,6 +46,12 @@ class VectorTargetTransformInfo; class formatted_raw_ostream; class raw_ostream; +// The old pass manager infrastructure is hidden in a legacy namespace now. +namespace legacy { +class PassManagerBase; +} +using legacy::PassManagerBase; + //===----------------------------------------------------------------------===// /// /// TargetMachine - Primary interface to the complete machine description for @@ -70,7 +75,8 @@ protected: // Can only create subclasses. std::string TargetFS; /// CodeGenInfo - Low level target information such as relocation model. - const MCCodeGenInfo *CodeGenInfo; + /// Non-const to allow resetting optimization level per-function. + MCCodeGenInfo *CodeGenInfo; /// AsmInfo - Contains target specific asm information. /// @@ -102,11 +108,14 @@ public: void resetTargetOptions(const MachineFunction *MF) const; // Interfaces to the major aspects of target machine information: + // // -- Instruction opcode and operand information // -- Pipelines and scheduling information // -- Stack frame information // -- Selection DAG lowering information // + // N.B. These objects may change during compilation. It's not safe to cache + // them between functions. virtual const TargetInstrInfo *getInstrInfo() const { return 0; } virtual const TargetFrameLowering *getFrameLowering() const { return 0; } virtual const TargetLowering *getTargetLowering() const { return 0; } @@ -205,6 +214,9 @@ public: /// Default, or Aggressive. CodeGenOpt::Level getOptLevel() const; + /// \brief Overrides the optimization level. + void setOptLevel(CodeGenOpt::Level Level) const; + void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } bool shouldPrintMachineCode() const { return Options.PrintMachineCode; } @@ -252,8 +264,8 @@ public: formatted_raw_ostream &, CodeGenFileType, bool /*DisableVerify*/ = true, - AnalysisID StartAfter = 0, - AnalysisID StopAfter = 0) { + AnalysisID /*StartAfter*/ = 0, + AnalysisID /*StopAfter*/ = 0) { return true; } @@ -292,6 +304,7 @@ protected: // Can only create subclasses. Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + void initAsmInfo(); public: /// \brief Register analysis passes for this target with a pass manager. /// diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h index 516e0706b8977..bd74cb9c0f45d 100644 --- a/include/llvm/Target/TargetOpcodes.h +++ b/include/llvm/Target/TargetOpcodes.h @@ -69,8 +69,9 @@ namespace TargetOpcode { DBG_VALUE = 11, /// REG_SEQUENCE - This variadic instruction is used to form a register that - /// represent a consecutive sequence of sub-registers. It's used as register - /// coalescing / allocation aid and must be eliminated before code emission. + /// represents a consecutive sequence of sub-registers. It's used as a + /// register coalescing / allocation aid and must be eliminated before code + /// emission. // In SDNode form, the first operand encodes the register class created by // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index // pair. Once it has been lowered to a MachineInstr, the regclass operand @@ -91,7 +92,19 @@ namespace TargetOpcode { /// Lifetime markers. LIFETIME_START = 15, - LIFETIME_END = 16 + LIFETIME_END = 16, + + /// A Stackmap instruction captures the location of live variables at its + /// position in the instruction stream. It is followed by a shadow of bytes + /// that must lie within the function and not contain another stackmap. + STACKMAP = 17, + + /// Patchable call instruction - this instruction represents a call to a + /// constant address, followed by a series of NOPs. It is intended to + /// support optimizations for dynamic languages (such as javascript) that + /// rewrite calls to runtimes with more efficient code sequences. + /// This also implies a stack map. + PATCHPOINT = 18 }; } // end namespace TargetOpcode } // end namespace llvm diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index c763a595dd5db..d9c8651e7ed0e 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -42,13 +42,13 @@ namespace llvm { public: TargetOptions() : PrintMachineCode(false), NoFramePointerElim(false), - NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false), + LessPreciseFPMADOption(false), UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false), - UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false), + UseSoftFloat(false), NoZerosInBSS(false), JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false), GuaranteedTailCallOpt(false), DisableTailCalls(false), - StackAlignmentOverride(0), RealignStack(true), SSPBufferSize(0), + StackAlignmentOverride(0), EnableFastISel(false), PositionIndependentExecutable(false), EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(""), FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Standard) @@ -64,12 +64,6 @@ namespace llvm { /// elimination optimization, this option should disable it. unsigned NoFramePointerElim : 1; - /// NoFramePointerElimNonLeaf - This flag is enabled when the - /// -disable-non-leaf-fp-elim is specified on the command line. If the - /// target supports the frame pointer elimination optimization, this option - /// should disable it for non-leaf functions. - unsigned NoFramePointerElimNonLeaf : 1; - /// DisableFramePointerElim - This returns true if frame pointer elimination /// optimization should be disabled for the given machine function. bool DisableFramePointerElim(const MachineFunction &MF) const; @@ -123,10 +117,6 @@ namespace llvm { /// crt*.o compiling). unsigned NoZerosInBSS : 1; - /// JITExceptionHandling - This flag indicates that the JIT should emit - /// exception handling information. - unsigned JITExceptionHandling : 1; - /// JITEmitDebugInfo - This flag indicates that the JIT should try to emit /// debug information and notify a debugger about it. unsigned JITEmitDebugInfo : 1; @@ -151,14 +141,6 @@ namespace llvm { /// StackAlignmentOverride - Override default stack alignment for target. unsigned StackAlignmentOverride; - /// RealignStack - This flag indicates whether the stack should be - /// automatically realigned, if needed. - unsigned RealignStack : 1; - - /// SSPBufferSize - The minimum size of buffers that will receive stack - /// smashing protection when -fstack-protection is used. - unsigned SSPBufferSize; - /// EnableFastISel - This flag enables fast-path instruction selection /// which trades away generated code quality in favor of reducing /// compile time. @@ -207,9 +189,41 @@ namespace llvm { /// via the llvm.fma.* intrinsic) will always be honored, regardless of /// the value of this option. FPOpFusion::FPOpFusionMode AllowFPOpFusion; - - bool operator==(const TargetOptions &); }; + +// Comparison operators: + + +inline bool operator==(const TargetOptions &LHS, + const TargetOptions &RHS) { +#define ARE_EQUAL(X) LHS.X == RHS.X + return + ARE_EQUAL(UnsafeFPMath) && + ARE_EQUAL(NoInfsFPMath) && + ARE_EQUAL(NoNaNsFPMath) && + ARE_EQUAL(HonorSignDependentRoundingFPMathOption) && + ARE_EQUAL(UseSoftFloat) && + ARE_EQUAL(NoZerosInBSS) && + ARE_EQUAL(JITEmitDebugInfo) && + ARE_EQUAL(JITEmitDebugInfoToDisk) && + ARE_EQUAL(GuaranteedTailCallOpt) && + ARE_EQUAL(DisableTailCalls) && + ARE_EQUAL(StackAlignmentOverride) && + ARE_EQUAL(EnableFastISel) && + ARE_EQUAL(PositionIndependentExecutable) && + ARE_EQUAL(EnableSegmentedStacks) && + ARE_EQUAL(UseInitArray) && + ARE_EQUAL(TrapFuncName) && + ARE_EQUAL(FloatABIType) && + ARE_EQUAL(AllowFPOpFusion); +#undef ARE_EQUAL +} + +inline bool operator!=(const TargetOptions &LHS, + const TargetOptions &RHS) { + return !(LHS == RHS); +} + } // End llvm namespace #endif diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 6b1e70bba11b2..958bea6f2b959 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -226,13 +226,15 @@ private: const unsigned *SubRegIndexLaneMasks; regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses + unsigned CoveringLanes; protected: TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, - const unsigned *SRILaneMasks); + const unsigned *SRILaneMasks, + unsigned CoveringLanes); virtual ~TargetRegisterInfo(); public: @@ -362,6 +364,31 @@ public: return SubRegIndexLaneMasks[SubIdx]; } + /// The lane masks returned by getSubRegIndexLaneMask() above can only be + /// used to determine if sub-registers overlap - they can't be used to + /// determine if a set of sub-registers completely cover another + /// sub-register. + /// + /// The X86 general purpose registers have two lanes corresponding to the + /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have + /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the + /// sub_32bit sub-register. + /// + /// On the other hand, the ARM NEON lanes fully cover their registers: The + /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. + /// This is related to the CoveredBySubRegs property on register definitions. + /// + /// This function returns a bit mask of lanes that completely cover their + /// sub-registers. More precisely, given: + /// + /// Covering = getCoveringLanes(); + /// MaskA = getSubRegIndexLaneMask(SubA); + /// MaskB = getSubRegIndexLaneMask(SubB); + /// + /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by + /// SubB. + unsigned getCoveringLanes() const { return CoveringLanes; } + /// regsOverlap - Returns true if the two registers are equal or alias each /// other. The registers may be virtual register. bool regsOverlap(unsigned regA, unsigned regB) const { @@ -874,6 +901,7 @@ static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; /// class PrintRegUnit { +protected: const TargetRegisterInfo *TRI; unsigned Unit; public: @@ -887,6 +915,21 @@ static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { return OS; } +/// PrintVRegOrUnit - It is often convenient to track virtual registers and +/// physical register units in the same list. +class PrintVRegOrUnit : protected PrintRegUnit { +public: + PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri) + : PrintRegUnit(VRegOrUnit, tri) {} + void print(raw_ostream&) const; +}; + +static inline raw_ostream &operator<<(raw_ostream &OS, + const PrintVRegOrUnit &PR) { + PR.print(OS); + return OS; +} + } // End llvm namespace #endif diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index 660d2c48b6c5a..9d4858ac32f2f 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -72,11 +72,13 @@ def instregex; // // Target hooks allow subtargets to associate LoadLatency and // HighLatency with groups of opcodes. +// +// See MCSchedule.h for detailed comments. class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. - int MinLatency = -1; // Determines which instrucions are allowed in a group. + int MinLatency = -1; // Determines which instructions are allowed in a group. // (-1) inorder (0) ooo, (1): inorder +var latencies. - int ILPWindow = -1; // Cycles of latency likely hidden by hardware buffers. + int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. int LoadLatency = -1; // Cycles for loads to access the cache. int HighLatency = -1; // Approximation of cycles for "high latency" ops. int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. @@ -84,6 +86,15 @@ class SchedMachineModel { // Per-cycle resources tables. ProcessorItineraries Itineraries = NoItineraries; + // Subtargets that define a model for only a subset of instructions + // that have a scheduling class (itinerary class or SchedRW list) + // and may actually be generated for that subtarget must clear this + // bit. Otherwise, the scheduler considers an unmodelled opcode to + // be an error. This should only be set during initial bringup, + // or there will be no way to catch simple errors in the model + // resulting from changes to the instruction definitions. + bit CompleteModel = 1; + bit NoModel = 0; // Special tag to indicate missing machine model. } @@ -106,7 +117,7 @@ class ProcResourceKind; // out-of-order engine that the compiler attempts to conserve. // Buffered resources may be held for multiple clock cycles, but the // scheduler does not pin them to a particular clock cycle relative to -// instruction dispatch. Setting Buffered=0 changes this to an +// instruction dispatch. Setting BufferSize=0 changes this to an // in-order resource. In this case, the scheduler counts down from the // cycle that the instruction issues in-order, forcing an interlock // with subsequent instructions that require the same resource until @@ -119,7 +130,7 @@ class ProcResourceUnits<ProcResourceKind kind, int num> { ProcResourceKind Kind = kind; int NumUnits = num; ProcResourceKind Super = ?; - bit Buffered = 1; + int BufferSize = -1; SchedMachineModel SchedModel = ?; } @@ -136,6 +147,7 @@ class ProcResource<int num> : ProcResourceKind, class ProcResGroup<list<ProcResource> resources> : ProcResourceKind { list<ProcResource> Resources = resources; SchedMachineModel SchedModel = ?; + int BufferSize = -1; } // A target architecture may define SchedReadWrite types and associate diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index d89a6e658e6c1..d94bdc67bf022 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -376,12 +376,14 @@ def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; +def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; +def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; @@ -463,6 +465,8 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; +def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", + SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1, 2>]>,[]>; // This operator does not do subvector type checking. The ARM // backend, at least, needs it. diff --git a/include/llvm/Target/TargetSelectionDAGInfo.h b/include/llvm/Target/TargetSelectionDAGInfo.h index 96793bc036e76..3474ee493eaed 100644 --- a/include/llvm/Target/TargetSelectionDAGInfo.h +++ b/include/llvm/Target/TargetSelectionDAGInfo.h @@ -54,7 +54,7 @@ public: /// for another call). If the target chooses to decline an AlwaysInline /// request here, legalize will resort to using simple loads and stores. virtual SDValue - EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, @@ -71,7 +71,7 @@ public: /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, @@ -87,13 +87,81 @@ public: /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const { return SDValue(); } + + /// EmitTargetCodeForMemcmp - Emit target-specific code that performs a + /// memcmp, in cases where that is faster than a libcall. The first + /// returned SDValue is the result of the memcmp and the second is + /// the chain. Both SDValues can be null if a normal libcall should + /// be used. + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, + SDValue Chain, + SDValue Op1, SDValue Op2, + SDValue Op3, MachinePointerInfo Op1PtrInfo, + MachinePointerInfo Op2PtrInfo) const { + return std::make_pair(SDValue(), SDValue()); + } + + /// EmitTargetCodeForMemchr - Emit target-specific code that performs a + /// memchr, in cases where that is faster than a libcall. The first + /// returned SDValue is the result of the memchr and the second is + /// the chain. Both SDValues can be null if a normal libcall should + /// be used. + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc dl, SDValue Chain, + SDValue Src, SDValue Char, SDValue Length, + MachinePointerInfo SrcPtrInfo) const { + return std::make_pair(SDValue(), SDValue()); + } + + /// EmitTargetCodeForStrcpy - Emit target-specific code that performs a + /// strcpy or stpcpy, in cases where that is faster than a libcall. + /// The first returned SDValue is the result of the copy (the start + /// of the destination string for strcpy, a pointer to the null terminator + /// for stpcpy) and the second is the chain. Both SDValues can be null + /// if a normal libcall should be used. + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, + SDValue Dest, SDValue Src, + MachinePointerInfo DestPtrInfo, + MachinePointerInfo SrcPtrInfo, + bool isStpcpy) const { + return std::make_pair(SDValue(), SDValue()); + } + + /// EmitTargetCodeForStrcmp - Emit target-specific code that performs a + /// strcmp, in cases where that is faster than a libcall. The first + /// returned SDValue is the result of the strcmp and the second is + /// the chain. Both SDValues can be null if a normal libcall should + /// be used. + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, + SDValue Chain, + SDValue Op1, SDValue Op2, + MachinePointerInfo Op1PtrInfo, + MachinePointerInfo Op2PtrInfo) const { + return std::make_pair(SDValue(), SDValue()); + } + + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, + SDValue Src, MachinePointerInfo SrcPtrInfo) const { + return std::make_pair(SDValue(), SDValue()); + } + + virtual std::pair<SDValue, SDValue> + EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, + SDValue Src, SDValue MaxLength, + MachinePointerInfo SrcPtrInfo) const { + return std::make_pair(SDValue(), SDValue()); + } }; } // end llvm namespace diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index b2d405de8464c..1b2e06acc2b01 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -25,6 +25,7 @@ class SDep; class SUnit; class TargetRegisterClass; class TargetSchedModel; +struct MachineSchedPolicy; template <typename T> class SmallVectorImpl; //===----------------------------------------------------------------------===// @@ -55,6 +56,9 @@ public: return 0; } + /// \brief Temporary API to test migration to MI scheduler. + bool useMachineScheduler() const; + /// \brief True if the subtarget should run MachineScheduler after aggressive /// coalescing. /// @@ -62,6 +66,16 @@ public: /// scheduler. It does not yet disable the postRA scheduler. virtual bool enableMachineScheduler() const; + /// \brief Override generic scheduling policy within a region. + /// + /// This is a convenient way for targets that don't provide any custom + /// scheduling heuristics (no custom MachineSchedStrategy) to make + /// changes to the generic scheduling policy. + virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, + MachineInstr *begin, + MachineInstr *end, + unsigned NumRegionInstrs) const {} + // enablePostRAScheduler - If the target can benefit from post-regalloc // scheduling and the specified optimization level meets the requirement // return true to enable post-register-allocation scheduling. In @@ -75,6 +89,10 @@ public: virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const { } + /// \brief Enable use of alias analysis during code generation (during MI + /// scheduling, DAGCombine, etc.). + virtual bool useAA() const; + /// \brief Reset the features for the subtarget. virtual void resetSubtargetFeatures(const MachineFunction *MF) { } }; |