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-rw-r--r--include/llvm/Target/SubtargetFeature.h2
-rw-r--r--include/llvm/Target/Target.td2
-rw-r--r--include/llvm/Target/TargetData.h2
-rw-r--r--include/llvm/Target/TargetInstrDesc.h8
-rw-r--r--include/llvm/Target/TargetInstrInfo.h32
-rw-r--r--include/llvm/Target/TargetJITInfo.h2
-rw-r--r--include/llvm/Target/TargetLowering.h26
-rw-r--r--include/llvm/Target/TargetSelectionDAG.td6
8 files changed, 51 insertions, 29 deletions
diff --git a/include/llvm/Target/SubtargetFeature.h b/include/llvm/Target/SubtargetFeature.h
index 58333e2b424f6..a709f523897c2 100644
--- a/include/llvm/Target/SubtargetFeature.h
+++ b/include/llvm/Target/SubtargetFeature.h
@@ -21,7 +21,7 @@
#include <string>
#include <vector>
#include <cstring>
-#include "llvm/Support/DataTypes.h"
+#include "llvm/System/DataTypes.h"
namespace llvm {
class raw_ostream;
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 4d65b19e2e71f..edb85829757b1 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -199,7 +199,7 @@ class Instruction {
bit isReMaterializable = 0; // Is this instruction re-materializable?
bit isPredicable = 0; // Is this instruction predicable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
- bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit usesCustomInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h
index f8ea64b4ea66b..af85f734e5ac3 100644
--- a/include/llvm/Target/TargetData.h
+++ b/include/llvm/Target/TargetData.h
@@ -21,7 +21,7 @@
#define LLVM_TARGET_TARGETDATA_H
#include "llvm/Pass.h"
-#include "llvm/Support/DataTypes.h"
+#include "llvm/System/DataTypes.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/SmallVector.h"
#include <string>
diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index d828a236cd88e..b0ed0bf0c8bbc 100644
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -109,7 +109,7 @@ namespace TID {
UnmodeledSideEffects,
Commutable,
ConvertibleTo3Addr,
- UsesCustomDAGSchedInserter,
+ UsesCustomInserter,
Rematerializable,
CheapAsAMove,
ExtraSrcRegAllocReq,
@@ -416,7 +416,7 @@ public:
return Flags & (1 << TID::ConvertibleTo3Addr);
}
- /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
+ /// usesCustomInsertionHook - Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block. If this is true for the instruction, it basically
/// means that it is a pseudo instruction used at SelectionDAG time that is
@@ -424,8 +424,8 @@ public:
///
/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
/// is used to insert this into the MachineBasicBlock.
- bool usesCustomDAGSchedInsertionHook() const {
- return Flags & (1 << TID::UsesCustomDAGSchedInserter);
+ bool usesCustomInsertionHook() const {
+ return Flags & (1 << TID::UsesCustomInserter);
}
/// isRematerializable - Returns true if this instruction is a candidate for
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 919bef1e7f2bb..1d42c323b9be8 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -133,13 +133,34 @@ private:
AliasAnalysis *AA) const;
public:
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
+ /// isMoveInstr - Return true if the instruction is a register to register
+ /// move and return the source and dest operands and their sub-register
+ /// indices by reference.
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& SrcReg, unsigned& DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
return false;
}
+
+ /// isIdentityCopy - Return true if the instruction is a copy (or
+ /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
+ /// destination registers are the same.
+ bool isIdentityCopy(const MachineInstr &MI) const {
+ unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
+ if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+ SrcReg == DstReg)
+ return true;
+
+ if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
+ MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
+ return true;
+
+ if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
+ MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
+ return true;
+ return false;
+ }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
@@ -384,9 +405,12 @@ public:
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
/// instruction after load / store are unfolded from an instruction of the
/// specified opcode. It returns zero if the specified unfolding is not
- /// possible.
+ /// possible. If LoadRegIndex is non-null, it is filled in with the operand
+ /// index of the operand which will hold the register holding the loaded
+ /// value.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
- bool UnfoldLoad, bool UnfoldStore) const {
+ bool UnfoldLoad, bool UnfoldStore,
+ unsigned *LoadRegIndex = 0) const {
return 0;
}
diff --git a/include/llvm/Target/TargetJITInfo.h b/include/llvm/Target/TargetJITInfo.h
index 9545689cb711a..809f1830abf6f 100644
--- a/include/llvm/Target/TargetJITInfo.h
+++ b/include/llvm/Target/TargetJITInfo.h
@@ -18,7 +18,7 @@
#define LLVM_TARGET_TARGETJITINFO_H
#include <cassert>
-#include "llvm/Support/DataTypes.h"
+#include "llvm/System/DataTypes.h"
namespace llvm {
class Function;
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 4f567b0b203a6..8bc39d0b2ce4b 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -325,12 +325,11 @@ public:
/// scalarizing vs using the wider vector type.
virtual EVT getWidenVectorType(EVT VT) const;
- typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
- legal_fpimm_iterator legal_fpimm_begin() const {
- return LegalFPImmediates.begin();
- }
- legal_fpimm_iterator legal_fpimm_end() const {
- return LegalFPImmediates.end();
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will materialize
+ /// the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ return false;
}
/// isShuffleMaskLegal - Targets can use this to indicate that they only
@@ -1051,12 +1050,6 @@ protected:
PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
}
- /// addLegalFPImmediate - Indicate that this target can instruction select
- /// the specified FP immediate natively.
- void addLegalFPImmediate(const APFloat& Imm) {
- LegalFPImmediates.push_back(Imm);
- }
-
/// setTargetDAGCombine - Targets should invoke this method for each target
/// independent node that they want to provide a custom DAG combiner for by
/// implementing the PerformDAGCombine virtual method.
@@ -1432,14 +1425,15 @@ public:
SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
- // Scheduler hooks
+ // Instruction Emitting Hooks
//
// EmitInstrWithCustomInserter - This method should be implemented by targets
- // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
+ // that mark instructions with the 'usesCustomInserter' flag. These
// instructions are special in various ways, which require special support to
// insert. The specified MachineInstr is created but not inserted into any
- // basic blocks, and the scheduler passes ownership of it to this method.
+ // basic blocks, and this method is called to expand it into a sequence of
+ // instructions, potentially also creating new basic blocks and control flow.
// When new basic blocks are inserted and the edges from MBB to its successors
// are modified, the method should insert pairs of <OldSucc, NewSucc> into the
// DenseMap.
@@ -1696,8 +1690,6 @@ private:
ValueTypeActionImpl ValueTypeActions;
- std::vector<APFloat> LegalFPImmediates;
-
std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 700c64c8ca533..f123d66b5af86 100644
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -269,6 +269,10 @@ def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
"ExternalSymbolSDNode">;
def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
"ExternalSymbolSDNode">;
+def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
+ "BlockAddressSDNode">;
+def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
+ "BlockAddressSDNode">;
def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
[SDNPCommutative, SDNPAssociative]>;
@@ -325,6 +329,8 @@ def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
+def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
+def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-26 03:05:14 +0000