diff options
Diffstat (limited to 'ld/testsuite/ld-arm')
67 files changed, 1069 insertions, 120 deletions
diff --git a/ld/testsuite/ld-arm/arm-app-abs32.d b/ld/testsuite/ld-arm/arm-app-abs32.d index 9a4da22b33f78..ce684d44e5060 100644 --- a/ld/testsuite/ld-arm/arm-app-abs32.d +++ b/ld/testsuite/ld-arm/arm-app-abs32.d @@ -7,7 +7,7 @@ start address .* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! @@ -19,9 +19,9 @@ Disassembly of section .text: .* <_start>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} - .*: e59f0004 ldr r0, \[pc, #4\] ; .* <.text\+0x14> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e92dd800 push {fp, ip, lr, pc} + .*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14> + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: .* .* diff --git a/ld/testsuite/ld-arm/arm-app.d b/ld/testsuite/ld-arm/arm-app.d index 207961ea0fa31..3ed76f06e9bfe 100644 --- a/ld/testsuite/ld-arm/arm-app.d +++ b/ld/testsuite/ld-arm/arm-app.d @@ -7,7 +7,7 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! @@ -19,16 +19,16 @@ Disassembly of section .text: .* <_start>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: eb000001 bl .* <app_func> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <app_func>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: ebfffff4 bl .* <_start-0xc> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <app_func2>: diff --git a/ld/testsuite/ld-arm/arm-be8.d b/ld/testsuite/ld-arm/arm-be8.d new file mode 100644 index 0000000000000..43ce9b016e1c6 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-be8.d @@ -0,0 +1,8 @@ + +.*: file format.* + +Contents of section .text: + 8000 0000a0e3 1eff2fe1 c0467047 fff7fcff .* + 8010 12345678 .* +# Ignore .ARM.attributes section +#... diff --git a/ld/testsuite/ld-arm/arm-be8.s b/ld/testsuite/ld-arm/arm-be8.s new file mode 100644 index 0000000000000..871b6911535bf --- /dev/null +++ b/ld/testsuite/ld-arm/arm-be8.s @@ -0,0 +1,14 @@ +.arch armv6 +.text +arm: +mov r0, #0 +$m: +bx lr +.thumb +.thumb_func +thumb: +nop +bx lr +bl thumb +data: +.word 0x12345678 diff --git a/ld/testsuite/ld-arm/arm-call.d b/ld/testsuite/ld-arm/arm-call.d index fd4cd1358cc8e..34c31d9a396a4 100644 --- a/ld/testsuite/ld-arm/arm-call.d +++ b/ld/testsuite/ld-arm/arm-call.d @@ -11,9 +11,9 @@ Disassembly of section .text: 8010: fa00000a blx 8040 <t1> 8014: fb000009 blx 8042 <t2> 8018: ea00000f b 805c <__t1_from_arm> - 801c: ea000011 b 8068 <__t2_from_arm> + 801c: ea000010 b 8064 <__t2_from_arm> 8020: 1b00000d blne 805c <__t1_from_arm> - 8024: 1b00000f blne 8068 <__t2_from_arm> + 8024: 1b00000e blne 8064 <__t2_from_arm> 8028: 1b000003 blne 803c <arm> 802c: eb000002 bl 803c <arm> 8030: faffffff blx 8034 <thumblocal> @@ -48,11 +48,9 @@ Disassembly of section .text: 8058: f7ff efd2 blx 8000 <_start> 0000805c <__t1_from_arm>: - 805c: e59fc000 ldr ip, \[pc, #0\] ; 8064 <__t1_from_arm\+0x8> - 8060: e12fff1c bx ip - 8064: 00008041 andeq r8, r0, r1, asr #32 - -00008068 <__t2_from_arm>: - 8068: e59fc000 ldr ip, \[pc, #0\] ; 8070 <__t2_from_arm\+0x8> - 806c: e12fff1c bx ip - 8070: 00008043 andeq r8, r0, r3, asr #32 + 805c: e51ff004 ldr pc, \[pc, #-4\] ; 8060 <__t1_from_arm\+0x4> + 8060: 00008041 .word 0x00008041 + +00008064 <__t2_from_arm>: + 8064: e51ff004 ldr pc, \[pc, #-4\] ; 8068 <__t2_from_arm\+0x4> + 8068: 00008043 .word 0x00008043 diff --git a/ld/testsuite/ld-arm/arm-dyn.ld b/ld/testsuite/ld-arm/arm-dyn.ld index 96bc10c0c4c5a..4f2e0de39e0ca 100644 --- a/ld/testsuite/ld-arm/arm-dyn.ld +++ b/ld/testsuite/ld-arm/arm-dyn.ld @@ -187,11 +187,6 @@ SECTIONS .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } - .stack 0x80000 : - { - _stack = .; - *(.stack) - } .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } /DISCARD/ : { *(.note.GNU-stack) } } diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 1a9fc00aeb8c0..a83c1eedf0b47 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -21,7 +21,7 @@ if {[istarget "arm-*-vxworks"]} { {"VxWorks shared library test 1" "-shared -Tvxworks1.ld" "" {vxworks1-lib.s} {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd} - {readelf --symbols vxworks1-lib.nd}} + {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}} "libvxworks1.so"} {"VxWorks executable test 1 (dynamic)" \ "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic" @@ -41,6 +41,7 @@ if {[istarget "arm-*-vxworks"]} { } run_ld_link_tests $armvxworkstests run_dump_test "vxworks1-static" + run_dump_test "emit-relocs1-vxworks" } # Exclude non-ARM-ELF targets. @@ -59,6 +60,12 @@ if { ![is_elf_format] || ![istarget "arm*-*-*"] } { # readelf: Apply readelf options on result. Compare with regex (last arg). set armelftests { + {"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s} + {{objdump -Dr group-relocs.d}} + "group-relocs"} + {"Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x401000" "" {thumb1-bl.s} + {{objdump -dr thumb1-bl.d}} + "thumb1-bl"} {"Simple non-PIC shared library" "-shared" "" {arm-lib.s} {{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}} "arm-lib.so"} @@ -74,7 +81,11 @@ set armelftests { {"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s} {{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}} "arm-app-abs32"} - {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld" "" + {"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork" + {mixed-lib.s} + {{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}} + "armthumb-lib.so"} + {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" "" {mixed-lib.s} {{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r} {readelf -Ds mixed-lib.sym}} @@ -122,6 +133,67 @@ set armelftests { {"thumb-rel32" "-static -T arm.ld" "" {thumb-rel32.s} {{objdump -s thumb-rel32.d}} "thumb-rel32"} + {"MOVW/MOVT" "-static -T arm.ld" "" {arm-movwt.s} + {{objdump -dw arm-movwt.d}} + "arm-movwt"} + {"BE8 Mapping Symbols" "-static -T arm.ld -EB --be8" "-EB" {arm-be8.s} + {{objdump -s arm-be8.d}} + "arm-be8"} + {"Using Thumb lib by another lib" "-shared tmpdir/mixed-lib.so" "" {use-thumb-lib.s} + {{readelf -Ds use-thumb-lib.sym}} + "use-thumb-lib.so"} + {"VFP11 denorm erratum fix, scalar operation" + "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-scalar.s} + {{objdump -dr vfp11-fix-scalar.d}} + "vfp11-fix-scalar"} + {"VFP11 denorm erratum fix, vector operation" + "-EB --vfp11-denorm-fix=vector -Ttext=0x8000" "-EB -mfpu=vfpxd" {vfp11-fix-vector.s} + {{objdump -dr vfp11-fix-vector.d}} + "vfp11-fix-vector"} + {"VFP11 denorm erratum fix, embedded code-like data" + "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-none.s} + {{objdump -dr vfp11-fix-none.d}} + "vfp11-fix-none"} + {"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s} + {{objdump -sj.data gc-unwind.d}} + "gc-unwind"} + {"arm-pic-veneer" "-static -T arm.ld --pic-veneer" "" {arm-pic-veneer.s} + {{objdump -d arm-pic-veneer.d}} + "arm-pic-veneer"} + {"Preempt Thumb symbol" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" "" + {preempt-app.s} + {{readelf -Ds preempt-app.sym}} + "preempt-app"} + {"jump19" "-static -T arm.ld" "" {jump19.s} + {{objdump -dr jump19.d}} + "jump19"} + {"EABI attribute merging" "-r" "" {attr-merge.s attr-merge.s} + {{readelf -A attr-merge.attr}} + "attr-merge"} + {"callweak" "-static -T arm.ld" "" {callweak.s} + {{objdump -dr callweak.d}} + "callweak"} } run_ld_link_tests $armelftests +run_dump_test "group-relocs-alu-bad" +run_dump_test "group-relocs-ldr-bad" +run_dump_test "group-relocs-ldrs-bad" +run_dump_test "group-relocs-ldc-bad" +run_dump_test "thumb2-bl-as-thumb1-bad" +run_dump_test "thumb2-bl-bad" +run_dump_test "emit-relocs1" + +# Exclude non-ARM-EABI targets. + +if { ![istarget "arm*-*-*eabi"] } { + return +} + +set armeabitests { + {"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x1001000" "" {thumb2-bl.s} + {{objdump -dr thumb2-bl.d}} + "thumb2-bl"} +} + +run_ld_link_tests $armeabitests diff --git a/ld/testsuite/ld-arm/arm-lib-plt32.d b/ld/testsuite/ld-arm/arm-lib-plt32.d index 58206f43796cf..d1b7944f643cb 100644 --- a/ld/testsuite/ld-arm/arm-lib-plt32.d +++ b/ld/testsuite/ld-arm/arm-lib-plt32.d @@ -7,7 +7,7 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! @@ -19,9 +19,9 @@ Disassembly of section .text: .* <lib_func1>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: ebfffff9 bl .* <lib_func1-0xc> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <lib_func2>: diff --git a/ld/testsuite/ld-arm/arm-lib.d b/ld/testsuite/ld-arm/arm-lib.d index e3257c9551496..9d25bbbfa78f8 100644 --- a/ld/testsuite/ld-arm/arm-lib.d +++ b/ld/testsuite/ld-arm/arm-lib.d @@ -7,7 +7,7 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! @@ -19,9 +19,9 @@ Disassembly of section .text: .* <lib_func1>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: ebfffff9 bl .* <lib_func1-0xc> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <lib_func2>: diff --git a/ld/testsuite/ld-arm/arm-lib.ld b/ld/testsuite/ld-arm/arm-lib.ld index 0415d20d8a676..2d2850e3da10b 100644 --- a/ld/testsuite/ld-arm/arm-lib.ld +++ b/ld/testsuite/ld-arm/arm-lib.ld @@ -180,11 +180,6 @@ SECTIONS .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } - .stack 0x80000 : - { - _stack = .; - *(.stack) - } .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } /DISCARD/ : { *(.note.GNU-stack) } } diff --git a/ld/testsuite/ld-arm/arm-movwt.d b/ld/testsuite/ld-arm/arm-movwt.d new file mode 100644 index 0000000000000..bf551648d6d85 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-movwt.d @@ -0,0 +1,39 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <[^>]*>: + 8000: e3000000 movw r0, #0 ; 0x0 + 8004: e3411234 movt r1, #4660 ; 0x1234 + 8008: e3082000 movw r2, #32768 ; 0x8000 + 800c: e3413233 movt r3, #4659 ; 0x1233 + 8010: e3004011 movw r4, #17 ; 0x11 + 8014: e3415234 movt r5, #4660 ; 0x1234 + 8018: e3086011 movw r6, #32785 ; 0x8011 + 801c: e3417233 movt r7, #4659 ; 0x1233 + +00008020 <[^>]*>: + 8020: f240 0700 movw r7, #0 ; 0x0 + 8024: f2c1 2634 movt r6, #4660 ; 0x1234 + 8028: f248 0500 movw r5, #32768 ; 0x8000 + 802c: f2c1 2433 movt r4, #4659 ; 0x1233 + 8030: f240 0311 movw r3, #17 ; 0x11 + 8034: f2c1 2234 movt r2, #4660 ; 0x1234 + 8038: f248 0111 movw r1, #32785 ; 0x8011 + 803c: f2c1 2033 movt r0, #4659 ; 0x1233 + +Disassembly of section .far: + +12340000 <[^>]*>: +12340000: e3080000 movw r0, #32768 ; 0x8000 +12340004: e34e0dcc movt r0, #60876 ; 0xedcc +12340008: e3080021 movw r0, #32801 ; 0x8021 +1234000c: e34e0dcc movt r0, #60876 ; 0xedcc + +12340010 <[^>]*>: +12340010: f248 0000 movw r0, #32768 ; 0x8000 +12340014: f6ce 50cc movt r0, #60876 ; 0xedcc +12340018: f248 0021 movw r0, #32801 ; 0x8021 +1234001c: f6ce 50cc movt r0, #60876 ; 0xedcc + diff --git a/ld/testsuite/ld-arm/arm-movwt.s b/ld/testsuite/ld-arm/arm-movwt.s new file mode 100644 index 0000000000000..ba8b1c5c2f34f --- /dev/null +++ b/ld/testsuite/ld-arm/arm-movwt.s @@ -0,0 +1,44 @@ + .text + .arch armv6t2 + .syntax unified + .global _start + .type _start, %function +_start: +base1: +arm1: + movw r0, #:lower16:arm2 + movt r1, #:upper16:arm2 + movw r2, #:lower16:(arm2 - arm1) + movt r3, #:upper16:(arm2 - arm1) + movw r4, #:lower16:thumb2 + movt r5, #:upper16:thumb2 + movw r6, #:lower16:(thumb2 - arm1) + movt r7, #:upper16:(thumb2 - arm1) + .thumb + .type thumb1, %function + .thumb_func +thumb1: + movw r7, #:lower16:arm2 + movt r6, #:upper16:arm2 + movw r5, #:lower16:(arm2 - arm1) + movt r4, #:upper16:(arm2 - arm1) + movw r3, #:lower16:thumb2 + movt r2, #:upper16:thumb2 + movw r1, #:lower16:(thumb2 - arm1) + movt r0, #:upper16:(thumb2 - arm1) + + .section .far, "ax", %progbits + .arm +arm2: + movw r0, #:lower16:(arm1 - arm2) + movt r0, #:upper16:(arm1 - arm2) + movw r0, #:lower16:(thumb1 - arm2) + movt r0, #:upper16:(thumb1 - arm2) + .thumb + .type thumb2, %function + .thumb_func +thumb2: + movw r0, #:lower16:(arm1 - arm2) + movt r0, #:upper16:(arm1 - arm2) + movw r0, #:lower16:(thumb1 - arm2) + movt r0, #:upper16:(thumb1 - arm2) diff --git a/ld/testsuite/ld-arm/arm-pic-veneer.d b/ld/testsuite/ld-arm/arm-pic-veneer.d new file mode 100644 index 0000000000000..97eeb52f153d4 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-pic-veneer.d @@ -0,0 +1,17 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <_start>: + 8000: ea000000 b 8008 <__foo_from_arm> + +00008004 <foo>: + 8004: 46c0 nop \(mov r8, r8\) + 8006: 4770 bx lr + +00008008 <__foo_from_arm>: + 8008: e59fc004 ldr ip, \[pc, #4\] ; 8014 <__foo_from_arm\+0xc> + 800c: e08cc00f add ip, ip, pc + 8010: e12fff1c bx ip + 8014: fffffff1 .word 0xfffffff1 diff --git a/ld/testsuite/ld-arm/arm-pic-veneer.s b/ld/testsuite/ld-arm/arm-pic-veneer.s new file mode 100644 index 0000000000000..9e09ed6333771 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-pic-veneer.s @@ -0,0 +1,14 @@ +.text +.arm +.global _start +.type _start, %function +_start: +b foo + +.thumb +.global foo +.type foo, %function +foo: +nop +bx lr + diff --git a/ld/testsuite/ld-arm/arm-static-app.d b/ld/testsuite/ld-arm/arm-static-app.d index 9a3309d6136b2..f18f3c6ceafa2 100644 --- a/ld/testsuite/ld-arm/arm-static-app.d +++ b/ld/testsuite/ld-arm/arm-static-app.d @@ -8,16 +8,16 @@ Disassembly of section .text: .* <_start>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: eb000001 bl .* <app_func> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <app_func>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: eb000001 bl .* <app_func2> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .* <app_func2>: diff --git a/ld/testsuite/ld-arm/arm.ld b/ld/testsuite/ld-arm/arm.ld index 4ef7d824ec223..c9e01e65a8228 100644 --- a/ld/testsuite/ld-arm/arm.ld +++ b/ld/testsuite/ld-arm/arm.ld @@ -14,5 +14,7 @@ SECTIONS } =0 . = 0x9000; .got : { *(.got) *(.got.plt)} + . = 0x12340000; + .far : { *(.far) } .ARM.attribues 0 : { *(.ARM.atttributes) } } diff --git a/ld/testsuite/ld-arm/armthumb-lib.d b/ld/testsuite/ld-arm/armthumb-lib.d new file mode 100644 index 0000000000000..bd45c87fce0c5 --- /dev/null +++ b/ld/testsuite/ld-arm/armthumb-lib.d @@ -0,0 +1,44 @@ + +tmpdir/armthumb-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1c> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop \(mov r0,r0\) + +.* <__real_lib_func2>: + .*: 4770 bx lr + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop \(mov r8, r8\) + +.* <lib_func2>: + .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc> + .*: e08cc00f add ip, ip, pc + .*: e12fff1c bx ip + .*: ffffffe5 .* diff --git a/ld/testsuite/ld-arm/armthumb-lib.sym b/ld/testsuite/ld-arm/armthumb-lib.sym new file mode 100644 index 0000000000000..d482ccd4ba2ab --- /dev/null +++ b/ld/testsuite/ld-arm/armthumb-lib.sym @@ -0,0 +1,17 @@ + +Symbol table for image: + Num Buc: Value Size Type Bind Vis Ndx Name + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end + .. ..: ........ 4 OBJECT GLOBAL DEFAULT 9 data_obj + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__ + .. ..: .......0 20 FUNC GLOBAL DEFAULT 6 lib_func1 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start + .. ..: 00000000 0 NOTYPE GLOBAL DEFAULT UND app_func2 + .. ..: .......0 2 FUNC GLOBAL DEFAULT 6 lib_func2 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end diff --git a/ld/testsuite/ld-arm/attr-merge.attr b/ld/testsuite/ld-arm/attr-merge.attr new file mode 100644 index 0000000000000..341e6d1e412cc --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge.attr @@ -0,0 +1,12 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align8_needed: Yes + Tag_ABI_align8_preserved: Yes, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug diff --git a/ld/testsuite/ld-arm/attr-merge.s b/ld/testsuite/ld-arm/attr-merge.s new file mode 100644 index 0000000000000..b56f6e32d6e36 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 4 + .file "attr-merge.s" diff --git a/ld/testsuite/ld-arm/emit-relocs1-vxworks.d b/ld/testsuite/ld-arm/emit-relocs1-vxworks.d new file mode 100644 index 0000000000000..6d84a4c349b8b --- /dev/null +++ b/ld/testsuite/ld-arm/emit-relocs1-vxworks.d @@ -0,0 +1,12 @@ +#source: emit-relocs1.s +#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs +#objdump: -dr +#... + +10000: e1a00000 nop .* + +10004: e1a00000 nop .* + +10008: e1a00000 nop .* + +1000c: e1a00000 nop .* + +10010: eaffeffa b c000 <target> + +10010: R_ARM_PC24 target\+0xf+8 + +10014: eaffeffd b c010 <target\+0x10> + +10014: R_ARM_PC24 target\+0x8 diff --git a/ld/testsuite/ld-arm/emit-relocs1.d b/ld/testsuite/ld-arm/emit-relocs1.d new file mode 100644 index 0000000000000..191cb52c8670e --- /dev/null +++ b/ld/testsuite/ld-arm/emit-relocs1.d @@ -0,0 +1,12 @@ +#source: emit-relocs1.s +#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs +#objdump: -dr +#... + +10000: e1a00000 nop .* + +10004: e1a00000 nop .* + +10008: e1a00000 nop .* + +1000c: e1a00000 nop .* + +10010: eaffeffa b c000 <target> + +10010: R_ARM_(JUMP|PC)24 target + +10014: eaffeffd b c010 <target\+0x10> + +10014: R_ARM_(JUMP|PC)24 target diff --git a/ld/testsuite/ld-arm/emit-relocs1.s b/ld/testsuite/ld-arm/emit-relocs1.s new file mode 100644 index 0000000000000..8971d4dbfabdc --- /dev/null +++ b/ld/testsuite/ld-arm/emit-relocs1.s @@ -0,0 +1,6 @@ + nop + nop + nop + nop + b target + b target+16 diff --git a/ld/testsuite/ld-arm/gc-unwind.d b/ld/testsuite/ld-arm/gc-unwind.d new file mode 100644 index 0000000000000..fbb79115b8f6e --- /dev/null +++ b/ld/testsuite/ld-arm/gc-unwind.d @@ -0,0 +1,5 @@ + +.*: file format.* + +Contents of section .data: + [^ ]* 22222222 .* diff --git a/ld/testsuite/ld-arm/gc-unwind.s b/ld/testsuite/ld-arm/gc-unwind.s new file mode 100644 index 0000000000000..c5326c28651a2 --- /dev/null +++ b/ld/testsuite/ld-arm/gc-unwind.s @@ -0,0 +1,38 @@ +@ Test -gc-sections and unwinding tables. .data.eh should be pulled in +@ via the EH tables, .data.foo should not. +.text +.global _start +.fnstart +_start: +bx lr +.personality my_pr +.handlerdata +.word 0 +.fnend + +.section .data.foo +my_foo: +.word 0x11111111 + +.section .text.foo +.fnstart +foo: +bx lr +.personality my_pr +.handlerdata +.word my_foo +.fnend + +.section .data.eh +my_eh: +.word 0x22222222 + +.section .text.eh +.fnstart +my_pr: +bx lr +.personality my_pr +.handlerdata +.word my_eh +.fnend + diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.d b/ld/testsuite/ld-arm/group-relocs-alu-bad.d new file mode 100644 index 0000000000000..0346db1a9732d --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.d @@ -0,0 +1,4 @@ +#name: ALU group relocations failure test +#source: group-relocs-alu-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x9010 +#error: Overflow whilst splitting 0x1010 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-alu-bad.s b/ld/testsuite/ld-arm/group-relocs-alu-bad.s new file mode 100644 index 0000000000000..e644669c3b9fc --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-alu-bad.s @@ -0,0 +1,20 @@ +@ Test intended to fail for ALU group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ a specific PC-relative offset arises. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0:(bar) + +@ We will place the section foo at 0x9004. + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.d b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d new file mode 100644 index 0000000000000..d4bfb2dfbddbf --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.d @@ -0,0 +1,4 @@ +#name: LDC group relocations failure test +#source: group-relocs-ldc-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x118400 +#error: Overflow whilst splitting 0x110400 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-ldc-bad.s b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s new file mode 100644 index 0000000000000..611255b063da4 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldc-bad.s @@ -0,0 +1,19 @@ +@ Test intended to fail for LDC group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0_nc:(bar) + ldc 0, c0, [r0, #:pc_g1:(bar + 4)] + +@ We will place the section foo at 0x118400. +@ (The relocations above would be OK if it were at 0x118200, for example.) + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.d b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d new file mode 100644 index 0000000000000..04586af34f5e4 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.d @@ -0,0 +1,4 @@ +#name: LDR group relocations failure test +#source: group-relocs-ldr-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8001000 +#error: .*Overflow whilst splitting 0x8001000 for group relocation.* diff --git a/ld/testsuite/ld-arm/group-relocs-ldr-bad.s b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s new file mode 100644 index 0000000000000..6ab4f3c97469b --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldr-bad.s @@ -0,0 +1,18 @@ +@ Test intended to fail for LDR group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldr r1, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8001000. + + .section foo + +bar: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d new file mode 100644 index 0000000000000..0520184b3363b --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d @@ -0,0 +1,4 @@ +#name: LDRS group relocations failure test +#source: group-relocs-ldrs-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8000100 +#error: Overflow whilst splitting 0x8000100 for group relocation diff --git a/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s new file mode 100644 index 0000000000000..4480d4aa5f02b --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s @@ -0,0 +1,17 @@ +@ Test intended to fail for LDRS group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldrd r2, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8000100. + + .section foo + +bar: + mov r0, #0 diff --git a/ld/testsuite/ld-arm/group-relocs.d b/ld/testsuite/ld-arm/group-relocs.d new file mode 100644 index 0000000000000..d1fdc7d1b773d --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs.d @@ -0,0 +1,69 @@ + +tmpdir/group-relocs: file format elf32-(little|big)arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: e28f00bc add r0, pc, #188 ; 0xbc + 8004: e28f0c6e add r0, pc, #28160 ; 0x6e00 + 8008: e28000ec add r0, r0, #236 ; 0xec + 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000 + 8010: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8014: e28000e4 add r0, r0, #228 ; 0xe4 + 8018: e2800000 add r0, r0, #0 ; 0x0 + 801c: e28f0cee add r0, pc, #60928 ; 0xee00 + 8020: e28000f0 add r0, r0, #240 ; 0xf0 + 8024: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8028: e2800cee add r0, r0, #60928 ; 0xee00 + 802c: e28000f0 add r0, r0, #240 ; 0xf0 + 8030: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8034: e59010c0 ldr r1, \[r0, #192\] + 8038: e28008ff add r0, r0, #16711680 ; 0xff0000 + 803c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8040: e59010b8 ldr r1, \[r0, #184\] + 8044: e5901000 ldr r1, \[r0\] + 8048: e2800cee add r0, r0, #60928 ; 0xee00 + 804c: e59010f0 ldr r1, \[r0, #240\] + 8050: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8054: e2800cee add r0, r0, #60928 ; 0xee00 + 8058: e59010f0 ldr r1, \[r0, #240\] + 805c: e1c026d0 ldrd r2, \[r0, #96\] + 8060: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8064: e1c029d0 ldrd r2, \[r0, #144\] + 8068: e28008ff add r0, r0, #16711680 ; 0xff0000 + 806c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8070: e1c028d8 ldrd r2, \[r0, #136\] + 8074: e1c020d0 ldrd r2, \[r0\] + 8078: e2800cee add r0, r0, #60928 ; 0xee00 + 807c: e1c02fd0 ldrd r2, \[r0, #240\] + 8080: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8084: e2800cee add r0, r0, #60928 ; 0xee00 + 8088: e1c02fd0 ldrd r2, \[r0, #240\] + 808c: ed90000c ldc 0, cr0, \[r0, #48\] + 8090: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8094: ed900018 ldc 0, cr0, \[r0, #96\] + 8098: e28008ff add r0, r0, #16711680 ; 0xff0000 + 809c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 80a0: ed900016 ldc 0, cr0, \[r0, #88\] + 80a4: ed900000 ldc 0, cr0, \[r0\] + 80a8: e2800cee add r0, r0, #60928 ; 0xee00 + 80ac: ed90003c ldc 0, cr0, \[r0, #240\] + 80b0: e28008ff add r0, r0, #16711680 ; 0xff0000 + 80b4: e2800cee add r0, r0, #60928 ; 0xee00 + 80b8: ed90003c ldc 0, cr0, \[r0, #240\] + +000080bc <one_group_needed_alu_pc>: + 80bc: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section zero: + +00000000 <one_group_needed_alu_sb>: + 0: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section alpha: + +0000eef0 <two_groups_needed_alu_pc>: + eef0: e3a00000 mov r0, #0 ; 0x0 +Disassembly of section beta: + +00ffeef0 <three_groups_needed_alu_pc>: + ffeef0: e3a00000 mov r0, #0 ; 0x0 +#... diff --git a/ld/testsuite/ld-arm/group-relocs.s b/ld/testsuite/ld-arm/group-relocs.s new file mode 100644 index 0000000000000..da1a150726810 --- /dev/null +++ b/ld/testsuite/ld-arm/group-relocs.s @@ -0,0 +1,156 @@ +@ Tests for group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ specific PC- and SB-relative offsets arise. +@ +@ Note that the gas tests have already checked that group relocations are +@ handled in the same way for local and external symbols. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + @ ALU, PC-relative + + @ Instructions start at .text + 0x0 + add r0, r15, #:pc_g0:(one_group_needed_alu_pc) + + @ Instructions start at .text + 0x4 + add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc) + add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4) + + @ Instructions start at .text + 0xc + add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4) + add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8) + + @ ALU, SB-relative + + add r0, r0, #:sb_g0:(one_group_needed_alu_sb) + + add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb) + add r0, r0, #:sb_g1:(two_groups_needed_alu_sb) + + add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g2:(three_groups_needed_alu_sb) + + @ LDR, PC-relative + + @ Instructions start at .text + 0x30 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc) + ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)] + + @ Instructions start at .text + 0x38 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4) + ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)] + + @ LDR, SB-relative + + ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)] + + @ LDRS, PC-relative + + @ Instructions start at .text + 0x5c + ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)] + + @ Instructions start at .text + 0x60 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc) + ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)] + + @ Instructions start at .text + 0x68 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4) + ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)] + + @ LDRS, SB-relative + + ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)] + + @ LDC, PC-relative + + @ Instructions start at .text + 0x8c + ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)] + + @ Instructions start at .text + 0x90 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc) + ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)] + + @ Instructions start at .text + 0x98 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4) + ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)] + + @ LDC, SB-relative + + ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)] + +@ This point in the file is .text + 0xbc. + +one_group_needed_alu_pc: +one_group_needed_ldrs_pc: +one_group_needed_ldc_pc: + mov r0, #0 + +@ We will place the section zero at 0x0. + + .section zero + +one_group_needed_alu_sb: +one_group_needed_ldr_sb: +one_group_needed_ldrs_sb: +one_group_needed_ldc_sb: + mov r0, #0 + +@ We will place the section alpha at 0xeef0. + + .section alpha + +two_groups_needed_alu_sb: +two_groups_needed_ldr_sb: +two_groups_needed_ldrs_sb: +two_groups_needed_ldc_sb: +two_groups_needed_alu_pc: +two_groups_needed_ldr_pc: +two_groups_needed_ldrs_pc: +two_groups_needed_ldc_pc: + mov r0, #0 + +@ We will place the section beta at 0xffeef0. + + .section beta + +three_groups_needed_alu_sb: +three_groups_needed_ldr_sb: +three_groups_needed_ldrs_sb: +three_groups_needed_ldc_sb: +three_groups_needed_alu_pc: +three_groups_needed_ldr_pc: +three_groups_needed_ldrs_pc: +three_groups_needed_ldc_pc: + mov r0, #0 + diff --git a/ld/testsuite/ld-arm/jump19.d b/ld/testsuite/ld-arm/jump19.d new file mode 100644 index 0000000000000..303477f622b15 --- /dev/null +++ b/ld/testsuite/ld-arm/jump19.d @@ -0,0 +1,12 @@ + +.*jump19: file format elf32-(big|little)arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: 4280 cmp r0, r0 + 8002: f010 8000 beq.w 18006 <bar> + ... + +00018006 <bar>: + 18006: 4770 bx lr diff --git a/ld/testsuite/ld-arm/jump19.s b/ld/testsuite/ld-arm/jump19.s new file mode 100644 index 0000000000000..1e3ddf06670a2 --- /dev/null +++ b/ld/testsuite/ld-arm/jump19.s @@ -0,0 +1,12 @@ +@ Test the Thumb-2 JUMP19 relocation. + + .syntax unified + .thumb + .global _start +_start: + cmp r0, r0 + beq.w bar + .space 65536 + .weak bar +bar: + bx lr diff --git a/ld/testsuite/ld-arm/mixed-app-v5.d b/ld/testsuite/ld-arm/mixed-app-v5.d index 9e8d4dd194bf5..88317d2d75eac 100644 --- a/ld/testsuite/ld-arm/mixed-app-v5.d +++ b/ld/testsuite/ld-arm/mixed-app-v5.d @@ -7,8 +7,8 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! - .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x20> + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x1c> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* @@ -22,9 +22,9 @@ Disassembly of section .text: .* <_start>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: eb000004 bl .* <app_func> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) @@ -32,9 +32,9 @@ Disassembly of section .text: .* <app_func>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: ebfffff. bl .* - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) diff --git a/ld/testsuite/ld-arm/mixed-app.d b/ld/testsuite/ld-arm/mixed-app.d index 381222727e692..a3679ddf616f1 100644 --- a/ld/testsuite/ld-arm/mixed-app.d +++ b/ld/testsuite/ld-arm/mixed-app.d @@ -7,12 +7,13 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! - .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x20> + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x2c> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: (46c04778 undefined|477846c0 ldrmib r4, \[r8, -r0, asr #13\]!) + .*: 4778 bx pc + .*: 46c0 nop \(mov r8, r8\) .*: e28fc6.* add ip, pc, #.* ; 0x.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]! @@ -23,9 +24,9 @@ Disassembly of section .text: .* <_start>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} + .*: e92dd800 push {fp, ip, lr, pc} .*: eb000004 bl .* <app_func> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) @@ -33,9 +34,9 @@ Disassembly of section .text: .* <app_func>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} - .*: ebfffff. bl .* - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebffff.. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) diff --git a/ld/testsuite/ld-arm/mixed-app.sym b/ld/testsuite/ld-arm/mixed-app.sym index 49c5edf1c5b1d..c63a34382693a 100644 --- a/ld/testsuite/ld-arm/mixed-app.sym +++ b/ld/testsuite/ld-arm/mixed-app.sym @@ -9,7 +9,6 @@ Symbol table for image: .. ..: 0*[^0]*.* 20 FUNC GLOBAL DEFAULT UND lib_func1 .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start .. ..: ........ 0 NOTYPE GLOBAL DEFAULT 11 __data_start - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _stack .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__ .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start .. ..: .......0 0 FUNC GLOBAL DEFAULT 8 app_func2 diff --git a/ld/testsuite/ld-arm/mixed-lib.d b/ld/testsuite/ld-arm/mixed-lib.d index b261c67fae283..d815e51b9a0df 100644 --- a/ld/testsuite/ld-arm/mixed-lib.d +++ b/ld/testsuite/ld-arm/mixed-lib.d @@ -7,8 +7,8 @@ start address 0x.* Disassembly of section .plt: .* <.plt>: - .*: e52de004 str lr, \[sp, #-4\]! - .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1.> + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1c> .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* @@ -19,9 +19,9 @@ Disassembly of section .text: .* <lib_func1>: .*: e1a0c00d mov ip, sp - .*: e92dd800 stmdb sp!, {fp, ip, lr, pc} - .*: ebfffff. bl .* <lib_func1-0x..> - .*: e89d6800 ldmia sp, {fp, sp, lr} + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) diff --git a/ld/testsuite/ld-arm/mixed-lib.sym b/ld/testsuite/ld-arm/mixed-lib.sym index 4ccccdb35aff6..677d2ed6514fc 100644 --- a/ld/testsuite/ld-arm/mixed-lib.sym +++ b/ld/testsuite/ld-arm/mixed-lib.sym @@ -2,17 +2,16 @@ Symbol table for image: Num Buc: Value Size Type Bind Vis Ndx Name .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata - .. ..: .......0 20 FUNC GLOBAL DEFAULT 6 lib_func1 - .. ..: .......1 2 FUNC GLOBAL DEFAULT 6 lib_func2 - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__ - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__ - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _stack - .. ..: ........ 4 OBJECT GLOBAL DEFAULT 9 data_obj .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__ - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end - .. ..: 00000000 0 NOTYPE GLOBAL DEFAULT UND app_func2 - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end + .. ..: ........ 4 OBJECT GLOBAL DEFAULT 9 data_obj + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__ + .. ..: .......0 20 FUNC GLOBAL DEFAULT 6 lib_func1 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start .. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__ - .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start + .. ..: 00000000 0 NOTYPE GLOBAL DEFAULT UND app_func2 + .. ..: .......1 2 FUNC GLOBAL DEFAULT 6 lib_func2 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end diff --git a/ld/testsuite/ld-arm/preempt-app.s b/ld/testsuite/ld-arm/preempt-app.s new file mode 100644 index 0000000000000..f1eccc2b0bb57 --- /dev/null +++ b/ld/testsuite/ld-arm/preempt-app.s @@ -0,0 +1,27 @@ + @ Preempt an ARM shared library function with a Thumb function + @ in the application. + .text + .p2align 4 + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl lib_func1 + ldmia sp, {r11, sp, lr} + bx lr + + .p2align 4 + .globl app_func2 + .type app_func2,%function +app_func2: + bx lr + + .p2align 4 + .globl lib_func1 + .type lib_func1,%function + .thumb_func +lib_func1: + bx lr + + .data + .long data_obj diff --git a/ld/testsuite/ld-arm/preempt-app.sym b/ld/testsuite/ld-arm/preempt-app.sym new file mode 100644 index 0000000000000..d8ebf3b4d8a9f --- /dev/null +++ b/ld/testsuite/ld-arm/preempt-app.sym @@ -0,0 +1,16 @@ + +Symbol table for image: + Num Buc: Value Size Type Bind Vis Ndx Name + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end + .. ..: ........ 4 OBJECT GLOBAL DEFAULT 10 data_obj + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__ + .. ..: .......1 20 FUNC GLOBAL DEFAULT 6 lib_func1 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start + .. ..: .......0 0 FUNC GLOBAL DEFAULT 6 app_func2 + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__ + .. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end diff --git a/ld/testsuite/ld-arm/thumb1-bl.d b/ld/testsuite/ld-arm/thumb1-bl.d new file mode 100644 index 0000000000000..09d70959b68ec --- /dev/null +++ b/ld/testsuite/ld-arm/thumb1-bl.d @@ -0,0 +1,11 @@ + +.*thumb1-bl: file format elf32-.*arm + +Disassembly of section .text: + +00001000 <_start>: + 1000: f3ff fffe bl 401000 <bar> +Disassembly of section .foo: + +00401000 <bar>: + 401000: 4770 bx lr diff --git a/ld/testsuite/ld-arm/thumb1-bl.s b/ld/testsuite/ld-arm/thumb1-bl.s new file mode 100644 index 0000000000000..cdecaa484b6e6 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb1-bl.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-1 BL works. + + .arch armv5t + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x401000. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d b/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d new file mode 100644 index 0000000000000..749b58f56672f --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d @@ -0,0 +1,4 @@ +#name: Thumb-2-as-Thumb-1 BL failure test +#source: thumb2-bl-as-thumb1-bad.s +#ld: -Ttext 0x1000 --section-start .foo=0x401004 +#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_THM_CALL against `bar' diff --git a/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s b/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s new file mode 100644 index 0000000000000..dae5d43972e24 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-1 BL with a Thumb-2-only offset fails. + + .arch armv5t + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x401004. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/ld/testsuite/ld-arm/thumb2-bl-bad.d b/ld/testsuite/ld-arm/thumb2-bl-bad.d new file mode 100644 index 0000000000000..0fc6e043e1fed --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-bad.d @@ -0,0 +1,4 @@ +#name: Thumb-2 BL failure test +#source: thumb2-bl-bad.s +#ld: -Ttext 0x1000 --section-start .foo=0x1001004 +#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_THM_CALL against `bar' diff --git a/ld/testsuite/ld-arm/thumb2-bl-bad.s b/ld/testsuite/ld-arm/thumb2-bl-bad.s new file mode 100644 index 0000000000000..63e3fe7e72711 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-bad.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-2 BL with an oversize offset fails. + + .arch armv7 + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x1001004. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/ld/testsuite/ld-arm/thumb2-bl.d b/ld/testsuite/ld-arm/thumb2-bl.d new file mode 100644 index 0000000000000..bdfb9b79b7e64 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl.d @@ -0,0 +1,11 @@ + +.*thumb2-bl: file format elf32-.*arm + +Disassembly of section .text: + +00001000 <_start>: + 1000: f3ff d7fe bl 1001000 <bar> +Disassembly of section .foo: + +01001000 <bar>: + 1001000: 4770 bx lr diff --git a/ld/testsuite/ld-arm/thumb2-bl.s b/ld/testsuite/ld-arm/thumb2-bl.s new file mode 100644 index 0000000000000..ddb1cd33fcb65 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl.s @@ -0,0 +1,23 @@ +@ Test to ensure that a Thumb-2 BL works with an offset that is +@ not permissable for Thumb-1. + + .arch armv7 + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x1001000. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/ld/testsuite/ld-arm/tls-app.d b/ld/testsuite/ld-arm/tls-app.d index 67e5de4dca5e5..fd3d6380087be 100644 --- a/ld/testsuite/ld-arm/tls-app.d +++ b/ld/testsuite/ld-arm/tls-app.d @@ -2,17 +2,17 @@ .*: file format elf32-.*arm architecture: arm, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED -start address 0x00008220 +start address 0x00008204 Disassembly of section .text: -00008220 <foo>: - 8220: e1a00000 nop \(mov r0,r0\) - 8224: e1a00000 nop \(mov r0,r0\) - 8228: e1a0f00e mov pc, lr - 822c: 000080bc streqh r8, \[r0\], -ip - 8230: 000080b4 streqh r8, \[r0\], -r4 - 8234: 000080ac andeq r8, r0, ip, lsr #1 - 8238: 00000004 andeq r0, r0, r4 - 823c: 000080c4 andeq r8, r0, r4, asr #1 - 8240: 00000014 andeq r0, r0, r4, lsl r0 +00008204 <foo>: + 8204: e1a00000 nop \(mov r0,r0\) + 8208: e1a00000 nop \(mov r0,r0\) + 820c: e1a0f00e mov pc, lr + 8210: 000080bc .word 0x000080bc + 8214: 000080b4 .word 0x000080b4 + 8218: 000080ac .word 0x000080ac + 821c: 00000004 .word 0x00000004 + 8220: 000080c4 .word 0x000080c4 + 8224: 00000014 .word 0x00000014 diff --git a/ld/testsuite/ld-arm/tls-lib.d b/ld/testsuite/ld-arm/tls-lib.d index 76dcfd0c94680..774ac91203f7e 100644 --- a/ld/testsuite/ld-arm/tls-lib.d +++ b/ld/testsuite/ld-arm/tls-lib.d @@ -10,6 +10,6 @@ Disassembly of section .text: .*: e1a00000 nop \(mov r0,r0\) .*: e1a00000 nop \(mov r0,r0\) .*: e1a0f00e mov pc, lr - .*: 00008098 muleq r0, r8, r0 - .*: 0000808c andeq r8, r0, ip, lsl #1 - .*: 00000004 andeq r0, r0, r4 + .*: 00008098 .word 0x00008098 + .*: 0000808c .word 0x0000808c + .*: 00000004 .word 0x00000004 diff --git a/ld/testsuite/ld-arm/use-thumb-lib.s b/ld/testsuite/ld-arm/use-thumb-lib.s new file mode 100644 index 0000000000000..07a7f57b77089 --- /dev/null +++ b/ld/testsuite/ld-arm/use-thumb-lib.s @@ -0,0 +1,25 @@ + .cpu arm10tdmi + .fpu softvfp + .eabi_attribute 18, 4 + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 2 + .eabi_attribute 30, 6 + .file "use_thumb_lib.c" + .text + .align 2 + .global foo + .type foo, %function +foo: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + bl lib_func2 + ldmfd sp, {fp, sp, pc} + .size foo, .-foo + .ident "GCC: (GNU) 4.1.0 (CodeSourcery ARM 2006q1-7)" diff --git a/ld/testsuite/ld-arm/use-thumb-lib.sym b/ld/testsuite/ld-arm/use-thumb-lib.sym new file mode 100644 index 0000000000000..6f845a17e929a --- /dev/null +++ b/ld/testsuite/ld-arm/use-thumb-lib.sym @@ -0,0 +1,4 @@ +#... + .. ..: 00000000 2 FUNC GLOBAL DEFAULT UND lib_func2 +#pass + diff --git a/ld/testsuite/ld-arm/vfp11-fix-none.d b/ld/testsuite/ld-arm/vfp11-fix-none.d new file mode 100644 index 0000000000000..64a67ae207dae --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-none.d @@ -0,0 +1,9 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: ee474a20 \.word 0xee474a20 + 8004: ed927a00 \.word 0xed927a00 + 8008: e12fff1e bx lr diff --git a/ld/testsuite/ld-arm/vfp11-fix-none.s b/ld/testsuite/ld-arm/vfp11-fix-none.s new file mode 100644 index 0000000000000..a016c49411bf6 --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-none.s @@ -0,0 +1,7 @@ + .arm + .text + .globl _start +_start: + .word 0xee474a20 + .word 0xed927a00 + bx lr diff --git a/ld/testsuite/ld-arm/vfp11-fix-scalar.d b/ld/testsuite/ld-arm/vfp11-fix-scalar.d new file mode 100644 index 0000000000000..b7fe136fe076c --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-scalar.d @@ -0,0 +1,15 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: 0a000001 beq 800c <__vfp11_veneer_0> + +00008004 <__vfp11_veneer_0_r>: + 8004: ed927a00 flds s14, \[r2\] + 8008: e12fff1e bx lr + +0000800c <__vfp11_veneer_0>: + 800c: 0e474a20 fmacseq s9, s14, s1 + 8010: eafffffb b 8004 <__vfp11_veneer_0_r> diff --git a/ld/testsuite/ld-arm/vfp11-fix-scalar.s b/ld/testsuite/ld-arm/vfp11-fix-scalar.s new file mode 100644 index 0000000000000..4ffb891df8963 --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-scalar.s @@ -0,0 +1,7 @@ + .arm + .text + .globl _start +_start: + fmacseq s9, s14, s1 + flds s14, [r2] + bx lr diff --git a/ld/testsuite/ld-arm/vfp11-fix-vector.d b/ld/testsuite/ld-arm/vfp11-fix-vector.d new file mode 100644 index 0000000000000..3474b8ce30aa7 --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-vector.d @@ -0,0 +1,16 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: 0a000002 beq 8010 <__vfp11_veneer_0> + +00008004 <__vfp11_veneer_0_r>: + 8004: e1a02003 mov r2, r3 + 8008: ed927a00 flds s14, \[r2\] + 800c: e12fff1e bx lr + +00008010 <__vfp11_veneer_0>: + 8010: 0e474a20 fmacseq s9, s14, s1 + 8014: eafffffa b 8004 <__vfp11_veneer_0_r> diff --git a/ld/testsuite/ld-arm/vfp11-fix-vector.s b/ld/testsuite/ld-arm/vfp11-fix-vector.s new file mode 100644 index 0000000000000..05b6100bf1957 --- /dev/null +++ b/ld/testsuite/ld-arm/vfp11-fix-vector.s @@ -0,0 +1,8 @@ + .arm + .text + .globl _start +_start: + fmacseq s9, s14, s1 + mov r2,r3 + flds s14, [r2] + bx lr diff --git a/ld/testsuite/ld-arm/vxworks1-lib.dd b/ld/testsuite/ld-arm/vxworks1-lib.dd index e13254d908eea..77bdf728c0e65 100644 --- a/ld/testsuite/ld-arm/vxworks1-lib.dd +++ b/ld/testsuite/ld-arm/vxworks1-lib.dd @@ -4,35 +4,35 @@ Disassembly of section \.plt: 00080800 <_PROCEDURE_LINKAGE_TABLE_>: - 80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8> + 80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <.*> 80804: e79cf009 ldr pc, \[ip, r9\] - 80808: 0000000c andeq r0, r0, ip - 8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14> + 80808: 0000000c .word 0x0000000c + 8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <.*> 80810: e599f008 ldr pc, \[r9, #8\] - 80814: 00000000 andeq r0, r0, r0 - 80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20> + 80814: 00000000 .word 0x00000000 + 80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <.*> 8081c: e79cf009 ldr pc, \[ip, r9\] - 80820: 00000010 andeq r0, r0, r0, lsl r0 - 80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <_PROCEDURE_LINKAGE_TABLE_\+0x2c> + 80820: 00000010 .word 0x00000010 + 80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <.*> 80828: e599f008 ldr pc, \[r9, #8\] - 8082c: 0000000c andeq r0, r0, ip + 8082c: 0000000c .word 0x0000000c Disassembly of section \.text: 00080c00 <foo>: - 80c00: e92dc200 stmdb sp!, {r9, lr, pc} - 80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <\.text\+0x30> + 80c00: e92dc200 push {r9, lr, pc} + 80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <.*> 80c08: e5999000 ldr r9, \[r9\] 80c0c: e5999000 ldr r9, \[r9\] - 80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <\.text\+0x34> + 80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <.*> 80c14: e7991000 ldr r1, \[r9, r0\] 80c18: e2811001 add r1, r1, #1 ; 0x1 80c1c: e7891000 str r1, \[r9, r0\] 80c20: eb000004 bl 80c38 <slocal> - 80c24: ebfffefb bl 80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18> - 80c28: ebfffef4 bl 80800 <_PROCEDURE_LINKAGE_TABLE_> - 80c2c: e8bd8200 ldmia sp!, {r9, pc} - 80c30: 00000000 andeq r0, r0, r0 - 80c34: 00000014 andeq r0, r0, r4, lsl r0 + 80c24: ebfffefb bl 80818 <.*> + 80c28: ebfffef4 bl 80800 <.*> + 80c2c: e8bd8200 pop {r9, pc} + 80c30: 00000000 .word 0x00000000 + 80c34: 00000014 .word 0x00000014 00080c38 <slocal>: 80c38: e1a0f00e mov pc, lr diff --git a/ld/testsuite/ld-arm/vxworks1-lib.rd b/ld/testsuite/ld-arm/vxworks1-lib.rd index c4c46f69098fd..226bd0955439a 100644 --- a/ld/testsuite/ld-arm/vxworks1-lib.rd +++ b/ld/testsuite/ld-arm/vxworks1-lib.rd @@ -6,7 +6,7 @@ Relocation section '\.rela\.plt' at offset .* contains 2 entries: Relocation section '\.rela\.dyn' at offset .* contains 4 entries: Offset Info Type Sym\.Value Sym\. Name \+ Addend -00081c00 00000017 R_ARM_RELATIVE * 00080c38 +00081800 00000017 R_ARM_RELATIVE * 00080c38 00080c0c .*06 R_ARM_ABS12 00000000 __GOTT_INDEX__ \+ 0 00080c30 .*02 R_ARM_ABS32 00000000 __GOTT_BASE__ \+ 0 -00081414 .*15 R_ARM_GLOB_DAT 00081800 x \+ 0 +00081414 .*15 R_ARM_GLOB_DAT 00081c00 x \+ 0 diff --git a/ld/testsuite/ld-arm/vxworks1-lib.td b/ld/testsuite/ld-arm/vxworks1-lib.td new file mode 100644 index 0000000000000..9f223e38da16c --- /dev/null +++ b/ld/testsuite/ld-arm/vxworks1-lib.td @@ -0,0 +1,3 @@ +#... + 0x0+16 \(TEXTREL\) +0x0 +#pass diff --git a/ld/testsuite/ld-arm/vxworks1.dd b/ld/testsuite/ld-arm/vxworks1.dd index 529e3a564079d..044312295ab37 100644 --- a/ld/testsuite/ld-arm/vxworks1.dd +++ b/ld/testsuite/ld-arm/vxworks1.dd @@ -5,32 +5,32 @@ Disassembly of section \.plt: 00080800 <_PROCEDURE_LINKAGE_TABLE_>: 80800: e52dc008 str ip, \[sp, #-8\]! - 80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <_PROCEDURE_LINKAGE_TABLE_\+0xc> + 80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <.*> 80808: e59cf008 ldr pc, \[ip, #8\] - 8080c: 00081400 andeq r1, r8, r0, lsl #8 + 8080c: 00081400 .word 0x00081400 8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_ - 80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <_PROCEDURE_LINKAGE_TABLE_\+0x18> + 80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <.*> 80814: e59cf000 ldr pc, \[ip\] - 80818: 0008140c andeq r1, r8, ip, lsl #8 + 80818: 0008140c .word 0x0008140c 80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc - 8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <_PROCEDURE_LINKAGE_TABLE_\+0x24> - 80820: eafffff6 b 80800 <_PROCEDURE_LINKAGE_TABLE_> - 80824: 00000000 andeq r0, r0, r0 - 80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <_PROCEDURE_LINKAGE_TABLE_\+0x30> + 8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <.*> + 80820: eafffff6 b 80800 <.*> + 80824: 00000000 .word 0x00000000 + 80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <.*> 8082c: e59cf000 ldr pc, \[ip\] - 80830: 00081410 andeq r1, r8, r0, lsl r4 + 80830: 00081410 .word 0x00081410 80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10 - 80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <_PROCEDURE_LINKAGE_TABLE_\+0x3c> - 80838: eafffff0 b 80800 <_PROCEDURE_LINKAGE_TABLE_> - 8083c: 0000000c andeq r0, r0, ip + 80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <.*> + 80838: eafffff0 b 80800 <.*> + 8083c: 0000000c .word 0x0000000c Disassembly of section \.text: 00080c00 <_start>: - 80c00: ebffff08 bl 80428 <_PROCEDURE_LINKAGE_TABLE_-0x3d8> + 80c00: ebffff08 bl 80828 <.*> 80c00: R_ARM_PC24 \.plt\+0x20 - 80c04: eb000000 bl 80c14 <sexternal\+0x8> + 80c04: eb000000 bl 80c0c <sexternal> 80c04: R_ARM_PC24 sexternal\+0xfffffff8 - 80c08: eaffff00 b 80408 <_PROCEDURE_LINKAGE_TABLE_-0x3f8> + 80c08: eaffff00 b 80810 <.*> 80c08: R_ARM_PC24 \.plt\+0x8 00080c0c <sexternal>: diff --git a/ld/testsuite/ld-arm/vxworks1.ld b/ld/testsuite/ld-arm/vxworks1.ld index ec5039d47ed30..65bf65d4e2ed4 100644 --- a/ld/testsuite/ld-arm/vxworks1.ld +++ b/ld/testsuite/ld-arm/vxworks1.ld @@ -23,8 +23,8 @@ SECTIONS .got : { *(.got.plt) *(.got) } . = ALIGN (0x400); - .bss : { *(.bss) *(.dynbss) } + .data : { *(.data) } . = ALIGN (0x400); - .data : { *(.data) } + .bss : { *(.bss) *(.dynbss) } } |