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-rw-r--r--lib/CodeGen/TargetRegisterInfo.cpp119
1 files changed, 74 insertions, 45 deletions
diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp
index eeb00a784b0d9..f03c3b8300f3c 100644
--- a/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/lib/CodeGen/TargetRegisterInfo.cpp
@@ -11,13 +11,17 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -27,9 +31,6 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Printable.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <utility>
@@ -41,11 +42,14 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *SRINames,
const LaneBitmask *SRILaneMasks,
- LaneBitmask SRICoveringLanes)
+ LaneBitmask SRICoveringLanes,
+ const RegClassInfo *const RCIs,
+ unsigned Mode)
: InfoDesc(ID), SubRegIndexNames(SRINames),
SubRegIndexLaneMasks(SRILaneMasks),
RegClassBegin(RCB), RegClassEnd(RCE),
- CoveringLanes(SRICoveringLanes) {
+ CoveringLanes(SRICoveringLanes),
+ RCInfos(RCIs), HwMode(Mode) {
}
TargetRegisterInfo::~TargetRegisterInfo() = default;
@@ -65,8 +69,8 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
continue;
for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
- dbgs() << "Error: Super register " << PrintReg(*SR, this)
- << " of reserved register " << PrintReg(Reg, this)
+ dbgs() << "Error: Super register " << printReg(*SR, this)
+ << " of reserved register " << printReg(Reg, this)
<< " is not reserved.\n";
return false;
}
@@ -81,7 +85,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
namespace llvm {
-Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
+Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg)
@@ -89,11 +93,15 @@ Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg))
- OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
- else if (TRI && Reg < TRI->getNumRegs())
- OS << '%' << TRI->getName(Reg);
- else
- OS << "%physreg" << Reg;
+ OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
+ else if (!TRI)
+ OS << '%' << "physreg" << Reg;
+ else if (Reg < TRI->getNumRegs()) {
+ OS << '%';
+ printLowerCase(TRI->getName(Reg), OS);
+ } else
+ llvm_unreachable("Register kind is unsupported.");
+
if (SubIdx) {
if (TRI)
OS << ':' << TRI->getSubRegIndexName(SubIdx);
@@ -103,7 +111,7 @@ Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
});
}
-Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
// Generic printout when TRI is missing.
if (!TRI) {
@@ -126,12 +134,27 @@ Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
});
}
-Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
if (TRI && TRI->isVirtualRegister(Unit)) {
- OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
+ OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
} else {
- OS << PrintRegUnit(Unit, TRI);
+ OS << printRegUnit(Unit, TRI);
+ }
+ });
+}
+
+Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
+ const TargetRegisterInfo *TRI) {
+ return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
+ if (RegInfo.getRegClassOrNull(Reg))
+ OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
+ else if (RegInfo.getRegBankOrNull(Reg))
+ OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
+ else {
+ OS << "_";
+ assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
+ "Generic registers must have a valid type");
}
});
}
@@ -357,7 +380,7 @@ bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
}
// Compute target-independent register allocator hints to help eliminate copies.
-void
+bool
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
@@ -365,49 +388,55 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
- std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
+ const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
+ MRI.getRegAllocationHints(VirtReg);
- // Hints with HintType != 0 were set by target-dependent code.
- // Such targets must provide their own implementation of
- // TRI::getRegAllocationHints to interpret those hint types.
- assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints");
+ // First hint may be a target hint.
+ bool Skip = (Hints_MRI.first != 0);
+ for (auto Reg : Hints_MRI.second) {
+ if (Skip) {
+ Skip = false;
+ continue;
+ }
- // Target-independent hints are either a physical or a virtual register.
- unsigned Phys = Hint.second;
- if (VRM && isVirtualRegister(Phys))
- Phys = VRM->getPhys(Phys);
+ // Target-independent hints are either a physical or a virtual register.
+ unsigned Phys = Reg;
+ if (VRM && isVirtualRegister(Phys))
+ Phys = VRM->getPhys(Phys);
- // Check that Phys is a valid hint in VirtReg's register class.
- if (!isPhysicalRegister(Phys))
- return;
- if (MRI.isReserved(Phys))
- return;
- // Check that Phys is in the allocation order. We shouldn't heed hints
- // from VirtReg's register class if they aren't in the allocation order. The
- // target probably has a reason for removing the register.
- if (!is_contained(Order, Phys))
- return;
+ // Check that Phys is a valid hint in VirtReg's register class.
+ if (!isPhysicalRegister(Phys))
+ continue;
+ if (MRI.isReserved(Phys))
+ continue;
+ // Check that Phys is in the allocation order. We shouldn't heed hints
+ // from VirtReg's register class if they aren't in the allocation order. The
+ // target probably has a reason for removing the register.
+ if (!is_contained(Order, Phys))
+ continue;
- // All clear, tell the register allocator to prefer this register.
- Hints.push_back(Phys);
+ // All clear, tell the register allocator to prefer this register.
+ Hints.push_back(Phys);
+ }
+ return false;
}
bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
- return !MF.getFunction()->hasFnAttribute("no-realign-stack");
+ return !MF.getFunction().hasFnAttribute("no-realign-stack");
}
bool TargetRegisterInfo::needsStackRealignment(
const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
- const Function *F = MF.getFunction();
+ const Function &F = MF.getFunction();
unsigned StackAlign = TFI->getStackAlignment();
bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
- F->hasFnAttribute(Attribute::StackAlignment));
- if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) {
+ F.hasFnAttribute(Attribute::StackAlignment));
+ if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
if (canRealignStack(MF))
return true;
- DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
+ DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n");
}
return false;
}
@@ -425,6 +454,6 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
LLVM_DUMP_METHOD
void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
const TargetRegisterInfo *TRI) {
- dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
+ dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
}
#endif
generated by cgit v1.3 (git 2.53.0) at 2026-05-13 09:30:42 +0000