summaryrefslogtreecommitdiff
path: root/lib/Target/AMDGPU/R600ISelLowering.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/AMDGPU/R600ISelLowering.cpp')
-rw-r--r--lib/Target/AMDGPU/R600ISelLowering.cpp52
1 files changed, 30 insertions, 22 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 69a63b6941ef2..66291d0be4e6b 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -211,6 +211,11 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ if (!Subtarget->hasFMA()) {
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ }
+
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
@@ -1145,7 +1150,9 @@ SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
// Load dword
// TODO: can we be smarter about machine pointer info?
- SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo());
+ MachinePointerInfo PtrInfo(UndefValue::get(
+ Type::getInt32PtrTy(*DAG.getContext(), AMDGPUASI.PRIVATE_ADDRESS)));
+ SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
Chain = Dst.getValue(1);
@@ -1184,7 +1191,7 @@ SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
// Store dword
// TODO: Can we be smarter about MachinePointerInfo?
- SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, MachinePointerInfo());
+ SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo);
// If we are part of expanded vector, make our neighbors depend on this store
if (VectorTrunc) {
@@ -1308,39 +1315,39 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
// return (512 + (kc_bank << 12)
static int
-ConstantAddressBlock(unsigned AddressSpace, AMDGPUAS AMDGPUASI) {
+ConstantAddressBlock(unsigned AddressSpace) {
switch (AddressSpace) {
- case AMDGPUASI.CONSTANT_BUFFER_0:
+ case AMDGPUAS::CONSTANT_BUFFER_0:
return 512;
- case AMDGPUASI.CONSTANT_BUFFER_1:
+ case AMDGPUAS::CONSTANT_BUFFER_1:
return 512 + 4096;
- case AMDGPUASI.CONSTANT_BUFFER_2:
+ case AMDGPUAS::CONSTANT_BUFFER_2:
return 512 + 4096 * 2;
- case AMDGPUASI.CONSTANT_BUFFER_3:
+ case AMDGPUAS::CONSTANT_BUFFER_3:
return 512 + 4096 * 3;
- case AMDGPUASI.CONSTANT_BUFFER_4:
+ case AMDGPUAS::CONSTANT_BUFFER_4:
return 512 + 4096 * 4;
- case AMDGPUASI.CONSTANT_BUFFER_5:
+ case AMDGPUAS::CONSTANT_BUFFER_5:
return 512 + 4096 * 5;
- case AMDGPUASI.CONSTANT_BUFFER_6:
+ case AMDGPUAS::CONSTANT_BUFFER_6:
return 512 + 4096 * 6;
- case AMDGPUASI.CONSTANT_BUFFER_7:
+ case AMDGPUAS::CONSTANT_BUFFER_7:
return 512 + 4096 * 7;
- case AMDGPUASI.CONSTANT_BUFFER_8:
+ case AMDGPUAS::CONSTANT_BUFFER_8:
return 512 + 4096 * 8;
- case AMDGPUASI.CONSTANT_BUFFER_9:
+ case AMDGPUAS::CONSTANT_BUFFER_9:
return 512 + 4096 * 9;
- case AMDGPUASI.CONSTANT_BUFFER_10:
+ case AMDGPUAS::CONSTANT_BUFFER_10:
return 512 + 4096 * 10;
- case AMDGPUASI.CONSTANT_BUFFER_11:
+ case AMDGPUAS::CONSTANT_BUFFER_11:
return 512 + 4096 * 11;
- case AMDGPUASI.CONSTANT_BUFFER_12:
+ case AMDGPUAS::CONSTANT_BUFFER_12:
return 512 + 4096 * 12;
- case AMDGPUASI.CONSTANT_BUFFER_13:
+ case AMDGPUAS::CONSTANT_BUFFER_13:
return 512 + 4096 * 13;
- case AMDGPUASI.CONSTANT_BUFFER_14:
+ case AMDGPUAS::CONSTANT_BUFFER_14:
return 512 + 4096 * 14;
- case AMDGPUASI.CONSTANT_BUFFER_15:
+ case AMDGPUAS::CONSTANT_BUFFER_15:
return 512 + 4096 * 15;
default:
return -1;
@@ -1371,7 +1378,9 @@ SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
// Load dword
// TODO: can we be smarter about machine pointer info?
- SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo());
+ MachinePointerInfo PtrInfo(UndefValue::get(
+ Type::getInt32PtrTy(*DAG.getContext(), AMDGPUASI.PRIVATE_ADDRESS)));
+ SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
// Get offset within the register.
SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
@@ -1424,8 +1433,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
return scalarizeVectorLoad(LoadNode, DAG);
}
- int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace(),
- AMDGPUASI);
+ int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
if (ConstantBlock > -1 &&
((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
(LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {