diff options
Diffstat (limited to 'lib/Target/AMDGPU/SIMachineScheduler.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/SIMachineScheduler.cpp | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/lib/Target/AMDGPU/SIMachineScheduler.cpp b/lib/Target/AMDGPU/SIMachineScheduler.cpp index 18754442898f7..fb7e670068fe6 100644 --- a/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -471,7 +471,7 @@ void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) { #ifndef NDEBUG if (SuccSU->NumPredsLeft == 0) { dbgs() << "*** Scheduling failed! ***\n"; - SuccSU->dump(DAG); + DAG->dumpNode(*SuccSU); dbgs() << " has been released too many times!\n"; llvm_unreachable(nullptr); } @@ -611,13 +611,11 @@ void SIScheduleBlock::printDebug(bool full) { dbgs() << "\nInstructions:\n"; if (!Scheduled) { - for (SUnit* SU : SUnits) { - SU->dump(DAG); - } + for (const SUnit* SU : SUnits) + DAG->dumpNode(*SU); } else { - for (SUnit* SU : SUnits) { - SU->dump(DAG); - } + for (const SUnit* SU : SUnits) + DAG->dumpNode(*SU); } dbgs() << "///////////////////////\n"; @@ -1933,7 +1931,7 @@ void SIScheduleDAGMI::schedule() LLVM_DEBUG(dbgs() << "Preparing Scheduling\n"); buildDAGWithRegPressure(); - LLVM_DEBUG(for (SUnit &SU : SUnits) SU.dumpAll(this)); + LLVM_DEBUG(dump()); topologicalSort(); findRootsAndBiasEdges(TopRoots, BotRoots); @@ -1957,12 +1955,12 @@ void SIScheduleDAGMI::schedule() for (unsigned i = 0, e = (unsigned)SUnits.size(); i != e; ++i) { SUnit *SU = &SUnits[i]; - unsigned BaseLatReg; + MachineOperand *BaseLatOp; int64_t OffLatReg; if (SITII->isLowLatencyInstruction(*SU->getInstr())) { IsLowLatencySU[i] = 1; - if (SITII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseLatReg, OffLatReg, - TRI)) + if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg, + TRI)) LowLatencyOffset[i] = OffLatReg; } else if (SITII->isHighLatencyInstruction(*SU->getInstr())) IsHighLatencySU[i] = 1; |