diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonScheduleV62.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonScheduleV62.td | 112 |
1 files changed, 10 insertions, 102 deletions
diff --git a/lib/Target/Hexagon/HexagonScheduleV62.td b/lib/Target/Hexagon/HexagonScheduleV62.td index 0758788a600be..a0a8595f185fb 100644 --- a/lib/Target/Hexagon/HexagonScheduleV62.td +++ b/lib/Target/Hexagon/HexagonScheduleV62.td @@ -6,115 +6,23 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// +// ScalarItin contains some old itineraries still used by a +// handful of instructions. Hopefully, we will be able to get rid of them soon. -// V62 follows the same schedule as V60 with following exceptions: -// Following instructions are permissible on any slot on V62: -// V4_J4_cmpeq_fp0_jump_nt -// V4_J4_cmpeq_fp0_jump_t -// V4_J4_cmpeq_fp1_jump_nt -// V4_J4_cmpeq_fp1_jump_t -// V4_J4_cmpeq_tp0_jump_nt -// V4_J4_cmpeq_tp0_jump_t -// V4_J4_cmpeq_tp1_jump_nt -// V4_J4_cmpeq_tp1_jump_t -// V4_J4_cmpeqi_fp0_jump_nt -// V4_J4_cmpeqi_fp0_jump_t -// V4_J4_cmpeqi_fp1_jump_nt -// V4_J4_cmpeqi_fp1_jump_t -// V4_J4_cmpeqi_tp0_jump_nt -// V4_J4_cmpeqi_tp0_jump_t -// V4_J4_cmpeqi_tp1_jump_nt -// V4_J4_cmpeqi_tp1_jump_t -// V4_J4_cmpeqn1_fp0_jump_nt -// V4_J4_cmpeqn1_fp0_jump_t -// V4_J4_cmpeqn1_fp1_jump_nt -// V4_J4_cmpeqn1_fp1_jump_t -// V4_J4_cmpeqn1_tp0_jump_nt -// V4_J4_cmpeqn1_tp0_jump_t -// V4_J4_cmpeqn1_tp1_jump_nt -// V4_J4_cmpeqn1_tp1_jump_t -// V4_J4_cmpgt_fp0_jump_nt -// V4_J4_cmpgt_fp0_jump_t -// V4_J4_cmpgt_fp1_jump_nt -// V4_J4_cmpgt_fp1_jump_t -// V4_J4_cmpgt_tp0_jump_nt -// V4_J4_cmpgt_tp0_jump_t -// V4_J4_cmpgt_tp1_jump_nt -// V4_J4_cmpgt_tp1_jump_t -// V4_J4_cmpgti_fp0_jump_nt -// V4_J4_cmpgti_fp0_jump_t -// V4_J4_cmpgti_fp1_jump_nt -// V4_J4_cmpgti_fp1_jump_t -// V4_J4_cmpgti_tp0_jump_nt -// V4_J4_cmpgti_tp0_jump_t -// V4_J4_cmpgti_tp1_jump_nt -// V4_J4_cmpgti_tp1_jump_t -// V4_J4_cmpgtn1_fp0_jump_nt -// V4_J4_cmpgtn1_fp0_jump_t -// V4_J4_cmpgtn1_fp1_jump_nt -// V4_J4_cmpgtn1_fp1_jump_t -// V4_J4_cmpgtn1_tp0_jump_nt -// V4_J4_cmpgtn1_tp0_jump_t -// V4_J4_cmpgtn1_tp1_jump_nt -// V4_J4_cmpgtn1_tp1_jump_t -// V4_J4_cmpgtu_fp0_jump_nt -// V4_J4_cmpgtu_fp0_jump_t -// V4_J4_cmpgtu_fp1_jump_nt -// V4_J4_cmpgtu_fp1_jump_t -// V4_J4_cmpgtu_tp0_jump_nt -// V4_J4_cmpgtu_tp0_jump_t -// V4_J4_cmpgtu_tp1_jump_nt -// V4_J4_cmpgtu_tp1_jump_t -// V4_J4_cmpgtui_fp0_jump_nt -// V4_J4_cmpgtui_fp0_jump_t -// V4_J4_cmpgtui_fp1_jump_nt -// V4_J4_cmpgtui_fp1_jump_t -// V4_J4_cmpgtui_tp0_jump_nt -// V4_J4_cmpgtui_tp0_jump_t -// V4_J4_cmpgtui_tp1_jump_nt -// V4_J4_cmpgtui_tp1_jump_t -// V4_J4_tstbit0_fp0_jump_nt -// V4_J4_tstbit0_fp0_jump_t -// V4_J4_tstbit0_fp1_jump_nt -// V4_J4_tstbit0_fp1_jump_t -// V4_J4_tstbit0_tp0_jump_nt -// V4_J4_tstbit0_tp0_jump_t -// V4_J4_tstbit0_tp1_jump_nt -// V4_J4_tstbit0_tp1_jump_t -// JMP -// JMPEXT -// JMPEXT_f -// JMPEXT_fnew_nt -// JMPEXT_fnew_t -// JMPEXT_t -// JMPEXT_tnew_nt -// JMPEXT_tnew_t -// JMPNOTEXT -// JMPNOTEXT_f -// JMPNOTEXT_fnew_nt -// JMPNOTEXT_fnew_t -// JMPNOTEXT_t -// JMPNOTEXT_tnew_nt -// JMPNOTEXT_tnew_t -// JMP_f -// JMP_fnew_nt -// JMP_fnew_t -// JMP_t -// JMP_tnew_nt -// JMP_tnew_t -// RESTORE_DEALLOC_RET_JMP_V4 -// RESTORE_DEALLOC_RET_JMP_V4_EXT - -def HexagonV62ItinList : ScalarItin, HVXV62Itin { +def HexagonV62ItinList : DepScalarItinV62, ScalarItin, + DepHVXItinV62, HVXItin, PseudoItin { list<InstrItinData> ItinList = - !listconcat(ScalarItin_list, HVXV62Itin_list); + !listconcat(DepScalarItinV62_list, ScalarItin_list, + DepHVXItinV62_list, HVXItin_list, PseudoItin_list); } def HexagonItinerariesV62 : ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, - CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], - [], HexagonV62ItinList.ItinList>; + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM], + [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>; def HexagonModelV62 : SchedMachineModel { // Max issue per cycle == bundle width. |