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-rw-r--r--lib/Target/Hexagon/HexagonExpandCondsets.cpp15
-rw-r--r--lib/Target/Hexagon/HexagonFrameLowering.cpp61
-rw-r--r--lib/Target/Hexagon/HexagonGenMux.cpp86
-rw-r--r--lib/Target/Hexagon/HexagonInstrInfo.cpp10
-rw-r--r--lib/Target/Hexagon/HexagonNewValueJump.cpp2
-rw-r--r--lib/Target/Hexagon/HexagonPeephole.cpp54
-rw-r--r--lib/Target/Hexagon/HexagonSubtarget.cpp32
-rw-r--r--lib/Target/Hexagon/HexagonSubtarget.h22
-rw-r--r--lib/Target/Hexagon/HexagonTargetMachine.cpp1
-rw-r--r--lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp18
-rw-r--r--lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp53
11 files changed, 188 insertions, 166 deletions
diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 9f8c9ded8127b..734f3c6658d92 100644
--- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -567,8 +567,19 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
}
llvm_unreachable("Invalid register operand");
}
- if (SO.isImm() || SO.isFPImm())
- return IfTrue ? C2_cmoveit : C2_cmoveif;
+ switch (SO.getType()) {
+ case MachineOperand::MO_Immediate:
+ case MachineOperand::MO_FPImmediate:
+ case MachineOperand::MO_ConstantPoolIndex:
+ case MachineOperand::MO_TargetIndex:
+ case MachineOperand::MO_JumpTableIndex:
+ case MachineOperand::MO_ExternalSymbol:
+ case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_BlockAddress:
+ return IfTrue ? C2_cmoveit : C2_cmoveif;
+ default:
+ break;
+ }
llvm_unreachable("Unexpected source operand");
}
diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 18e49c69b8e36..2b0ceaa66258e 100644
--- a/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1051,10 +1051,26 @@ int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
bool HasExtraAlign = HRI.needsStackRealignment(MF);
bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ unsigned FrameSize = MFI.getStackSize();
unsigned SP = HRI.getStackRegister(), FP = HRI.getFrameRegister();
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
unsigned AP = HMFI.getStackAlignBasePhysReg();
- unsigned FrameSize = MFI.getStackSize();
+ // It may happen that AP will be absent even HasAlloca && HasExtraAlign
+ // is true. HasExtraAlign may be set because of vector spills, without
+ // aligned locals or aligned outgoing function arguments. Since vector
+ // spills will ultimately be "unaligned", it is safe to use FP as the
+ // base register.
+ // In fact, in such a scenario the stack is actually not required to be
+ // aligned, although it may end up being aligned anyway, since this
+ // particular case is not easily detectable. The alignment will be
+ // unnecessary, but not incorrect.
+ // Unfortunately there is no quick way to verify that the above is
+ // indeed the case (and that it's not a result of an error), so just
+ // assume that missing AP will be replaced by FP.
+ // (A better fix would be to rematerialize AP from FP and always align
+ // vector spills.)
+ if (AP == 0)
+ AP = FP;
bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
// Use FP at -O0, except when there are objects with extra alignment.
@@ -2454,9 +2470,44 @@ bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
auto &HST = MF.getSubtarget<HexagonSubtarget>();
// A fairly simplistic guess as to whether a potential load/store to a
- // stack location could require an extra register. It does not account
- // for store-immediate instructions.
- if (HST.useHVXOps())
- return StackSize > 256;
+ // stack location could require an extra register.
+ if (HST.useHVXOps() && StackSize > 256)
+ return true;
+
+ // Check if the function has store-immediate instructions that access
+ // the stack. Since the offset field is not extendable, if the stack
+ // size exceeds the offset limit (6 bits, shifted), the stores will
+ // require a new base register.
+ bool HasImmStack = false;
+ unsigned MinLS = ~0u; // Log_2 of the memory access size.
+
+ for (const MachineBasicBlock &B : MF) {
+ for (const MachineInstr &MI : B) {
+ unsigned LS = 0;
+ switch (MI.getOpcode()) {
+ case Hexagon::S4_storeirit_io:
+ case Hexagon::S4_storeirif_io:
+ case Hexagon::S4_storeiri_io:
+ ++LS;
+ LLVM_FALLTHROUGH;
+ case Hexagon::S4_storeirht_io:
+ case Hexagon::S4_storeirhf_io:
+ case Hexagon::S4_storeirh_io:
+ ++LS;
+ LLVM_FALLTHROUGH;
+ case Hexagon::S4_storeirbt_io:
+ case Hexagon::S4_storeirbf_io:
+ case Hexagon::S4_storeirb_io:
+ if (MI.getOperand(0).isFI())
+ HasImmStack = true;
+ MinLS = std::min(MinLS, LS);
+ break;
+ }
+ }
+ }
+
+ if (HasImmStack)
+ return !isUInt<6>(StackSize >> MinLS);
+
return false;
}
diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp
index 11ac5454f6043..5abbcbba72ddd 100644
--- a/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -28,6 +28,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -295,15 +296,12 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0;
bool Failure = false, CanUp = true, CanDown = true;
- bool Used1 = false, Used2 = false;
for (unsigned X = MinX+1; X < MaxX; X++) {
const DefUseInfo &DU = DUM.lookup(X);
if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) {
Failure = true;
break;
}
- Used1 |= DU.Uses[SR1];
- Used2 |= DU.Uses[SR2];
if (CanDown && DU.Defs[SR1])
CanDown = false;
if (CanUp && DU.Defs[SR2])
@@ -317,64 +315,52 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
// Prefer "down", since this will move the MUX farther away from the
// predicate definition.
MachineBasicBlock::iterator At = CanDown ? Def2 : Def1;
- if (CanDown) {
- // If the MUX is placed "down", we need to make sure that there aren't
- // any kills of the source registers between the two defs.
- if (Used1 || Used2) {
- auto ResetKill = [this] (unsigned Reg, MachineInstr &MI) -> bool {
- if (MachineOperand *Op = MI.findRegisterUseOperand(Reg, true, HRI)) {
- Op->setIsKill(false);
- return true;
- }
- return false;
- };
- bool KilledSR1 = false, KilledSR2 = false;
- for (MachineInstr &MJ : make_range(std::next(It1), It2)) {
- if (SR1)
- KilledSR1 |= ResetKill(SR1, MJ);
- if (SR2)
- KilledSR2 |= ResetKill(SR1, MJ);
- }
- // If any of the source registers were killed in this range, transfer
- // the kills to the source operands: they will me "moved" to the
- // resulting MUX and their parent instructions will be deleted.
- if (KilledSR1) {
- assert(Src1->isReg());
- Src1->setIsKill(true);
- }
- if (KilledSR2) {
- assert(Src2->isReg());
- Src2->setIsKill(true);
- }
- }
- } else {
- // If the MUX is placed "up", it shouldn't kill any source registers
- // that are still used afterwards. We can reset the kill flags directly
- // on the operands, because the source instructions will be erased.
- if (Used1 && Src1->isReg())
- Src1->setIsKill(false);
- if (Used2 && Src2->isReg())
- Src2->setIsKill(false);
- }
ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
}
- for (unsigned I = 0, N = ML.size(); I < N; ++I) {
- MuxInfo &MX = ML[I];
- MachineBasicBlock &B = *MX.At->getParent();
- DebugLoc DL = MX.At->getDebugLoc();
+ for (MuxInfo &MX : ML) {
unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF);
if (!MxOpc)
continue;
- BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
- .addReg(MX.PredR)
- .add(*MX.SrcT)
- .add(*MX.SrcF);
+ MachineBasicBlock &B = *MX.At->getParent();
+ const DebugLoc &DL = B.findDebugLoc(MX.At);
+ auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
+ .addReg(MX.PredR)
+ .add(*MX.SrcT)
+ .add(*MX.SrcF);
+ NewMux->clearKillInfo();
B.erase(MX.Def1);
B.erase(MX.Def2);
Changed = true;
}
+ // Fix up kill flags.
+
+ LivePhysRegs LPR(*HRI);
+ LPR.addLiveOuts(B);
+ auto IsLive = [&LPR,this] (unsigned Reg) -> bool {
+ for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S)
+ if (LPR.contains(*S))
+ return true;
+ return false;
+ };
+ for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {
+ if (I->isDebugValue())
+ continue;
+ // This isn't 100% accurate, but it's safe.
+ // It won't detect (as a kill) a case like this
+ // r0 = add r0, 1 <-- r0 should be "killed"
+ // ... = r0
+ for (MachineOperand &Op : I->operands()) {
+ if (!Op.isReg() || !Op.isUse())
+ continue;
+ assert(Op.getSubReg() == 0 && "Should have physical registers only");
+ bool Live = IsLive(Op.getReg());
+ Op.setIsKill(!Live);
+ }
+ LPR.stepBackward(*I);
+ }
+
return Changed;
}
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index f43101fa456d5..fec2dc5ce3066 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -94,10 +94,6 @@ static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
///
/// Constants for Hexagon instructions.
///
-const int Hexagon_MEMV_OFFSET_MAX_128B = 896; // #s4: -8*128...7*128
-const int Hexagon_MEMV_OFFSET_MIN_128B = -1024; // #s4
-const int Hexagon_MEMV_OFFSET_MAX = 448; // #s4: -8*64...7*64
-const int Hexagon_MEMV_OFFSET_MIN = -512; // #s4
const int Hexagon_MEMW_OFFSET_MAX = 4095;
const int Hexagon_MEMW_OFFSET_MIN = -4096;
const int Hexagon_MEMD_OFFSET_MAX = 8191;
@@ -2443,8 +2439,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
case Hexagon::V6_vS32b_ai:
case Hexagon::V6_vL32Ub_ai:
case Hexagon::V6_vS32Ub_ai:
- return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
- (Offset <= Hexagon_MEMV_OFFSET_MAX);
+ return isShiftedInt<4,6>(Offset);
case Hexagon::PS_vstorerq_ai_128B:
case Hexagon::PS_vstorerw_ai_128B:
@@ -2454,8 +2449,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
case Hexagon::V6_vS32b_ai_128B:
case Hexagon::V6_vL32Ub_ai_128B:
case Hexagon::V6_vS32Ub_ai_128B:
- return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
- (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
+ return isShiftedInt<4,7>(Offset);
case Hexagon::J2_loop0i:
case Hexagon::J2_loop1i:
diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp
index d73fc7c73185d..de6b203015d8e 100644
--- a/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -629,7 +629,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
if (MO.isReg() && MO.isUse()) {
unsigned feederReg = MO.getReg();
for (MachineBasicBlock::iterator localII = feederPos,
- end = jmpPos; localII != end; localII++) {
+ end = cmpInstr->getIterator(); localII != end; localII++) {
MachineInstr &localMI = *localII;
for (unsigned j = 0; j < localMI.getNumOperands(); j++) {
MachineOperand &localMO = localMI.getOperand(j);
diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp
index ee3209354688d..7d961a238ae28 100644
--- a/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -100,9 +100,6 @@ namespace {
void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU);
}
-
- private:
- void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
};
}
@@ -132,7 +129,9 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
PeepholeDoubleRegsMap.clear();
// Traverse the basic block.
- for (MachineInstr &MI : *MBB) {
+ for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
+ NextI = std::next(I);
+ MachineInstr &MI = *I;
// Look for sign extends:
// %vreg170<def> = SXTW %vreg166
if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
@@ -280,14 +279,13 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
if (NewOp) {
unsigned PSrc = MI.getOperand(PR).getReg();
if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
- MI.getOperand(PR).setReg(POrig);
+ BuildMI(*MBB, MI.getIterator(), MI.getDebugLoc(),
+ QII->get(NewOp), MI.getOperand(0).getReg())
+ .addReg(POrig)
+ .add(MI.getOperand(S2))
+ .add(MI.getOperand(S1));
MRI->clearKillFlags(POrig);
- MI.setDesc(QII->get(NewOp));
- // Swap operands S1 and S2.
- MachineOperand Op1 = MI.getOperand(S1);
- MachineOperand Op2 = MI.getOperand(S2);
- ChangeOpInto(MI.getOperand(S1), Op2);
- ChangeOpInto(MI.getOperand(S2), Op1);
+ MI.eraseFromParent();
}
} // if (NewOp)
} // if (!Done)
@@ -299,40 +297,6 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
return true;
}
-void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
- assert (&Dst != &Src && "Cannot duplicate into itself");
- switch (Dst.getType()) {
- case MachineOperand::MO_Register:
- if (Src.isReg()) {
- Dst.setReg(Src.getReg());
- Dst.setSubReg(Src.getSubReg());
- MRI->clearKillFlags(Src.getReg());
- } else if (Src.isImm()) {
- Dst.ChangeToImmediate(Src.getImm());
- } else {
- llvm_unreachable("Unexpected src operand type");
- }
- break;
-
- case MachineOperand::MO_Immediate:
- if (Src.isImm()) {
- Dst.setImm(Src.getImm());
- } else if (Src.isReg()) {
- Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
- false, Src.isDead(), Src.isUndef(),
- Src.isDebug());
- Dst.setSubReg(Src.getSubReg());
- } else {
- llvm_unreachable("Unexpected src operand type");
- }
- break;
-
- default:
- llvm_unreachable("Unexpected dst operand type");
- break;
- }
-}
-
FunctionPass *llvm::createHexagonPeephole() {
return new HexagonPeephole();
}
diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp
index 8851a23ae8ace..0aada8a53c979 100644
--- a/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -1,4 +1,4 @@
-//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
+//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,13 +11,23 @@
//
//===----------------------------------------------------------------------===//
-#include "HexagonSubtarget.h"
#include "Hexagon.h"
+#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
+#include <algorithm>
+#include <cassert>
#include <map>
using namespace llvm;
@@ -119,9 +129,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
- InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
- FrameLowering() {
-
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
initializeEnvironment();
// Initialize scheduling itinerary for the specified CPU.
@@ -196,7 +204,6 @@ void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
updateLatency(*SrcInst, *DstInst, Dep);
}
-
void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
for (auto &SU : DAG->SUnits) {
if (!SU.isInstr())
@@ -240,18 +247,18 @@ void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
}
}
-
void HexagonSubtarget::getPostRAMutations(
- std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
- Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
+ std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
+ Mutations.push_back(
+ llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
}
void HexagonSubtarget::getSMSMutations(
- std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
- Mutations.push_back(make_unique<HexagonSubtarget::HexagonDAGMutation>());
+ std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
+ Mutations.push_back(
+ llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
}
-
// Pin the vtable to this file.
void HexagonSubtarget::anchor() {}
@@ -447,4 +454,3 @@ unsigned HexagonSubtarget::getL1PrefetchDistance() const {
bool HexagonSubtarget::enableSubRegLiveness() const {
return EnableSubregLiveness;
}
-
diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h
index 4379efa79c9cd..753dca0000652 100644
--- a/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/lib/Target/Hexagon/HexagonSubtarget.h
@@ -1,4 +1,4 @@
-//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
+//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,12 +15,17 @@
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
#include "HexagonFrameLowering.h"
-#include "HexagonISelLowering.h"
#include "HexagonInstrInfo.h"
+#include "HexagonISelLowering.h"
#include "HexagonSelectionDAGInfo.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/ScheduleDAGMutation.h"
+#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <memory>
#include <string>
+#include <vector>
#define GET_SUBTARGETINFO_HEADER
#include "HexagonGenSubtargetInfo.inc"
@@ -30,6 +35,12 @@
namespace llvm {
+class MachineInstr;
+class SDep;
+class SUnit;
+class TargetMachine;
+class Triple;
+
class HexagonSubtarget : public HexagonGenSubtargetInfo {
virtual void anchor();
@@ -57,6 +68,7 @@ private:
HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering;
InstrItineraryData InstrItins;
+
void initializeEnvironment();
public:
@@ -108,6 +120,7 @@ public:
bool useBSBScheduling() const { return UseBSBScheduling; }
bool enableMachineScheduler() const override;
+
// Always use the TargetLowering default scheduler.
// FIXME: This will use the vliw scheduler which is probably just hurting
// compiler time and will be removed eventually anyway.
@@ -124,6 +137,7 @@ public:
unsigned getSmallDataThreshold() const {
return Hexagon_SMALL_DATA_THRESHOLD;
}
+
const HexagonArchEnum &getHexagonArchVersion() const {
return HexagonArchVersion;
}
@@ -155,4 +169,4 @@ private:
} // end namespace llvm
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index e507a797871fc..031a1bdefafbf 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -291,7 +291,6 @@ bool HexagonPassConfig::addInstSelector() {
if (EnableBitSimplify)
addPass(createHexagonBitSimplify());
addPass(createHexagonPeephole());
- printAndVerify("After hexagon peephole pass");
// Constant propagation.
if (!DisableHCP) {
addPass(createHexagonConstPropagationPass());
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 545c8b6b2acde..093ce80bc2e3f 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -202,10 +202,8 @@ public:
/// processFixupValue - Target hook to adjust the literal value of a fixup
/// if necessary. IsResolved signals whether the caller believes a relocation
/// is needed; the target can modify the value. The default does nothing.
- void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCFixup &Fixup, const MCFragment *DF,
- const MCValue &Target, uint64_t &Value,
- bool &IsResolved) override {
+ void processFixupValue(const MCAssembler &Asm, const MCFixup &Fixup,
+ const MCValue &Target, bool &IsResolved) override {
MCFixupKind Kind = Fixup.getKind();
switch((unsigned)Kind) {
@@ -415,9 +413,9 @@ public:
/// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
/// data fragment, at the offset specified by the fixup and following the
/// fixup kind as appropriate.
- void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t FixupValue, bool IsPCRel,
- MCContext &Ctx) const override {
+ void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+ const MCValue &Target, MutableArrayRef<char> Data,
+ uint64_t FixupValue, bool IsPCRel) const override {
// When FixupValue is 0 the relocation is external and there
// is nothing for us to do.
@@ -432,8 +430,8 @@ public:
// to a real offset before we can use it.
uint32_t Offset = Fixup.getOffset();
unsigned NumBytes = getFixupKindNumBytes(Kind);
- assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
- char *InstAddr = Data + Offset;
+ assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
+ char *InstAddr = Data.data() + Offset;
Value = adjustFixupValue(Kind, FixupValue);
if(!Value)
@@ -517,7 +515,7 @@ public:
dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) <<
": AValue=0x"; dbgs().write_hex(FixupValue) <<
": Offset=" << Offset <<
- ": Size=" << DataSize <<
+ ": Size=" << Data.size() <<
": OInst=0x"; dbgs().write_hex(OldData) <<
": Reloc=0x"; dbgs().write_hex(Reloc););
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
index e8f154a1fa533..c7114c7f18a0a 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
@@ -701,33 +701,32 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
break;
case Hexagon::A2_addi:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
- assert(Absolute);(void)Absolute;
- if (Value == 1) {
- Result.setOpcode(Hexagon::SA1_inc);
- addOps(Result, Inst, 0);
- addOps(Result, Inst, 1);
- break;
- } // 1,2 SUBInst $Rd = add($Rs, #1)
- else if (Value == -1) {
- Result.setOpcode(Hexagon::SA1_dec);
- addOps(Result, Inst, 0);
- addOps(Result, Inst, 1);
- addOps(Result, Inst, 2);
- break;
- } // 1,2 SUBInst $Rd = add($Rs,#-1)
- else if (Inst.getOperand(1).getReg() == Hexagon::R29) {
- Result.setOpcode(Hexagon::SA1_addsp);
- addOps(Result, Inst, 0);
- addOps(Result, Inst, 2);
- break;
- } // 1,3 SUBInst $Rd = add(r29, #$u6_2)
- else {
- Result.setOpcode(Hexagon::SA1_addi);
- addOps(Result, Inst, 0);
- addOps(Result, Inst, 1);
- addOps(Result, Inst, 2);
- break;
- } // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
+ if (Absolute) {
+ if (Value == 1) {
+ Result.setOpcode(Hexagon::SA1_inc);
+ addOps(Result, Inst, 0);
+ addOps(Result, Inst, 1);
+ break;
+ } // 1,2 SUBInst $Rd = add($Rs, #1)
+ if (Value == -1) {
+ Result.setOpcode(Hexagon::SA1_dec);
+ addOps(Result, Inst, 0);
+ addOps(Result, Inst, 1);
+ addOps(Result, Inst, 2);
+ break;
+ } // 1,2 SUBInst $Rd = add($Rs,#-1)
+ if (Inst.getOperand(1).getReg() == Hexagon::R29) {
+ Result.setOpcode(Hexagon::SA1_addsp);
+ addOps(Result, Inst, 0);
+ addOps(Result, Inst, 2);
+ break;
+ } // 1,3 SUBInst $Rd = add(r29, #$u6_2)
+ }
+ Result.setOpcode(Hexagon::SA1_addi);
+ addOps(Result, Inst, 0);
+ addOps(Result, Inst, 1);
+ addOps(Result, Inst, 2);
+ break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
case Hexagon::A2_add:
Result.setOpcode(Hexagon::SA1_addrx);
addOps(Result, Inst, 0);
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-11 14:49:59 +0000