diff options
Diffstat (limited to 'lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp')
| -rw-r--r-- | lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 4397c971d0802..265d1141cb0b2 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -13,6 +13,7 @@ // #include "MCTargetDesc/MipsAsmBackend.h" +#include "MCTargetDesc/MipsABIInfo.h" #include "MCTargetDesc/MipsFixupKinds.h" #include "MCTargetDesc/MipsMCExpr.h" #include "MCTargetDesc/MipsMCTargetDesc.h" @@ -338,6 +339,8 @@ Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16) .Case("R_MICROMIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16) + .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR) + .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR) .Default(MCAsmBackend::getFixupKind(Name)); } @@ -416,7 +419,9 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, { "fixup_Mips_SUB", 0, 64, 0 }, - { "fixup_MICROMIPS_SUB", 0, 64, 0 } + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } }; static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS little endian fixup kinds added!"); @@ -494,7 +499,9 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, { "fixup_Mips_SUB", 0, 64, 0 }, - { "fixup_MICROMIPS_SUB", 0, 64, 0 } + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } }; static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS big endian fixup kinds added!"); @@ -552,6 +559,7 @@ bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, case Mips::fixup_Mips_TLSLDM: case Mips::fixup_Mips_TPREL_HI: case Mips::fixup_Mips_TPREL_LO: + case Mips::fixup_Mips_JALR: case Mips::fixup_MICROMIPS_CALL16: case Mips::fixup_MICROMIPS_GOT_DISP: case Mips::fixup_MICROMIPS_GOT_PAGE: @@ -564,14 +572,23 @@ bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, case Mips::fixup_MICROMIPS_TLS_LDM: case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: + case Mips::fixup_MICROMIPS_JALR: return true; } } +bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { + if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) { + if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + } + return false; +} + MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { - return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), - Options.ABIName == "n32"); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options); + return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32()); } |