diff options
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 8a18b517d16be..3e7570ff46ed3 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -90,7 +90,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error("Code generation for MIPS-V is not implemented", false); // Check if Architecture and ABI are compatible. - assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); @@ -114,7 +114,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error(ISA + " is not compatible with the DSP ASE", false); } - if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_) + if (NoABICalls && TM.isPositionIndependent()) report_fatal_error("position-independent code requires '-mabicalls'"); // Set UseSmallSection. @@ -126,6 +126,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, } } +bool MipsSubtarget::isPositionIndependent() const { + return TM.isPositionIndependent(); +} + /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool MipsSubtarget::enablePostRAScheduler() const { return true; } @@ -164,7 +168,6 @@ Reloc::Model MipsSubtarget::getRelocationModel() const { return TM.getRelocationModel(); } -bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); } bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } |