diff options
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc')
6 files changed, 33 insertions, 48 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/Makefile b/lib/Target/PowerPC/MCTargetDesc/Makefile deleted file mode 100644 index 9db66622cced3..0000000000000 --- a/lib/Target/PowerPC/MCTargetDesc/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -##===- lib/Target/PowerPC/TargetDesc/Makefile --------------*- Makefile -*-===## -# -# The LLVM Compiler Infrastructure -# -# This file is distributed under the University of Illinois Open Source -# License. See LICENSE.TXT for details. -# -##===----------------------------------------------------------------------===## - -LEVEL = ../../../.. -LIBRARYNAME = LLVMPowerPCDesc - -# Hack: we need to include 'main' target directory to grab private headers -CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. - -include $(LEVEL)/Makefile.common diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index b6dd595ffb0e0..9100ecb4aa371 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -168,8 +168,8 @@ public: llvm_unreachable("relaxInstruction() unimplemented"); } - - void relaxInstruction(const MCInst &Inst, MCInst &Res) const override { + void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, + MCInst &Res) const override { // FIXME. llvm_unreachable("relaxInstruction() unimplemented"); } diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index dd994956870fd..fd279c60f3f59 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -25,8 +25,8 @@ namespace { PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI); protected: - unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel) const override; + unsigned getRelocType(MCContext &Ctx, const MCValue &Target, + const MCFixup &Fixup, bool IsPCRel) const override; bool needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const override; @@ -66,7 +66,7 @@ static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target, llvm_unreachable("unknown PPCMCExpr kind"); } -unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, +unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup); @@ -186,7 +186,7 @@ unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, case MCSymbolRefExpr::VK_PPC_TOC_HA: Type = ELF::R_PPC64_TOC16_HA; break; - case MCSymbolRefExpr::VK_PPC_TPREL: + case MCSymbolRefExpr::VK_TPREL: Type = ELF::R_PPC_TPREL16; break; case MCSymbolRefExpr::VK_PPC_TPREL_LO: @@ -210,7 +210,7 @@ unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, case MCSymbolRefExpr::VK_PPC_TPREL_HIGHESTA: Type = ELF::R_PPC64_TPREL16_HIGHESTA; break; - case MCSymbolRefExpr::VK_PPC_DTPREL: + case MCSymbolRefExpr::VK_DTPREL: Type = ELF::R_PPC64_DTPREL16; break; case MCSymbolRefExpr::VK_PPC_DTPREL_LO: @@ -319,13 +319,13 @@ unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, case MCSymbolRefExpr::VK_PPC_TOC_LO: Type = ELF::R_PPC64_TOC16_LO_DS; break; - case MCSymbolRefExpr::VK_PPC_TPREL: + case MCSymbolRefExpr::VK_TPREL: Type = ELF::R_PPC64_TPREL16_DS; break; case MCSymbolRefExpr::VK_PPC_TPREL_LO: Type = ELF::R_PPC64_TPREL16_LO_DS; break; - case MCSymbolRefExpr::VK_PPC_DTPREL: + case MCSymbolRefExpr::VK_DTPREL: Type = ELF::R_PPC64_DTPREL16_DS; break; case MCSymbolRefExpr::VK_PPC_DTPREL_LO: @@ -380,10 +380,10 @@ unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, case MCSymbolRefExpr::VK_PPC_DTPMOD: Type = ELF::R_PPC64_DTPMOD64; break; - case MCSymbolRefExpr::VK_PPC_TPREL: + case MCSymbolRefExpr::VK_TPREL: Type = ELF::R_PPC64_TPREL64; break; - case MCSymbolRefExpr::VK_PPC_DTPREL: + case MCSymbolRefExpr::VK_DTPREL: Type = ELF::R_PPC64_DTPREL64; break; } diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index b7291561c75db..e7b2d8369f2f8 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -69,6 +69,9 @@ public: unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; @@ -102,19 +105,16 @@ public: void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override { - // For fast-isel, a float COPY_TO_REGCLASS can survive this long. - // It's just a nop to keep the register classes happy, so don't - // generate anything. unsigned Opcode = MI.getOpcode(); const MCInstrDesc &Desc = MCII.get(Opcode); - if (Opcode == TargetOpcode::COPY_TO_REGCLASS) - return; uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); // Output the constant in big/little endian byte order. unsigned Size = Desc.getSize(); switch (Size) { + case 0: + break; case 4: if (IsLittleEndian) { support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); @@ -249,6 +249,19 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, return RegBits; } +unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + // Encode (imm, reg) as a memrix16, which has the low 12-bits as the + // displacement and the next 5 bits as the register #. + assert(MI.getOperand(OpNo+1).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; + + const MCOperand &MO = MI.getOperand(OpNo); + assert(MO.isImm()); + + return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; +} unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 30f232a9a91e0..c9074448fe45e 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -15,7 +15,6 @@ #include "InstPrinter/PPCInstPrinter.h" #include "PPCMCAsmInfo.h" #include "PPCTargetStreamer.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCExpr.h" @@ -87,24 +86,13 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - - if (RM == Reloc::Default) { - if (TT.isOSDarwin()) - RM = Reloc::DynamicNoPIC; - else - RM = Reloc::Static; - } +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { if (CM == CodeModel::Default) { if (!TT.isOSDarwin() && (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)) CM = CodeModel::Medium; } - X->initMCCodeGenInfo(RM, CM, OL); - return X; } namespace { @@ -245,7 +233,7 @@ extern "C" void LLVMInitializePowerPCTargetMC() { RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); // Register the MC codegen info. - TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo); + TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo); diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp index b54a0e1b86b14..1f38a8c947e73 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp @@ -79,7 +79,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) { } /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum. -/// Outline based on PPCELFObjectWriter::GetRelocType(). +/// Outline based on PPCELFObjectWriter::getRelocType(). static unsigned getRelocType(const MCValue &Target, const MCFixupKind FixupKind, // from // Fixup.getKind() |