diff options
Diffstat (limited to 'lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp')
| -rw-r--r-- | lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp b/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp index 14221993603a8..c95af88c6f435 100644 --- a/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp +++ b/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp @@ -60,8 +60,7 @@ static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) { assert(MI.hasOneMemOperand() && "Load and store instructions have exactly one mem operand"); assert((*MI.memoperands_begin())->getSize() == - (UINT64_C(1) - << WebAssembly::GetDefaultP2Align(MI.getOpcode())) && + (UINT64_C(1) << WebAssembly::GetDefaultP2Align(MI.getOpcode())) && "Default p2align value should be natural"); assert(MI.getDesc().OpInfo[OperandNo].OperandType == WebAssembly::OPERAND_P2ALIGN && @@ -69,8 +68,8 @@ static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) { uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment()); // WebAssembly does not currently support supernatural alignment. - P2Align = std::min( - P2Align, uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode()))); + P2Align = std::min(P2Align, + uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode()))); MI.getOperand(OperandNo).setImm(P2Align); } @@ -90,6 +89,12 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { case WebAssembly::LOAD_I64: case WebAssembly::LOAD_F32: case WebAssembly::LOAD_F64: + case WebAssembly::LOAD_v16i8: + case WebAssembly::LOAD_v8i16: + case WebAssembly::LOAD_v4i32: + case WebAssembly::LOAD_v2i64: + case WebAssembly::LOAD_v4f32: + case WebAssembly::LOAD_v2f64: case WebAssembly::LOAD8_S_I32: case WebAssembly::LOAD8_U_I32: case WebAssembly::LOAD16_S_I32: @@ -119,6 +124,8 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { case WebAssembly::ATOMIC_RMW8_U_XOR_I64: case WebAssembly::ATOMIC_RMW8_U_XCHG_I32: case WebAssembly::ATOMIC_RMW8_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32: + case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64: case WebAssembly::ATOMIC_RMW16_U_ADD_I32: case WebAssembly::ATOMIC_RMW16_U_ADD_I64: case WebAssembly::ATOMIC_RMW16_U_SUB_I32: @@ -131,6 +138,8 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { case WebAssembly::ATOMIC_RMW16_U_XOR_I64: case WebAssembly::ATOMIC_RMW16_U_XCHG_I32: case WebAssembly::ATOMIC_RMW16_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32: + case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64: case WebAssembly::ATOMIC_RMW_ADD_I32: case WebAssembly::ATOMIC_RMW32_U_ADD_I64: case WebAssembly::ATOMIC_RMW_SUB_I32: @@ -143,18 +152,30 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { case WebAssembly::ATOMIC_RMW32_U_XOR_I64: case WebAssembly::ATOMIC_RMW_XCHG_I32: case WebAssembly::ATOMIC_RMW32_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW_CMPXCHG_I32: + case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64: case WebAssembly::ATOMIC_RMW_ADD_I64: case WebAssembly::ATOMIC_RMW_SUB_I64: case WebAssembly::ATOMIC_RMW_AND_I64: case WebAssembly::ATOMIC_RMW_OR_I64: case WebAssembly::ATOMIC_RMW_XOR_I64: case WebAssembly::ATOMIC_RMW_XCHG_I64: + case WebAssembly::ATOMIC_RMW_CMPXCHG_I64: + case WebAssembly::ATOMIC_NOTIFY: + case WebAssembly::ATOMIC_WAIT_I32: + case WebAssembly::ATOMIC_WAIT_I64: RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo); break; case WebAssembly::STORE_I32: case WebAssembly::STORE_I64: case WebAssembly::STORE_F32: case WebAssembly::STORE_F64: + case WebAssembly::STORE_v16i8: + case WebAssembly::STORE_v8i16: + case WebAssembly::STORE_v4i32: + case WebAssembly::STORE_v2i64: + case WebAssembly::STORE_v4f32: + case WebAssembly::STORE_v2f64: case WebAssembly::STORE8_I32: case WebAssembly::STORE16_I32: case WebAssembly::STORE8_I64: |