diff options
Diffstat (limited to 'lib/Target/X86/InstPrinter/X86InstComments.cpp')
| -rw-r--r-- | lib/Target/X86/InstPrinter/X86InstComments.cpp | 837 |
1 files changed, 528 insertions, 309 deletions
diff --git a/lib/Target/X86/InstPrinter/X86InstComments.cpp b/lib/Target/X86/InstPrinter/X86InstComments.cpp index 73f654cba38c9..f5379566b619f 100644 --- a/lib/Target/X86/InstPrinter/X86InstComments.cpp +++ b/lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -21,6 +21,143 @@ using namespace llvm; +#define CASE_SSE_INS_COMMON(Inst, src) \ + case X86::Inst##src: + +#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ + case X86::V##Inst##Suffix##src: + +#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ + case X86::V##Inst##Suffix##src##k: + +#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \ + case X86::V##Inst##Suffix##src##kz: + +#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \ + CASE_AVX_INS_COMMON(Inst, Suffix, src) \ + CASE_MASK_INS_COMMON(Inst, Suffix, src) \ + CASE_MASKZ_INS_COMMON(Inst, Suffix, src) + +#define CASE_MOVDUP(Inst, src) \ + CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ + CASE_AVX_INS_COMMON(Inst, , r##src) \ + CASE_AVX_INS_COMMON(Inst, Y, r##src) \ + CASE_SSE_INS_COMMON(Inst, r##src) + +#define CASE_MASK_MOVDUP(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z128, r##src) + +#define CASE_MASKZ_MOVDUP(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) + +#define CASE_PMOVZX(Inst, src) \ + CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ + CASE_AVX_INS_COMMON(Inst, , r##src) \ + CASE_AVX_INS_COMMON(Inst, Y, r##src) \ + CASE_SSE_INS_COMMON(Inst, r##src) + +#define CASE_MASK_PMOVZX(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z128, r##src) + +#define CASE_MASKZ_PMOVZX(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) + +#define CASE_UNPCK(Inst, src) \ + CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ + CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ + CASE_AVX_INS_COMMON(Inst, , r##src) \ + CASE_AVX_INS_COMMON(Inst, Y, r##src) \ + CASE_SSE_INS_COMMON(Inst, r##src) + +#define CASE_MASK_UNPCK(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z128, r##src) + +#define CASE_MASKZ_UNPCK(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ + CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) + +#define CASE_SHUF(Inst, suf) \ + CASE_AVX512_INS_COMMON(Inst, Z, suf) \ + CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ + CASE_AVX512_INS_COMMON(Inst, Z128, suf) \ + CASE_AVX_INS_COMMON(Inst, , suf) \ + CASE_AVX_INS_COMMON(Inst, Y, suf) \ + CASE_SSE_INS_COMMON(Inst, suf) + +#define CASE_MASK_SHUF(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ + CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ + CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) + +#define CASE_MASKZ_SHUF(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \ + CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i) + +#define CASE_VPERMILPI(Inst, src) \ + CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ + CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ + CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \ + CASE_AVX_INS_COMMON(Inst, , src##i) \ + CASE_AVX_INS_COMMON(Inst, Y, src##i) + +#define CASE_MASK_VPERMILPI(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, src##i) \ + CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ + CASE_MASK_INS_COMMON(Inst, Z128, src##i) + +#define CASE_MASKZ_VPERMILPI(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \ + CASE_MASKZ_INS_COMMON(Inst, Z128, src##i) + +#define CASE_VPERM(Inst, src) \ + CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ + CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ + CASE_AVX_INS_COMMON(Inst, Y, src##i) + +#define CASE_MASK_VPERM(Inst, src) \ + CASE_MASK_INS_COMMON(Inst, Z, src##i) \ + CASE_MASK_INS_COMMON(Inst, Z256, src##i) + +#define CASE_MASKZ_VPERM(Inst, src) \ + CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ + CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) + +#define CASE_VSHUF(Inst, src) \ + CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ + CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ + CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ + CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i) + +#define CASE_MASK_VSHUF(Inst, src) \ + CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ + CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ + CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ + CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) + +#define CASE_MASKZ_VSHUF(Inst, src) \ + CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ + CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ + CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ + CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i) + static unsigned getVectorRegSize(unsigned RegNo) { if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31) return 512; @@ -41,159 +178,184 @@ static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, getVectorRegSize(OpReg)/ScalarVT.getSizeInBits()); } -/// \brief Extracts the src/dst types for a given zero extension instruction. -/// \note While the number of elements in DstVT type correct, the -/// number in the SrcVT type is expanded to fill the src xmm register and the -/// upper elements may not be included in the dst xmm/ymm register. -static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { +/// \brief Extracts the dst type for a given zero extension instruction. +static MVT getZeroExtensionResultType(const MCInst *MI) { switch (MI->getOpcode()) { default: llvm_unreachable("Unknown zero extension instruction"); - // i8 zero extension - case X86::PMOVZXBWrm: - case X86::PMOVZXBWrr: - case X86::VPMOVZXBWrm: - case X86::VPMOVZXBWrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v8i16; - break; - case X86::VPMOVZXBWYrm: - case X86::VPMOVZXBWYrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v16i16; - break; - case X86::PMOVZXBDrm: - case X86::PMOVZXBDrr: - case X86::VPMOVZXBDrm: - case X86::VPMOVZXBDrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v4i32; - break; - case X86::VPMOVZXBDYrm: - case X86::VPMOVZXBDYrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v8i32; - break; - case X86::PMOVZXBQrm: - case X86::PMOVZXBQrr: - case X86::VPMOVZXBQrm: - case X86::VPMOVZXBQrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v2i64; - break; - case X86::VPMOVZXBQYrm: - case X86::VPMOVZXBQYrr: - SrcVT = MVT::v16i8; - DstVT = MVT::v4i64; - break; - // i16 zero extension - case X86::PMOVZXWDrm: - case X86::PMOVZXWDrr: - case X86::VPMOVZXWDrm: - case X86::VPMOVZXWDrr: - SrcVT = MVT::v8i16; - DstVT = MVT::v4i32; - break; - case X86::VPMOVZXWDYrm: - case X86::VPMOVZXWDYrr: - SrcVT = MVT::v8i16; - DstVT = MVT::v8i32; - break; - case X86::PMOVZXWQrm: - case X86::PMOVZXWQrr: - case X86::VPMOVZXWQrm: - case X86::VPMOVZXWQrr: - SrcVT = MVT::v8i16; - DstVT = MVT::v2i64; - break; - case X86::VPMOVZXWQYrm: - case X86::VPMOVZXWQYrr: - SrcVT = MVT::v8i16; - DstVT = MVT::v4i64; - break; - // i32 zero extension - case X86::PMOVZXDQrm: - case X86::PMOVZXDQrr: - case X86::VPMOVZXDQrm: - case X86::VPMOVZXDQrr: - SrcVT = MVT::v4i32; - DstVT = MVT::v2i64; - break; - case X86::VPMOVZXDQYrm: - case X86::VPMOVZXDQYrr: - SrcVT = MVT::v4i32; - DstVT = MVT::v4i64; - break; + // zero extension to i16 + CASE_PMOVZX(PMOVZXBW, m) + CASE_PMOVZX(PMOVZXBW, r) + return getRegOperandVectorVT(MI, MVT::i16, 0); + // zero extension to i32 + CASE_PMOVZX(PMOVZXBD, m) + CASE_PMOVZX(PMOVZXBD, r) + CASE_PMOVZX(PMOVZXWD, m) + CASE_PMOVZX(PMOVZXWD, r) + return getRegOperandVectorVT(MI, MVT::i32, 0); + // zero extension to i64 + CASE_PMOVZX(PMOVZXBQ, m) + CASE_PMOVZX(PMOVZXBQ, r) + CASE_PMOVZX(PMOVZXWQ, m) + CASE_PMOVZX(PMOVZXWQ, r) + CASE_PMOVZX(PMOVZXDQ, m) + CASE_PMOVZX(PMOVZXDQ, r) + return getRegOperandVectorVT(MI, MVT::i64, 0); } } -#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ - case X86::V##Inst##Suffix##src: \ - case X86::V##Inst##Suffix##src##k: \ - case X86::V##Inst##Suffix##src##kz: - -#define CASE_SSE_INS_COMMON(Inst, src) \ - case X86::Inst##src: - -#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ - case X86::V##Inst##Suffix##src: +/// Wraps the destination register name with AVX512 mask/maskz filtering. +static std::string getMaskName(const MCInst *MI, const char *DestName, + const char *(*getRegName)(unsigned)) { + std::string OpMaskName(DestName); -#define CASE_MOVDUP(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src) \ - CASE_AVX_INS_COMMON(Inst, , r##src) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src) \ - CASE_SSE_INS_COMMON(Inst, r##src) \ - -#define CASE_UNPCK(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src) \ - CASE_AVX_INS_COMMON(Inst, , r##src) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src) \ - CASE_SSE_INS_COMMON(Inst, r##src) \ - -#define CASE_SHUF(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) \ - CASE_AVX_INS_COMMON(Inst, , r##src##i) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \ - CASE_SSE_INS_COMMON(Inst, r##src##i) \ - -#define CASE_VPERM(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, src##i) \ - CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ - CASE_MASK_INS_COMMON(Inst, Z128, src##i) \ - CASE_AVX_INS_COMMON(Inst, , src##i) \ - CASE_AVX_INS_COMMON(Inst, Y, src##i) \ + bool MaskWithZero = false; + const char *MaskRegName = nullptr; -#define CASE_VSHUF(Inst, src) \ - CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \ - -/// \brief Extracts the types and if it has memory operand for a given -/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction. -static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) { - HasMemOp = false; switch (MI->getOpcode()) { default: - llvm_unreachable("Unknown VSHUF64x2 family instructions."); + return OpMaskName; + CASE_MASKZ_MOVDUP(MOVDDUP, m) + CASE_MASKZ_MOVDUP(MOVDDUP, r) + CASE_MASKZ_MOVDUP(MOVSHDUP, m) + CASE_MASKZ_MOVDUP(MOVSHDUP, r) + CASE_MASKZ_MOVDUP(MOVSLDUP, m) + CASE_MASKZ_MOVDUP(MOVSLDUP, r) + CASE_MASKZ_PMOVZX(PMOVZXBD, m) + CASE_MASKZ_PMOVZX(PMOVZXBD, r) + CASE_MASKZ_PMOVZX(PMOVZXBQ, m) + CASE_MASKZ_PMOVZX(PMOVZXBQ, r) + CASE_MASKZ_PMOVZX(PMOVZXBW, m) + CASE_MASKZ_PMOVZX(PMOVZXBW, r) + CASE_MASKZ_PMOVZX(PMOVZXDQ, m) + CASE_MASKZ_PMOVZX(PMOVZXDQ, r) + CASE_MASKZ_PMOVZX(PMOVZXWD, m) + CASE_MASKZ_PMOVZX(PMOVZXWD, r) + CASE_MASKZ_PMOVZX(PMOVZXWQ, m) + CASE_MASKZ_PMOVZX(PMOVZXWQ, r) + CASE_MASKZ_UNPCK(PUNPCKHBW, m) + CASE_MASKZ_UNPCK(PUNPCKHBW, r) + CASE_MASKZ_UNPCK(PUNPCKHWD, m) + CASE_MASKZ_UNPCK(PUNPCKHWD, r) + CASE_MASKZ_UNPCK(PUNPCKHDQ, m) + CASE_MASKZ_UNPCK(PUNPCKHDQ, r) + CASE_MASKZ_UNPCK(PUNPCKLBW, m) + CASE_MASKZ_UNPCK(PUNPCKLBW, r) + CASE_MASKZ_UNPCK(PUNPCKLWD, m) + CASE_MASKZ_UNPCK(PUNPCKLWD, r) + CASE_MASKZ_UNPCK(PUNPCKLDQ, m) + CASE_MASKZ_UNPCK(PUNPCKLDQ, r) + CASE_MASKZ_UNPCK(UNPCKHPD, m) + CASE_MASKZ_UNPCK(UNPCKHPD, r) + CASE_MASKZ_UNPCK(UNPCKHPS, m) + CASE_MASKZ_UNPCK(UNPCKHPS, r) + CASE_MASKZ_UNPCK(UNPCKLPD, m) + CASE_MASKZ_UNPCK(UNPCKLPD, r) + CASE_MASKZ_UNPCK(UNPCKLPS, m) + CASE_MASKZ_UNPCK(UNPCKLPS, r) + CASE_MASKZ_SHUF(PALIGNR, r) + CASE_MASKZ_SHUF(PALIGNR, m) + CASE_MASKZ_SHUF(SHUFPD, m) + CASE_MASKZ_SHUF(SHUFPD, r) + CASE_MASKZ_SHUF(SHUFPS, m) + CASE_MASKZ_SHUF(SHUFPS, r) + CASE_MASKZ_VPERMILPI(PERMILPD, m) + CASE_MASKZ_VPERMILPI(PERMILPD, r) + CASE_MASKZ_VPERMILPI(PERMILPS, m) + CASE_MASKZ_VPERMILPI(PERMILPS, r) + CASE_MASKZ_VPERMILPI(PSHUFD, m) + CASE_MASKZ_VPERMILPI(PSHUFD, r) + CASE_MASKZ_VPERMILPI(PSHUFHW, m) + CASE_MASKZ_VPERMILPI(PSHUFHW, r) + CASE_MASKZ_VPERMILPI(PSHUFLW, m) + CASE_MASKZ_VPERMILPI(PSHUFLW, r) + CASE_MASKZ_VPERM(PERMPD, m) + CASE_MASKZ_VPERM(PERMPD, r) + CASE_MASKZ_VPERM(PERMQ, m) + CASE_MASKZ_VPERM(PERMQ, r) + CASE_MASKZ_VSHUF(64X2, m) + CASE_MASKZ_VSHUF(64X2, r) + CASE_MASKZ_VSHUF(32X4, m) + CASE_MASKZ_VSHUF(32X4, r) + MaskWithZero = true; + MaskRegName = getRegName(MI->getOperand(1).getReg()); break; - CASE_VSHUF(64X2, m) - HasMemOp = true; // FALL THROUGH. - CASE_VSHUF(64X2, r) - VT = getRegOperandVectorVT(MI, MVT::i64, 0); - break; - CASE_VSHUF(32X4, m) - HasMemOp = true; // FALL THROUGH. - CASE_VSHUF(32X4, r) - VT = getRegOperandVectorVT(MI, MVT::i32, 0); + CASE_MASK_MOVDUP(MOVDDUP, m) + CASE_MASK_MOVDUP(MOVDDUP, r) + CASE_MASK_MOVDUP(MOVSHDUP, m) + CASE_MASK_MOVDUP(MOVSHDUP, r) + CASE_MASK_MOVDUP(MOVSLDUP, m) + CASE_MASK_MOVDUP(MOVSLDUP, r) + CASE_MASK_PMOVZX(PMOVZXBD, m) + CASE_MASK_PMOVZX(PMOVZXBD, r) + CASE_MASK_PMOVZX(PMOVZXBQ, m) + CASE_MASK_PMOVZX(PMOVZXBQ, r) + CASE_MASK_PMOVZX(PMOVZXBW, m) + CASE_MASK_PMOVZX(PMOVZXBW, r) + CASE_MASK_PMOVZX(PMOVZXDQ, m) + CASE_MASK_PMOVZX(PMOVZXDQ, r) + CASE_MASK_PMOVZX(PMOVZXWD, m) + CASE_MASK_PMOVZX(PMOVZXWD, r) + CASE_MASK_PMOVZX(PMOVZXWQ, m) + CASE_MASK_PMOVZX(PMOVZXWQ, r) + CASE_MASK_UNPCK(PUNPCKHBW, m) + CASE_MASK_UNPCK(PUNPCKHBW, r) + CASE_MASK_UNPCK(PUNPCKHWD, m) + CASE_MASK_UNPCK(PUNPCKHWD, r) + CASE_MASK_UNPCK(PUNPCKHDQ, m) + CASE_MASK_UNPCK(PUNPCKHDQ, r) + CASE_MASK_UNPCK(PUNPCKLBW, m) + CASE_MASK_UNPCK(PUNPCKLBW, r) + CASE_MASK_UNPCK(PUNPCKLWD, m) + CASE_MASK_UNPCK(PUNPCKLWD, r) + CASE_MASK_UNPCK(PUNPCKLDQ, m) + CASE_MASK_UNPCK(PUNPCKLDQ, r) + CASE_MASK_UNPCK(UNPCKHPD, m) + CASE_MASK_UNPCK(UNPCKHPD, r) + CASE_MASK_UNPCK(UNPCKHPS, m) + CASE_MASK_UNPCK(UNPCKHPS, r) + CASE_MASK_UNPCK(UNPCKLPD, m) + CASE_MASK_UNPCK(UNPCKLPD, r) + CASE_MASK_UNPCK(UNPCKLPS, m) + CASE_MASK_UNPCK(UNPCKLPS, r) + CASE_MASK_SHUF(PALIGNR, r) + CASE_MASK_SHUF(PALIGNR, m) + CASE_MASK_SHUF(SHUFPD, m) + CASE_MASK_SHUF(SHUFPD, r) + CASE_MASK_SHUF(SHUFPS, m) + CASE_MASK_SHUF(SHUFPS, r) + CASE_MASK_VPERMILPI(PERMILPD, m) + CASE_MASK_VPERMILPI(PERMILPD, r) + CASE_MASK_VPERMILPI(PERMILPS, m) + CASE_MASK_VPERMILPI(PERMILPS, r) + CASE_MASK_VPERMILPI(PSHUFD, m) + CASE_MASK_VPERMILPI(PSHUFD, r) + CASE_MASK_VPERMILPI(PSHUFHW, m) + CASE_MASK_VPERMILPI(PSHUFHW, r) + CASE_MASK_VPERMILPI(PSHUFLW, m) + CASE_MASK_VPERMILPI(PSHUFLW, r) + CASE_MASK_VPERM(PERMPD, m) + CASE_MASK_VPERM(PERMPD, r) + CASE_MASK_VPERM(PERMQ, m) + CASE_MASK_VPERM(PERMQ, r) + CASE_MASK_VSHUF(64X2, m) + CASE_MASK_VSHUF(64X2, r) + CASE_MASK_VSHUF(32X4, m) + CASE_MASK_VSHUF(32X4, r) + MaskRegName = getRegName(MI->getOperand(2).getReg()); break; } + + // MASK: zmmX {%kY} + OpMaskName += " {%"; + OpMaskName += MaskRegName; + OpMaskName += "}"; + + // MASKZ: zmmX {%kY} {z} + if (MaskWithZero) + OpMaskName += " {z}"; + + return OpMaskName; } //===----------------------------------------------------------------------===// @@ -208,6 +370,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // If this is a shuffle operation, the switch should fill in this state. SmallVector<int, 8> ShuffleMask; const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr; + unsigned NumOperands = MI->getNumOperands(); + bool RegForm = false; switch (MI->getOpcode()) { default: @@ -222,9 +386,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::BLENDPDrmi: case X86::VBLENDPDrmi: case X86::VBLENDPDYrmi: - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -238,9 +402,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::BLENDPSrmi: case X86::VBLENDPSrmi: case X86::VBLENDPSYrmi: - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -254,9 +418,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PBLENDWrmi: case X86::VPBLENDWrmi: case X86::VPBLENDWYrmi: - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -268,9 +432,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // FALL THROUGH. case X86::VPBLENDDrmi: case X86::VPBLENDDYrmi: - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -278,14 +442,16 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::INSERTPSrr: case X86::VINSERTPSrr: + case X86::VINSERTPSzrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. case X86::INSERTPSrm: case X86::VINSERTPSrm: + case X86::VINSERTPSzrm: DestName = getRegName(MI->getOperand(0).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) - DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(), + if (MI->getOperand(NumOperands - 1).isImm()) + DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; @@ -307,8 +473,40 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, DecodeMOVHLPSMask(2, ShuffleMask); break; + case X86::MOVHPDrm: + case X86::VMOVHPDrm: + case X86::VMOVHPDZ128rm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask); + break; + + case X86::MOVHPSrm: + case X86::VMOVHPSrm: + case X86::VMOVHPSZ128rm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask); + break; + + case X86::MOVLPDrm: + case X86::VMOVLPDrm: + case X86::VMOVLPDZ128rm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask); + break; + + case X86::MOVLPSrm: + case X86::VMOVLPSrm: + case X86::VMOVLPSZ128rm: + Src1Name = getRegName(MI->getOperand(1).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask); + break; + CASE_MOVDUP(MOVSLDUP, r) - Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); // FALL THROUGH. CASE_MOVDUP(MOVSLDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); @@ -316,7 +514,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, break; CASE_MOVDUP(MOVSHDUP, r) - Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); // FALL THROUGH. CASE_MOVDUP(MOVSHDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); @@ -324,7 +522,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, break; CASE_MOVDUP(MOVDDUP, r) - Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); // FALL THROUGH. CASE_MOVDUP(MOVDDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); @@ -334,83 +532,80 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSLLDQri: case X86::VPSLLDQri: case X86::VPSLLDQYri: + case X86::VPSLLDQZ128rr: + case X86::VPSLLDQZ256rr: + case X86::VPSLLDQZ512rr: Src1Name = getRegName(MI->getOperand(1).getReg()); + case X86::VPSLLDQZ128rm: + case X86::VPSLLDQZ256rm: + case X86::VPSLLDQZ512rm: DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; case X86::PSRLDQri: case X86::VPSRLDQri: case X86::VPSRLDQYri: + case X86::VPSRLDQZ128rr: + case X86::VPSRLDQZ256rr: + case X86::VPSRLDQZ512rr: Src1Name = getRegName(MI->getOperand(1).getReg()); + case X86::VPSRLDQZ128rm: + case X86::VPSRLDQZ256rm: + case X86::VPSRLDQZ512rm: DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; - case X86::PALIGNR128rr: - case X86::VPALIGNR128rr: - case X86::VPALIGNR256rr: - Src1Name = getRegName(MI->getOperand(2).getReg()); + CASE_SHUF(PALIGNR, rri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; // FALL THROUGH. - case X86::PALIGNR128rm: - case X86::VPALIGNR128rm: - case X86::VPALIGNR256rm: - Src2Name = getRegName(MI->getOperand(1).getReg()); + CASE_SHUF(PALIGNR, rmi) + Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; - case X86::PSHUFDri: - case X86::VPSHUFDri: - case X86::VPSHUFDYri: - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_SHUF(PSHUFD, ri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - case X86::PSHUFDmi: - case X86::VPSHUFDmi: - case X86::VPSHUFDYmi: + CASE_SHUF(PSHUFD, mi) DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; - case X86::PSHUFHWri: - case X86::VPSHUFHWri: - case X86::VPSHUFHWYri: - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_SHUF(PSHUFHW, ri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - case X86::PSHUFHWmi: - case X86::VPSHUFHWmi: - case X86::VPSHUFHWYmi: + CASE_SHUF(PSHUFHW, mi) DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; - case X86::PSHUFLWri: - case X86::VPSHUFLWri: - case X86::VPSHUFLWYri: - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_SHUF(PSHUFLW, ri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - case X86::PSHUFLWmi: - case X86::VPSHUFLWmi: - case X86::VPSHUFLWYmi: + CASE_SHUF(PSHUFLW, mi) DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; @@ -419,9 +614,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, // FALL THROUGH. case X86::MMX_PSHUFWmi: DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(MVT::v4i16, - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); break; @@ -435,188 +630,204 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(PUNPCKHBW, r) case X86::MMX_PUNPCKHBWirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKHBW, m) case X86::MMX_PUNPCKHBWirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKHWD, r) case X86::MMX_PUNPCKHWDirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKHWD, m) case X86::MMX_PUNPCKHWDirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKHDQ, r) case X86::MMX_PUNPCKHDQirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKHDQ, m) case X86::MMX_PUNPCKHDQirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKHQDQ, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKHQDQ, m) - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKLBW, r) case X86::MMX_PUNPCKLBWirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKLBW, m) case X86::MMX_PUNPCKLBWirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKLWD, r) case X86::MMX_PUNPCKLWDirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKLWD, m) case X86::MMX_PUNPCKLWDirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKLDQ, r) case X86::MMX_PUNPCKLDQirr: - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKLDQ, m) case X86::MMX_PUNPCKLDQirm: - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); break; CASE_UNPCK(PUNPCKLQDQ, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(PUNPCKLQDQ, m) - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); break; - CASE_SHUF(SHUFPD, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + CASE_SHUF(SHUFPD, rri) + Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; // FALL THROUGH. - CASE_SHUF(SHUFPD, m) - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + CASE_SHUF(SHUFPD, rmi) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; - CASE_SHUF(SHUFPS, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + CASE_SHUF(SHUFPS, rri) + Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; // FALL THROUGH. - CASE_SHUF(SHUFPS, m) - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + CASE_SHUF(SHUFPS, rmi) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; CASE_VSHUF(64X2, r) + Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; + // FALL THROUGH. CASE_VSHUF(64X2, m) + decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0), + MI->getOperand(NumOperands - 1).getImm(), + ShuffleMask); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_VSHUF(32X4, r) - CASE_VSHUF(32X4, m) { - MVT VT; - bool HasMemOp; - unsigned NumOp = MI->getNumOperands(); - getVSHUF64x2FamilyInfo(MI, VT, HasMemOp); - decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(), + Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; + // FALL THROUGH. + CASE_VSHUF(32X4, m) + decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); - if (HasMemOp) { - assert((NumOp >= 8) && "Expected at least 8 operands!"); - Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg()); - } else { - assert((NumOp >= 4) && "Expected at least 4 operands!"); - Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg()); - Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg()); - } break; - } CASE_UNPCK(UNPCKLPD, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(UNPCKLPD, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; CASE_UNPCK(UNPCKLPS, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(UNPCKLPS, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; CASE_UNPCK(UNPCKHPD, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(UNPCKHPD, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; CASE_UNPCK(UNPCKHPS, r) - Src2Name = getRegName(MI->getOperand(2).getReg()); + Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + RegForm = true; // FALL THROUGH. CASE_UNPCK(UNPCKHPS, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); + Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; - CASE_VPERM(PERMILPS, r) - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_VPERMILPI(PERMILPS, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - CASE_VPERM(PERMILPS, m) - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + CASE_VPERMILPI(PERMILPS, m) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; - CASE_VPERM(PERMILPD, r) - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_VPERMILPI(PERMILPD, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - CASE_VPERM(PERMILPD, m) - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + CASE_VPERMILPI(PERMILPD, m) + if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0), - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -628,44 +839,58 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPERM2F128rm: case X86::VPERM2I128rm: // For instruction comments purpose, assume the 256-bit vector is v4i64. - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) + if (MI->getOperand(NumOperands - 1).isImm()) DecodeVPERM2X128Mask(MVT::v4i64, - MI->getOperand(MI->getNumOperands() - 1).getImm(), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(1).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); break; - case X86::VPERMQYri: - case X86::VPERMPDYri: - Src1Name = getRegName(MI->getOperand(1).getReg()); + CASE_VPERM(PERMPD, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); // FALL THROUGH. - case X86::VPERMQYmi: - case X86::VPERMPDYmi: - if (MI->getOperand(MI->getNumOperands() - 1).isImm()) - DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(), + CASE_VPERM(PERMPD, m) + if (MI->getOperand(NumOperands - 1).isImm()) + DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0), + MI->getOperand(NumOperands - 1).getImm(), + ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + + CASE_VPERM(PERMQ, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + // FALL THROUGH. + CASE_VPERM(PERMQ, m) + if (MI->getOperand(NumOperands - 1).isImm()) + DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0), + MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::MOVSDrr: case X86::VMOVSDrr: + case X86::VMOVSDZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::MOVSDrm: case X86::VMOVSDrm: + case X86::VMOVSDZrm: DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; case X86::MOVSSrr: case X86::VMOVSSrr: + case X86::VMOVSSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. case X86::MOVSSrm: case X86::VMOVSSrm: + case X86::VMOVSSZrm: DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -681,6 +906,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MOVZQI2PQIrm: case X86::MOVZPQILo2PQIrm: case X86::VMOVQI2PQIrm: + case X86::VMOVQI2PQIZrm: case X86::VMOVZQI2PQIrm: case X86::VMOVZPQILo2PQIrm: case X86::VMOVZPQILo2PQIZrm: @@ -690,6 +916,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MOVDI2PDIrm: case X86::VMOVDI2PDIrm: + case X86::VMOVDI2PDIZrm: DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -717,49 +944,41 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, Src2Name = getRegName(MI->getOperand(2).getReg()); break; - case X86::PMOVZXBWrr: - case X86::PMOVZXBDrr: - case X86::PMOVZXBQrr: - case X86::PMOVZXWDrr: - case X86::PMOVZXWQrr: - case X86::PMOVZXDQrr: - case X86::VPMOVZXBWrr: - case X86::VPMOVZXBDrr: - case X86::VPMOVZXBQrr: - case X86::VPMOVZXWDrr: - case X86::VPMOVZXWQrr: - case X86::VPMOVZXDQrr: - case X86::VPMOVZXBWYrr: - case X86::VPMOVZXBDYrr: - case X86::VPMOVZXBQYrr: - case X86::VPMOVZXWDYrr: - case X86::VPMOVZXWQYrr: - case X86::VPMOVZXDQYrr: - Src1Name = getRegName(MI->getOperand(1).getReg()); + case X86::VBROADCASTF128: + case X86::VBROADCASTI128: + DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + + CASE_PMOVZX(PMOVZXBW, r) + CASE_PMOVZX(PMOVZXBD, r) + CASE_PMOVZX(PMOVZXBQ, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + // FALL THROUGH. + CASE_PMOVZX(PMOVZXBW, m) + CASE_PMOVZX(PMOVZXBD, m) + CASE_PMOVZX(PMOVZXBQ, m) + DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + + CASE_PMOVZX(PMOVZXWD, r) + CASE_PMOVZX(PMOVZXWQ, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); // FALL THROUGH. - case X86::PMOVZXBWrm: - case X86::PMOVZXBDrm: - case X86::PMOVZXBQrm: - case X86::PMOVZXWDrm: - case X86::PMOVZXWQrm: - case X86::PMOVZXDQrm: - case X86::VPMOVZXBWrm: - case X86::VPMOVZXBDrm: - case X86::VPMOVZXBQrm: - case X86::VPMOVZXWDrm: - case X86::VPMOVZXWQrm: - case X86::VPMOVZXDQrm: - case X86::VPMOVZXBWYrm: - case X86::VPMOVZXBDYrm: - case X86::VPMOVZXBQYrm: - case X86::VPMOVZXWDYrm: - case X86::VPMOVZXWQYrm: - case X86::VPMOVZXDQYrm: { - MVT SrcVT, DstVT; - getZeroExtensionTypes(MI, SrcVT, DstVT); - DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - } break; + CASE_PMOVZX(PMOVZXWD, m) + CASE_PMOVZX(PMOVZXWQ, m) + DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + + CASE_PMOVZX(PMOVZXDQ, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + // FALL THROUGH. + CASE_PMOVZX(PMOVZXDQ, m) + DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; } // The only comments we decode are shuffles, so give up if we were unable to @@ -768,7 +987,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, return false; if (!DestName) DestName = Src1Name; - OS << (DestName ? DestName : "mem") << " = "; + OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = "; // If the two sources are the same, canonicalize the input elements to be // from the first src so that we get larger element spans. |