diff options
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 64 |
1 files changed, 34 insertions, 30 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index f4e97c9a17149..be242a0e5e54f 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -174,7 +174,8 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{ return N->isExactlyValue(+0.0); }]>; -def PSxLDQ_imm : SDNodeXForm<imm, [{ +// BYTE_imm - Transform bit immediates into byte immediates. +def BYTE_imm : SDNodeXForm<imm, [{ // Transformation function: imm >> 3 return getI32Imm(N->getZExtValue() >> 3); }]>; @@ -298,10 +299,9 @@ def palign : PatFrag<(ops node:$lhs, node:$rhs), // SSE scalar FP Instructions //===----------------------------------------------------------------------===// -// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the -// scheduler into a branch sequence. -// These are expanded by the scheduler. -let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { +// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after +// instruction selection into a branch sequence. +let Uses = [EFLAGS], usesCustomInserter = 1 in { def CMOV_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), "#CMOV_FR32 PSEUDO!", @@ -1996,21 +1996,21 @@ let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { let Predicates = [HasSSE2] in { def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), - (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>; def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2), - (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>; def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2), (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>; def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2), (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>; def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)), - (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>; // Shift up / down and insert zero's. def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))), - (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; + (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>; def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))), - (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; + (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>; } // Logical @@ -2822,37 +2822,41 @@ let Constraints = "$src1 = $dst" in { def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, i16imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR64:$dst, - (int_x86_ssse3_palign_r - VR64:$src1, VR64:$src2, - imm:$src3))]>; + []>; def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2, i16imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR64:$dst, - (int_x86_ssse3_palign_r - VR64:$src1, - (bitconvert (memopv2i32 addr:$src2)), - imm:$src3))]>; + []>; def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR128:$dst, - (int_x86_ssse3_palign_r_128 - VR128:$src1, VR128:$src2, - imm:$src3))]>, OpSize; + []>, OpSize; def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2, i32imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR128:$dst, - (int_x86_ssse3_palign_r_128 - VR128:$src1, - (bitconvert (memopv4i32 addr:$src2)), - imm:$src3))]>, OpSize; + []>, OpSize; } // palignr patterns. +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i16 imm:$src3)), + (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>, + Requires<[HasSSSE3]>; +def : Pat<(int_x86_ssse3_palign_r VR64:$src1, + (memop64 addr:$src2), + (i16 imm:$src3)), + (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>, + Requires<[HasSSSE3]>; + +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i32 imm:$src3)), + (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>, + Requires<[HasSSSE3]>; +def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, + (memopv2i64 addr:$src2), + (i32 imm:$src3)), + (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>, + Requires<[HasSSSE3]>; + let AddedComplexity = 5 in { def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)), (PALIGNR128rr VR128:$src2, VR128:$src1, @@ -3802,7 +3806,7 @@ let Constraints = "$src1 = $dst" in { } // String/text processing instructions. -let Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { +let Defs = [EFLAGS], usesCustomInserter = 1 in { def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "#PCMPISTRM128rr PSEUDO!", @@ -3830,7 +3834,7 @@ def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs), } let Defs = [EFLAGS], Uses = [EAX, EDX], - usesCustomDAGSchedInserter = 1 in { + usesCustomInserter = 1 in { def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src3, i8imm:$src5), "#PCMPESTRM128rr PSEUDO!", |