diff options
Diffstat (limited to 'lib/libpmc/libpmc.c')
| -rw-r--r-- | lib/libpmc/libpmc.c | 2098 |
1 files changed, 1 insertions, 2097 deletions
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c index c598d9e17847f..555b2be9fc4a4 100644 --- a/lib/libpmc/libpmc.c +++ b/lib/libpmc/libpmc.c @@ -48,29 +48,9 @@ __FBSDID("$FreeBSD$"); #include "libpmcinternal.h" /* Function prototypes */ -#if defined(__i386__) -static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -#endif #if defined(__amd64__) || defined(__i386__) -static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); -static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -#endif -#if defined(__i386__) -static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, - struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__amd64__) || defined(__i386__) static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, @@ -157,18 +137,13 @@ struct pmc_class_descr { } PMC_CLASSDEP_TABLE(iaf, IAF); -PMC_CLASSDEP_TABLE(k7, K7); PMC_CLASSDEP_TABLE(k8, K8); -PMC_CLASSDEP_TABLE(p4, P4); -PMC_CLASSDEP_TABLE(p5, P5); -PMC_CLASSDEP_TABLE(p6, P6); PMC_CLASSDEP_TABLE(xscale, XSCALE); PMC_CLASSDEP_TABLE(armv7, ARMV7); PMC_CLASSDEP_TABLE(armv8, ARMV8); PMC_CLASSDEP_TABLE(mips24k, MIPS24K); PMC_CLASSDEP_TABLE(mips74k, MIPS74K); PMC_CLASSDEP_TABLE(octeon, OCTEON); -PMC_CLASSDEP_TABLE(ucf, UCF); PMC_CLASSDEP_TABLE(ppc7450, PPC7450); PMC_CLASSDEP_TABLE(ppc970, PPC970); PMC_CLASSDEP_TABLE(e500, E500); @@ -178,122 +153,6 @@ static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; #undef __PMC_EV_ALIAS #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, -static const struct pmc_event_descr atom_event_table[] = -{ - __PMC_EV_ALIAS_ATOM() -}; - -static const struct pmc_event_descr atom_silvermont_event_table[] = -{ - __PMC_EV_ALIAS_ATOM_SILVERMONT() -}; - -static const struct pmc_event_descr core_event_table[] = -{ - __PMC_EV_ALIAS_CORE() -}; - - -static const struct pmc_event_descr core2_event_table[] = -{ - __PMC_EV_ALIAS_CORE2() -}; - -static const struct pmc_event_descr corei7_event_table[] = -{ - __PMC_EV_ALIAS_COREI7() -}; - -static const struct pmc_event_descr nehalem_ex_event_table[] = -{ - __PMC_EV_ALIAS_COREI7() -}; - -static const struct pmc_event_descr haswell_event_table[] = -{ - __PMC_EV_ALIAS_HASWELL() -}; - -static const struct pmc_event_descr haswell_xeon_event_table[] = -{ - __PMC_EV_ALIAS_HASWELL_XEON() -}; - -static const struct pmc_event_descr broadwell_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELL() -}; - -static const struct pmc_event_descr broadwell_xeon_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELL_XEON() -}; - -static const struct pmc_event_descr skylake_event_table[] = -{ - __PMC_EV_ALIAS_SKYLAKE() -}; - -static const struct pmc_event_descr skylake_xeon_event_table[] = -{ - __PMC_EV_ALIAS_SKYLAKE_XEON() -}; - -static const struct pmc_event_descr ivybridge_event_table[] = -{ - __PMC_EV_ALIAS_IVYBRIDGE() -}; - -static const struct pmc_event_descr ivybridge_xeon_event_table[] = -{ - __PMC_EV_ALIAS_IVYBRIDGE_XEON() -}; - -static const struct pmc_event_descr sandybridge_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGE() -}; - -static const struct pmc_event_descr sandybridge_xeon_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGE_XEON() -}; - -static const struct pmc_event_descr westmere_event_table[] = -{ - __PMC_EV_ALIAS_WESTMERE() -}; - -static const struct pmc_event_descr westmere_ex_event_table[] = -{ - __PMC_EV_ALIAS_WESTMERE() -}; - -static const struct pmc_event_descr corei7uc_event_table[] = -{ - __PMC_EV_ALIAS_COREI7UC() -}; - -static const struct pmc_event_descr haswelluc_event_table[] = -{ - __PMC_EV_ALIAS_HASWELLUC() -}; - -static const struct pmc_event_descr broadwelluc_event_table[] = -{ - __PMC_EV_ALIAS_BROADWELLUC() -}; - -static const struct pmc_event_descr sandybridgeuc_event_table[] = -{ - __PMC_EV_ALIAS_SANDYBRIDGEUC() -}; - -static const struct pmc_event_descr westmereuc_event_table[] = -{ - __PMC_EV_ALIAS_WESTMEREUC() -}; - static const struct pmc_event_descr cortex_a8_event_table[] = { __PMC_EV_ALIAS_ARMV7_CORTEX_A8() @@ -324,29 +183,7 @@ static const struct pmc_event_descr cortex_a57_event_table[] = PMC_CLASS_##C, __VA_ARGS__ \ } -PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(skylake_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); -PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); -PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); -PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); @@ -379,42 +216,7 @@ static const struct pmc_class_descr NAME##_class_table_descr = \ } #if defined(__i386__) || defined(__amd64__) -PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); -PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); -PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); -PMC_CLASS_TABLE_DESC(core, IAP, core, iap); -PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); -PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); -PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); -PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); -PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap); -PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap); -PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap); -PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap); -PMC_CLASS_TABLE_DESC(skylake_xeon, IAP, skylake_xeon, iap); -PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); -PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); -PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); -PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); -PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); -PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); -PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); -PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); -PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); -PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp); -PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); -PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); -#endif -#if defined(__i386__) -PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); -#endif -#if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); -PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); -#endif -#if defined(__i386__) -PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); -PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); #endif #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); @@ -556,616 +358,10 @@ pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } -#if defined(__i386__) - -/* - * AMD K7 (Athlon) CPUs. - */ - -static struct pmc_event_alias k7_aliases[] = { - EV_ALIAS("branches", "k7-retired-branches"), - EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "k7-dc-misses"), - EV_ALIAS("ic-misses", "k7-ic-misses"), - EV_ALIAS("instructions", "k7-retired-instructions"), - EV_ALIAS("interrupts", "k7-hardware-interrupts"), - EV_ALIAS(NULL, NULL) -}; - -#define K7_KW_COUNT "count" -#define K7_KW_EDGE "edge" -#define K7_KW_INV "inv" -#define K7_KW_OS "os" -#define K7_KW_UNITMASK "unitmask" -#define K7_KW_USR "usr" - -static int -k7_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - int c, has_unitmask; - uint32_t count, unitmask; - - pmc_config->pm_md.pm_amd.pm_amd_config = 0; - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - - if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || - pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || - pe == PMC_EV_K7_DC_WRITEBACKS) { - has_unitmask = 1; - unitmask = AMD_PMC_UNITMASK_MOESI; - } else - unitmask = has_unitmask = 0; - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_amd.pm_amd_config |= - AMD_PMC_TO_COUNTER(count); - - } else if (KWMATCH(p, K7_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, K7_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, K7_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { - if (has_unitmask == 0) - return (-1); - unitmask = 0; - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - while ((c = tolower(*q++)) != 0) - if (c == 'm') - unitmask |= AMD_PMC_UNITMASK_M; - else if (c == 'o') - unitmask |= AMD_PMC_UNITMASK_O; - else if (c == 'e') - unitmask |= AMD_PMC_UNITMASK_E; - else if (c == 's') - unitmask |= AMD_PMC_UNITMASK_S; - else if (c == 'i') - unitmask |= AMD_PMC_UNITMASK_I; - else if (c == '+') - continue; - else - return (-1); - - if (unitmask == 0) - return (-1); - - } else if (KWMATCH(p, K7_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else - return (-1); - } - - if (has_unitmask) { - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - pmc_config->pm_md.pm_amd.pm_amd_config |= - AMD_PMC_TO_UNITMASK(unitmask); - } - - return (0); - -} - -#endif - #if defined(__amd64__) || defined(__i386__) - -/* - * Intel Core (Family 6, Model E) PMCs. - */ - -static struct pmc_event_alias core_aliases[] = { - EV_ALIAS("branches", "iap-br-instr-ret"), - EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-icache-misses"), - EV_ALIAS("instructions", "iap-instr-ret"), - EV_ALIAS("interrupts", "iap-core-hw-int-rx"), - EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), - EV_ALIAS(NULL, NULL) -}; - -/* - * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) - * and Atom (Family 6, model 1CH) PMCs. - * - * We map aliases to events on the fixed-function counters if these - * are present. Note that not all CPUs in this family contain fixed-function - * counters. - */ - -static struct pmc_event_alias core2_aliases[] = { - EV_ALIAS("branches", "iap-br-inst-retired.any"), - EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-l1i-misses"), - EV_ALIAS("instructions", "iaf-instr-retired.any"), - EV_ALIAS("interrupts", "iap-hw-int-rcv"), - EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), - EV_ALIAS(NULL, NULL) -}; - -static struct pmc_event_alias core2_aliases_without_iaf[] = { - EV_ALIAS("branches", "iap-br-inst-retired.any"), - EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), - EV_ALIAS("cycles", "tsc-tsc"), - EV_ALIAS("ic-misses", "iap-l1i-misses"), - EV_ALIAS("instructions", "iap-inst-retired.any_p"), - EV_ALIAS("interrupts", "iap-hw-int-rcv"), - EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), - EV_ALIAS(NULL, NULL) -}; - -#define atom_aliases core2_aliases -#define atom_aliases_without_iaf core2_aliases_without_iaf -#define atom_silvermont_aliases core2_aliases -#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf -#define corei7_aliases core2_aliases -#define corei7_aliases_without_iaf core2_aliases_without_iaf -#define nehalem_ex_aliases core2_aliases -#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf -#define haswell_aliases core2_aliases -#define haswell_aliases_without_iaf core2_aliases_without_iaf -#define haswell_xeon_aliases core2_aliases -#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf -#define broadwell_aliases core2_aliases -#define broadwell_aliases_without_iaf core2_aliases_without_iaf -#define broadwell_xeon_aliases core2_aliases -#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf -#define skylake_aliases core2_aliases -#define skylake_aliases_without_iaf core2_aliases_without_iaf -#define skylake_xeon_aliases core2_aliases -#define skylake_xeon_aliases_without_iaf core2_aliases_without_iaf -#define ivybridge_aliases core2_aliases -#define ivybridge_aliases_without_iaf core2_aliases_without_iaf -#define ivybridge_xeon_aliases core2_aliases -#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf -#define sandybridge_aliases core2_aliases -#define sandybridge_aliases_without_iaf core2_aliases_without_iaf -#define sandybridge_xeon_aliases core2_aliases -#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf -#define westmere_aliases core2_aliases -#define westmere_aliases_without_iaf core2_aliases_without_iaf -#define westmere_ex_aliases core2_aliases -#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf - -#define IAF_KW_OS "os" -#define IAF_KW_USR "usr" -#define IAF_KW_ANYTHREAD "anythread" - -/* - * Parse an event specifier for Intel fixed function counters. - */ -static int -iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *p; - - (void) pe; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWMATCH(p, IAF_KW_OS)) - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - else if (KWMATCH(p, IAF_KW_USR)) - pmc_config->pm_caps |= PMC_CAP_USER; - else if (KWMATCH(p, IAF_KW_ANYTHREAD)) - pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; - else - return (-1); - } - - return (0); -} - -/* - * Core/Core2 support. - */ - -#define IAP_KW_AGENT "agent" -#define IAP_KW_ANYTHREAD "anythread" -#define IAP_KW_CACHESTATE "cachestate" -#define IAP_KW_CMASK "cmask" -#define IAP_KW_CORE "core" -#define IAP_KW_EDGE "edge" -#define IAP_KW_INV "inv" -#define IAP_KW_OS "os" -#define IAP_KW_PREFETCH "prefetch" -#define IAP_KW_SNOOPRESPONSE "snoopresponse" -#define IAP_KW_SNOOPTYPE "snooptype" -#define IAP_KW_TRANSITION "trans" -#define IAP_KW_USR "usr" -#define IAP_KW_RSP "rsp" - -static struct pmc_masks iap_core_mask[] = { - PMCMASK(all, (0x3 << 14)), - PMCMASK(this, (0x1 << 14)), - NULLMASK -}; - -static struct pmc_masks iap_agent_mask[] = { - PMCMASK(this, 0), - PMCMASK(any, (0x1 << 13)), - NULLMASK -}; - -static struct pmc_masks iap_prefetch_mask[] = { - PMCMASK(both, (0x3 << 12)), - PMCMASK(only, (0x1 << 12)), - PMCMASK(exclude, 0), - NULLMASK -}; - -static struct pmc_masks iap_cachestate_mask[] = { - PMCMASK(i, (1 << 8)), - PMCMASK(s, (1 << 9)), - PMCMASK(e, (1 << 10)), - PMCMASK(m, (1 << 11)), - NULLMASK -}; - -static struct pmc_masks iap_snoopresponse_mask[] = { - PMCMASK(clean, (1 << 8)), - PMCMASK(hit, (1 << 9)), - PMCMASK(hitm, (1 << 11)), - NULLMASK -}; - -static struct pmc_masks iap_snooptype_mask[] = { - PMCMASK(cmp2s, (1 << 8)), - PMCMASK(cmp2i, (1 << 9)), - NULLMASK -}; - -static struct pmc_masks iap_transition_mask[] = { - PMCMASK(any, 0x00), - PMCMASK(frequency, 0x10), - NULLMASK -}; - -static struct pmc_masks iap_rsp_mask_i7_wm[] = { - PMCMASK(DMND_DATA_RD, (1 << 0)), - PMCMASK(DMND_RFO, (1 << 1)), - PMCMASK(DMND_IFETCH, (1 << 2)), - PMCMASK(WB, (1 << 3)), - PMCMASK(PF_DATA_RD, (1 << 4)), - PMCMASK(PF_RFO, (1 << 5)), - PMCMASK(PF_IFETCH, (1 << 6)), - PMCMASK(OTHER, (1 << 7)), - PMCMASK(UNCORE_HIT, (1 << 8)), - PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), - PMCMASK(OTHER_CORE_HITM, (1 << 10)), - PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), - PMCMASK(REMOTE_DRAM, (1 << 13)), - PMCMASK(LOCAL_DRAM, (1 << 14)), - PMCMASK(NON_DRAM, (1 << 15)), - NULLMASK -}; - -static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_WB, (1ULL << 3)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), - PMCMASK(REQ_PF_RFO, (1ULL << 5)), - PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), - PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), - PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), - PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), - PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), - PMCMASK(REQ_STRM_ST, (1ULL << 11)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), - PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), - NULLMASK -}; - -/* Broadwell is defined to use the same mask as Haswell */ -static struct pmc_masks iap_rsp_mask_haswell[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), - PMCMASK(REQ_PF_RFO, (1ULL << 5)), - PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), - PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), - /* - * For processor type 06_45H 22 is L4_HIT_LOCAL_L4 - * and 23, 24 and 25 are also defined. - */ - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), - NULLMASK -}; - -static struct pmc_masks iap_rsp_mask_skylake[] = { - PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), - PMCMASK(REQ_DMND_RFO, (1ULL << 1)), - PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), - PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)), - PMCMASK(REQ_PF_RFO, (1ULL << 8)), - PMCMASK(REQ_STRM_ST, (1ULL << 11)), - PMCMASK(REQ_OTHER, (1ULL << 15)), - PMCMASK(RES_ANY, (1ULL << 16)), - PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), - PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), - PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), - PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), - PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)), - PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)), - PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)), - PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), - PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), - PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), - PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), - PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), - PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), - PMCMASK(RES_NON_DRAM, (1ULL << 37)), - NULLMASK -}; - - -static int -iap_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - uint64_t cachestate, evmask, rsp; - int count, n; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | - PMC_CAP_QUALIFIER); - pmc_config->pm_md.pm_iap.pm_iap_config = 0; - - cachestate = evmask = rsp = 0; - - /* Parse additional modifiers if present */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - - n = 0; - if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_iap.pm_iap_config |= - IAP_CMASK(count); - } else if (KWMATCH(p, IAP_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, IAP_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, IAP_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWMATCH(p, IAP_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { - pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; - } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { - n = pmc_parse_mask(iap_core_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { - n = pmc_parse_mask(iap_agent_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { - n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { - n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && - KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { - n = pmc_parse_mask(iap_transition_mask, p, &evmask); - if (n != 1) - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || - cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || - cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || - cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { - if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { - n = pmc_parse_mask(iap_snoopresponse_mask, p, - &evmask); - } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { - n = pmc_parse_mask(iap_snooptype_mask, p, - &evmask); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || - cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || - cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || - cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || - cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); - } else - return (-1); - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL || - cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) { - /* Broadwell is defined to use same mask as haswell */ - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); - } else - return (-1); - - } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE || - cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE_XEON) { - if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp); - } else - return (-1); - - } else - return (-1); - - if (n < 0) /* Parsing failed. */ - return (-1); - } - - pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; - - /* - * If the event requires a 'cachestate' qualifier but was not - * specified by the user, use a sensible default. - */ - switch (pe) { - case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ - case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ - case PMC_EV_IAP_EVENT_32H: /* Core */ - case PMC_EV_IAP_EVENT_40H: /* Core */ - case PMC_EV_IAP_EVENT_41H: /* Core */ - case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ - if (cachestate == 0) - cachestate = (0xF << 8); - break; - case PMC_EV_IAP_EVENT_77H: /* Atom */ - /* IAP_EVENT_77H only accepts a cachestate qualifier on the - * Atom processor - */ - if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) - cachestate = (0xF << 8); - break; - default: - break; - } - - pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; - pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; - - return (0); -} - -/* - * Intel Uncore. - */ - -static int -ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - (void) pe; - (void) ctrspec; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; - - return (0); -} - -#define UCP_KW_CMASK "cmask" -#define UCP_KW_EDGE "edge" -#define UCP_KW_INV "inv" - -static int -ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - int count, n; - - (void) pe; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | - PMC_CAP_QUALIFIER); - pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; - - /* Parse additional modifiers if present */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - - n = 0; - if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_ucp.pm_ucp_config |= - UCP_CMASK(count); - } else if (KWMATCH(p, UCP_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, UCP_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else - return (-1); - - if (n < 0) /* Parsing failed. */ - return (-1); - } - - return (0); -} - /* * AMD K8 PMCs. * - * These are very similar to AMD K7 PMCs, but support more kinds of - * events. */ static struct pmc_event_alias k8_aliases[] = { @@ -1520,962 +716,6 @@ k8_allocate_pmc(enum pmc_event pe, char *ctrspec, #endif -#if defined(__amd64__) || defined(__i386__) - -/* - * Intel P4 PMCs - */ - -static struct pmc_event_alias p4_aliases[] = { - EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), - EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("instructions", - "p4-instr-retired,mask=nbogusntag+nbogustag"), - EV_ALIAS("unhalted-cycles", "p4-global-power-events"), - EV_ALIAS(NULL, NULL) -}; - -#define P4_KW_ACTIVE "active" -#define P4_KW_ACTIVE_ANY "any" -#define P4_KW_ACTIVE_BOTH "both" -#define P4_KW_ACTIVE_NONE "none" -#define P4_KW_ACTIVE_SINGLE "single" -#define P4_KW_BUSREQTYPE "busreqtype" -#define P4_KW_CASCADE "cascade" -#define P4_KW_EDGE "edge" -#define P4_KW_INV "complement" -#define P4_KW_OS "os" -#define P4_KW_MASK "mask" -#define P4_KW_PRECISE "precise" -#define P4_KW_TAG "tag" -#define P4_KW_THRESHOLD "threshold" -#define P4_KW_USR "usr" - -#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) - -static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ - __P4MASK(dd, 0), - __P4MASK(db, 1), - __P4MASK(di, 2), - __P4MASK(bd, 3), - __P4MASK(bb, 4), - __P4MASK(bi, 5), - __P4MASK(id, 6), - __P4MASK(ib, 7), - NULLMASK -}; - -static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ - __P4MASK(tcmiss, 0), - NULLMASK, -}; - -static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ - __P4MASK(hit, 0), - __P4MASK(miss, 1), - __P4MASK(hit-uc, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ - __P4MASK(st-rb-full, 2), - __P4MASK(64k-conf, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ - __P4MASK(lsc, 0), - __P4MASK(ssc, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ - __P4MASK(split-ld, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ - __P4MASK(split-st, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ - __P4MASK(no-sta, 1), - __P4MASK(no-std, 3), - __P4MASK(partial-data, 4), - __P4MASK(unalgn-addr, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ - __P4MASK(dtmiss, 0), - __P4MASK(itmiss, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ - __P4MASK(rd-2ndl-hits, 0), - __P4MASK(rd-2ndl-hite, 1), - __P4MASK(rd-2ndl-hitm, 2), - __P4MASK(rd-3rdl-hits, 3), - __P4MASK(rd-3rdl-hite, 4), - __P4MASK(rd-3rdl-hitm, 5), - __P4MASK(rd-2ndl-miss, 8), - __P4MASK(rd-3rdl-miss, 9), - __P4MASK(wr-2ndl-miss, 10), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ - __P4MASK(all-read, 5), - __P4MASK(all-write, 6), - __P4MASK(mem-uc, 7), - __P4MASK(mem-wc, 8), - __P4MASK(mem-wt, 9), - __P4MASK(mem-wp, 10), - __P4MASK(mem-wb, 11), - __P4MASK(own, 13), - __P4MASK(other, 14), - __P4MASK(prefetch, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ - __P4MASK(all-read, 5), - __P4MASK(all-write, 6), - __P4MASK(mem-uc, 7), - __P4MASK(mem-wc, 8), - __P4MASK(mem-wt, 9), - __P4MASK(mem-wp, 10), - __P4MASK(mem-wb, 11), - __P4MASK(own, 13), - __P4MASK(other, 14), - __P4MASK(prefetch, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ - __P4MASK(drdy-drv, 0), - __P4MASK(drdy-own, 1), - __P4MASK(drdy-other, 2), - __P4MASK(dbsy-drv, 3), - __P4MASK(dbsy-own, 4), - __P4MASK(dbsy-other, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ - __P4MASK(req-type0, 0), - __P4MASK(req-type1, 1), - __P4MASK(req-len0, 2), - __P4MASK(req-len1, 3), - __P4MASK(req-io-type, 5), - __P4MASK(req-lock-type, 6), - __P4MASK(req-cache-type, 7), - __P4MASK(req-split-type, 8), - __P4MASK(req-dem-type, 9), - __P4MASK(req-ord-type, 10), - __P4MASK(mem-type0, 11), - __P4MASK(mem-type1, 12), - __P4MASK(mem-type2, 13), - NULLMASK -}; - -static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ - __P4MASK(all, 15), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ - __P4MASK(allp0, 3), - __P4MASK(allp2, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ - __P4MASK(running, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ - __P4MASK(cisc, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ - __P4MASK(from-tc-build, 0), - __P4MASK(from-tc-deliver, 1), - __P4MASK(from-rom, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rmbt[] = { - /* retired mispred branch type */ - __P4MASK(conditional, 1), - __P4MASK(call, 2), - __P4MASK(return, 3), - __P4MASK(indirect, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ - __P4MASK(conditional, 1), - __P4MASK(call, 2), - __P4MASK(retired, 3), - __P4MASK(indirect, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ - __P4MASK(sbfull, 5), - NULLMASK -}; - -static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ - __P4MASK(wcb-evicts, 0), - __P4MASK(wcb-full-evict, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_fee[] = { /* front end event */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ee[] = { /* execution event */ - __P4MASK(nbogus0, 0), - __P4MASK(nbogus1, 1), - __P4MASK(nbogus2, 2), - __P4MASK(nbogus3, 3), - __P4MASK(bogus0, 4), - __P4MASK(bogus1, 5), - __P4MASK(bogus2, 6), - __P4MASK(bogus3, 7), - NULLMASK -}; - -static const struct pmc_masks p4_mask_re[] = { /* replay event */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ - __P4MASK(nbogusntag, 0), - __P4MASK(nbogustag, 1), - __P4MASK(bogusntag, 2), - __P4MASK(bogustag, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ - __P4MASK(nbogus, 0), - __P4MASK(bogus, 1), - NULLMASK -}; - -static const struct pmc_masks p4_mask_ut[] = { /* uop type */ - __P4MASK(tagloads, 1), - __P4MASK(tagstores, 2), - NULLMASK -}; - -static const struct pmc_masks p4_mask_br[] = { /* branch retired */ - __P4MASK(mmnp, 0), - __P4MASK(mmnm, 1), - __P4MASK(mmtp, 2), - __P4MASK(mmtm, 3), - NULLMASK -}; - -static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ - __P4MASK(nbogus, 0), - NULLMASK -}; - -static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ - __P4MASK(fpsu, 0), - __P4MASK(fpso, 1), - __P4MASK(poao, 2), - __P4MASK(poau, 3), - __P4MASK(prea, 4), - NULLMASK -}; - -static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ - __P4MASK(clear, 0), - __P4MASK(moclear, 2), - __P4MASK(smclear, 3), - NULLMASK -}; - -/* P4 event parser */ -static int -p4_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - - char *e, *p, *q; - int count, has_tag, has_busreqtype, n; - uint32_t cccractivemask; - uint64_t evmask; - const struct pmc_masks *pm, *pmask; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = - pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; - - pmask = NULL; - evmask = 0; - cccractivemask = 0x3; - has_tag = has_busreqtype = 0; - -#define __P4SETMASK(M) do { \ - pmask = p4_mask_##M; \ -} while (0) - - switch (pe) { - case PMC_EV_P4_TC_DELIVER_MODE: - __P4SETMASK(tcdm); - break; - case PMC_EV_P4_BPU_FETCH_REQUEST: - __P4SETMASK(bfr); - break; - case PMC_EV_P4_ITLB_REFERENCE: - __P4SETMASK(ir); - break; - case PMC_EV_P4_MEMORY_CANCEL: - __P4SETMASK(memcan); - break; - case PMC_EV_P4_MEMORY_COMPLETE: - __P4SETMASK(memcomp); - break; - case PMC_EV_P4_LOAD_PORT_REPLAY: - __P4SETMASK(lpr); - break; - case PMC_EV_P4_STORE_PORT_REPLAY: - __P4SETMASK(spr); - break; - case PMC_EV_P4_MOB_LOAD_REPLAY: - __P4SETMASK(mlr); - break; - case PMC_EV_P4_PAGE_WALK_TYPE: - __P4SETMASK(pwt); - break; - case PMC_EV_P4_BSQ_CACHE_REFERENCE: - __P4SETMASK(bcr); - break; - case PMC_EV_P4_IOQ_ALLOCATION: - __P4SETMASK(ia); - has_busreqtype = 1; - break; - case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: - __P4SETMASK(iae); - has_busreqtype = 1; - break; - case PMC_EV_P4_FSB_DATA_ACTIVITY: - __P4SETMASK(fda); - break; - case PMC_EV_P4_BSQ_ALLOCATION: - __P4SETMASK(ba); - break; - case PMC_EV_P4_SSE_INPUT_ASSIST: - __P4SETMASK(sia); - break; - case PMC_EV_P4_PACKED_SP_UOP: - __P4SETMASK(psu); - break; - case PMC_EV_P4_PACKED_DP_UOP: - __P4SETMASK(pdu); - break; - case PMC_EV_P4_SCALAR_SP_UOP: - __P4SETMASK(ssu); - break; - case PMC_EV_P4_SCALAR_DP_UOP: - __P4SETMASK(sdu); - break; - case PMC_EV_P4_64BIT_MMX_UOP: - __P4SETMASK(64bmu); - break; - case PMC_EV_P4_128BIT_MMX_UOP: - __P4SETMASK(128bmu); - break; - case PMC_EV_P4_X87_FP_UOP: - __P4SETMASK(xfu); - break; - case PMC_EV_P4_X87_SIMD_MOVES_UOP: - __P4SETMASK(xsmu); - break; - case PMC_EV_P4_GLOBAL_POWER_EVENTS: - __P4SETMASK(gpe); - break; - case PMC_EV_P4_TC_MS_XFER: - __P4SETMASK(tmx); - break; - case PMC_EV_P4_UOP_QUEUE_WRITES: - __P4SETMASK(uqw); - break; - case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: - __P4SETMASK(rmbt); - break; - case PMC_EV_P4_RETIRED_BRANCH_TYPE: - __P4SETMASK(rbt); - break; - case PMC_EV_P4_RESOURCE_STALL: - __P4SETMASK(rs); - break; - case PMC_EV_P4_WC_BUFFER: - __P4SETMASK(wb); - break; - case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: - case PMC_EV_P4_B2B_CYCLES: - case PMC_EV_P4_BNR: - case PMC_EV_P4_SNOOP: - case PMC_EV_P4_RESPONSE: - break; - case PMC_EV_P4_FRONT_END_EVENT: - __P4SETMASK(fee); - break; - case PMC_EV_P4_EXECUTION_EVENT: - __P4SETMASK(ee); - break; - case PMC_EV_P4_REPLAY_EVENT: - __P4SETMASK(re); - break; - case PMC_EV_P4_INSTR_RETIRED: - __P4SETMASK(insret); - break; - case PMC_EV_P4_UOPS_RETIRED: - __P4SETMASK(ur); - break; - case PMC_EV_P4_UOP_TYPE: - __P4SETMASK(ut); - break; - case PMC_EV_P4_BRANCH_RETIRED: - __P4SETMASK(br); - break; - case PMC_EV_P4_MISPRED_BRANCH_RETIRED: - __P4SETMASK(mbr); - break; - case PMC_EV_P4_X87_ASSIST: - __P4SETMASK(xa); - break; - case PMC_EV_P4_MACHINE_CLEAR: - __P4SETMASK(machclr); - break; - default: - return (-1); - } - - /* process additional flags */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) - cccractivemask = 0x0; - else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) - cccractivemask = 0x1; - else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) - cccractivemask = 0x2; - else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) - cccractivemask = 0x3; - else - return (-1); - - } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { - if (has_busreqtype == 0) - return (-1); - - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - evmask = (evmask & ~0x1F) | (count & 0x1F); - } else if (KWMATCH(p, P4_KW_CASCADE)) - pmc_config->pm_caps |= PMC_CAP_CASCADE; - else if (KWMATCH(p, P4_KW_EDGE)) - pmc_config->pm_caps |= PMC_CAP_EDGE; - else if (KWMATCH(p, P4_KW_INV)) - pmc_config->pm_caps |= PMC_CAP_INVERT; - else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { - if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) - return (-1); - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } else if (KWMATCH(p, P4_KW_OS)) - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - else if (KWMATCH(p, P4_KW_PRECISE)) - pmc_config->pm_caps |= PMC_CAP_PRECISE; - else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { - if (has_tag == 0) - return (-1); - - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_TAGGING; - pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= - P4_ESCR_TO_TAG_VALUE(count); - } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= - ~P4_CCCR_THRESHOLD_MASK; - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= - P4_CCCR_TO_THRESHOLD(count); - } else if (KWMATCH(p, P4_KW_USR)) - pmc_config->pm_caps |= PMC_CAP_USER; - else - return (-1); - } - - /* other post processing */ - if (pe == PMC_EV_P4_IOQ_ALLOCATION || - pe == PMC_EV_P4_FSB_DATA_ACTIVITY || - pe == PMC_EV_P4_BSQ_ALLOCATION) - pmc_config->pm_caps |= PMC_CAP_EDGE; - - /* fill in thread activity mask */ - pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= - P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); - - if (evmask) - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - - switch (pe) { - case PMC_EV_P4_FSB_DATA_ACTIVITY: - if ((evmask & 0x06) == 0x06 || - (evmask & 0x18) == 0x18) - return (-1); /* can't have own+other bits together */ - if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ - evmask = 0x1D; - break; - case PMC_EV_P4_MACHINE_CLEAR: - /* only one bit is allowed to be set */ - if ((evmask & (evmask - 1)) != 0) - return (-1); - if (evmask == 0) { - evmask = 0x1; /* 'CLEAR' */ - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - break; - default: - if (evmask == 0 && pmask) { - for (pm = pmask; pm->pm_name; pm++) - evmask |= pm->pm_value; - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - } - - pmc_config->pm_md.pm_p4.pm_p4_escrconfig = - P4_ESCR_TO_EVENT_MASK(evmask); - - return (0); -} - -#endif - -#if defined(__i386__) - -/* - * Pentium style PMCs - */ - -static struct pmc_event_alias p5_aliases[] = { - EV_ALIAS("branches", "p5-taken-branches"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), - EV_ALIAS("ic-misses", "p5-code-cache-miss"), - EV_ALIAS("instructions", "p5-instructions-executed"), - EV_ALIAS("interrupts", "p5-hardware-interrupts"), - EV_ALIAS("unhalted-cycles", - "p5-number-of-cycles-not-in-halt-state"), - EV_ALIAS(NULL, NULL) -}; - -static int -p5_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ -} - -/* - * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, - * and Pentium M CPUs. - */ - -static struct pmc_event_alias p6_aliases[] = { - EV_ALIAS("branches", "p6-br-inst-retired"), - EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), - EV_ALIAS("cycles", "tsc"), - EV_ALIAS("dc-misses", "p6-dcu-lines-in"), - EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), - EV_ALIAS("instructions", "p6-inst-retired"), - EV_ALIAS("interrupts", "p6-hw-int-rx"), - EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), - EV_ALIAS(NULL, NULL) -}; - -#define P6_KW_CMASK "cmask" -#define P6_KW_EDGE "edge" -#define P6_KW_INV "inv" -#define P6_KW_OS "os" -#define P6_KW_UMASK "umask" -#define P6_KW_USR "usr" - -static struct pmc_masks p6_mask_mesi[] = { - PMCMASK(m, 0x01), - PMCMASK(e, 0x02), - PMCMASK(s, 0x04), - PMCMASK(i, 0x08), - NULLMASK -}; - -static struct pmc_masks p6_mask_mesihw[] = { - PMCMASK(m, 0x01), - PMCMASK(e, 0x02), - PMCMASK(s, 0x04), - PMCMASK(i, 0x08), - PMCMASK(nonhw, 0x00), - PMCMASK(hw, 0x10), - PMCMASK(both, 0x30), - NULLMASK -}; - -static struct pmc_masks p6_mask_hw[] = { - PMCMASK(nonhw, 0x00), - PMCMASK(hw, 0x10), - PMCMASK(both, 0x30), - NULLMASK -}; - -static struct pmc_masks p6_mask_any[] = { - PMCMASK(self, 0x00), - PMCMASK(any, 0x20), - NULLMASK -}; - -static struct pmc_masks p6_mask_ekp[] = { - PMCMASK(nta, 0x00), - PMCMASK(t1, 0x01), - PMCMASK(t2, 0x02), - PMCMASK(wos, 0x03), - NULLMASK -}; - -static struct pmc_masks p6_mask_pps[] = { - PMCMASK(packed-and-scalar, 0x00), - PMCMASK(scalar, 0x01), - NULLMASK -}; - -static struct pmc_masks p6_mask_mite[] = { - PMCMASK(packed-multiply, 0x01), - PMCMASK(packed-shift, 0x02), - PMCMASK(pack, 0x04), - PMCMASK(unpack, 0x08), - PMCMASK(packed-logical, 0x10), - PMCMASK(packed-arithmetic, 0x20), - NULLMASK -}; - -static struct pmc_masks p6_mask_fmt[] = { - PMCMASK(mmxtofp, 0x00), - PMCMASK(fptommx, 0x01), - NULLMASK -}; - -static struct pmc_masks p6_mask_sr[] = { - PMCMASK(es, 0x01), - PMCMASK(ds, 0x02), - PMCMASK(fs, 0x04), - PMCMASK(gs, 0x08), - NULLMASK -}; - -static struct pmc_masks p6_mask_eet[] = { - PMCMASK(all, 0x00), - PMCMASK(freq, 0x02), - NULLMASK -}; - -static struct pmc_masks p6_mask_efur[] = { - PMCMASK(all, 0x00), - PMCMASK(loadop, 0x01), - PMCMASK(stdsta, 0x02), - NULLMASK -}; - -static struct pmc_masks p6_mask_essir[] = { - PMCMASK(sse-packed-single, 0x00), - PMCMASK(sse-packed-single-scalar-single, 0x01), - PMCMASK(sse2-packed-double, 0x02), - PMCMASK(sse2-scalar-double, 0x03), - NULLMASK -}; - -static struct pmc_masks p6_mask_esscir[] = { - PMCMASK(sse-packed-single, 0x00), - PMCMASK(sse-scalar-single, 0x01), - PMCMASK(sse2-packed-double, 0x02), - PMCMASK(sse2-scalar-double, 0x03), - NULLMASK -}; - -/* P6 event parser */ -static int -p6_allocate_pmc(enum pmc_event pe, char *ctrspec, - struct pmc_op_pmcallocate *pmc_config) -{ - char *e, *p, *q; - uint64_t evmask; - int count, n; - const struct pmc_masks *pm, *pmask; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; - - evmask = 0; - -#define P6MASKSET(M) pmask = p6_mask_ ## M - - switch(pe) { - case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; - case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; - case PMC_EV_P6_BUS_DRDY_CLOCKS: - case PMC_EV_P6_BUS_LOCK_CLOCKS: - case PMC_EV_P6_BUS_TRAN_BRD: - case PMC_EV_P6_BUS_TRAN_RFO: - case PMC_EV_P6_BUS_TRANS_WB: - case PMC_EV_P6_BUS_TRAN_IFETCH: - case PMC_EV_P6_BUS_TRAN_INVAL: - case PMC_EV_P6_BUS_TRAN_PWR: - case PMC_EV_P6_BUS_TRANS_P: - case PMC_EV_P6_BUS_TRANS_IO: - case PMC_EV_P6_BUS_TRAN_DEF: - case PMC_EV_P6_BUS_TRAN_BURST: - case PMC_EV_P6_BUS_TRAN_ANY: - case PMC_EV_P6_BUS_TRAN_MEM: - P6MASKSET(any); break; - case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: - case PMC_EV_P6_EMON_KNI_PREF_MISS: - P6MASKSET(ekp); break; - case PMC_EV_P6_EMON_KNI_INST_RETIRED: - case PMC_EV_P6_EMON_KNI_COMP_INST_RET: - P6MASKSET(pps); break; - case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: - P6MASKSET(mite); break; - case PMC_EV_P6_FP_MMX_TRANS: - P6MASKSET(fmt); break; - case PMC_EV_P6_SEG_RENAME_STALLS: - case PMC_EV_P6_SEG_REG_RENAMES: - P6MASKSET(sr); break; - case PMC_EV_P6_EMON_EST_TRANS: - P6MASKSET(eet); break; - case PMC_EV_P6_EMON_FUSED_UOPS_RET: - P6MASKSET(efur); break; - case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: - P6MASKSET(essir); break; - case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: - P6MASKSET(esscir); break; - default: - pmask = NULL; - break; - } - - /* Pentium M PMCs have a few events with different semantics */ - if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { - if (pe == PMC_EV_P6_L2_LD || - pe == PMC_EV_P6_L2_LINES_IN || - pe == PMC_EV_P6_L2_LINES_OUT) - P6MASKSET(mesihw); - else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) - P6MASKSET(hw); - } - - /* Parse additional modifiers if present */ - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { - q = strchr(p, '='); - if (*++q == '\0') /* skip '=' */ - return (-1); - count = strtol(q, &e, 0); - if (e == q || *e != '\0') - return (-1); - pmc_config->pm_caps |= PMC_CAP_THRESHOLD; - pmc_config->pm_md.pm_ppro.pm_ppro_config |= - P6_EVSEL_TO_CMASK(count); - } else if (KWMATCH(p, P6_KW_EDGE)) { - pmc_config->pm_caps |= PMC_CAP_EDGE; - } else if (KWMATCH(p, P6_KW_INV)) { - pmc_config->pm_caps |= PMC_CAP_INVERT; - } else if (KWMATCH(p, P6_KW_OS)) { - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { - evmask = 0; - if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) - return (-1); - if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || - pe == PMC_EV_P6_BUS_LOCK_CLOCKS || - pe == PMC_EV_P6_BUS_TRAN_BRD || - pe == PMC_EV_P6_BUS_TRAN_RFO || - pe == PMC_EV_P6_BUS_TRAN_IFETCH || - pe == PMC_EV_P6_BUS_TRAN_INVAL || - pe == PMC_EV_P6_BUS_TRAN_PWR || - pe == PMC_EV_P6_BUS_TRAN_DEF || - pe == PMC_EV_P6_BUS_TRAN_BURST || - pe == PMC_EV_P6_BUS_TRAN_ANY || - pe == PMC_EV_P6_BUS_TRAN_MEM || - pe == PMC_EV_P6_BUS_TRANS_IO || - pe == PMC_EV_P6_BUS_TRANS_P || - pe == PMC_EV_P6_BUS_TRANS_WB || - pe == PMC_EV_P6_EMON_EST_TRANS || - pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || - pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || - pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || - pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || - pe == PMC_EV_P6_EMON_KNI_PREF_MISS || - pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || - pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || - pe == PMC_EV_P6_FP_MMX_TRANS) - && (n > 1)) /* Only one mask keyword is allowed. */ - return (-1); - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } else if (KWMATCH(p, P6_KW_USR)) { - pmc_config->pm_caps |= PMC_CAP_USER; - } else - return (-1); - } - - /* post processing */ - switch (pe) { - - /* - * The following events default to an evmask of 0 - */ - - /* default => 'self' */ - case PMC_EV_P6_BUS_DRDY_CLOCKS: - case PMC_EV_P6_BUS_LOCK_CLOCKS: - case PMC_EV_P6_BUS_TRAN_BRD: - case PMC_EV_P6_BUS_TRAN_RFO: - case PMC_EV_P6_BUS_TRANS_WB: - case PMC_EV_P6_BUS_TRAN_IFETCH: - case PMC_EV_P6_BUS_TRAN_INVAL: - case PMC_EV_P6_BUS_TRAN_PWR: - case PMC_EV_P6_BUS_TRANS_P: - case PMC_EV_P6_BUS_TRANS_IO: - case PMC_EV_P6_BUS_TRAN_DEF: - case PMC_EV_P6_BUS_TRAN_BURST: - case PMC_EV_P6_BUS_TRAN_ANY: - case PMC_EV_P6_BUS_TRAN_MEM: - - /* default => 'nta' */ - case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: - case PMC_EV_P6_EMON_KNI_PREF_MISS: - - /* default => 'packed and scalar' */ - case PMC_EV_P6_EMON_KNI_INST_RETIRED: - case PMC_EV_P6_EMON_KNI_COMP_INST_RET: - - /* default => 'mmx to fp transitions' */ - case PMC_EV_P6_FP_MMX_TRANS: - - /* default => 'SSE Packed Single' */ - case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: - case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: - - /* default => 'all fused micro-ops' */ - case PMC_EV_P6_EMON_FUSED_UOPS_RET: - - /* default => 'all transitions' */ - case PMC_EV_P6_EMON_EST_TRANS: - break; - - case PMC_EV_P6_MMX_UOPS_EXEC: - evmask = 0x0F; /* only value allowed */ - break; - - default: - /* - * For all other events, set the default event mask - * to a logical OR of all the allowed event mask bits. - */ - if (evmask == 0 && pmask) { - for (pm = pmask; pm->pm_name; pm++) - evmask |= pm->pm_value; - pmc_config->pm_caps |= PMC_CAP_QUALIFIER; - } - - break; - } - - if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) - pmc_config->pm_md.pm_ppro.pm_ppro_config |= - P6_EVSEL_TO_UMASK(evmask); - - return (0); -} - -#endif - #if defined(__i386__) || defined(__amd64__) static int tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, @@ -2982,145 +1222,14 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, ev = iaf_event_table; count = PMC_EVENT_TABLE_SIZE(iaf); break; - case PMC_CLASS_IAP: - /* - * Return the most appropriate set of event name - * spellings for the current CPU. - */ - switch (cpu_info.pm_cputype) { - default: - case PMC_CPU_INTEL_ATOM: - ev = atom_event_table; - count = PMC_EVENT_TABLE_SIZE(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - ev = atom_silvermont_event_table; - count = PMC_EVENT_TABLE_SIZE(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - ev = core_event_table; - count = PMC_EVENT_TABLE_SIZE(core); - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - ev = core2_event_table; - count = PMC_EVENT_TABLE_SIZE(core2); - break; - case PMC_CPU_INTEL_COREI7: - ev = corei7_event_table; - count = PMC_EVENT_TABLE_SIZE(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - ev = nehalem_ex_event_table; - count = PMC_EVENT_TABLE_SIZE(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswell_event_table; - count = PMC_EVENT_TABLE_SIZE(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - ev = haswell_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwell_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - ev = broadwell_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - ev = skylake_event_table; - count = PMC_EVENT_TABLE_SIZE(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - ev = skylake_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - ev = ivybridge_event_table; - count = PMC_EVENT_TABLE_SIZE(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - ev = ivybridge_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridge_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - ev = sandybridge_xeon_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmere_event_table; - count = PMC_EVENT_TABLE_SIZE(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - ev = westmere_ex_event_table; - count = PMC_EVENT_TABLE_SIZE(westmere_ex); - break; - } - break; - case PMC_CLASS_UCF: - ev = ucf_event_table; - count = PMC_EVENT_TABLE_SIZE(ucf); - break; - case PMC_CLASS_UCP: - /* - * Return the most appropriate set of event name - * spellings for the current CPU. - */ - switch (cpu_info.pm_cputype) { - default: - case PMC_CPU_INTEL_COREI7: - ev = corei7uc_event_table; - count = PMC_EVENT_TABLE_SIZE(corei7uc); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswelluc_event_table; - count = PMC_EVENT_TABLE_SIZE(haswelluc); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwelluc_event_table; - count = PMC_EVENT_TABLE_SIZE(broadwelluc); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridgeuc_event_table; - count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmereuc_event_table; - count = PMC_EVENT_TABLE_SIZE(westmereuc); - break; - } - break; case PMC_CLASS_TSC: ev = tsc_event_table; count = PMC_EVENT_TABLE_SIZE(tsc); break; - case PMC_CLASS_K7: - ev = k7_event_table; - count = PMC_EVENT_TABLE_SIZE(k7); - break; case PMC_CLASS_K8: ev = k8_event_table; count = PMC_EVENT_TABLE_SIZE(k8); break; - case PMC_CLASS_P4: - ev = p4_event_table; - count = PMC_EVENT_TABLE_SIZE(p4); - break; - case PMC_CLASS_P5: - ev = p5_event_table; - count = PMC_EVENT_TABLE_SIZE(p5); - break; - case PMC_CLASS_P6: - ev = p6_event_table; - count = PMC_EVENT_TABLE_SIZE(p6); - break; case PMC_CLASS_XSCALE: ev = xscale_event_table; count = PMC_EVENT_TABLE_SIZE(xscale); @@ -3356,98 +1465,11 @@ pmc_init(void) /* Configure the event name parser. */ switch (cpu_info.pm_cputype) { -#if defined(__i386__) - case PMC_CPU_AMD_K7: - PMC_MDEP_INIT(k7); - pmc_class_table[n] = &k7_class_table_descr; - break; - case PMC_CPU_INTEL_P5: - PMC_MDEP_INIT(p5); - pmc_class_table[n] = &p5_class_table_descr; - break; - case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ - case PMC_CPU_INTEL_PII: /* similar PMCs. */ - case PMC_CPU_INTEL_PIII: - case PMC_CPU_INTEL_PM: - PMC_MDEP_INIT(p6); - pmc_class_table[n] = &p6_class_table_descr; - break; -#endif #if defined(__amd64__) || defined(__i386__) case PMC_CPU_AMD_K8: PMC_MDEP_INIT(k8); pmc_class_table[n] = &k8_class_table_descr; break; - case PMC_CPU_INTEL_ATOM: - PMC_MDEP_INIT_INTEL_V2(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - PMC_MDEP_INIT_INTEL_V2(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - PMC_MDEP_INIT(core); - pmc_class_table[n] = &core_class_table_descr; - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - PMC_MDEP_INIT_INTEL_V2(core2); - break; - case PMC_CPU_INTEL_COREI7: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &corei7uc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - PMC_MDEP_INIT_INTEL_V2(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &haswelluc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - PMC_MDEP_INIT_INTEL_V2(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &broadwelluc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - PMC_MDEP_INIT_INTEL_V2(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - PMC_MDEP_INIT_INTEL_V2(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - PMC_MDEP_INIT_INTEL_V2(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - PMC_MDEP_INIT_INTEL_V2(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &sandybridgeuc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - pmc_class_table[n++] = &ucf_class_table_descr; - pmc_class_table[n++] = &westmereuc_class_table_descr; - PMC_MDEP_INIT_INTEL_V2(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - PMC_MDEP_INIT_INTEL_V2(westmere_ex); - break; - case PMC_CPU_INTEL_PIV: - PMC_MDEP_INIT(p4); - pmc_class_table[n] = &p4_class_table_descr; - break; #endif case PMC_CPU_GENERIC: PMC_MDEP_INIT(generic); @@ -3581,127 +1603,9 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) const struct pmc_event_descr *ev, *evfence; ev = evfence = NULL; - if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { - ev = iaf_event_table; - evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); - } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { - switch (cpu) { - case PMC_CPU_INTEL_ATOM: - ev = atom_event_table; - evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); - break; - case PMC_CPU_INTEL_ATOM_SILVERMONT: - ev = atom_silvermont_event_table; - evfence = atom_silvermont_event_table + - PMC_EVENT_TABLE_SIZE(atom_silvermont); - break; - case PMC_CPU_INTEL_CORE: - ev = core_event_table; - evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); - break; - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - ev = core2_event_table; - evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); - break; - case PMC_CPU_INTEL_COREI7: - ev = corei7_event_table; - evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); - break; - case PMC_CPU_INTEL_NEHALEM_EX: - ev = nehalem_ex_event_table; - evfence = nehalem_ex_event_table + - PMC_EVENT_TABLE_SIZE(nehalem_ex); - break; - case PMC_CPU_INTEL_HASWELL: - ev = haswell_event_table; - evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); - break; - case PMC_CPU_INTEL_HASWELL_XEON: - ev = haswell_xeon_event_table; - evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); - break; - case PMC_CPU_INTEL_BROADWELL: - ev = broadwell_event_table; - evfence = broadwell_event_table + PMC_EVENT_TABLE_SIZE(broadwell); - break; - case PMC_CPU_INTEL_BROADWELL_XEON: - ev = broadwell_xeon_event_table; - evfence = broadwell_xeon_event_table + PMC_EVENT_TABLE_SIZE(broadwell_xeon); - break; - case PMC_CPU_INTEL_SKYLAKE: - ev = skylake_event_table; - evfence = skylake_event_table + - PMC_EVENT_TABLE_SIZE(skylake); - break; - case PMC_CPU_INTEL_SKYLAKE_XEON: - ev = skylake_xeon_event_table; - evfence = skylake_xeon_event_table + - PMC_EVENT_TABLE_SIZE(skylake_xeon); - break; - case PMC_CPU_INTEL_IVYBRIDGE: - ev = ivybridge_event_table; - evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); - break; - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - ev = ivybridge_xeon_event_table; - evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridge_event_table; - evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); - break; - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - ev = sandybridge_xeon_event_table; - evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmere_event_table; - evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); - break; - case PMC_CPU_INTEL_WESTMERE_EX: - ev = westmere_ex_event_table; - evfence = westmere_ex_event_table + - PMC_EVENT_TABLE_SIZE(westmere_ex); - break; - default: /* Unknown CPU type. */ - break; - } - } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { - ev = ucf_event_table; - evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); - } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { - switch (cpu) { - case PMC_CPU_INTEL_COREI7: - ev = corei7uc_event_table; - evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); - break; - case PMC_CPU_INTEL_SANDYBRIDGE: - ev = sandybridgeuc_event_table; - evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); - break; - case PMC_CPU_INTEL_WESTMERE: - ev = westmereuc_event_table; - evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); - break; - default: /* Unknown CPU type. */ - break; - } - } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { - ev = k7_event_table; - evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); - } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { + if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { ev = k8_event_table; evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); - } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { - ev = p4_event_table; - evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); - } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { - ev = p5_event_table; - evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); - } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { - ev = p6_event_table; - evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { ev = xscale_event_table; evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); |