diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64Subtarget.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 67 |
1 files changed, 64 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 3636d8d2b628c..029535cb98b57 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -13,12 +13,12 @@ #include "AArch64Subtarget.h" #include "AArch64.h" -#include "AArch64CallLowering.h" #include "AArch64InstrInfo.h" -#include "AArch64LegalizerInfo.h" #include "AArch64PBQPRegAlloc.h" -#include "AArch64RegisterBankInfo.h" #include "AArch64TargetMachine.h" +#include "GISel/AArch64CallLowering.h" +#include "GISel/AArch64LegalizerInfo.h" +#include "GISel/AArch64RegisterBankInfo.h" #include "MCTargetDesc/AArch64AddressingModes.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/MachineScheduler.h" @@ -47,6 +47,18 @@ static cl::opt<bool> cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden); +static cl::opt<unsigned> SVEVectorBitsMax( + "aarch64-sve-vector-bits-max", + cl::desc("Assume SVE vector registers are at most this big, " + "with zero meaning no maximum size is assumed."), + cl::init(0), cl::Hidden); + +static cl::opt<unsigned> SVEVectorBitsMin( + "aarch64-sve-vector-bits-min", + cl::desc("Assume SVE vector registers are at least this big, " + "with zero meaning no minimum size is assumed."), + cl::init(0), cl::Hidden); + AArch64Subtarget & AArch64Subtarget::initializeSubtargetDependencies(StringRef FS, StringRef CPUString) { @@ -68,6 +80,9 @@ void AArch64Subtarget::initializeProperties() { switch (ARMProcFamily) { case Others: break; + case Carmel: + CacheLineSize = 64; + break; case CortexA35: break; case CortexA53: @@ -86,8 +101,16 @@ void AArch64Subtarget::initializeProperties() { case CortexA73: case CortexA75: case CortexA76: + case CortexA77: + case CortexA78: + case CortexX1: PrefFunctionLogAlignment = 4; break; + case A64FX: + CacheLineSize = 256; + PrefFunctionLogAlignment = 5; + PrefLoopLogAlignment = 5; + break; case AppleA7: case AppleA10: case AppleA11: @@ -160,6 +183,17 @@ void AArch64Subtarget::initializeProperties() { PrefFunctionLogAlignment = 4; PrefLoopLogAlignment = 2; break; + case ThunderX3T110: + CacheLineSize = 64; + PrefFunctionLogAlignment = 4; + PrefLoopLogAlignment = 2; + MaxInterleaveFactor = 4; + PrefetchDistance = 128; + MinPrefetchStride = 1024; + MaxPrefetchIterationsAhead = 4; + // FIXME: remove this to enable 64-bit SLP if performance looks good. + MinVectorRegisterBitWidth = 128; + break; } } @@ -177,6 +211,7 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, ReserveXRegister.set(18); CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering())); + InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering())); Legalizer.reset(new AArch64LegalizerInfo(*this)); auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo()); @@ -194,6 +229,10 @@ const CallLowering *AArch64Subtarget::getCallLowering() const { return CallLoweringInfo.get(); } +const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const { + return InlineAsmLoweringInfo.get(); +} + InstructionSelector *AArch64Subtarget::getInstructionSelector() const { return InstSelector.get(); } @@ -305,3 +344,25 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const { if (!MFI.isMaxCallFrameSizeComputed()) MFI.computeMaxCallFrameSize(MF); } + +unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const { + assert(HasSVE && "Tried to get SVE vector length without SVE support!"); + assert(SVEVectorBitsMax % 128 == 0 && + "SVE requires vector length in multiples of 128!"); + assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) && + "Minimum SVE vector size should not be larger than its maximum!"); + if (SVEVectorBitsMax == 0) + return 0; + return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128; +} + +unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const { + assert(HasSVE && "Tried to get SVE vector length without SVE support!"); + assert(SVEVectorBitsMin % 128 == 0 && + "SVE requires vector length in multiples of 128!"); + assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) && + "Minimum SVE vector size should not be larger than its maximum!"); + if (SVEVectorBitsMax == 0) + return (SVEVectorBitsMin / 128) * 128; + return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128; +} |