diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp b/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp index ee011286b8ff3..90e48c63b5dca 100644 --- a/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp +++ b/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp @@ -111,10 +111,6 @@ bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) { unsigned ActiveLanes = TII->isGather4(Opcode) ? 4 : countPopulation(dmask); - // Subreg indices are counted from 1 - // When D16 then we want next whole VGPR after write data. - static_assert(AMDGPU::sub0 == 1 && AMDGPU::sub4 == 5, "Subreg indices different from expected"); - bool Packed = !ST.hasUnpackedD16VMem(); unsigned InitIdx = @@ -137,7 +133,7 @@ bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) { // all the result registers to 0, otherwise just the error indication // register (VGPRn+1) unsigned SizeLeft = ST.usePRTStrictNull() ? InitIdx : 1; - unsigned CurrIdx = ST.usePRTStrictNull() ? 1 : InitIdx; + unsigned CurrIdx = ST.usePRTStrictNull() ? 0 : (InitIdx - 1); if (DstSize == 1) { // In this case we can just initialize the result directly @@ -158,7 +154,7 @@ bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) { BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst) .addReg(PrevDst) .addReg(SubReg) - .addImm(CurrIdx); + .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx)); PrevDst = NewDst; } |