diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.h | 63 |
1 files changed, 49 insertions, 14 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index d59495b052a4f..f4c0764640575 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -42,7 +42,8 @@ private: SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, - uint64_t Offset, unsigned Align, bool Signed, + uint64_t Offset, Align Alignment, + bool Signed, const ISD::InputArg *Arg = nullptr) const; SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, @@ -60,7 +61,7 @@ private: SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, SelectionDAG &DAG) const; SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, - SDValue GLC, SDValue DLC, SelectionDAG &DAG) const; + SDValue CachePolicy, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; @@ -107,7 +108,7 @@ private: /// Converts \p Op, which must be of floating point type, to the /// floating point type \p VT, by either extending or truncating it. - SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, + SDValue getFPExtOrFPRound(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, EVT VT) const; @@ -119,6 +120,7 @@ private: /// Custom lowering for ISD::FP_ROUND for MVT::f16. SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, SelectionDAG &DAG) const; @@ -199,6 +201,15 @@ public: /// global value \p GV, false otherwise. bool shouldEmitPCReloc(const GlobalValue *GV) const; + /// \returns true if this should use a literal constant for an LDS address, + /// and not emit a relocation for an LDS global. + bool shouldUseLDSConstAddress(const GlobalValue *GV) const; + + /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be + /// expanded into a set of cmp/select instructions. + static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, + bool IsDivergentIdx); + private: // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the // three offsets (voffset, soffset and instoffset) into the SDValue[3] array @@ -206,7 +217,7 @@ private: /// \returns 0 If there is a non-constant offset or if the offset is 0. /// Otherwise returns the constant offset. unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, - SDValue *Offsets, unsigned Align = 4) const; + SDValue *Offsets, Align Alignment = Align(4)) const; // Handle 8 bit and 16 bit buffer loads SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, @@ -253,15 +264,18 @@ public: MachineMemOperand::Flags Flags = MachineMemOperand::MONone, bool *IsFast = nullptr) const override; - EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, - unsigned SrcAlign, bool IsMemset, - bool ZeroMemset, - bool MemcpyStrSrc, + EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override; bool isMemOpUniform(const SDNode *N) const; bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; + static bool isNonGlobalAddrSpace(unsigned AS) { + return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS || + AS == AMDGPUAS::PRIVATE_ADDRESS; + } + + // FIXME: Missing constant_32bit static bool isFlatGlobalAddrSpace(unsigned AS) { return AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS || @@ -330,6 +344,9 @@ public: SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const override; + SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; + Register getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const override; @@ -351,8 +368,7 @@ public: MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override; - bool isFMADLegalForFAddFSub(const SelectionDAG &DAG, - const SDNode *N) const override; + bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; @@ -377,17 +393,29 @@ public: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; ConstraintType getConstraintType(StringRef Constraint) const override; + void LowerAsmOperandForConstraint(SDValue Op, + std::string &Constraint, + std::vector<SDValue> &Ops, + SelectionDAG &DAG) const override; + bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; + bool checkAsmConstraintVal(SDValue Op, + const std::string &Constraint, + uint64_t Val) const; + bool checkAsmConstraintValA(SDValue Op, + uint64_t Val, + unsigned MaxSize = 64) const; SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const; void finalizeLowering(MachineFunction &MF) const override; - void computeKnownBitsForFrameIndex(const SDValue Op, + void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, - const APInt &DemandedElts, - const SelectionDAG &DAG, - unsigned Depth = 0) const override; + const MachineFunction &MF) const override; + Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, + const MachineRegisterInfo &MRI, + unsigned Depth = 0) const override; bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; @@ -432,6 +460,13 @@ public: MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const; + void allocateSpecialInputVGPRsFixed(CCState &CCInfo, + MachineFunction &MF, + const SIRegisterInfo &TRI, + SIMachineFunctionInfo &Info) const; + + std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL, + Type *Ty) const; }; } // End namespace llvm |