diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
107 files changed, 22131 insertions, 16264 deletions
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index cee1954e369b1..1e7862c36ea09 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -116,6 +116,8 @@ class HexagonAsmParser : public MCTargetAsmParser { bool ParseDirectiveFalign(unsigned Size, SMLoc L); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseDirectiveSubsection(SMLoc L); bool ParseDirectiveComm(bool IsLocal, SMLoc L); bool RegisterMatchesArch(unsigned MatchNum) const; @@ -312,6 +314,8 @@ public: bool iss30_2Imm() const { return true; } bool iss29_3Imm() const { return true; } bool iss27_2Imm() const { return CheckImmRange(27, 2, true, true, false); } + bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); } + bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); } bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); } bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); } bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); } @@ -467,13 +471,16 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { LLVM_DEBUG(dbgs() << "--\n"); MCB.setLoc(IDLoc); + // Check the bundle for errors. const MCRegisterInfo *RI = getContext().getRegisterInfo(); - HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI); + MCSubtargetInfo const &STI = getSTI(); + + MCInst OrigBundle = MCB; + HexagonMCChecker Check(getContext(), MII, STI, MCB, *RI, true); - bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(), - getContext(), MCB, - &Check); + bool CheckOk = HexagonMCInstrInfo::canonicalizePacket( + MII, STI, getContext(), MCB, &Check, true); if (CheckOk) { if (HexagonMCInstrInfo::bundleSize(MCB) == 0) { @@ -482,15 +489,12 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { // Empty packets are valid yet aren't emitted return false; } - Out.EmitInstruction(MCB, getSTI()); - } else { - // If compounding and duplexing didn't reduce the size below - // 4 or less we have a packet that is too big. - if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) { - Error(IDLoc, "invalid instruction packet: out of slots"); - } + + assert(HexagonMCInstrInfo::isBundle(MCB)); + + Out.emitInstruction(MCB, STI); + } else return true; // Error - } return false; // No error } @@ -518,6 +522,8 @@ bool HexagonAsmParser::matchBundleOptions() { HexagonMCInstrInfo::setMemReorderDisabled(MCB); else return getParser().Error(IDLoc, MemNoShuffMsg); + } else if (Option.compare_lower("mem_no_order") == 0) { + // Nothing. } else return getParser().Error(IDLoc, llvm::Twine("'") + Option + "' is not a valid bundle option"); @@ -578,6 +584,7 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, case Match_MnemonicFail: return Error(IDLoc, "unrecognized instruction"); case Match_InvalidOperand: + LLVM_FALLTHROUGH; case Match_InvalidTiedOperand: SMLoc ErrorLoc = IDLoc; if (ErrorInfo != ~0U) { @@ -937,8 +944,8 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) { assert(Second.is(AsmToken::Colon)); StringRef Raw(String.data(), Third.getString().data() - String.data() + Third.getString().size()); - std::string Collapsed = Raw; - Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end()); + std::string Collapsed = std::string(Raw); + Collapsed.erase(llvm::remove_if(Collapsed, isSpace), Collapsed.end()); StringRef Whole = Collapsed; std::pair<StringRef, StringRef> DotSplit = Whole.split('.'); if (!matchRegister(DotSplit.first.lower())) @@ -959,6 +966,12 @@ bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} + +OperandMatchResultTy HexagonAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { MCAsmLexer &Lexer = getLexer(); StartLoc = getLexer().getLoc(); SmallVector<AsmToken, 5> Lookahead; @@ -983,8 +996,8 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, Again = (Contigious && Type) || (Workaround && Type); NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type)); } - std::string Collapsed = RawString; - Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end()); + std::string Collapsed = std::string(RawString); + Collapsed.erase(llvm::remove_if(Collapsed, isSpace), Collapsed.end()); StringRef FullString = Collapsed; std::pair<StringRef, StringRef> DotSplit = FullString.split('.'); unsigned DotReg = matchRegister(DotSplit.first.lower()); @@ -993,8 +1006,8 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = DotReg; EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } else { RegNo = DotReg; size_t First = RawString.find('.'); @@ -1002,28 +1015,26 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString)); EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } } std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':'); unsigned ColonReg = matchRegister(ColonSplit.first.lower()); if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { do { - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); - } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon)); + Lexer.UnLex(Lookahead.pop_back_val()); + } while (!Lookahead.empty() && !Lexer.is(AsmToken::Colon)); RegNo = ColonReg; EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } while (!Lookahead.empty()) { - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); + Lexer.UnLex(Lookahead.pop_back_val()); } - return true; + return MatchOperand_NoMatch; } bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) { @@ -1283,9 +1294,28 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc) { MCContext &Context = getParser().getContext(); const MCRegisterInfo *RI = getContext().getRegisterInfo(); - std::string r = "r"; - std::string v = "v"; - std::string Colon = ":"; + const std::string r = "r"; + const std::string v = "v"; + const std::string Colon = ":"; + using RegPairVals = std::pair<unsigned, unsigned>; + auto GetRegPair = [this, r](RegPairVals RegPair) { + const std::string R1 = r + utostr(RegPair.first); + const std::string R2 = r + utostr(RegPair.second); + + return std::make_pair(matchRegister(R1), matchRegister(R2)); + }; + auto GetScalarRegs = [RI, GetRegPair](unsigned RegPair) { + const unsigned Lower = RI->getEncodingValue(RegPair); + const RegPairVals RegPair_ = std::make_pair(Lower + 1, Lower); + + return GetRegPair(RegPair_); + }; + auto GetVecRegs = [GetRegPair](unsigned VecRegPair) { + const RegPairVals RegPair = + HexagonMCInstrInfo::GetVecRegPairIndices(VecRegPair); + + return GetRegPair(RegPair); + }; bool is32bit = false; // used to distinguish between CONST32 and CONST64 switch (Inst.getOpcode()) { @@ -1377,14 +1407,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" case Hexagon::A2_tfrp: { MCOperand &MO = Inst.getOperand(1); - unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); - std::string R1 = r + utostr(RegPairNum + 1); - StringRef Reg1(R1); - MO.setReg(matchRegister(Reg1)); - // Add a new operand for the second register in the pair. - std::string R2 = r + utostr(RegPairNum); - StringRef Reg2(R2); - Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); + const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg()); + MO.setReg(RegPair.first); + Inst.addOperand(MCOperand::createReg(RegPair.second)); Inst.setOpcode(Hexagon::A2_combinew); break; } @@ -1392,14 +1417,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::A2_tfrpt: case Hexagon::A2_tfrpf: { MCOperand &MO = Inst.getOperand(2); - unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); - std::string R1 = r + utostr(RegPairNum + 1); - StringRef Reg1(R1); - MO.setReg(matchRegister(Reg1)); - // Add a new operand for the second register in the pair. - std::string R2 = r + utostr(RegPairNum); - StringRef Reg2(R2); - Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); + const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg()); + MO.setReg(RegPair.first); + Inst.addOperand(MCOperand::createReg(RegPair.second)); Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) ? Hexagon::C2_ccombinewt : Hexagon::C2_ccombinewf); @@ -1408,14 +1428,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::A2_tfrptnew: case Hexagon::A2_tfrpfnew: { MCOperand &MO = Inst.getOperand(2); - unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); - std::string R1 = r + utostr(RegPairNum + 1); - StringRef Reg1(R1); - MO.setReg(matchRegister(Reg1)); - // Add a new operand for the second register in the pair. - std::string R2 = r + utostr(RegPairNum); - StringRef Reg2(R2); - Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); + const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg()); + MO.setReg(RegPair.first); + Inst.addOperand(MCOperand::createReg(RegPair.second)); Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) ? Hexagon::C2_ccombinewnewt : Hexagon::C2_ccombinewnewf); @@ -1425,12 +1440,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)" case Hexagon::V6_vassignp: { MCOperand &MO = Inst.getOperand(1); - unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); - std::string R1 = v + utostr(RegPairNum + 1); - MO.setReg(MatchRegisterName(R1)); - // Add a new operand for the second register in the pair. - std::string R2 = v + utostr(RegPairNum); - Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2))); + const std::pair<unsigned, unsigned> RegPair = GetVecRegs(MO.getReg()); + MO.setReg(RegPair.first); + Inst.addOperand(MCOperand::createReg(RegPair.second)); Inst.setOpcode(Hexagon::V6_vcombine); break; } @@ -1485,7 +1497,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MES->SwitchSection(mySection); unsigned byteSize = is32bit ? 4 : 8; - getStreamer().EmitCodeAlignment(byteSize, byteSize); + getStreamer().emitCodeAlignment(byteSize, byteSize); MCSymbol *Sym; @@ -1495,9 +1507,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, if (Absolute) { Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16)); if (Sym->isUndefined()) { - getStreamer().EmitLabel(Sym); - getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); - getStreamer().EmitIntValue(Value, byteSize); + getStreamer().emitLabel(Sym); + getStreamer().emitSymbolAttribute(Sym, MCSA_Global); + getStreamer().emitIntValue(Value, byteSize); } } else if (MO_1.isExpr()) { const char *StringStart = nullptr; @@ -1517,9 +1529,9 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, if (Sym->isUndefined()) { // case where symbol is not yet defined: emit symbol - getStreamer().EmitLabel(Sym); - getStreamer().EmitSymbolAttribute(Sym, MCSA_Local); - getStreamer().EmitValue(MO_1.getExpr(), 4); + getStreamer().emitLabel(Sym); + getStreamer().emitSymbolAttribute(Sym, MCSA_Local); + getStreamer().emitValue(MO_1.getExpr(), 4); } } else llvm_unreachable("unexpected type of machine operand!"); diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 8a07b991ff5aa..7ef23ef35a745 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -954,6 +954,9 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { ++It; } while (FallsThrough && It != End); + if (B.mayHaveInlineAsmBr()) + DefaultToAll = true; + if (!DefaultToAll) { // Need to add all CFG successors that lead to EH landing pads. // There won't be explicit branches to these blocks, but they must diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 7a90d585eb9a8..f3a87ef20a608 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -185,7 +185,10 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return Result; if (Size > HEXAGON_MAX_PACKET_SIZE) return MCDisassembler::Fail; - HexagonMCChecker Checker(getContext(), *MCII, STI, MI, + + const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI); + const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI; + HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, *getContext().getRegisterInfo(), false); if (!Checker.check()) return MCDisassembler::Fail; @@ -495,9 +498,13 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { unsigned Producer = HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); - if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) - Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; - else if (SubregBit) + + if (HexagonMCInstrInfo::IsVecRegPair(Producer)) { + const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); + const unsigned ProdPairIndex = + Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0; + Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0; + } else if (SubregBit) // Hexagon PRM 10.11 New-value operands // Nt[0] is reserved and should always be encoded as zero. return MCDisassembler::Fail; @@ -603,12 +610,16 @@ static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg HvxWRDecoderTable[] = { - Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, - Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, - Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, - Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; + Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, + Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, + Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7, + Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9, + Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12, + Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14, + Hexagon::W15, Hexagon::WR15, + }; - return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); + return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); } LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 26869391c7a31..2fadb0b5ddc48 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -23,6 +23,9 @@ include "llvm/Target/Target.td" // Hexagon Architectures include "HexagonDepArch.td" +def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily", + "TinyCore", "Hexagon Tiny Core">; + // Hexagon ISA Extensions def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true", "Hexagon ZReg extension instructions">; @@ -42,14 +45,25 @@ def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion", "Hexagon::ArchEnum::V66", "Hexagon HVX instructions", [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionZReg]>; +def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion", + "Hexagon::ArchEnum::V67", "Hexagon HVX instructions", + [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>; + def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>; def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>; +def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true", + "Hexagon Audio extension instructions">; + +def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true", + "Use compound instructions">; def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true", "Support for instruction packets">; +def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true", + "Support features deprecated in v65">; def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", @@ -64,6 +78,8 @@ def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true", "Allow GP-relative addressing of global variables">; def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", "Enable generation of duplex instruction">; +def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true", + "Use unsafe FP math">; def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", "true", "Reserve register R19">; def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim", @@ -76,21 +92,36 @@ def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim", def UseMEMOPS : Predicate<"HST->useMemops()">; def UseHVX64B : Predicate<"HST->useHVX64BOps()">, - AssemblerPredicate<"ExtensionHVX64B">; + AssemblerPredicate<(all_of ExtensionHVX64B)>; def UseHVX128B : Predicate<"HST->useHVX128BOps()">, - AssemblerPredicate<"ExtensionHVX128B">; + AssemblerPredicate<(all_of ExtensionHVX128B)>; def UseHVX : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV60">; -def UseHVXV60 : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV60">; -def UseHVXV62 : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV62">; -def UseHVXV65 : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV65">; -def UseHVXV66 : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV66">; + AssemblerPredicate<(all_of ExtensionHVXV60)>; +def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV60)>; +def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV62)>; +def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV65)>; +def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV66)>; +def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV67)>; +def UseAudio : Predicate<"HST->useAudioOps()">, + AssemblerPredicate<(all_of ExtensionAudio)>; def UseZReg : Predicate<"HST->useZRegOps()">, - AssemblerPredicate<"ExtensionZReg">; + AssemblerPredicate<(all_of ExtensionZReg)>; +def UseCompound : Predicate<"HST->useCompound()">; +def HasPreV65 : Predicate<"HST->hasPreV65()">, + AssemblerPredicate<(all_of FeaturePreV65)>; +def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">, + AssemblerPredicate<(all_of FeatureMemNoShuf)>; +def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">; +def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||" + "MF->getFunction().hasOptSize()"> { + let RecomputePerFunction = 1; +} +def UseSmallData : Predicate<"HST->useSmallData()">; def Hvx64: HwMode<"+hvx-length64b">; def Hvx128: HwMode<"+hvx-length128b">; @@ -99,6 +130,7 @@ def Hvx128: HwMode<"+hvx-length128b">; // Classes used for relation maps. //===----------------------------------------------------------------------===// +// The classes below should remain in hierarchical order... class ImmRegShl; // ImmRegRel - Filter class used to relate instructions having reg-reg form // with their reg-imm counterparts. @@ -106,17 +138,14 @@ class ImmRegRel; // PredRel - Filter class used to relate non-predicated instructions with their // predicated forms. class PredRel; -// PredNewRel - Filter class used to relate predicated instructions with their -// predicate-new forms. class PredNewRel: PredRel; // NewValueRel - Filter class used to relate regular store instructions with // their new-value store form. class NewValueRel: PredNewRel; -// NewValueRel - Filter class used to relate load/store instructions having -// different addressing modes with each other. class AddrModeRel: NewValueRel; class PostInc_BaseImm; class IntrinsicsRel; +// ... through here. //===----------------------------------------------------------------------===// // Generate mapping table to relate non-predicate instructions with their @@ -335,31 +364,43 @@ class Proc<string Name, SchedMachineModel Model, def : Proc<"generic", HexagonModelV60, [ArchV5, ArchV55, ArchV60, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv5", HexagonModelV5, [ArchV5, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv55", HexagonModelV55, [ArchV5, ArchV55, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv60", HexagonModelV60, [ArchV5, ArchV55, ArchV60, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv62", HexagonModelV62, [ArchV5, ArchV55, ArchV60, ArchV62, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv65", HexagonModelV65, [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, - FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, - FeatureNVS, FeaturePackets, FeatureSmallData]>; + FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv66", HexagonModelV66, [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, - FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, + FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; +def : Proc<"hexagonv67", HexagonModelV67, + [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, + FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; +// Need to update the correct features for tiny core. +// Disable NewValueJumps since the packetizer is unable to handle a packet with +// a new value jump and another SLOT0 instruction. +def : Proc<"hexagonv67t", HexagonModelV67T, + [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, + ProcTinyCore, ExtensionAudio, + FeatureCompound, FeatureMemNoShuf, FeatureMemops, FeatureNVS, FeaturePackets, FeatureSmallData]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonArch.h b/llvm/lib/Target/Hexagon/HexagonArch.h new file mode 100644 index 0000000000000..e5d528390c510 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonArch.h @@ -0,0 +1,37 @@ +//===- HexagonArch.h ------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/StringRef.h" +#include "HexagonDepArch.h" +#include <algorithm> + +namespace llvm { +namespace Hexagon { + +template <class ArchCont, typename Val> +bool ValidArch(ArchCont const &ArchList, Val HexArch) { + return std::any_of(std::begin(ArchList), std::end(ArchList), + [HexArch](Val V) { return V == HexArch; }); +} + +template <class ArchCont, typename Val> +llvm::Optional<ArchEnum> GetCpu(ArchCont const &ArchList, Val CPUString) { + llvm::Optional<ArchEnum> Res; + auto Entry = ArchList.find(CPUString); + if (Entry != ArchList.end()) + Res = Entry->second; + return Res; +} +} // namespace Hexagon +} // namespace llvm +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 30fdde70d01af..f3017d02995ee 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -206,10 +206,10 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI, Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName)); if (Sym->isUndefined()) { - OutStreamer.EmitLabel(Sym); - OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global); - OutStreamer.EmitIntValue(Value, AlignSize); - OutStreamer.EmitCodeAlignment(AlignSize); + OutStreamer.emitLabel(Sym); + OutStreamer.emitSymbolAttribute(Sym, MCSA_Global); + OutStreamer.emitIntValue(Value, AlignSize); + OutStreamer.emitCodeAlignment(AlignSize); } } else { assert(Imm.isExpr() && "Expected expression and found none"); @@ -234,10 +234,10 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI, OutStreamer.SwitchSection(Section); Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName)); if (Sym->isUndefined()) { - OutStreamer.EmitLabel(Sym); - OutStreamer.EmitSymbolAttribute(Sym, MCSA_Local); - OutStreamer.EmitValue(Imm.getExpr(), AlignSize); - OutStreamer.EmitCodeAlignment(AlignSize); + OutStreamer.emitLabel(Sym); + OutStreamer.emitSymbolAttribute(Sym, MCSA_Local); + OutStreamer.emitValue(Imm.getExpr(), AlignSize); + OutStreamer.emitCodeAlignment(AlignSize); } } return Sym; @@ -740,7 +740,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, } /// Print out a single Hexagon MI to the current output stream. -void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void HexagonAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst MCB; MCB.setOpcode(Hexagon::BUNDLE); MCB.addOperand(MCOperand::createImm(0)); @@ -768,7 +768,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { assert(Ok); (void)Ok; if (HexagonMCInstrInfo::bundleSize(MCB) == 0) return; - OutStreamer->EmitInstruction(MCB, getSubtargetInfo()); + OutStreamer->emitInstruction(MCB, getSubtargetInfo()); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmPrinter() { diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h index 6c4b664e83f52..3932def878544 100755 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -46,7 +46,7 @@ class TargetMachine; bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 799b85ed48b4c..49edb0d994928 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1433,10 +1433,16 @@ unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, .addImm(int32_t(Lo)); return Reg; } + MachineFunction *MF = B.getParent(); + auto &HST = MF->getSubtarget<HexagonSubtarget>(); - BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg) - .addImm(C); - return Reg; + // Disable CONST64 for tiny core since it takes a LD resource. + if (!HST.isTinyCore() || + MF->getFunction().hasOptSize()) { + BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg) + .addImm(C); + return Reg; + } } if (RC == &Hexagon::PredRegsRegClass) { diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index ebd060ce503ef..1e4030b84bc18 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -330,7 +330,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, case PS_fi: { int FI = op(1).getIndex(); int Off = op(2).getImm(); - unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off); + unsigned A = MFI.getObjectAlign(FI).value() + std::abs(Off); unsigned L = countTrailingZeros(A); RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); RC.fill(0, L, BT::BitValue::Zero); diff --git a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp index 08f7408068798..6891455631a80 100644 --- a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -105,7 +105,7 @@ void HexagonBranchRelaxation::computeOffset(MachineFunction &MF, // offset of the current instruction from the start. unsigned InstOffset = 0; for (auto &B : MF) { - if (B.getAlignment() != Align::None()) { + if (B.getAlignment() != Align(1)) { // Although we don't know the exact layout of the final code, we need // to account for alignment padding somehow. This heuristic pads each // aligned basic block according to the alignment value. diff --git a/llvm/lib/Target/Hexagon/HexagonCallingConv.td b/llvm/lib/Target/Hexagon/HexagonCallingConv.td index 5c31a81a1e871..93e17e608dd10 100644 --- a/llvm/lib/Target/Hexagon/HexagonCallingConv.td +++ b/llvm/lib/Target/Hexagon/HexagonCallingConv.td @@ -18,7 +18,7 @@ def CC_HexagonStack: CallingConv<[ CCAssignToStack<8,8>> ]>; -def CC_Hexagon: CallingConv<[ +def CC_Hexagon_Legacy: CallingConv<[ CCIfType<[i1,i8,i16], CCPromoteToType<i32>>, CCIfType<[f32], @@ -48,6 +48,36 @@ def CC_Hexagon: CallingConv<[ CCDelegateTo<CC_HexagonStack> ]>; +def CC_Hexagon: CallingConv<[ + CCIfType<[i1,i8,i16], + CCPromoteToType<i32>>, + CCIfType<[f32], + CCBitConvertToType<i32>>, + CCIfType<[f64], + CCBitConvertToType<i64>>, + + CCIfByVal< + CCPassByVal<8,1>>, + CCIfArgIsVarArg< + CCDelegateTo<CC_HexagonStack>>, + + // Pass split values in pairs, allocate odd register if necessary. + CCIfType<[i32], + CCIfSplit< + CCCustom<"CC_SkipOdd">>>, + + CCIfType<[i32,v2i16,v4i8], + CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>, + // Make sure to allocate any skipped 32-bit register, so it does not get + // allocated to a subsequent 32-bit value. + CCIfType<[i64,v2i32,v4i16,v8i8], + CCCustom<"CC_SkipOdd">>, + CCIfType<[i64,v2i32,v4i16,v8i8], + CCAssignToReg<[D0,D1,D2]>>, + + CCDelegateTo<CC_HexagonStack> +]>; + def RetCC_Hexagon: CallingConv<[ CCIfType<[i1,i8,i16], CCPromoteToType<i32>>, diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index 6d2aadb066cf9..6a5192c866cc9 100644 --- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -204,17 +204,7 @@ namespace { Type *next_type(Type *Ty, Value *Idx) { if (auto *PTy = dyn_cast<PointerType>(Ty)) return PTy->getElementType(); - // Advance the type. - if (!Ty->isStructTy()) { - Type *NexTy = cast<SequentialType>(Ty)->getElementType(); - return NexTy; - } - // Otherwise it is a struct type. - ConstantInt *CI = dyn_cast<ConstantInt>(Idx); - assert(CI && "Struct type with non-constant index"); - int64_t i = CI->getValue().getSExtValue(); - Type *NextTy = cast<StructType>(Ty)->getElementType(i); - return NextTy; + return GetElementPtrInst::getTypeAtIndex(Ty, Idx); } raw_ostream &operator<< (raw_ostream &OS, const GepNode &GN) { @@ -1302,7 +1292,8 @@ bool HexagonCommonGEP::runOnFunction(Function &F) { #ifdef EXPENSIVE_CHECKS // Run this only when expensive checks are enabled. - verifyFunction(F); + if (verifyFunction(F, &dbgs())) + report_fatal_error("Broken function"); #endif return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index aa9a715718bf7..05b95d8b7314b 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -379,6 +379,7 @@ namespace { using AssignmentMap = std::map<ExtenderInit, IndexList>; using LocDefList = std::vector<std::pair<Loc, IndexList>>; + const HexagonSubtarget *HST = nullptr; const HexagonInstrInfo *HII = nullptr; const HexagonRegisterInfo *HRI = nullptr; MachineDominatorTree *MDT = nullptr; @@ -1562,13 +1563,31 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) { .add(ExtOp); } } else { - unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri - : Hexagon::S4_addi_asl_ri; - // DefR = add(##EV,asl(Rb,S)) - InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) - .add(ExtOp) - .add(MachineOperand(Ex.Rs)) - .addImm(Ex.S); + if (HST->useCompound()) { + unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri + : Hexagon::S4_addi_asl_ri; + // DefR = add(##EV,asl(Rb,S)) + InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) + .add(ExtOp) + .add(MachineOperand(Ex.Rs)) + .addImm(Ex.S); + } else { + // No compounds are available. It is not clear whether we should + // even process such extenders where the initializer cannot be + // a single instruction, but do it for now. + unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); + BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR) + .add(MachineOperand(Ex.Rs)) + .addImm(Ex.S); + if (Ex.Neg) + InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) + .add(ExtOp) + .add(MachineOperand(Register(TmpR, 0))); + else + InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) + .add(MachineOperand(Register(TmpR, 0))) + .add(ExtOp); + } } } @@ -1952,8 +1971,9 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { } LLVM_DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr)); - HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); - HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); + HST = &MF.getSubtarget<HexagonSubtarget>(); + HII = HST->getInstrInfo(); + HRI = HST->getRegisterInfo(); MDT = &getAnalysis<MachineDominatorTree>(); MRI = &MF.getRegInfo(); AssignmentMap IMap; diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 5b61d1084e08a..77578378b0588 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -754,6 +754,9 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { ++It; } + if (B.mayHaveInlineAsmBr()) + EvalOk = false; + if (EvalOk) { // Need to add all CFG successors that lead to EH landing pads. // There won't be explicit branches to these blocks, but they must @@ -810,8 +813,12 @@ void MachineConstPropagator::visitUsesOf(unsigned Reg) { bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, SetVector<const MachineBasicBlock*> &Targets) { + Targets.clear(); + MachineBasicBlock::const_iterator FirstBr = MB->end(); for (const MachineInstr &MI : *MB) { + if (MI.getOpcode() == TargetOpcode::INLINEASM_BR) + return false; if (MI.isDebugInstr()) continue; if (MI.isBranch()) { @@ -820,7 +827,6 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, } } - Targets.clear(); MachineBasicBlock::const_iterator End = MB->end(); bool DoNext = true; @@ -2836,6 +2842,9 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, if (MI.isCopy()) return false; + MachineFunction *MF = MI.getParent()->getParent(); + auto &HST = MF->getSubtarget<HexagonSubtarget>(); + // Collect all virtual register-def operands. SmallVector<unsigned,2> DefRegs; for (const MachineOperand &MO : MI.operands()) { @@ -2923,11 +2932,13 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, NewMI = BuildMI(B, At, DL, *NewD, NewR) .addImm(Hi) .addImm(Lo); - } else { + } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) { + // Disable CONST64 for tiny core since it takes a LD resource. NewD = &HII.get(Hexagon::CONST64); NewMI = BuildMI(B, At, DL, *NewD, NewR) .addImm(V); - } + } else + return false; } } (void)NewMI; diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 394a329ac4476..587527d8c32cb 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -21,7 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/PassSupport.h" +#include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -212,7 +212,7 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI, // There is a combine of two constant extended values into CONST64, // provided both constants are true immediates. if (isGreaterThanNBitTFRI<16>(HighRegInst) && - isGreaterThanNBitTFRI<16>(LowRegInst)) + isGreaterThanNBitTFRI<16>(LowRegInst) && !IsConst64Disabled) return (HighRegInst.getOperand(1).isImm() && LowRegInst.getOperand(1).isImm()); @@ -279,11 +279,11 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // A reverse_iterator instantiated like below starts before I2, and I1 // respectively. // Look at instructions I in between I2 and (excluding) I1. - MachineBasicBlock::reverse_iterator I(I2), - End = --(MachineBasicBlock::reverse_iterator(I1)); + MachineBasicBlock::reverse_iterator I = ++I2.getIterator().getReverse(); + MachineBasicBlock::reverse_iterator End = I1.getIterator().getReverse(); // At 03 we got better results (dhrystone!) by being more conservative. if (!ShouldCombineAggressively) - End = MachineBasicBlock::reverse_iterator(I1); + End = ++I1.getIterator().getReverse(); // If I2 kills its operand and we move I2 over an instruction that also // uses I2's use reg we need to modify that (first) instruction to now kill // this reg. @@ -477,6 +477,10 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { ShouldCombineAggressively = MF.getTarget().getOptLevel() <= CodeGenOpt::Default; + // Disable CONST64 for tiny core since it takes a LD resource. + if (!OptForSize && ST->isTinyCore()) + IsConst64Disabled = true; + // Traverse basic blocks. for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE; ++BI) { diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h index 529be7ef0ac74..45b4cf042443a 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.h +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -5,15 +5,44 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -#ifndef HEXAGON_DEP_ARCH_H -#define HEXAGON_DEP_ARCH_H +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/StringRef.h" +#include <map> + namespace llvm { namespace Hexagon { -enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66 }; +enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; + +static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67}; +static constexpr ArrayRef<unsigned> ArchValsNum(ArchValsNumArray); + +static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67" }; +static constexpr ArrayRef<StringLiteral> ArchValsText(ArchValsTextArray); + +static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t" }; +static constexpr ArrayRef<StringLiteral> CpuValsText(CpuValsTextArray); + +static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t" }; +static constexpr ArrayRef<StringLiteral> CpuNickText(CpuNickTextArray); + +static const std::map<std::string, ArchEnum> CpuTable{ + {"generic", Hexagon::ArchEnum::V60}, + {"hexagonv5", Hexagon::ArchEnum::V5}, + {"hexagonv55", Hexagon::ArchEnum::V55}, + {"hexagonv60", Hexagon::ArchEnum::V60}, + {"hexagonv62", Hexagon::ArchEnum::V62}, + {"hexagonv65", Hexagon::ArchEnum::V65}, + {"hexagonv66", Hexagon::ArchEnum::V66}, + {"hexagonv67", Hexagon::ArchEnum::V67}, + {"hexagonv67t", Hexagon::ArchEnum::V67}, +}; } // namespace Hexagon } // namespace llvm; -#endif // HEXAGON_DEP_ARCH_H +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.td b/llvm/lib/Target/Hexagon/HexagonDepArch.td index 115cf2383a7af..9374055eae7db 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.td +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -5,18 +5,20 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V66 architecture">; -def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<"ArchV66">; -def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">; -def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<"ArchV65">; -def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">; -def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<"ArchV62">; -def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">; -def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">; -def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">; -def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">; def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">; -def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<"ArchV5">; +def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<(all_of ArchV5)>; +def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">; +def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<(all_of ArchV55)>; +def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">; +def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<(all_of ArchV60)>; +def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">; +def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<(all_of ArchV62)>; +def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">; +def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<(all_of ArchV65)>; +def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V66 architecture">; +def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<(all_of ArchV66)>; +def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V67 architecture">; +def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<(all_of ArchV67)>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc index 10068abce7ec8..ce7aa02e3e061 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc +++ b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// // clang-format off @@ -15,39 +15,44 @@ #pragma clang diagnostic ignored "-Wunused-function" #endif +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<8>(MI, tmp, Decoder); + return MCDisassembler::Success; +} static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { signedDecoder<4>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<14>(MI, tmp, Decoder); + signedDecoder<12>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<8>(MI, tmp, Decoder); + signedDecoder<5>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<7>(MI, tmp, Decoder); + signedDecoder<13>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<12>(MI, tmp, Decoder); + signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<3>(MI, tmp, Decoder); + signedDecoder<14>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<13>(MI, tmp, Decoder); + signedDecoder<7>(MI, tmp, Decoder); return MCDisassembler::Success; } static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, @@ -60,14 +65,9 @@ static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, signedDecoder<9>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { - signedDecoder<5>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); + signedDecoder<3>(MI, tmp, Decoder); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td b/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td index fefbbfd3f1ac1..1547e8f769b17 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// def tc_04da405a : InstrItinClass; @@ -2554,3 +2554,494 @@ class DepHVXItinV66 { [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> ]; } + +class DepHVXItinV67 { + list<InstrItinData> DepHVXItinV67_list = [ + InstrItinData <tc_04da405a, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_05058f6f, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_05ac6f98, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_05ca8cfd, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_08a4f1b6, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_0b04c6c7, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_131f1c81, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_1381a97c, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [], + []>, + + InstrItinData <tc_15fdf750, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_16ff9ef8, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7], + [Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_1ad8a370, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2], + [HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], + [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2], + [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_309dbb4f, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_3904b926, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7], + [HVX_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3ce09744, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_46d6c3e0, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_51d0ecc3, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_52447ecc, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_540c3da3, /*SLOT0,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], + [Hex_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_54a0dc47, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_561aaa58, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_56c4f9fe, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_56e64202, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_58d21193, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_5bf8afbb, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_649072c2, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_660769f1, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_663c80a7, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_6e7fa133, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_71646d06, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_7177e272, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_718b5c53, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + + InstrItinData <tc_7273323b, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_7417e785, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_767c4e9d, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [3, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_7e6a3e89, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_8772086c, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_87adc037, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_8e420e4d, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_90bcc1db, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_946013d8, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_9d1dc972, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_9f363d21, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_a02a10a8, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_ZW]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ab23f776, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_abe8c3b2, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac4046bc, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_af25efd9, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7], + [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_b091f1c6, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_b28e51aa, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_b4416217, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_b9db8205, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c0749f3c, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c127de3a, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_c4edf264, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_c5dba46e, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_c7039829, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_cd94bfe0, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_d8287c14, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_db5555f3, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_ZW]>], [2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [3], + [HVX_FWD]>, + + InstrItinData <tc_e675c45a, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e699ae41, /*SLOT01,ZW*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_ZW]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_e99d4c2e, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_f1de44ef, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_f21e8abb, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_fd7610da, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + ]; +} diff --git a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td index 34da0be02d192..fecccb250198d 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td +++ b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td @@ -5,3792 +5,7079 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -def tc_002cb246 : InstrItinClass; -def tc_0371abea : InstrItinClass; -def tc_05c070ec : InstrItinClass; -def tc_05d3a09b : InstrItinClass; -def tc_0663f615 : InstrItinClass; -def tc_096199d3 : InstrItinClass; -def tc_0a705168 : InstrItinClass; -def tc_0ae0825c : InstrItinClass; -def tc_0b2be201 : InstrItinClass; -def tc_0d8f5752 : InstrItinClass; -def tc_13bfbcf9 : InstrItinClass; -def tc_14b272fa : InstrItinClass; -def tc_14b5c689 : InstrItinClass; -def tc_15aa71c5 : InstrItinClass; -def tc_174516e8 : InstrItinClass; -def tc_17e0d2cd : InstrItinClass; -def tc_1a2fd869 : InstrItinClass; -def tc_1ad90acd : InstrItinClass; -def tc_1ae57e39 : InstrItinClass; -def tc_1b6f7cec : InstrItinClass; -def tc_1c4528a2 : InstrItinClass; -def tc_1c80410a : InstrItinClass; -def tc_1d81e60e : InstrItinClass; -def tc_1fc97744 : InstrItinClass; -def tc_20cdee80 : InstrItinClass; -def tc_2332b92e : InstrItinClass; -def tc_24b66c99 : InstrItinClass; -def tc_25a78932 : InstrItinClass; -def tc_2b8da4c2 : InstrItinClass; -def tc_2eabeebe : InstrItinClass; -def tc_2f7c551d : InstrItinClass; -def tc_2ff964b4 : InstrItinClass; -def tc_30b9bb4a : InstrItinClass; -def tc_32779c6f : InstrItinClass; -def tc_36153880 : InstrItinClass; -def tc_362c6592 : InstrItinClass; -def tc_3962fa26 : InstrItinClass; -def tc_39dfefe8 : InstrItinClass; -def tc_3a867367 : InstrItinClass; -def tc_3b470976 : InstrItinClass; -def tc_3b5b7ef9 : InstrItinClass; -def tc_3bd75825 : InstrItinClass; -def tc_3c76b0ff : InstrItinClass; -def tc_3d495a39 : InstrItinClass; -def tc_40116ca8 : InstrItinClass; -def tc_434c8e1e : InstrItinClass; -def tc_4414d8b1 : InstrItinClass; -def tc_44d3da28 : InstrItinClass; -def tc_4560740b : InstrItinClass; -def tc_4837eefb : InstrItinClass; -def tc_49a8207d : InstrItinClass; -def tc_4ae7b58b : InstrItinClass; -def tc_4b68bce4 : InstrItinClass; -def tc_4c5ba658 : InstrItinClass; -def tc_4d5fa3a1 : InstrItinClass; -def tc_53559e35 : InstrItinClass; -def tc_56336eb0 : InstrItinClass; -def tc_56f114f4 : InstrItinClass; -def tc_57890846 : InstrItinClass; -def tc_5a2711e5 : InstrItinClass; -def tc_5abb5e3f : InstrItinClass; -def tc_5aee39f7 : InstrItinClass; -def tc_5b54b33f : InstrItinClass; -def tc_5b7c0967 : InstrItinClass; -def tc_5bf126a6 : InstrItinClass; -def tc_5d7f5414 : InstrItinClass; -def tc_5ef37dc4 : InstrItinClass; -def tc_6132ba3d : InstrItinClass; -def tc_61830035 : InstrItinClass; -def tc_640086b5 : InstrItinClass; -def tc_643b4717 : InstrItinClass; -def tc_67435e81 : InstrItinClass; -def tc_675e4897 : InstrItinClass; -def tc_679309b8 : InstrItinClass; -def tc_6b25e783 : InstrItinClass; -def tc_703e822c : InstrItinClass; -def tc_7186d325 : InstrItinClass; -def tc_7646c131 : InstrItinClass; -def tc_76851da1 : InstrItinClass; -def tc_779080bf : InstrItinClass; -def tc_784490da : InstrItinClass; -def tc_785f65a7 : InstrItinClass; -def tc_7a91e76a : InstrItinClass; -def tc_838b34ea : InstrItinClass; -def tc_85c9c08f : InstrItinClass; -def tc_85d5d03f : InstrItinClass; -def tc_862b3e70 : InstrItinClass; -def tc_88b4f13d : InstrItinClass; -def tc_89e94ad3 : InstrItinClass; -def tc_8b121f4a : InstrItinClass; -def tc_8b3e402a : InstrItinClass; -def tc_8c945be0 : InstrItinClass; -def tc_8c99de45 : InstrItinClass; -def tc_8d9d0154 : InstrItinClass; -def tc_8fb7ab1b : InstrItinClass; -def tc_9461ff31 : InstrItinClass; -def tc_946df596 : InstrItinClass; -def tc_9ad9998f : InstrItinClass; -def tc_9bfd761f : InstrItinClass; -def tc_9c3ecd83 : InstrItinClass; -def tc_9ca930f7 : InstrItinClass; -def tc_9da59d12 : InstrItinClass; -def tc_9debc299 : InstrItinClass; -def tc_9e313203 : InstrItinClass; -def tc_9fc3dae0 : InstrItinClass; -def tc_a1123dda : InstrItinClass; -def tc_a1c00888 : InstrItinClass; -def tc_a58fd5cc : InstrItinClass; -def tc_a5d4aeec : InstrItinClass; -def tc_a6b1eca9 : InstrItinClass; -def tc_a813cf9a : InstrItinClass; -def tc_a9d88b22 : InstrItinClass; -def tc_ae53734a : InstrItinClass; -def tc_b31c2e97 : InstrItinClass; -def tc_b343892a : InstrItinClass; -def tc_b43e7930 : InstrItinClass; -def tc_b4407292 : InstrItinClass; -def tc_b44ecf75 : InstrItinClass; -def tc_b4b5c03a : InstrItinClass; -def tc_b51dc29a : InstrItinClass; -def tc_b83e6d73 : InstrItinClass; -def tc_b857bf4e : InstrItinClass; -def tc_b8bffe55 : InstrItinClass; -def tc_b90a29b1 : InstrItinClass; -def tc_b9272d6c : InstrItinClass; -def tc_b9e09e03 : InstrItinClass; -def tc_bab0eed9 : InstrItinClass; -def tc_bafaade3 : InstrItinClass; -def tc_bcf98408 : InstrItinClass; -def tc_bd8382d1 : InstrItinClass; -def tc_bdceeac1 : InstrItinClass; -def tc_be9602ff : InstrItinClass; -def tc_bf061958 : InstrItinClass; -def tc_bfec0f01 : InstrItinClass; -def tc_c4db48cb : InstrItinClass; -def tc_c4f596e3 : InstrItinClass; -def tc_c79a189f : InstrItinClass; -def tc_c8ce0b5c : InstrItinClass; -def tc_cd374165 : InstrItinClass; -def tc_cf8126ae : InstrItinClass; -def tc_cfd8378a : InstrItinClass; -def tc_d08ee0f4 : InstrItinClass; -def tc_d1aa9eaa : InstrItinClass; -def tc_d2e63d61 : InstrItinClass; -def tc_d5b7b0c1 : InstrItinClass; -def tc_d5c0729a : InstrItinClass; -def tc_d63f638c : InstrItinClass; -def tc_d65dbf51 : InstrItinClass; -def tc_d773585a : InstrItinClass; -def tc_d9d43ecb : InstrItinClass; -def tc_da4a37ed : InstrItinClass; -def tc_da97ee82 : InstrItinClass; -def tc_db2bce9c : InstrItinClass; -def tc_de4df740 : InstrItinClass; -def tc_de554571 : InstrItinClass; -def tc_df3319ed : InstrItinClass; -def tc_e06f432a : InstrItinClass; -def tc_e4a7f9f0 : InstrItinClass; -def tc_e4b3cb20 : InstrItinClass; -def tc_e78647bd : InstrItinClass; -def tc_e86aa961 : InstrItinClass; -def tc_e93a3d71 : InstrItinClass; -def tc_e95795ec : InstrItinClass; -def tc_e9f3243f : InstrItinClass; -def tc_f429765c : InstrItinClass; -def tc_f675fee8 : InstrItinClass; -def tc_f8e23f0b : InstrItinClass; -def tc_f9058dd7 : InstrItinClass; -def tc_fc3999b4 : InstrItinClass; -def tc_fcc3ddf9 : InstrItinClass; -def tc_fe211424 : InstrItinClass; +def tc_011e0e9d : InstrItinClass; +def tc_01d44cb2 : InstrItinClass; +def tc_01e1be3b : InstrItinClass; +def tc_02fe1c65 : InstrItinClass; +def tc_0655b949 : InstrItinClass; +def tc_075c8dd8 : InstrItinClass; +def tc_0a195f2c : InstrItinClass; +def tc_0a6c20ae : InstrItinClass; +def tc_0ba0d5da : InstrItinClass; +def tc_0dfac0a7 : InstrItinClass; +def tc_0fac1eb8 : InstrItinClass; +def tc_1044324a : InstrItinClass; +def tc_10b884b7 : InstrItinClass; +def tc_112d30d6 : InstrItinClass; +def tc_1242dc2a : InstrItinClass; +def tc_1248597c : InstrItinClass; +def tc_14ab4f41 : InstrItinClass; +def tc_151bf368 : InstrItinClass; +def tc_158aa3f7 : InstrItinClass; +def tc_197dce51 : InstrItinClass; +def tc_1981450d : InstrItinClass; +def tc_1b8138fc : InstrItinClass; +def tc_1c2c7a4a : InstrItinClass; +def tc_1c7522a8 : InstrItinClass; +def tc_1d41f8b7 : InstrItinClass; +def tc_1e7875f0 : InstrItinClass; +def tc_1fcb8495 : InstrItinClass; +def tc_1fe4ab69 : InstrItinClass; +def tc_20131976 : InstrItinClass; +def tc_2237d952 : InstrItinClass; +def tc_234f8560 : InstrItinClass; +def tc_23708a21 : InstrItinClass; +def tc_24e109c7 : InstrItinClass; +def tc_24f426ab : InstrItinClass; +def tc_27106296 : InstrItinClass; +def tc_280f7fe1 : InstrItinClass; +def tc_28e55c6f : InstrItinClass; +def tc_2c13e7f5 : InstrItinClass; +def tc_2c3e17fc : InstrItinClass; +def tc_2f573607 : InstrItinClass; +def tc_2f669c77 : InstrItinClass; +def tc_362b0be2 : InstrItinClass; +def tc_38382228 : InstrItinClass; +def tc_388f9897 : InstrItinClass; +def tc_38e0bae9 : InstrItinClass; +def tc_3d14a17b : InstrItinClass; +def tc_3edca78f : InstrItinClass; +def tc_3fbf1042 : InstrItinClass; +def tc_407e96f9 : InstrItinClass; +def tc_40d64c94 : InstrItinClass; +def tc_4222e6bf : InstrItinClass; +def tc_42ff66ba : InstrItinClass; +def tc_442395f3 : InstrItinClass; +def tc_449acf79 : InstrItinClass; +def tc_44d5a428 : InstrItinClass; +def tc_44fffc58 : InstrItinClass; +def tc_45791fb8 : InstrItinClass; +def tc_45f9d1be : InstrItinClass; +def tc_49fdfd4b : InstrItinClass; +def tc_4a55d03c : InstrItinClass; +def tc_4abdbdc6 : InstrItinClass; +def tc_4ac61d92 : InstrItinClass; +def tc_4c1520ae : InstrItinClass; +def tc_503ce0f3 : InstrItinClass; +def tc_53c851ab : InstrItinClass; +def tc_5502c366 : InstrItinClass; +def tc_55255f2b : InstrItinClass; +def tc_556f6577 : InstrItinClass; +def tc_55a9a350 : InstrItinClass; +def tc_55b33fda : InstrItinClass; +def tc_56a124a7 : InstrItinClass; +def tc_57a55b54 : InstrItinClass; +def tc_5944960d : InstrItinClass; +def tc_59a7822c : InstrItinClass; +def tc_5a4b5e58 : InstrItinClass; +def tc_5b347363 : InstrItinClass; +def tc_5ceb2f9e : InstrItinClass; +def tc_5d636bc7 : InstrItinClass; +def tc_5da50c4b : InstrItinClass; +def tc_5deb5e47 : InstrItinClass; +def tc_5e4cf0e8 : InstrItinClass; +def tc_5f2afaf7 : InstrItinClass; +def tc_60e324ff : InstrItinClass; +def tc_63567288 : InstrItinClass; +def tc_64b00d8a : InstrItinClass; +def tc_651cbe02 : InstrItinClass; +def tc_65279839 : InstrItinClass; +def tc_65cbd974 : InstrItinClass; +def tc_69bfb303 : InstrItinClass; +def tc_6ae3426b : InstrItinClass; +def tc_6d861a95 : InstrItinClass; +def tc_6e20402a : InstrItinClass; +def tc_6f42bc60 : InstrItinClass; +def tc_6fb32599 : InstrItinClass; +def tc_6fc5dbea : InstrItinClass; +def tc_711c805f : InstrItinClass; +def tc_713b66bf : InstrItinClass; +def tc_7401744f : InstrItinClass; +def tc_7476d766 : InstrItinClass; +def tc_74a42bda : InstrItinClass; +def tc_76bb5435 : InstrItinClass; +def tc_77f94a5e : InstrItinClass; +def tc_788b1d09 : InstrItinClass; +def tc_7b9187d3 : InstrItinClass; +def tc_7c31e19a : InstrItinClass; +def tc_7c6d32e4 : InstrItinClass; +def tc_7dc63b5c : InstrItinClass; +def tc_7dcd9d89 : InstrItinClass; +def tc_7f7f45f5 : InstrItinClass; +def tc_7f8ae742 : InstrItinClass; +def tc_8035e91f : InstrItinClass; +def tc_822c3c68 : InstrItinClass; +def tc_829d8a86 : InstrItinClass; +def tc_838c4d7a : InstrItinClass; +def tc_84a7500d : InstrItinClass; +def tc_86173609 : InstrItinClass; +def tc_887d1bb7 : InstrItinClass; +def tc_8a6d0d94 : InstrItinClass; +def tc_8a825db2 : InstrItinClass; +def tc_8b5bd4f5 : InstrItinClass; +def tc_8e82e8ca : InstrItinClass; +def tc_9124c04f : InstrItinClass; +def tc_9165014d : InstrItinClass; +def tc_92240447 : InstrItinClass; +def tc_934753bb : InstrItinClass; +def tc_937dd41c : InstrItinClass; +def tc_9406230a : InstrItinClass; +def tc_95a33176 : InstrItinClass; +def tc_96ef76ef : InstrItinClass; +def tc_975a4e54 : InstrItinClass; +def tc_9783714b : InstrItinClass; +def tc_988416e3 : InstrItinClass; +def tc_9b34f5e0 : InstrItinClass; +def tc_9b3c0462 : InstrItinClass; +def tc_9bcfb2ee : InstrItinClass; +def tc_9c52f549 : InstrItinClass; +def tc_9e27f2f9 : InstrItinClass; +def tc_9e72dc89 : InstrItinClass; +def tc_9edb7c77 : InstrItinClass; +def tc_9edefe01 : InstrItinClass; +def tc_9f6cd987 : InstrItinClass; +def tc_a08b630b : InstrItinClass; +def tc_a1297125 : InstrItinClass; +def tc_a154b476 : InstrItinClass; +def tc_a2b365d2 : InstrItinClass; +def tc_a3070909 : InstrItinClass; +def tc_a32e03e7 : InstrItinClass; +def tc_a38c45dc : InstrItinClass; +def tc_a4e22bbd : InstrItinClass; +def tc_a4ee89db : InstrItinClass; +def tc_a7a13fac : InstrItinClass; +def tc_a7bdb22c : InstrItinClass; +def tc_a9edeffa : InstrItinClass; +def tc_abfd9a6d : InstrItinClass; +def tc_ac65613f : InstrItinClass; +def tc_addc37a8 : InstrItinClass; +def tc_ae5babd7 : InstrItinClass; +def tc_aee6250c : InstrItinClass; +def tc_b1ae5f67 : InstrItinClass; +def tc_b34eb232 : InstrItinClass; +def tc_b4dc7630 : InstrItinClass; +def tc_b570493d : InstrItinClass; +def tc_b7c4062a : InstrItinClass; +def tc_b837298f : InstrItinClass; +def tc_ba9255a6 : InstrItinClass; +def tc_bb07f2c5 : InstrItinClass; +def tc_bb831a7c : InstrItinClass; +def tc_bf2ffc0f : InstrItinClass; +def tc_c20701f0 : InstrItinClass; +def tc_c21d7447 : InstrItinClass; +def tc_c57d9f39 : InstrItinClass; +def tc_c818ff7f : InstrItinClass; +def tc_ce59038e : InstrItinClass; +def tc_cfa0e29b : InstrItinClass; +def tc_d03278fd : InstrItinClass; +def tc_d33e5eee : InstrItinClass; +def tc_d3632d88 : InstrItinClass; +def tc_d45ba9cd : InstrItinClass; +def tc_d47648a2 : InstrItinClass; +def tc_d57d649c : InstrItinClass; +def tc_d61dfdc3 : InstrItinClass; +def tc_d68dca5c : InstrItinClass; +def tc_d7718fbe : InstrItinClass; +def tc_db596beb : InstrItinClass; +def tc_db96aa6b : InstrItinClass; +def tc_dc51281d : InstrItinClass; +def tc_decdde8a : InstrItinClass; +def tc_df4536ae : InstrItinClass; +def tc_df5d53f9 : InstrItinClass; +def tc_e3d699e3 : InstrItinClass; +def tc_e9170fb7 : InstrItinClass; +def tc_ed03645c : InstrItinClass; +def tc_eed07714 : InstrItinClass; +def tc_eeda4109 : InstrItinClass; +def tc_ef921005 : InstrItinClass; +def tc_f098b237 : InstrItinClass; +def tc_f0cdeccf : InstrItinClass; +def tc_f0e8e832 : InstrItinClass; +def tc_f34c1c21 : InstrItinClass; +def tc_f38f92e1 : InstrItinClass; +def tc_f529831b : InstrItinClass; +def tc_f6e2aff9 : InstrItinClass; +def tc_f7569068 : InstrItinClass; +def tc_f999c66e : InstrItinClass; +def tc_fae9dfa5 : InstrItinClass; +def tc_fedb7e19 : InstrItinClass; class DepScalarItinV5 { list<InstrItinData> DepScalarItinV5_list = [ - InstrItinData <tc_002cb246, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_0371abea, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_05c070ec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_05d3a09b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_0663f615, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_096199d3, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_0a705168, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_0ae0825c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_0b2be201, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_0d8f5752, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_13bfbcf9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_14b272fa, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_14b5c689, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_15aa71c5, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_174516e8, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_17e0d2cd, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_1a2fd869, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1ad90acd, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_1ae57e39, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_1b6f7cec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_1c4528a2, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_1c80410a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_1d81e60e, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1fc97744, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_20cdee80, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2332b92e, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_24b66c99, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_25a78932, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_2b8da4c2, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_2eabeebe, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_2f7c551d, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2ff964b4, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_30b9bb4a, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_32779c6f, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_36153880, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_362c6592, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3962fa26, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_39dfefe8, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3a867367, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3b470976, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3b5b7ef9, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3bd75825, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_3c76b0ff, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3d495a39, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_40116ca8, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_434c8e1e, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_4414d8b1, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_44d3da28, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_4560740b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_4837eefb, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_49a8207d, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_4ae7b58b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_4b68bce4, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_4c5ba658, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_4d5fa3a1, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_53559e35, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_56336eb0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_56f114f4, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_57890846, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_5a2711e5, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_5abb5e3f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_5aee39f7, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_5b54b33f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5b7c0967, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_5bf126a6, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_5d7f5414, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_5ef37dc4, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_6132ba3d, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_61830035, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_640086b5, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_643b4717, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_67435e81, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_675e4897, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_679309b8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_6b25e783, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_703e822c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_7186d325, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_7646c131, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_76851da1, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_779080bf, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_784490da, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_785f65a7, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7a91e76a, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_838b34ea, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_85c9c08f, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_85d5d03f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_862b3e70, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_88b4f13d, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_89e94ad3, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_8b121f4a, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_8b3e402a, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_8c945be0, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_8c99de45, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_8d9d0154, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_8fb7ab1b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9461ff31, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_946df596, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9ad9998f, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_9bfd761f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9c3ecd83, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9ca930f7, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9da59d12, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9debc299, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9e313203, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9fc3dae0, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a1123dda, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a1c00888, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a58fd5cc, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a5d4aeec, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a6b1eca9, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a813cf9a, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_a9d88b22, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_ae53734a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b31c2e97, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b343892a, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b43e7930, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b4407292, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b44ecf75, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b4b5c03a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b51dc29a, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_b83e6d73, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_b857bf4e, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b8bffe55, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b90a29b1, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_b9272d6c, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_b9e09e03, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_bab0eed9, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_bafaade3, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_bcf98408, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_bd8382d1, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_bdceeac1, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_be9602ff, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_bf061958, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_bfec0f01, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_c4db48cb, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c4f596e3, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c79a189f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_c8ce0b5c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_cd374165, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_cf8126ae, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_cfd8378a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d08ee0f4, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_d1aa9eaa, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d2e63d61, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_d5b7b0c1, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_d5c0729a, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_d63f638c, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_d65dbf51, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_d773585a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d9d43ecb, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_da4a37ed, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_da97ee82, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_db2bce9c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_de4df740, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_de554571, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_df3319ed, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_e06f432a, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e4a7f9f0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e4b3cb20, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_e78647bd, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_e86aa961, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_e93a3d71, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_e95795ec, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e9f3243f, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_f429765c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f675fee8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f8e23f0b, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_f9058dd7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_fc3999b4, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_fcc3ddf9, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_fe211424, [InstrStage<1, [SLOT0]>]> ]; + InstrItinData <tc_011e0e9d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_01d44cb2, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_01e1be3b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_02fe1c65, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_0655b949, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_075c8dd8, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0a195f2c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_0a6c20ae, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_0ba0d5da, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_0dfac0a7, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_0fac1eb8, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1044324a, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_10b884b7, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_112d30d6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_1242dc2a, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1248597c, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_14ab4f41, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_151bf368, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_158aa3f7, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_197dce51, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_1981450d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1b8138fc, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1c2c7a4a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_1c7522a8, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_1d41f8b7, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1e7875f0, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_1fcb8495, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1fe4ab69, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_20131976, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2237d952, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_234f8560, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_23708a21, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_24e109c7, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_24f426ab, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_27106296, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_280f7fe1, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_28e55c6f, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_2c13e7f5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2c3e17fc, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_2f573607, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_2f669c77, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_362b0be2, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_38382228, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_388f9897, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_38e0bae9, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_3d14a17b, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_3edca78f, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_3fbf1042, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_407e96f9, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_40d64c94, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_4222e6bf, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_42ff66ba, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_442395f3, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_449acf79, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_44d5a428, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_44fffc58, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_45791fb8, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_45f9d1be, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_49fdfd4b, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_4a55d03c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4abdbdc6, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_4ac61d92, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_4c1520ae, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_503ce0f3, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_53c851ab, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_5502c366, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_55255f2b, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_556f6577, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_55a9a350, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_55b33fda, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_56a124a7, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_57a55b54, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_5944960d, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_59a7822c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_5a4b5e58, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_5b347363, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_5ceb2f9e, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_5d636bc7, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5da50c4b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_5deb5e47, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5e4cf0e8, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_5f2afaf7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_60e324ff, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_63567288, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_64b00d8a, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_651cbe02, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_65279839, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_65cbd974, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_69bfb303, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_6ae3426b, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_6d861a95, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_6e20402a, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6f42bc60, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6fb32599, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_6fc5dbea, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_711c805f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_713b66bf, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_7401744f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_7476d766, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_74a42bda, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_76bb5435, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_77f94a5e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_788b1d09, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_7b9187d3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_7c31e19a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_7c6d32e4, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_7dc63b5c, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_7dcd9d89, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_7f7f45f5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_7f8ae742, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8035e91f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_822c3c68, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_829d8a86, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_838c4d7a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_84a7500d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_86173609, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_887d1bb7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_8a6d0d94, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_8a825db2, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8b5bd4f5, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_8e82e8ca, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9124c04f, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_9165014d, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_92240447, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_934753bb, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_937dd41c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9406230a, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_95a33176, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_96ef76ef, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_975a4e54, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_9783714b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_988416e3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_9b34f5e0, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_9b3c0462, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9bcfb2ee, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_9c52f549, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_9e27f2f9, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9e72dc89, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9edb7c77, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9edefe01, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9f6cd987, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a08b630b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a1297125, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a154b476, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a2b365d2, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a3070909, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_a32e03e7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a38c45dc, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a4e22bbd, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a4ee89db, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_a7a13fac, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a7bdb22c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a9edeffa, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_abfd9a6d, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_ac65613f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_addc37a8, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_ae5babd7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_aee6250c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b1ae5f67, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b34eb232, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b4dc7630, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b570493d, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_b7c4062a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b837298f, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_ba9255a6, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_bb07f2c5, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_bb831a7c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_bf2ffc0f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_c20701f0, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c21d7447, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c57d9f39, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_c818ff7f, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_ce59038e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_cfa0e29b, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_d03278fd, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_d33e5eee, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_d3632d88, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d45ba9cd, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_d47648a2, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_d57d649c, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_d61dfdc3, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d68dca5c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d7718fbe, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_db596beb, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_db96aa6b, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_dc51281d, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_decdde8a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_df4536ae, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_df5d53f9, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e3d699e3, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e9170fb7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_ed03645c, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_eed07714, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_eeda4109, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_ef921005, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f098b237, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f0cdeccf, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f0e8e832, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f34c1c21, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f38f92e1, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f529831b, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f6e2aff9, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f7569068, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f999c66e, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_fae9dfa5, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_fedb7e19, [InstrStage<1, [SLOT0, SLOT1]>]> ]; } class DepScalarItinV55 { list<InstrItinData> DepScalarItinV55_list = [ - InstrItinData <tc_002cb246, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0371abea, /*tc_st*/ + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05c070ec, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05d3a09b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0663f615, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_096199d3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0a705168, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_1044324a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_10b884b7, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14ab4f41, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0ae0825c, /*tc_1*/ + InstrItinData <tc_151bf368, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0b2be201, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0d8f5752, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_1981450d, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_13bfbcf9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b272fa, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b5c689, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1d41f8b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_15aa71c5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_174516e8, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, - - InstrItinData <tc_17e0d2cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1a2fd869, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ad90acd, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_20131976, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ae57e39, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6f7cec, /*tc_2early*/ + InstrItinData <tc_23708a21, /*tc_2early*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_1c4528a2, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_24e109c7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_24f426ab, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c80410a, /*tc_1*/ + InstrItinData <tc_2f669c77, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_362b0be2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_388f9897, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1d81e60e, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_38e0bae9, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fc97744, /*tc_1*/ + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_407e96f9, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20cdee80, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_40d64c94, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2332b92e, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_42ff66ba, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_24b66c99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + InstrItinData <tc_442395f3, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_25a78932, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44fffc58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2b8da4c2, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_2eabeebe, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], - []>, + InstrItinData <tc_49fdfd4b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2f7c551d, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_4a55d03c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2ff964b4, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4abdbdc6, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30b9bb4a, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_32779c6f, /*tc_3x*/ + InstrItinData <tc_4c1520ae, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_36153880, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_362c6592, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + InstrItinData <tc_53c851ab, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3962fa26, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_39dfefe8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], + InstrItinData <tc_55255f2b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_3a867367, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_3b470976, /*tc_3x*/ + InstrItinData <tc_556f6577, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b5b7ef9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55b33fda, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_56a124a7, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_57a55b54, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bd75825, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_59a7822c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3c76b0ff, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d495a39, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_40116ca8, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_434c8e1e, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4414d8b1, /*tc_1*/ + InstrItinData <tc_5da50c4b, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_44d3da28, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4560740b, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2], + InstrItinData <tc_5f2afaf7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4837eefb, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_49a8207d, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_60e324ff, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_4ae7b58b, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_63567288, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_4b68bce4, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_651cbe02, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4c5ba658, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_65279839, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4d5fa3a1, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_69bfb303, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_53559e35, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56336eb0, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6d861a95, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56f114f4, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_57890846, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_6fb32599, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_711c805f, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5a2711e5, /*tc_1*/ + InstrItinData <tc_713b66bf, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5abb5e3f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7476d766, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5aee39f7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_5b54b33f, /*tc_3*/ + InstrItinData <tc_788b1d09, /*tc_3*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b7c0967, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_7b9187d3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5bf126a6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d7f5414, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5ef37dc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_7f7f45f5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6132ba3d, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_61830035, /*tc_2*/ + InstrItinData <tc_84a7500d, /*tc_2*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_640086b5, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_86173609, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_643b4717, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_67435e81, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_8b5bd4f5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_675e4897, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 2], + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_679309b8, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6b25e783, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_703e822c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_975a4e54, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9783714b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7186d325, /*tc_st*/ + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7646c131, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_9c52f549, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76851da1, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_9e27f2f9, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_779080bf, /*tc_2*/ + InstrItinData <tc_9e72dc89, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edb7c77, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a08b630b, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_784490da, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a1297125, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_785f65a7, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7a91e76a, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_838b34ea, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85c9c08f, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4e22bbd, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_a7a13fac, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85d5d03f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_862b3e70, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_88b4f13d, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_89e94ad3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b121f4a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [], + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_b34eb232, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_8b3e402a, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], - [Hex_FWD]>, + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c945be0, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_b570493d, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c99de45, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_8d9d0154, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], - [Hex_FWD]>, + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fb7ab1b, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb831a7c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9461ff31, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_c20701f0, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_946df596, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ad9998f, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [], + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c818ff7f, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_9bfd761f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2], + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c3ecd83, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ca930f7, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_d33e5eee, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da59d12, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 3, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_9debc299, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d47648a2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d57d649c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_9e313203, /*tc_3x*/ + InstrItinData <tc_d61dfdc3, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9fc3dae0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + InstrItinData <tc_d68dca5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_dc51281d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1123dda, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_decdde8a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_a1c00888, /*tc_1*/ + InstrItinData <tc_df4536ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_df5d53f9, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e3d699e3, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a58fd5cc, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ed03645c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eeda4109, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a5d4aeec, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_f529831b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a6b1eca9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], + InstrItinData <tc_f6e2aff9, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a813cf9a, /*tc_2*/ + InstrItinData <tc_f7569068, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f999c66e, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9d88b22, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV60 { + list<InstrItinData> DepScalarItinV60_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae53734a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b31c2e97, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b343892a, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 3, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b43e7930, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4407292, /*tc_2early*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_b44ecf75, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_b4b5c03a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, - InstrItinData <tc_b51dc29a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b83e6d73, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b857bf4e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_151bf368, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b8bffe55, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1], + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b90a29b1, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9272d6c, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_1d41f8b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9e09e03, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 2, 2], + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bab0eed9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bafaade3, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_20131976, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf98408, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd8382d1, /*tc_3stall*/ + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_23708a21, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bdceeac1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_24f426ab, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be9602ff, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf061958, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bfec0f01, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_c4db48cb, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4f596e3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c79a189f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_362b0be2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, - InstrItinData <tc_c8ce0b5c, /*tc_3x*/ + InstrItinData <tc_38382228, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cd374165, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_388f9897, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38e0bae9, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cf8126ae, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cfd8378a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_407e96f9, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d08ee0f4, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1aa9eaa, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + InstrItinData <tc_42ff66ba, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_442395f3, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2e63d61, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d5b7b0c1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_44fffc58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_d5c0729a, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63f638c, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_d65dbf51, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_49fdfd4b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d773585a, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4a55d03c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d9d43ecb, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], + InstrItinData <tc_4abdbdc6, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da4a37ed, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da97ee82, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_db2bce9c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_53c851ab, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de4df740, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de554571, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_55255f2b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55b33fda, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_df3319ed, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_56a124a7, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e06f432a, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3], - [Hex_FWD]>, + InstrItinData <tc_57a55b54, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4a7f9f0, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4b3cb20, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_e78647bd, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_59a7822c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e86aa961, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e93a3d71, /*tc_ld*/ + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e95795ec, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e9f3243f, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f429765c, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f675fee8, /*tc_2*/ + InstrItinData <tc_5e4cf0e8, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f8e23f0b, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5f2afaf7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f9058dd7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_60e324ff, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, - InstrItinData <tc_fc3999b4, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_63567288, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_fcc3ddf9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_651cbe02, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fe211424, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], - [Hex_FWD, Hex_FWD]> - ]; -} + InstrItinData <tc_69bfb303, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, -class DepScalarItinV60 { - list<InstrItinData> DepScalarItinV60_list = [ - InstrItinData <tc_002cb246, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0371abea, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_6d861a95, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05c070ec, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05d3a09b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_711c805f, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0663f615, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_7476d766, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_096199d3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0a705168, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0ae0825c, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0b2be201, /*tc_st*/ + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8035e91f, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0d8f5752, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_13bfbcf9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84a7500d, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b272fa, /*tc_st*/ + InstrItinData <tc_86173609, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_887d1bb7, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b5c689, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_15aa71c5, /*tc_ld*/ + InstrItinData <tc_8a6d0d94, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_174516e8, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_17e0d2cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_8b5bd4f5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1a2fd869, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ad90acd, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ae57e39, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6f7cec, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], []>, - InstrItinData <tc_1c4528a2, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c80410a, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1d81e60e, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fc97744, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20cdee80, /*tc_2early*/ + InstrItinData <tc_9e27f2f9, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2332b92e, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_24b66c99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_25a78932, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2b8da4c2, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2eabeebe, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_2f7c551d, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_a7a13fac, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2ff964b4, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30b9bb4a, /*tc_st*/ + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_32779c6f, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_36153880, /*tc_newvjump*/ + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_b34eb232, /*tc_3stall*/ [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_362c6592, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3962fa26, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_39dfefe8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_3a867367, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_3b470976, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b5b7ef9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bd75825, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, - - InstrItinData <tc_3c76b0ff, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d495a39, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_40116ca8, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_434c8e1e, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4414d8b1, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_44d3da28, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4560740b, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d33e5eee, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_d47648a2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_4837eefb, /*tc_3stall*/ + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d68dca5c, /*tc_3stall*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_49a8207d, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_4ae7b58b, /*tc_2early*/ + InstrItinData <tc_dc51281d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_decdde8a, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_4b68bce4, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4c5ba658, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ed03645c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eeda4109, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4d5fa3a1, /*tc_newvjump*/ + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_53559e35, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + InstrItinData <tc_f529831b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56336eb0, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56f114f4, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_57890846, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_f999c66e, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5a2711e5, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5abb5e3f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} - InstrItinData <tc_5aee39f7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], +class DepScalarItinV60se { + list<InstrItinData> DepScalarItinV60se_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b54b33f, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_01d44cb2, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b7c0967, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5bf126a6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_0655b949, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d7f5414, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5ef37dc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6132ba3d, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_61830035, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_640086b5, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_643b4717, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_151bf368, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_67435e81, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_675e4897, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_679309b8, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1d41f8b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6b25e783, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_703e822c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_20131976, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7186d325, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7646c131, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_23708a21, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76851da1, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_24f426ab, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_779080bf, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_784490da, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_785f65a7, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7a91e76a, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_838b34ea, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, - InstrItinData <tc_85c9c08f, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_2f573607, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85d5d03f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_862b3e70, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_362b0be2, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [1], [Hex_FWD]>, - InstrItinData <tc_88b4f13d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_89e94ad3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_388f9897, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38e0bae9, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b121f4a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [], - []>, + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b3e402a, /*tc_1*/ + InstrItinData <tc_3fbf1042, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_8c945be0, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_407e96f9, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c99de45, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8d9d0154, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_42ff66ba, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_442395f3, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44fffc58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2], [Hex_FWD]>, - InstrItinData <tc_8fb7ab1b, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_49fdfd4b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4a55d03c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4abdbdc6, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9461ff31, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_53c851ab, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_946df596, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ad9998f, /*tc_3stall*/ + InstrItinData <tc_55255f2b, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_9bfd761f, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c3ecd83, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ca930f7, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_55b33fda, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da59d12, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], + InstrItinData <tc_56a124a7, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_57a55b54, /*tc_2early*/ + [InstrStage<1, [SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9debc299, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + InstrItinData <tc_59a7822c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9e313203, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9fc3dae0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1123dda, /*tc_1*/ + InstrItinData <tc_5f2afaf7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60e324ff, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_63567288, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_a1c00888, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a58fd5cc, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + InstrItinData <tc_651cbe02, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a5d4aeec, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_69bfb303, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a6b1eca9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a813cf9a, /*tc_2*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_6d861a95, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9d88b22, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae53734a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_b31c2e97, /*tc_2early*/ + InstrItinData <tc_6fc5dbea, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b343892a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2, 3, 2], + InstrItinData <tc_711c805f, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b43e7930, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7476d766, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4407292, /*tc_2early*/ + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_b44ecf75, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_b4b5c03a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b51dc29a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b83e6d73, /*tc_st*/ + InstrItinData <tc_7c31e19a, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b857bf4e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b8bffe55, /*tc_4x*/ + InstrItinData <tc_7f7f45f5, /*tc_4x*/ [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b90a29b1, /*tc_st*/ + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_829d8a86, /*tc_st*/ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9272d6c, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84a7500d, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_86173609, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9e09e03, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 2, 2], + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bab0eed9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_8b5bd4f5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bafaade3, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf98408, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd8382d1, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bdceeac1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be9602ff, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf061958, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e27f2f9, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bfec0f01, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4db48cb, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4f596e3, /*tc_st*/ + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a2b365d2, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c79a189f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8ce0b5c, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, - InstrItinData <tc_cd374165, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a7a13fac, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cf8126ae, /*tc_2*/ + InstrItinData <tc_a7bdb22c, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cfd8378a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_d08ee0f4, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1aa9eaa, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2e63d61, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d5b7b0c1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_d5c0729a, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_b34eb232, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63f638c, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d65dbf51, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d773585a, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, - InstrItinData <tc_d9d43ecb, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da4a37ed, /*tc_st*/ + InstrItinData <tc_bb07f2c5, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da97ee82, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_db2bce9c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de4df740, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de554571, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d33e5eee, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_df3319ed, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_d47648a2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e06f432a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3], + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2], [Hex_FWD]>, - InstrItinData <tc_e4a7f9f0, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4b3cb20, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, - InstrItinData <tc_e78647bd, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_db596beb, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_dc51281d, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e86aa961, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_decdde8a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, - InstrItinData <tc_e93a3d71, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e95795ec, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e9f3243f, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f429765c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f675fee8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ed03645c, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [3, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f8e23f0b, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f9058dd7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + InstrItinData <tc_eeda4109, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fc3999b4, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2], [Hex_FWD]>, - InstrItinData <tc_fcc3ddf9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_f529831b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fe211424, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], - [Hex_FWD, Hex_FWD]> + InstrItinData <tc_f999c66e, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> ]; } class DepScalarItinV62 { list<InstrItinData> DepScalarItinV62_list = [ - InstrItinData <tc_002cb246, /*tc_2*/ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0371abea, /*tc_st*/ + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05c070ec, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05d3a09b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0663f615, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_096199d3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0a705168, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0ae0825c, /*tc_1*/ + InstrItinData <tc_151bf368, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0b2be201, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0d8f5752, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_13bfbcf9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b272fa, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b5c689, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1d41f8b7, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_15aa71c5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_174516e8, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, - - InstrItinData <tc_17e0d2cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1a2fd869, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ad90acd, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_20131976, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ae57e39, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6f7cec, /*tc_2early*/ + InstrItinData <tc_23708a21, /*tc_2early*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_1c4528a2, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_24e109c7, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_24f426ab, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c80410a, /*tc_1*/ + InstrItinData <tc_362b0be2, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_388f9897, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1d81e60e, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_38e0bae9, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fc97744, /*tc_1*/ + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_407e96f9, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20cdee80, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2332b92e, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_42ff66ba, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_24b66c99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + InstrItinData <tc_442395f3, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_25a78932, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44fffc58, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2b8da4c2, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_2eabeebe, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], - []>, + InstrItinData <tc_49fdfd4b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2f7c551d, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_4a55d03c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2ff964b4, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4abdbdc6, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30b9bb4a, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_32779c6f, /*tc_3stall*/ + InstrItinData <tc_4c1520ae, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_36153880, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_362c6592, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + InstrItinData <tc_53c851ab, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3962fa26, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_39dfefe8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], + InstrItinData <tc_55255f2b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_3a867367, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55b33fda, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b470976, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_56a124a7, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b5b7ef9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_57a55b54, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bd75825, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_59a7822c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3c76b0ff, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d495a39, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2], + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_40116ca8, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_434c8e1e, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4414d8b1, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_44d3da28, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4560740b, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + InstrItinData <tc_5f2afaf7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4837eefb, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_49a8207d, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_60e324ff, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_4ae7b58b, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_63567288, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_4b68bce4, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_651cbe02, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4c5ba658, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4d5fa3a1, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_69bfb303, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_53559e35, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56336eb0, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6d861a95, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56f114f4, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_57890846, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_711c805f, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5a2711e5, /*tc_1*/ + InstrItinData <tc_713b66bf, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5abb5e3f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7476d766, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5aee39f7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b54b33f, /*tc_3x*/ + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_788b1d09, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b7c0967, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5bf126a6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d7f5414, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5ef37dc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6132ba3d, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_61830035, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_640086b5, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_84a7500d, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_643b4717, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_86173609, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_67435e81, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_675e4897, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_679309b8, /*tc_2*/ + InstrItinData <tc_8a825db2, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6b25e783, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_8b5bd4f5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_703e822c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7186d325, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7646c131, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76851da1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_779080bf, /*tc_2*/ + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_784490da, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e27f2f9, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_785f65a7, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7a91e76a, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_838b34ea, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85c9c08f, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_a7a13fac, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85d5d03f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_862b3e70, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_88b4f13d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_89e94ad3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b121f4a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [], + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_b34eb232, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_8b3e402a, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], - [Hex_FWD]>, + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c945be0, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c99de45, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_8d9d0154, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [2], - [Hex_FWD]>, + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fb7ab1b, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9461ff31, /*tc_2*/ + InstrItinData <tc_c20701f0, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_946df596, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ad9998f, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [], + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_9bfd761f, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c3ecd83, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ca930f7, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_d33e5eee, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da59d12, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_9debc299, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d47648a2, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9e313203, /*tc_2*/ + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_d61dfdc3, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9fc3dae0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_dc51281d, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1123dda, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_decdde8a, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_a1c00888, /*tc_1*/ + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ed03645c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eeda4109, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a58fd5cc, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + InstrItinData <tc_f098b237, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a5d4aeec, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_f529831b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a6b1eca9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a813cf9a, /*tc_2*/ + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f999c66e, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9d88b22, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV65 { + list<InstrItinData> DepScalarItinV65_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae53734a, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b31c2e97, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b343892a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2, 3, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b43e7930, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4407292, /*tc_2early*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_b44ecf75, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_b4b5c03a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, - InstrItinData <tc_b51dc29a, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b83e6d73, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b857bf4e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_151bf368, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b8bffe55, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b90a29b1, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9272d6c, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_1d41f8b7, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9e09e03, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 2, 2], + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bab0eed9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bafaade3, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_20131976, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf98408, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd8382d1, /*tc_newvjump*/ + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_23708a21, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bdceeac1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_24f426ab, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be9602ff, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf061958, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bfec0f01, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_c4db48cb, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4f596e3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c79a189f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8ce0b5c, /*tc_3x*/ + InstrItinData <tc_362b0be2, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_38382228, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cd374165, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_388f9897, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38e0bae9, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cf8126ae, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cfd8378a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_407e96f9, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d08ee0f4, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1aa9eaa, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + InstrItinData <tc_42ff66ba, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_442395f3, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2e63d61, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d5b7b0c1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_44fffc58, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_d5c0729a, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63f638c, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_d65dbf51, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_49fdfd4b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d773585a, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4a55d03c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d9d43ecb, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], + InstrItinData <tc_4abdbdc6, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da4a37ed, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da97ee82, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_db2bce9c, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_53c851ab, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de4df740, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55255f2b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de554571, /*tc_2early*/ + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55b33fda, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_df3319ed, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_56a124a7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e06f432a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3], - [Hex_FWD]>, + InstrItinData <tc_57a55b54, /*tc_1*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4a7f9f0, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4b3cb20, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_e78647bd, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_59a7822c, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e86aa961, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e93a3d71, /*tc_ld*/ + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e95795ec, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e9f3243f, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f429765c, /*tc_2*/ + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f675fee8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_5f2afaf7, /*tc_latepredldaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60e324ff, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_63567288, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4], + [Hex_FWD]>, + + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_651cbe02, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f8e23f0b, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_69bfb303, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6d861a95, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f9058dd7, /*tc_2*/ + InstrItinData <tc_711c805f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7401744f, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fc3999b4, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], - [Hex_FWD]>, + InstrItinData <tc_7476d766, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fcc3ddf9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fe211424, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], - [Hex_FWD, Hex_FWD]> - ]; -} + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, -class DepScalarItinV65 { - list<InstrItinData> DepScalarItinV65_list = [ - InstrItinData <tc_002cb246, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0371abea, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05c070ec, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05d3a09b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0663f615, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_096199d3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0a705168, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_84a7500d, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0ae0825c, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_86173609, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0b2be201, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0d8f5752, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_13bfbcf9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b272fa, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8b5bd4f5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b5c689, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_15aa71c5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_174516e8, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_17e0d2cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1a2fd869, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, - InstrItinData <tc_1ad90acd, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ae57e39, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6f7cec, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], - []>, + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c4528a2, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c80410a, /*tc_1*/ + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1d81e60e, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_9e27f2f9, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fc97744, /*tc_1*/ + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20cdee80, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2332b92e, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_24b66c99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_25a78932, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2b8da4c2, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2eabeebe, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_2f7c551d, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_a7a13fac, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2ff964b4, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30b9bb4a, /*tc_st*/ + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_32779c6f, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_36153880, /*tc_newvjump*/ + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_b34eb232, /*tc_3stall*/ [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_362c6592, /*tc_st*/ + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_ba9255a6, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3962fa26, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_39dfefe8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_3a867367, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d33e5eee, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_d47648a2, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_dc51281d, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_decdde8a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b470976, /*tc_4x*/ + InstrItinData <tc_ed03645c, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eeda4109, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0e8e832, /*tc_4x*/ [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b5b7ef9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bd75825, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_3c76b0ff, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + InstrItinData <tc_f529831b, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d495a39, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_40116ca8, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_434c8e1e, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_f999c66e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4414d8b1, /*tc_2*/ + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV66 { + list<InstrItinData> DepScalarItinV66_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_44d3da28, /*tc_ld*/ + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_075c8dd8, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4560740b, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4837eefb, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_0ba0d5da, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_49a8207d, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_4ae7b58b, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_4b68bce4, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4c5ba658, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_151bf368, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4d5fa3a1, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData <tc_53559e35, /*tc_latepredstaia*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56336eb0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + InstrItinData <tc_1d41f8b7, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56f114f4, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20131976, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_57890846, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5a2711e5, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5abb5e3f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_23708a21, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5aee39f7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + InstrItinData <tc_24f426ab, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b54b33f, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b7c0967, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5bf126a6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d7f5414, /*tc_3stall*/ + InstrItinData <tc_362b0be2, /*tc_3*/ [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_5ef37dc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6132ba3d, /*tc_1*/ + InstrItinData <tc_388f9897, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38e0bae9, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_407e96f9, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_61830035, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_640086b5, /*tc_1*/ + InstrItinData <tc_42ff66ba, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_442395f3, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44fffc58, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_49fdfd4b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4a55d03c, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_643b4717, /*tc_1*/ + InstrItinData <tc_4abdbdc6, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_53c851ab, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5502c366, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_67435e81, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_55255f2b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_675e4897, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 1], + InstrItinData <tc_55b33fda, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_679309b8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_56a124a7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6b25e783, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_57a55b54, /*tc_1*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_703e822c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_59a7822c, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7186d325, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7646c131, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76851da1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_779080bf, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_784490da, /*tc_2*/ + InstrItinData <tc_5e4cf0e8, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_785f65a7, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5f2afaf7, /*tc_latepredldaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7a91e76a, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_60e324ff, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_838b34ea, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_63567288, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4], + [Hex_FWD]>, - InstrItinData <tc_85c9c08f, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [2, 2], + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85d5d03f, /*tc_1*/ + InstrItinData <tc_651cbe02, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_862b3e70, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_69bfb303, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6d861a95, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_88b4f13d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_711c805f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_89e94ad3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7476d766, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b121f4a, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [], + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_8b3e402a, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4], - [Hex_FWD]>, + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c945be0, /*tc_newvjump*/ + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c99de45, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8d9d0154, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [2], - [Hex_FWD]>, + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fb7ab1b, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9461ff31, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_946df596, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ad9998f, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [], - []>, + InstrItinData <tc_84a7500d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9bfd761f, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_86173609, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c3ecd83, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ca930f7, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da59d12, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1], + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9debc299, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + InstrItinData <tc_8b5bd4f5, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9e313203, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9fc3dae0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1123dda, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData <tc_a1c00888, /*tc_1*/ + InstrItinData <tc_9b34f5e0, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e27f2f9, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a58fd5cc, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a5d4aeec, /*tc_ld*/ + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a32e03e7, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a6b1eca9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a813cf9a, /*tc_2*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_a7a13fac, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9d88b22, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae53734a, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_b31c2e97, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_b34eb232, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b343892a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2, 3, 2], + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b43e7930, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4407292, /*tc_2early*/ + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_b44ecf75, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2], + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4b5c03a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b51dc29a, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [3, 2], + InstrItinData <tc_d33e5eee, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b83e6d73, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_d47648a2, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b857bf4e, /*tc_st*/ + InstrItinData <tc_db96aa6b, /*tc_st*/ [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_b8bffe55, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + InstrItinData <tc_dc51281d, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_decdde8a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b90a29b1, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9272d6c, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9e09e03, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [4, 1, 2], + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ed03645c, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bab0eed9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_eeda4109, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bafaade3, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf98408, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd8382d1, /*tc_newvjump*/ + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_f529831b, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bdceeac1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be9602ff, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_f999c66e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV67 { + list<InstrItinData> DepScalarItinV67_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf061958, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bfec0f01, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4db48cb, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_0655b949, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4f596e3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c79a189f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8ce0b5c, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cd374165, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cf8126ae, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cfd8378a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d08ee0f4, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1aa9eaa, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_151bf368, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2e63d61, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d5b7b0c1, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData <tc_d5c0729a, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63f638c, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_1d41f8b7, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d65dbf51, /*tc_latepredstaia*/ - [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d773585a, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_20131976, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d9d43ecb, /*tc_1*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da4a37ed, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da97ee82, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_23708a21, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_24f426ab, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_db2bce9c, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de4df740, /*tc_1*/ + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_2f573607, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_362b0be2, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_388f9897, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de554571, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_38e0bae9, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_df3319ed, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e06f432a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3], + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], [Hex_FWD]>, - InstrItinData <tc_e4a7f9f0, /*tc_1*/ + InstrItinData <tc_407e96f9, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4b3cb20, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e78647bd, /*tc_1*/ + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_42ff66ba, /*tc_1*/ [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e86aa961, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_442395f3, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e93a3d71, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + InstrItinData <tc_449acf79, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e95795ec, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e9f3243f, /*tc_latepredldaia*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], + InstrItinData <tc_44fffc58, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f429765c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_45f9d1be, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, - InstrItinData <tc_f675fee8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_49fdfd4b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f8e23f0b, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4a55d03c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f9058dd7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4abdbdc6, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fc3999b4, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], - [Hex_FWD]>, + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fcc3ddf9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fe211424, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], - [Hex_FWD, Hex_FWD]> - ]; -} + InstrItinData <tc_53c851ab, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, -class DepScalarItinV66 { - list<InstrItinData> DepScalarItinV66_list = [ - InstrItinData <tc_002cb246, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_5502c366, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0371abea, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 3], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_55255f2b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, - InstrItinData <tc_05c070ec, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_05d3a09b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0663f615, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_55b33fda, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_56a124a7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_57a55b54, /*tc_1*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_096199d3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_59a7822c, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0a705168, /*tc_1*/ + InstrItinData <tc_5b347363, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0ae0825c, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0b2be201, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0d8f5752, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_5f2afaf7, /*tc_latepredldaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60e324ff, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_63567288, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4], + [Hex_FWD]>, + + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_13bfbcf9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_651cbe02, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b272fa, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 3], + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14b5c689, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_69bfb303, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_15aa71c5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6d861a95, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_174516e8, /*tc_3x*/ + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_17e0d2cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_6fc5dbea, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_711c805f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1a2fd869, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ad90acd, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_7476d766, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1ae57e39, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6f7cec, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_1c4528a2, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1c80410a, /*tc_2*/ + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_829d8a86, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84a7500d, /*tc_2*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1d81e60e, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_86173609, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fc97744, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8b5bd4f5, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20cdee80, /*tc_1*/ + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2332b92e, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_24b66c99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_25a78932, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2b8da4c2, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1], + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2eabeebe, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], []>, - InstrItinData <tc_2f7c551d, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2ff964b4, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30b9bb4a, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_32779c6f, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_36153880, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_362c6592, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 3], + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3962fa26, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 3], + InstrItinData <tc_9bcfb2ee, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c52f549, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e27f2f9, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_39dfefe8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], - []>, + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3a867367, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b470976, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b5b7ef9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_a1297125, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bd75825, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3c76b0ff, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + InstrItinData <tc_a2b365d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d495a39, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_a7a13fac, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_40116ca8, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 3], + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_b34eb232, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_b4dc7630, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_434c8e1e, /*tc_3stall*/ + InstrItinData <tc_b570493d, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4414d8b1, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_44d3da28, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4560740b, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4837eefb, /*tc_3stall*/ + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c21d7447, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_49a8207d, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4ae7b58b, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_4b68bce4, /*tc_st*/ + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4c5ba658, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4d5fa3a1, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2], + InstrItinData <tc_d33e5eee, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_53559e35, /*tc_latepredstaia*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d47648a2, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56336eb0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_56f114f4, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_db596beb, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_57890846, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_dc51281d, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5a2711e5, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_decdde8a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5abb5e3f, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5aee39f7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ed03645c, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_eeda4109, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b54b33f, /*tc_3x*/ + InstrItinData <tc_f0cdeccf, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5b7c0967, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_f529831b, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f999c66e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5bf126a6, /*tc_st*/ + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV67T { + list<InstrItinData> DepScalarItinV67T_list = [ + InstrItinData <tc_011e0e9d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01d44cb2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_01e1be3b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_02fe1c65, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0655b949, /*tc_st*/ [InstrStage<1, [SLOT0]>], [2, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d7f5414, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_075c8dd8, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5ef37dc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_0a195f2c, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6132ba3d, /*tc_2*/ + InstrItinData <tc_0a6c20ae, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0ba0d5da, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_0dfac0a7, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_61830035, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_0fac1eb8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_640086b5, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_1044324a, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_10b884b7, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_112d30d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1242dc2a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_1248597c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14ab4f41, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_643b4717, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_151bf368, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_158aa3f7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_67435e81, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_197dce51, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_675e4897, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 1], + InstrItinData <tc_1981450d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b8138fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_679309b8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_1c2c7a4a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c7522a8, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1d41f8b7, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e7875f0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1fcb8495, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6b25e783, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_1fe4ab69, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_703e822c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_20131976, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2237d952, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7186d325, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_234f8560, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7646c131, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_23708a21, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_24e109c7, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76851da1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_24f426ab, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_779080bf, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_27106296, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_784490da, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_280f7fe1, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_785f65a7, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_28e55c6f, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7a91e76a, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + InstrItinData <tc_2c13e7f5, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_838b34ea, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2c3e17fc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, - InstrItinData <tc_85c9c08f, /*tc_1*/ + InstrItinData <tc_2f573607, /*tc_1*/ [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_85d5d03f, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2f669c77, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_862b3e70, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_362b0be2, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_88b4f13d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_38382228, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_89e94ad3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_388f9897, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38e0bae9, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d14a17b, /*tc_1*/ + [InstrStage<1, [SLOT0]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b121f4a, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [], - []>, + InstrItinData <tc_3edca78f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8b3e402a, /*tc_2latepred*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4], + InstrItinData <tc_3fbf1042, /*tc_1*/ + [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData <tc_8c945be0, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_407e96f9, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_40d64c94, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c99de45, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_4222e6bf, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_42ff66ba, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_442395f3, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_449acf79, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44d5a428, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44fffc58, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_45791fb8, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8d9d0154, /*tc_3stall*/ + InstrItinData <tc_45f9d1be, /*tc_2early*/ [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_8fb7ab1b, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_49fdfd4b, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4a55d03c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4abdbdc6, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4ac61d92, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4c1520ae, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_503ce0f3, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9461ff31, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_53c851ab, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_946df596, /*tc_1*/ + InstrItinData <tc_5502c366, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ad9998f, /*tc_3stall*/ + InstrItinData <tc_55255f2b, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_9bfd761f, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], + InstrItinData <tc_556f6577, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c3ecd83, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_55a9a350, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ca930f7, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_55b33fda, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da59d12, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1], + InstrItinData <tc_56a124a7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_57a55b54, /*tc_1*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5944960d, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9debc299, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + InstrItinData <tc_59a7822c, /*tc_1*/ + [InstrStage<1, [SLOT0]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5a4b5e58, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5b347363, /*tc_1*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ceb2f9e, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9e313203, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_5d636bc7, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9fc3dae0, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5da50c4b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1123dda, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_5deb5e47, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5e4cf0e8, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5f2afaf7, /*tc_latepredldaia*/ + [InstrStage<1, [SLOT0]>], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60e324ff, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_a1c00888, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_63567288, /*tc_2latepred*/ + [InstrStage<1, [SLOT0]>], [4], + [Hex_FWD]>, + + InstrItinData <tc_64b00d8a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a58fd5cc, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + InstrItinData <tc_651cbe02, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65279839, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_65cbd974, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a5d4aeec, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_69bfb303, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a6b1eca9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ae3426b, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a813cf9a, /*tc_2*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_6d861a95, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9d88b22, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_6e20402a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae53734a, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_6f42bc60, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6fb32599, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_b31c2e97, /*tc_1*/ + InstrItinData <tc_6fc5dbea, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b343892a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], + InstrItinData <tc_711c805f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_713b66bf, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b43e7930, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_7401744f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7476d766, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4407292, /*tc_2early*/ + InstrItinData <tc_74a42bda, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_76bb5435, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_77f94a5e, /*tc_st*/ [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_b44ecf75, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2], + InstrItinData <tc_788b1d09, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7b9187d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c31e19a, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b4b5c03a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_7c6d32e4, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b51dc29a, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [3, 2], + InstrItinData <tc_7dc63b5c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b83e6d73, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_7dcd9d89, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f7f45f5, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b857bf4e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_7f8ae742, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b8bffe55, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + InstrItinData <tc_8035e91f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_822c3c68, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b90a29b1, /*tc_st*/ + InstrItinData <tc_829d8a86, /*tc_st*/ [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9272d6c, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_838c4d7a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84a7500d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_86173609, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_887d1bb7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8a6d0d94, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b9e09e03, /*tc_3stall*/ - [InstrStage<1, [SLOT2]>], [4, 1, 2], + InstrItinData <tc_8a825db2, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bab0eed9, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_8b5bd4f5, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8e82e8ca, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9124c04f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9165014d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_92240447, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bafaade3, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_934753bb, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf98408, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_937dd41c, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_9406230a, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd8382d1, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_95a33176, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bdceeac1, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_96ef76ef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be9602ff, /*tc_st*/ + InstrItinData <tc_975a4e54, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9783714b, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_988416e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_9b34f5e0, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_9b3c0462, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9bcfb2ee, /*tc_st*/ [InstrStage<1, [SLOT0]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf061958, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_9c52f549, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e27f2f9, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9e72dc89, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bfec0f01, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + InstrItinData <tc_9edb7c77, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4db48cb, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_9edefe01, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9f6cd987, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c4f596e3, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_a08b630b, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a1297125, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a154b476, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c79a189f, /*tc_st*/ + InstrItinData <tc_a2b365d2, /*tc_st*/ [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8ce0b5c, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_cd374165, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_a3070909, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cf8126ae, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a32e03e7, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cfd8378a, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_a38c45dc, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4e22bbd, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a4ee89db, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_a7a13fac, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a7bdb22c, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d08ee0f4, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_a9edeffa, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1aa9eaa, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + InstrItinData <tc_abfd9a6d, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ac65613f, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_addc37a8, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2e63d61, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], + InstrItinData <tc_ae5babd7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d5b7b0c1, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_aee6250c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b1ae5f67, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_d5c0729a, /*tc_st*/ + InstrItinData <tc_b34eb232, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_b4dc7630, /*tc_st*/ [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63f638c, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_b570493d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d65dbf51, /*tc_latepredstaia*/ - [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + InstrItinData <tc_b7c4062a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d773585a, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_b837298f, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_ba9255a6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb07f2c5, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bb831a7c, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bf2ffc0f, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d9d43ecb, /*tc_1*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_c20701f0, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c21d7447, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c57d9f39, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da4a37ed, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 3], + InstrItinData <tc_c818ff7f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_ce59038e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cfa0e29b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da97ee82, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 3], + InstrItinData <tc_d03278fd, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_db2bce9c, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_d33e5eee, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d3632d88, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_de4df740, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d45ba9cd, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_de554571, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_d47648a2, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_df3319ed, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_d57d649c, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_d61dfdc3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e06f432a, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3], + InstrItinData <tc_d68dca5c, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d7718fbe, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_e4a7f9f0, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_db596beb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e4b3cb20, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_db96aa6b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_e78647bd, /*tc_1*/ - [InstrStage<1, [SLOT2]>], [2, 2], + InstrItinData <tc_dc51281d, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e86aa961, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_decdde8a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_e93a3d71, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_df4536ae, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e95795ec, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_df5d53f9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e9f3243f, /*tc_latepredldaia*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e3d699e3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f429765c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9170fb7, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f675fee8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ed03645c, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f8e23f0b, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_eed07714, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f9058dd7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + InstrItinData <tc_eeda4109, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef921005, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f098b237, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f0cdeccf, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fc3999b4, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_f0e8e832, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f34c1c21, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f38f92e1, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_fcc3ddf9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_f529831b, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f6e2aff9, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f7569068, /*tc_4x*/ + [InstrStage<1, [SLOT3]>], [5, 5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fe211424, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], - [Hex_FWD, Hex_FWD]> + InstrItinData <tc_f999c66e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fae9dfa5, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fedb7e19, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> ]; } diff --git a/llvm/lib/Target/Hexagon/HexagonDepITypes.h b/llvm/lib/Target/Hexagon/HexagonDepITypes.h index 358345e027d81..b261b46531270 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepITypes.h +++ b/llvm/lib/Target/Hexagon/HexagonDepITypes.h @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// namespace llvm { @@ -16,49 +16,48 @@ enum Type { TypeALU32_ADDI = 2, TypeALU64 = 3, TypeCJ = 4, - TypeCOPROC_VX = 5, - TypeCR = 6, - TypeCVI_4SLOT_MPY = 7, - TypeCVI_GATHER = 8, - TypeCVI_GATHER_RST = 9, - TypeCVI_HIST = 10, - TypeCVI_SCATTER = 11, - TypeCVI_SCATTER_DV = 12, - TypeCVI_SCATTER_NEW_RST = 13, - TypeCVI_SCATTER_NEW_ST = 14, - TypeCVI_SCATTER_RST = 15, - TypeCVI_VA = 16, - TypeCVI_VA_DV = 17, - TypeCVI_VINLANESAT = 18, - TypeCVI_VM_LD = 19, - TypeCVI_VM_NEW_ST = 20, - TypeCVI_VM_ST = 21, - TypeCVI_VM_STU = 22, - TypeCVI_VM_TMP_LD = 23, - TypeCVI_VM_VP_LDU = 24, - TypeCVI_VP = 25, - TypeCVI_VP_VS = 26, - TypeCVI_VS = 27, - TypeCVI_VS_VX = 28, - TypeCVI_VX = 29, - TypeCVI_VX_DV = 30, - TypeCVI_VX_LATE = 31, - TypeCVI_ZW = 32, - TypeDUPLEX = 33, - TypeENDLOOP = 34, - TypeEXTENDER = 35, - TypeJ = 36, - TypeLD = 37, - TypeM = 38, - TypeMAPPING = 39, - TypeNCJ = 40, - TypePSEUDO = 41, - TypeST = 42, - TypeSUBINSN = 43, - TypeS_2op = 44, - TypeS_3op = 45, - TypeV2LDST = 48, - TypeV4LDST = 49, + TypeCR = 7, + TypeCVI_4SLOT_MPY = 8, + TypeCVI_GATHER = 9, + TypeCVI_GATHER_DV = 10, + TypeCVI_GATHER_RST = 11, + TypeCVI_HIST = 12, + TypeCVI_SCATTER = 13, + TypeCVI_SCATTER_DV = 14, + TypeCVI_SCATTER_NEW_RST = 15, + TypeCVI_SCATTER_NEW_ST = 16, + TypeCVI_SCATTER_RST = 17, + TypeCVI_VA = 18, + TypeCVI_VA_DV = 19, + TypeCVI_VM_LD = 20, + TypeCVI_VM_NEW_ST = 21, + TypeCVI_VM_ST = 22, + TypeCVI_VM_STU = 23, + TypeCVI_VM_TMP_LD = 24, + TypeCVI_VM_VP_LDU = 25, + TypeCVI_VP = 26, + TypeCVI_VP_VS = 27, + TypeCVI_VS = 28, + TypeCVI_VS_VX = 29, + TypeCVI_VX = 30, + TypeCVI_VX_DV = 31, + TypeCVI_VX_LATE = 32, + TypeCVI_ZW = 33, + TypeDUPLEX = 34, + TypeENDLOOP = 35, + TypeEXTENDER = 36, + TypeJ = 37, + TypeLD = 38, + TypeM = 39, + TypeMAPPING = 40, + TypeNCJ = 41, + TypePSEUDO = 42, + TypeST = 43, + TypeSUBINSN = 44, + TypeS_2op = 45, + TypeS_3op = 46, + TypeV2LDST = 49, + TypeV4LDST = 50, }; } } diff --git a/llvm/lib/Target/Hexagon/HexagonDepITypes.td b/llvm/lib/Target/Hexagon/HexagonDepITypes.td index 91c02b84b87c0..f251a291c23c1 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepITypes.td +++ b/llvm/lib/Target/Hexagon/HexagonDepITypes.td @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// class IType<bits<7> t> { bits<7> Value = t; } @@ -14,46 +14,45 @@ def TypeALU32_3op : IType<1>; def TypeALU32_ADDI : IType<2>; def TypeALU64 : IType<3>; def TypeCJ : IType<4>; -def TypeCOPROC_VX : IType<5>; -def TypeCR : IType<6>; -def TypeCVI_4SLOT_MPY : IType<7>; -def TypeCVI_GATHER : IType<8>; -def TypeCVI_GATHER_RST : IType<9>; -def TypeCVI_HIST : IType<10>; -def TypeCVI_SCATTER : IType<11>; -def TypeCVI_SCATTER_DV : IType<12>; -def TypeCVI_SCATTER_NEW_RST : IType<13>; -def TypeCVI_SCATTER_NEW_ST : IType<14>; -def TypeCVI_SCATTER_RST : IType<15>; -def TypeCVI_VA : IType<16>; -def TypeCVI_VA_DV : IType<17>; -def TypeCVI_VINLANESAT : IType<18>; -def TypeCVI_VM_LD : IType<19>; -def TypeCVI_VM_NEW_ST : IType<20>; -def TypeCVI_VM_ST : IType<21>; -def TypeCVI_VM_STU : IType<22>; -def TypeCVI_VM_TMP_LD : IType<23>; -def TypeCVI_VM_VP_LDU : IType<24>; -def TypeCVI_VP : IType<25>; -def TypeCVI_VP_VS : IType<26>; -def TypeCVI_VS : IType<27>; -def TypeCVI_VS_VX : IType<28>; -def TypeCVI_VX : IType<29>; -def TypeCVI_VX_DV : IType<30>; -def TypeCVI_VX_LATE : IType<31>; -def TypeCVI_ZW : IType<32>; -def TypeDUPLEX : IType<33>; -def TypeENDLOOP : IType<34>; -def TypeEXTENDER : IType<35>; -def TypeJ : IType<36>; -def TypeLD : IType<37>; -def TypeM : IType<38>; -def TypeMAPPING : IType<39>; -def TypeNCJ : IType<40>; -def TypePSEUDO : IType<41>; -def TypeST : IType<42>; -def TypeSUBINSN : IType<43>; -def TypeS_2op : IType<44>; -def TypeS_3op : IType<45>; -def TypeV2LDST : IType<48>; -def TypeV4LDST : IType<49>; +def TypeCR : IType<7>; +def TypeCVI_4SLOT_MPY : IType<8>; +def TypeCVI_GATHER : IType<9>; +def TypeCVI_GATHER_DV : IType<10>; +def TypeCVI_GATHER_RST : IType<11>; +def TypeCVI_HIST : IType<12>; +def TypeCVI_SCATTER : IType<13>; +def TypeCVI_SCATTER_DV : IType<14>; +def TypeCVI_SCATTER_NEW_RST : IType<15>; +def TypeCVI_SCATTER_NEW_ST : IType<16>; +def TypeCVI_SCATTER_RST : IType<17>; +def TypeCVI_VA : IType<18>; +def TypeCVI_VA_DV : IType<19>; +def TypeCVI_VM_LD : IType<20>; +def TypeCVI_VM_NEW_ST : IType<21>; +def TypeCVI_VM_ST : IType<22>; +def TypeCVI_VM_STU : IType<23>; +def TypeCVI_VM_TMP_LD : IType<24>; +def TypeCVI_VM_VP_LDU : IType<25>; +def TypeCVI_VP : IType<26>; +def TypeCVI_VP_VS : IType<27>; +def TypeCVI_VS : IType<28>; +def TypeCVI_VS_VX : IType<29>; +def TypeCVI_VX : IType<30>; +def TypeCVI_VX_DV : IType<31>; +def TypeCVI_VX_LATE : IType<32>; +def TypeCVI_ZW : IType<33>; +def TypeDUPLEX : IType<34>; +def TypeENDLOOP : IType<35>; +def TypeEXTENDER : IType<36>; +def TypeJ : IType<37>; +def TypeLD : IType<38>; +def TypeM : IType<39>; +def TypeMAPPING : IType<40>; +def TypeNCJ : IType<41>; +def TypePSEUDO : IType<42>; +def TypeST : IType<43>; +def TypeSUBINSN : IType<44>; +def TypeS_2op : IType<45>; +def TypeS_3op : IType<46>; +def TypeV2LDST : IType<49>; +def TypeV4LDST : IType<50>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td index c08d9a388d3e5..305115da57636 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -5,113 +5,138 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -class Enc_890909 : OpcodeHexagon { +class Enc_5e2823 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; - bits <2> Pe4; - let Inst{6-5} = Pe4{1-0}; } -class Enc_9be1de : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; +class Enc_b9c5fb : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_527412 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; +class Enc_5ab2be : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_efaed8 : OpcodeHexagon { - bits <1> Ii; - let Inst{8-8} = Ii{0-0}; -} -class Enc_a568d4 : OpcodeHexagon { +class Enc_bd6011 : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_27b757 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_cb9321 : OpcodeHexagon { + bits <16> Ii; + let Inst{27-21} = Ii{15-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_1de724 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-22} = n1{2-0}; +class Enc_a56825 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_0e41fa : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; +class Enc_140c83 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_18c338 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_be32a5 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_3d6d37 : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; +class Enc_ea23e4 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_e3b0c4 : OpcodeHexagon { + +} +class Enc_ea4c54 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_a641d0 : OpcodeHexagon { +class Enc_e38e1f : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_9b0bc1 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_802dc0 : OpcodeHexagon { - bits <1> Ii; - let Inst{8-8} = Ii{0-0}; - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; +class Enc_90cd8b : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_6b197f : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_3a3d62 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_0cb018 : OpcodeHexagon { + bits <5> Cs32; + let Inst{20-16} = Cs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } class Enc_51436c : OpcodeHexagon { bits <16> Ii; @@ -120,142 +145,281 @@ class Enc_51436c : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_c7a204 : OpcodeHexagon { - bits <6> II; - let Inst{5-0} = II{5-0}; +class Enc_bd811a : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Cd32; + let Inst{4-0} = Cd32{4-0}; +} +class Enc_5e87ce : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_fcf7a7 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_db40cd : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; +class Enc_88c16c : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_2b3f60 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Px4; + let Inst{6-5} = Px4{1-0}; +} +class Enc_311abd : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_c2b48e : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_a1e29d : OpcodeHexagon { +class Enc_08d755 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_02553a : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_f0cca7 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <6> II; + let Inst{20-16} = II{5-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9cdba7 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_a05677 : OpcodeHexagon { bits <5> Ii; let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_d15d19 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_e90a15 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{22-22} = n1{0-0}; +class Enc_2b518f : OpcodeHexagon { + bits <32> Ii; + let Inst{27-16} = Ii{31-20}; + let Inst{13-0} = Ii{19-6}; } -class Enc_e0a47a : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; +class Enc_fb6577 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; } -class Enc_140c83 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; +class Enc_b8c967 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_7eee72 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; +class Enc_667b39 : OpcodeHexagon { + bits <5> Css32; + let Inst{20-16} = Css32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; } -class Enc_310ba1 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_0ed752 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Cdd32; + let Inst{4-0} = Cdd32{4-0}; +} +class Enc_03833b : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_0d8adb : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_3680c2 : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_412ff0 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rxx32; + let Inst{12-8} = Rxx32{4-0}; +} +class Enc_831a7d : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; } -class Enc_d7dc10 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_d2216a : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_6baed4 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_d2c7f1 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; } -class Enc_736575 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{25-23} = n1{2-0}; +class Enc_5eac98 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_8dec2e : OpcodeHexagon { +class Enc_927852 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_7e5a82 : OpcodeHexagon { bits <5> Ii; let Inst{12-8} = Ii{4-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_65d691 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_454a26 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_5d6c34 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_cb4b4e : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_cda00a : OpcodeHexagon { + bits <12> Ii; + let Inst{19-16} = Ii{11-8}; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_28dcbb : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{4-0} = Vvv32{4-0}; +class Enc_bd0b33 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_eaa9f8 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qx4; - let Inst{1-0} = Qx4{1-0}; +class Enc_c0cdde : OpcodeHexagon { + bits <9> Ii; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_509701 : OpcodeHexagon { - bits <19> Ii; - let Inst{26-25} = Ii{18-17}; - let Inst{20-16} = Ii{16-12}; - let Inst{13-5} = Ii{11-3}; +class Enc_78e566 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } @@ -270,80 +434,29 @@ class Enc_830e5d : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_79b8c8 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_58a8bf : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_041d7b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{24-23} = n1{3-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; +class Enc_f5e933 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_f44229 : OpcodeHexagon { - bits <7> Ii; - let Inst{13-13} = Ii{6-6}; - let Inst{7-3} = Ii{5-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_48b75f : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_aad80c : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_87c142 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-4} = Ii{6-2}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_86a14b : OpcodeHexagon { - bits <8> Ii; - let Inst{7-3} = Ii{7-3}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_9a33d5 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_527412 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_a56825 : OpcodeHexagon { +class Enc_329361 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; bits <5> Rtt32; @@ -351,81 +464,85 @@ class Enc_a56825 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_9ea4cf : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_284ebb : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_ee5ed0 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; - bits <2> n1; - let Inst{9-8} = n1{1-0}; +class Enc_607661 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_bddee3 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vyyyy32; - let Inst{4-0} = Vyyyy32{4-0}; - bits <3> Rx8; - let Inst{18-16} = Rx8{2-0}; +class Enc_9ac432 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pu4; + let Inst{7-6} = Pu4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_935d9b : OpcodeHexagon { +class Enc_1f19b5 : OpcodeHexagon { bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{9-5} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_61f0b0 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; +class Enc_e6c957 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_bd6011 : OpcodeHexagon { - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_83ee64 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_65d691 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } -class Enc_e8c45e : OpcodeHexagon { - bits <7> Ii; - let Inst{13-13} = Ii{6-6}; - let Inst{7-3} = Ii{5-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_2ae154 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; } -class Enc_ca3887 : OpcodeHexagon { +class Enc_437f33 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_6c9440 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_890909 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; } class Enc_a94f3b : OpcodeHexagon { bits <5> Rs32; @@ -437,51 +554,98 @@ class Enc_a94f3b : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } -class Enc_625deb : OpcodeHexagon { - bits <4> Ii; - let Inst{10-8} = Ii{3-1}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; +class Enc_0aa344 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_1f5ba6 : OpcodeHexagon { - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; +class Enc_44271f : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_cd82bc : OpcodeHexagon { - bits <4> Ii; - let Inst{21-21} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <6> II; - let Inst{13-8} = II{5-0}; +class Enc_ed5027 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} +class Enc_621fba : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; } -class Enc_399e12 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; +class Enc_81ac1d : OpcodeHexagon { + bits <24> Ii; + let Inst{24-16} = Ii{23-15}; + let Inst{13-1} = Ii{14-2}; } -class Enc_d7a65e : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <6> II; - let Inst{13-13} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; +class Enc_daea09 : OpcodeHexagon { + bits <17> Ii; + let Inst{23-22} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-1} = Ii{8-2}; + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; +} +class Enc_ecbcc8 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } -class Enc_607661 : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_88d4d9 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_0fa531 : OpcodeHexagon { + bits <15> Ii; + let Inst{21-21} = Ii{14-14}; + let Inst{13-13} = Ii{13-13}; + let Inst{11-1} = Ii{12-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_4dc228 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <10> II; + let Inst{20-16} = II{9-5}; + let Inst{7-5} = II{4-2}; + let Inst{1-0} = II{1-0}; +} +class Enc_864a5a : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_a51a9a : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; +} +class Enc_33f8ba : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_c9a18e : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; } class Enc_6a5972 : OpcodeHexagon { bits <11> Ii; @@ -492,74 +656,56 @@ class Enc_6a5972 : OpcodeHexagon { bits <4> Rt16; let Inst{11-8} = Rt16{3-0}; } -class Enc_ff3442 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; +class Enc_eafd18 : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; } -class Enc_53dca9 : OpcodeHexagon { - bits <6> Ii; - let Inst{11-8} = Ii{5-2}; +class Enc_14d27a : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_27fd0e : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_d7bc34 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vyyyy32; - let Inst{4-0} = Vyyyy32{4-0}; -} -class Enc_93af4c : OpcodeHexagon { - bits <7> Ii; - let Inst{10-4} = Ii{6-0}; - bits <4> Rx16; - let Inst{3-0} = Rx16{3-0}; -} -class Enc_621fba : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Gd32; - let Inst{4-0} = Gd32{4-0}; + let Inst{19-16} = Rs16{3-0}; } -class Enc_5bdd42 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-5} = Ii{6-3}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_e90a15 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{22-22} = n1{0-0}; } -class Enc_ad9bef : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; +class Enc_5a18b3 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{22-22} = n1{1-1}; + let Inst{13-13} = n1{0-0}; } -class Enc_71f1b4 : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_1de724 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; } class Enc_14640c : OpcodeHexagon { bits <11> Ii; @@ -572,165 +718,215 @@ class Enc_14640c : OpcodeHexagon { let Inst{24-22} = n1{3-1}; let Inst{13-13} = n1{0-0}; } -class Enc_31db33 : OpcodeHexagon { - bits <2> Qt4; - let Inst{6-5} = Qt4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_668704 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-22} = n1{3-0}; } -class Enc_65f095 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_800e04 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{13-13} = n1{0-0}; } -class Enc_784502 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_4aca3a : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <3> n1; + let Inst{29-29} = n1{2-2}; + let Inst{26-25} = n1{1-0}; } -class Enc_6413b6 : OpcodeHexagon { +class Enc_f7ea77 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; let Inst{7-1} = Ii{8-2}; bits <3> Ns8; let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{23-23} = n1{1-1}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; let Inst{13-13} = n1{0-0}; } -class Enc_7a0ea6 : OpcodeHexagon { - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; - bits <1> n1; - let Inst{9-9} = n1{0-0}; +class Enc_405228 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <3> n1; + let Inst{28-28} = n1{2-2}; + let Inst{24-23} = n1{1-0}; } -class Enc_84bff1 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_3a2484 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{13-13} = n1{0-0}; } -class Enc_f4413a : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_736575 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{25-23} = n1{2-0}; } -class Enc_78e566 : OpcodeHexagon { - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_8e583a : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{13-13} = n1{0-0}; } -class Enc_437f33 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; +class Enc_3694bd : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-22} = n1{1-0}; } -class Enc_0527db : OpcodeHexagon { +class Enc_a6853f : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <6> n1; + let Inst{29-29} = n1{5-5}; + let Inst{26-25} = n1{4-3}; + let Inst{23-22} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_a42857 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rx16; - let Inst{3-0} = Rx16{3-0}; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{8-8} = n1{0-0}; } -class Enc_420cf3 : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; +class Enc_f6fe0b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{24-22} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; } -class Enc_e39bb2 : OpcodeHexagon { - bits <6> Ii; - let Inst{9-4} = Ii{5-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; +class Enc_3e3989 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{8-8} = n1{0-0}; } -class Enc_1b64fb : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_b909d2 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <7> n1; + let Inst{28-28} = n1{6-6}; + let Inst{25-22} = n1{5-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; } -class Enc_c1d806 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <2> Qe4; - let Inst{6-5} = Qe4{1-0}; +class Enc_f82302 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{23-23} = n1{0-0}; } -class Enc_c6220b : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <3> Nt8; - let Inst{2-0} = Nt8{2-0}; +class Enc_6413b6 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-23} = n1{1-1}; + let Inst{13-13} = n1{0-0}; } -class Enc_322e1b : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <6> II; - let Inst{23-23} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; +class Enc_b78edd : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{8-8} = n1{0-0}; } -class Enc_989021 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; +class Enc_041d7b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-23} = n1{3-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_b1e1fb : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{8-8} = n1{0-0}; } class Enc_178717 : OpcodeHexagon { bits <11> Ii; @@ -744,62 +940,63 @@ class Enc_178717 : OpcodeHexagon { let Inst{13-13} = n1{1-1}; let Inst{8-8} = n1{0-0}; } -class Enc_78cbf0 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_052c7d : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; +class Enc_5de85f : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; } -class Enc_fcf7a7 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; +class Enc_9e4c3f : OpcodeHexagon { + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rd16; + let Inst{19-16} = Rd16{3-0}; } -class Enc_55355c : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{4-0} = Rtt32{4-0}; +class Enc_66bce1 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rd16; + let Inst{11-8} = Rd16{3-0}; } -class Enc_211aaa : OpcodeHexagon { +class Enc_69d63b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_ad1c74 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_a27588 : OpcodeHexagon { bits <11> Ii; let Inst{26-25} = Ii{10-9}; let Inst{13-5} = Ii{8-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; } -class Enc_6185fe : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_1f5d8f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } class Enc_74aef2 : OpcodeHexagon { bits <4> Ii; @@ -811,127 +1008,123 @@ class Enc_74aef2 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_cd4705 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; +class Enc_6b197f : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_2ebe3b : OpcodeHexagon { +class Enc_5cd7e9 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_9e2e1c : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_3d5b28 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_bd1cbc : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_5ab2be : OpcodeHexagon { +class Enc_de0214 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_fef969 : OpcodeHexagon { - bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_74d4e5 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_63eaeb : OpcodeHexagon { - bits <2> Ii; - let Inst{1-0} = Ii{1-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; +class Enc_e83554 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_95441f : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; +class Enc_152467 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_372c9d : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; +class Enc_2d7491 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_7eee72 : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_4dff07 : OpcodeHexagon { - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; +class Enc_70b24b : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_04c959 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; -} -class Enc_b62ef7 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_71f1b4 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_2b518f : OpcodeHexagon { - bits <32> Ii; - let Inst{27-16} = Ii{31-20}; - let Inst{13-0} = Ii{19-6}; -} -class Enc_b388cf : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; +class Enc_211aaa : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_ad1c74 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; -} -class Enc_74d4e5 : OpcodeHexagon { +class Enc_e0a47a : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; bits <5> Rd32; @@ -939,14 +1132,6 @@ class Enc_74d4e5 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_c90aca : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} class Enc_222336 : OpcodeHexagon { bits <4> Ii; let Inst{8-5} = Ii{3-0}; @@ -955,338 +1140,162 @@ class Enc_222336 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_5e87ce : OpcodeHexagon { +class Enc_25bef0 : OpcodeHexagon { bits <16> Ii; - let Inst{23-22} = Ii{15-14}; + let Inst{26-25} = Ii{15-14}; let Inst{20-16} = Ii{13-9}; let Inst{13-5} = Ii{8-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_158beb : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{4-0} = Vv32{4-0}; -} -class Enc_f7ea77 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_245865 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_88d4d9 : OpcodeHexagon { - bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_226535 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; +class Enc_fa3ba4 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-5} = Ii{11-3}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_31aa6a : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_b05839 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_397f23 : OpcodeHexagon { - bits <8> Ii; - let Inst{13-13} = Ii{7-7}; - let Inst{7-3} = Ii{6-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_865390 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_5bdd42 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_98c0b8 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_509701 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-5} = Ii{11-3}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_bfbf03 : OpcodeHexagon { - bits <2> Qs4; - let Inst{9-8} = Qs4{1-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; +class Enc_8df4be : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_ecbcc8 : OpcodeHexagon { +class Enc_2a3787 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; -} -class Enc_f5e933 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_3fc427 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_01d3d0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_b0e9d8 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_27fd0e : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_1bd127 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vdddd32; - let Inst{4-0} = Vdddd32{4-0}; -} -class Enc_3694bd : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{23-22} = n1{1-0}; -} -class Enc_a42857 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{24-22} = n1{3-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_b7fad3 : OpcodeHexagon { - bits <2> Pv4; - let Inst{9-8} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + let Inst{20-16} = Rx32{4-0}; } -class Enc_223005 : OpcodeHexagon { +class Enc_3d920a : OpcodeHexagon { bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; + let Inst{8-5} = Ii{5-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_9e4c3f : OpcodeHexagon { - bits <6> II; - let Inst{13-8} = II{5-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rd16; - let Inst{19-16} = Rd16{3-0}; +class Enc_4f4ed7 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_8b8d61 : OpcodeHexagon { +class Enc_a21d47 : OpcodeHexagon { bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; + let Inst{10-5} = Ii{5-0}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; -} -class Enc_88c16c : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; + let Inst{4-0} = Rd32{4-0}; } -class Enc_770858 : OpcodeHexagon { - bits <2> Ps4; - let Inst{6-5} = Ps4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_f4413a : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_bd811a : OpcodeHexagon { +class Enc_acd6ed : OpcodeHexagon { + bits <9> Ii; + let Inst{10-5} = Ii{8-3}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Cd32; - let Inst{4-0} = Cd32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_b05839 : OpcodeHexagon { +class Enc_9d1247 : OpcodeHexagon { bits <7> Ii; let Inst{8-5} = Ii{6-3}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_bc03e5 : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_412ff0 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rxx32; - let Inst{12-8} = Rxx32{4-0}; -} -class Enc_ef601b : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; -} -class Enc_c9a18e : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_be32a5 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_e6abcf : OpcodeHexagon { +class Enc_a198f6 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-5} = Ii{6-1}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; -} -class Enc_d6990d : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_6c9440 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; +class Enc_733b27 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_0d8adb : OpcodeHexagon { +class Enc_f82eaf : OpcodeHexagon { bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_50e578 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; + let Inst{10-5} = Ii{7-2}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_1cf4ca : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_48b75f : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} class Enc_b97f71 : OpcodeHexagon { bits <6> Ii; let Inst{8-5} = Ii{5-2}; @@ -1297,379 +1306,267 @@ class Enc_b97f71 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_9d1247 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-5} = Ii{6-3}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_7b7ba8 : OpcodeHexagon { - bits <2> Qu4; - let Inst{9-8} = Qu4{1-0}; +class Enc_d44e31 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{4-0} = Rt32{4-0}; } -class Enc_f7430e : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; +class Enc_163a3c : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; -} -class Enc_e7581c : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_2301d6 : OpcodeHexagon { - bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{8-8} = Ii{0-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + let Inst{4-0} = Rt32{4-0}; } -class Enc_c31910 : OpcodeHexagon { +class Enc_226535 : OpcodeHexagon { bits <8> Ii; - let Inst{23-21} = Ii{7-5}; - let Inst{13-13} = Ii{4-4}; - let Inst{7-5} = Ii{3-1}; - let Inst{3-3} = Ii{0-0}; - bits <5> II; - let Inst{12-8} = II{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_2f2f04 : OpcodeHexagon { - bits <1> Ii; - let Inst{5-5} = Ii{0-0}; - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_8d8a30 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; + let Inst{12-7} = Ii{7-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{4-0} = Rt32{4-0}; } -class Enc_2d7491 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-5} = Ii{10-2}; +class Enc_46c951 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> II; + let Inst{4-0} = II{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; } -class Enc_a803e0 : OpcodeHexagon { +class Enc_e66a97 : OpcodeHexagon { bits <7> Ii; let Inst{12-7} = Ii{6-1}; - bits <8> II; - let Inst{13-13} = II{7-7}; - let Inst{6-0} = II{6-0}; + bits <5> II; + let Inst{4-0} = II{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } -class Enc_45364e : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_84b2cd : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_b909d2 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <7> n1; - let Inst{28-28} = n1{6-6}; - let Inst{25-22} = n1{5-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; +class Enc_f394d3 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; } -class Enc_e6c957 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_04c959 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; } -class Enc_0d8870 : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_323f2d : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; } -class Enc_9fae8a : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_4f677b : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_18c338 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <8> II; - let Inst{22-16} = II{7-1}; - let Inst{13-13} = II{0-0}; +class Enc_7fa7f6 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; } -class Enc_5ccba9 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; +class Enc_6185fe : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; bits <6> II; - let Inst{13-13} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_0ed752 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Cdd32; - let Inst{4-0} = Cdd32{4-0}; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_143445 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; +class Enc_da664b : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_3a3d62 : OpcodeHexagon { +class Enc_84bff1 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_3e3989 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{25-22} = n1{4-1}; - let Inst{8-8} = n1{0-0}; +class Enc_2301d6 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_152467 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; +class Enc_2e1979 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; } -class Enc_9ac432 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; +class Enc_2a7b91 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Pu4; - let Inst{7-6} = Pu4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_a90628 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_f37377 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; - bits <8> II; - let Inst{13-13} = II{7-7}; - let Inst{6-0} = II{6-0}; +class Enc_98c0b8 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_a198f6 : OpcodeHexagon { - bits <7> Ii; - let Inst{10-5} = Ii{6-1}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; +class Enc_b7fad3 : OpcodeHexagon { + bits <2> Pv4; + let Inst{9-8} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_4e4a80 : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; +class Enc_a75aa6 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; + let Inst{12-8} = Rt32{4-0}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{4-0} = Vvv32{4-0}; -} -class Enc_3dac0b : OpcodeHexagon { - bits <2> Qt4; - let Inst{6-5} = Qt4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; } -class Enc_e38e1f : OpcodeHexagon { +class Enc_c90aca : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; - bits <2> Pu4; - let Inst{22-21} = Pu4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_f8ecf9 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{20-16} = Vvv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; } -class Enc_7f1a05 : OpcodeHexagon { - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; +class Enc_61f0b0 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Ry32; - let Inst{12-8} = Ry32{4-0}; -} -class Enc_2df31d : OpcodeHexagon { - bits <8> Ii; - let Inst{9-4} = Ii{7-2}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_25bef0 : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_f82302 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{23-23} = n1{0-0}; -} -class Enc_44271f : OpcodeHexagon { - bits <5> Gs32; - let Inst{20-16} = Gs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; } -class Enc_83ee64 : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; +class Enc_a568d4 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; } -class Enc_adf111 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_3d5b28 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <2> Qx4; - let Inst{1-0} = Qx4{1-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_46c951 : OpcodeHexagon { +class Enc_322e1b : OpcodeHexagon { bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <5> II; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{23-23} = II{5-5}; let Inst{4-0} = II{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; } -class Enc_5d6c34 : OpcodeHexagon { +class Enc_420cf3 : OpcodeHexagon { bits <6> Ii; - let Inst{13-8} = Ii{5-0}; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; } -class Enc_4df4e9 : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; +class Enc_277737 : OpcodeHexagon { + bits <8> Ii; + let Inst{22-21} = Ii{7-6}; + let Inst{13-13} = Ii{5-5}; + let Inst{7-5} = Ii{4-2}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_263841 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_91b9fe : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; } class Enc_a7b8e8 : OpcodeHexagon { bits <6> Ii; @@ -1683,175 +1580,151 @@ class Enc_a7b8e8 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_2b3f60 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_7f1a05 : OpcodeHexagon { + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ry32; + let Inst{12-8} = Ry32{4-0}; +} +class Enc_1b64fb : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_ad1831 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_5c124a : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <2> Px4; - let Inst{6-5} = Px4{1-0}; } -class Enc_bd1cbc : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_c85e2a : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_fda92c : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; } -class Enc_a30110 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_bc03e5 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_33f8ba : OpcodeHexagon { - bits <8> Ii; - let Inst{12-8} = Ii{7-3}; - let Inst{4-2} = Ii{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_541f26 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; } -class Enc_690862 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; +class Enc_78cbf0 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; let Inst{13-13} = Ii{10-10}; let Inst{7-0} = Ii{9-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } -class Enc_2a3787 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-5} = Ii{10-2}; +class Enc_47ef61 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_d5c73f : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; +class Enc_22c845 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_3f97c8 : OpcodeHexagon { +class Enc_70fb07 : OpcodeHexagon { bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_28a2dc : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{4-0} = Rx32{4-0}; } -class Enc_d50cd3 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; +class Enc_12b6e9 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_729ff7 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_1aa186 : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_217147 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; } -class Enc_b9c5fb : OpcodeHexagon { +class Enc_8dec2e : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_f394d3 : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_0cb018 : OpcodeHexagon { - bits <5> Cs32; - let Inst{20-16} = Cs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_541f26 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_724154 : OpcodeHexagon { - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_179b35 : OpcodeHexagon { +class Enc_b388cf : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_585242 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-13} = Ii{5-5}; - let Inst{7-3} = Ii{4-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_e07374 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_cf1927 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } class Enc_b84c4c : OpcodeHexagon { bits <6> Ii; @@ -1864,121 +1737,87 @@ class Enc_b84c4c : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_8203bb : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <8> II; - let Inst{13-13} = II{7-7}; - let Inst{6-0} = II{6-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_e66a97 : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; +class Enc_a1e29d : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; bits <5> II; - let Inst{4-0} = II{4-0}; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; -} -class Enc_8c2412 : OpcodeHexagon { - bits <2> Ps4; - let Inst{6-5} = Ps4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_284ebb : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_733b27 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{4-0} = Rx32{4-0}; } -class Enc_22c845 : OpcodeHexagon { - bits <14> Ii; - let Inst{10-0} = Ii{13-3}; +class Enc_179b35 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{4-0} = Rx32{4-0}; } -class Enc_ed5027 : OpcodeHexagon { +class Enc_143a3c : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <5> Gdd32; - let Inst{4-0} = Gdd32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; } -class Enc_9b0bc1 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_c85e2a : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_ea4c54 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; +class Enc_da8d43 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; } -class Enc_b72622 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_cc449f : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_569cfe : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; +class Enc_585242 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_96ce4f : OpcodeHexagon { +class Enc_52a5dd : OpcodeHexagon { bits <4> Ii; let Inst{6-3} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_143a3c : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <6> II; - let Inst{23-21} = II{5-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} class Enc_57a33e : OpcodeHexagon { bits <9> Ii; let Inst{13-13} = Ii{8-8}; @@ -1990,206 +1829,145 @@ class Enc_57a33e : OpcodeHexagon { bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; } -class Enc_311abd : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; +class Enc_9a33d5 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_e8c45e : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; } -class Enc_a1640c : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_b886fd : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_de0214 : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-5} = Ii{9-1}; +class Enc_f44229 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_daea09 : OpcodeHexagon { - bits <17> Ii; - let Inst{23-22} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-1} = Ii{8-2}; - bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; +class Enc_31aa6a : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_fda92c : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; +class Enc_397f23 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } -class Enc_831a7d : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; - bits <2> Pe4; - let Inst{6-5} = Pe4{1-0}; -} -class Enc_11a146 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b15941 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; +class Enc_7eaeb6 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_b78edd : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-23} = n1{2-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_a27588 : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-5} = Ii{8-0}; +class Enc_8dbdfe : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_2a7b91 : OpcodeHexagon { +class Enc_65f095 : OpcodeHexagon { bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{8-8} = Ii{0-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_b43b67 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <2> Qx4; - let Inst{6-5} = Qx4{1-0}; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_4aca3a : OpcodeHexagon { +class Enc_448f7f : OpcodeHexagon { bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <3> n1; - let Inst{29-29} = n1{2-2}; - let Inst{26-25} = n1{1-0}; -} -class Enc_b38ffc : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_cda00a : OpcodeHexagon { - bits <12> Ii; - let Inst{19-16} = Ii{11-8}; - let Inst{12-5} = Ii{7-0}; - bits <2> Pu4; - let Inst{22-21} = Pu4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_2fbf3c : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; } -class Enc_70b24b : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; +class Enc_d5c73f : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_2ae154 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_b15941 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_50b5ac : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; + let Inst{20-16} = Rx32{4-0}; } -class Enc_2ea740 : OpcodeHexagon { +class Enc_10bc21 : OpcodeHexagon { bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; + let Inst{6-3} = Ii{3-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_08d755 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; +class Enc_4df4e9 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_1178da : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } class Enc_8dbe85 : OpcodeHexagon { bits <1> Mu2; @@ -2199,275 +1977,299 @@ class Enc_8dbe85 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_5a18b3 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{22-22} = n1{1-1}; - let Inst{13-13} = n1{0-0}; +class Enc_96ce4f : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_14d27a : OpcodeHexagon { - bits <5> II; - let Inst{12-8} = II{4-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; +class Enc_c7cd90 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_a05677 : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; +class Enc_ce6828 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_f0cca7 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <6> II; - let Inst{20-16} = II{5-1}; - let Inst{13-13} = II{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_500cb0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_7e5a82 : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_12b6e9 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_6f70ca : OpcodeHexagon { - bits <8> Ii; - let Inst{8-4} = Ii{7-3}; -} -class Enc_7222b7 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; } -class Enc_e3b0c4 : OpcodeHexagon { - +class Enc_928ca1 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_a255dc : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_395cc4 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_cb785b : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_85bf58 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_cb4b4e : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; +class Enc_e957fb : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; } -class Enc_1f5d8f : OpcodeHexagon { +class Enc_935d9b : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_9cdba7 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_052c7d : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_5cd7e9 : OpcodeHexagon { +class Enc_0d8870 : OpcodeHexagon { bits <12> Ii; let Inst{26-25} = Ii{11-10}; - let Inst{13-5} = Ii{9-1}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; -} -class Enc_454a26 : OpcodeHexagon { - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_a6853f : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <6> n1; - let Inst{29-29} = n1{5-5}; - let Inst{26-25} = n1{4-3}; - let Inst{23-22} = n1{2-1}; - let Inst{13-13} = n1{0-0}; +class Enc_91b9fe : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_c175d0 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; +class Enc_e26546 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_16c48b : OpcodeHexagon { +class Enc_143445 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_79b8c8 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; -} -class Enc_895bd9 : OpcodeHexagon { - bits <2> Qu4; - let Inst{9-8} = Qu4{1-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_ea23e4 : OpcodeHexagon { - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_4dc228 : OpcodeHexagon { - bits <9> Ii; - let Inst{12-8} = Ii{8-4}; - let Inst{4-3} = Ii{3-2}; - bits <10> II; - let Inst{20-16} = II{9-5}; - let Inst{7-5} = II{4-2}; - let Inst{1-0} = II{1-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_10bc21 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; +class Enc_db40cd : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_1aaec1 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; +class Enc_690862 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_3f97c8 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_329361 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_223005 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_cd82bc : OpcodeHexagon { + bits <4> Ii; + let Inst{21-21} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_729ff7 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_d2c7f1 : OpcodeHexagon { +class Enc_8c6530 : OpcodeHexagon { bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; - bits <2> Pe4; - let Inst{6-5} = Pe4{1-0}; } -class Enc_3680c2 : OpcodeHexagon { - bits <7> Ii; - let Inst{11-5} = Ii{6-0}; +class Enc_d50cd3 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_1ef990 : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_dbd70c : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8b8d61 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_c31910 : OpcodeHexagon { + bits <8> Ii; + let Inst{23-21} = Ii{7-5}; + let Inst{13-13} = Ii{4-4}; + let Inst{7-5} = Ii{3-1}; + let Inst{3-3} = Ii{0-0}; + bits <5> II; + let Inst{12-8} = II{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_e957fb : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; +class Enc_9fae8a : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a1640c : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_fef969 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{5-5} = Ii{0-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_c0cdde : OpcodeHexagon { - bits <9> Ii; +class Enc_b0e9d8 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; let Inst{13-5} = Ii{8-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; } -class Enc_c9e3bc : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; +class Enc_b4e6cf : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1cf4ca : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; + let Inst{12-8} = Rt32{4-0}; } -class Enc_2e1979 : OpcodeHexagon { +class Enc_6339d5 : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; let Inst{7-7} = Ii{0-0}; @@ -2475,28 +2277,21 @@ class Enc_2e1979 : OpcodeHexagon { let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_0b2e5b : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{4-0} = Rt32{4-0}; } -class Enc_6f83e7 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; +class Enc_44215c : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_6339d5 : OpcodeHexagon { +class Enc_47ee5e : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; let Inst{7-7} = Ii{0-0}; @@ -2506,108 +2301,141 @@ class Enc_6339d5 : OpcodeHexagon { let Inst{20-16} = Rs32{4-0}; bits <5> Ru32; let Inst{12-8} = Ru32{4-0}; - bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; } -class Enc_d483b9 : OpcodeHexagon { - bits <1> Ii; - let Inst{5-5} = Ii{0-0}; - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; +class Enc_50b5ac : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; } -class Enc_51635c : OpcodeHexagon { - bits <7> Ii; - let Inst{8-4} = Ii{6-2}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; +class Enc_1a9974 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; } -class Enc_e26546 : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_d7dc10 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_70fb07 : OpcodeHexagon { +class Enc_8203bb : OpcodeHexagon { bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; + let Inst{12-7} = Ii{5-0}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_6c9ee0 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_d7a65e : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_fa3ba4 : OpcodeHexagon { - bits <14> Ii; - let Inst{26-25} = Ii{13-12}; - let Inst{13-5} = Ii{11-3}; +class Enc_a803e0 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; } -class Enc_44661f : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_f20719 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_277737 : OpcodeHexagon { +class Enc_f37377 : OpcodeHexagon { bits <8> Ii; - let Inst{22-21} = Ii{7-6}; - let Inst{13-13} = Ii{5-5}; - let Inst{7-5} = Ii{4-2}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; + let Inst{12-7} = Ii{7-2}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; } -class Enc_5c124a : OpcodeHexagon { - bits <19> Ii; - let Inst{26-25} = Ii{18-17}; - let Inst{20-16} = Ii{16-12}; - let Inst{13-13} = Ii{11-11}; - let Inst{7-0} = Ii{10-3}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_5ccba9 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_928ca1 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_8bcba4 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; } -class Enc_da664b : OpcodeHexagon { +class Enc_eca7c8 : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; let Inst{7-7} = Ii{0-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_9ea4cf : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; } -class Enc_47ee5e : OpcodeHexagon { +class Enc_724154 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_c6220b : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Ru32; @@ -2615,776 +2443,1334 @@ class Enc_47ee5e : OpcodeHexagon { bits <3> Nt8; let Inst{2-0} = Nt8{2-0}; } -class Enc_8bcba4 : OpcodeHexagon { +class Enc_7eb485 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; bits <6> II; let Inst{5-0} = II{5-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_c7a204 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; bits <5> Re32; let Inst{20-16} = Re32{4-0}; } -class Enc_3a2484 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-23} = n1{2-1}; - let Inst{13-13} = n1{0-0}; +class Enc_55355c : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; } -class Enc_a5ed8a : OpcodeHexagon { +class Enc_f79415 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_645d54 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_cb9321 : OpcodeHexagon { - bits <16> Ii; - let Inst{27-21} = Ii{15-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_b72622 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_11a146 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_668704 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; +class Enc_93af4c : OpcodeHexagon { + bits <7> Ii; + let Inst{10-4} = Ii{6-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_0527db : OpcodeHexagon { bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-22} = n1{3-0}; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; } -class Enc_a7341a : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; +class Enc_2df31d : OpcodeHexagon { + bits <8> Ii; + let Inst{9-4} = Ii{7-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; } -class Enc_5eac98 : OpcodeHexagon { +class Enc_97d666 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_1f5ba6 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_63eaeb : OpcodeHexagon { + bits <2> Ii; + let Inst{1-0} = Ii{1-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_ed48be : OpcodeHexagon { + bits <2> Ii; + let Inst{6-5} = Ii{1-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_399e12 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_ee5ed0 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <2> n1; + let Inst{9-8} = n1{1-0}; +} +class Enc_e39bb2 : OpcodeHexagon { bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + let Inst{9-4} = Ii{5-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; } -class Enc_02553a : OpcodeHexagon { +class Enc_7a0ea6 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <1> n1; + let Inst{9-9} = n1{0-0}; +} +class Enc_53dca9 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_c175d0 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_2fbf3c : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_86a14b : OpcodeHexagon { + bits <8> Ii; + let Inst{7-3} = Ii{7-3}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_2bae10 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_51635c : OpcodeHexagon { bits <7> Ii; - let Inst{11-5} = Ii{6-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + let Inst{8-4} = Ii{6-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; } -class Enc_acd6ed : OpcodeHexagon { +class Enc_b38ffc : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_f55a0c : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_6f70ca : OpcodeHexagon { + bits <8> Ii; + let Inst{8-4} = Ii{7-3}; +} +class Enc_84d359 : OpcodeHexagon { + bits <4> Ii; + let Inst{3-0} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_b8309d : OpcodeHexagon { bits <9> Ii; - let Inst{10-5} = Ii{8-3}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + let Inst{8-3} = Ii{8-3}; + bits <3> Rtt8; + let Inst{2-0} = Rtt8{2-0}; } -class Enc_8e583a : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; +class Enc_625deb : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-23} = n1{3-1}; - let Inst{13-13} = n1{0-0}; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; } -class Enc_b886fd : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_87c142 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; } -class Enc_24a7dc : OpcodeHexagon { +class Enc_a6ce9c : OpcodeHexagon { + bits <6> Ii; + let Inst{3-0} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_2146c1 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qss8; + let Inst{2-0} = Qss8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_843e80 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <3> Qxx8; + let Inst{2-0} = Qxx8{2-0}; +} +class Enc_1f3376 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_8e9fbd : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_57e245 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; } -class Enc_2d829e : OpcodeHexagon { - bits <14> Ii; - let Inst{10-0} = Ii{13-3}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_274a4c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; } -class Enc_4f4ed7 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-5} = Ii{10-2}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_fbacc2 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; } -class Enc_84b2cd : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; - bits <5> II; - let Inst{4-0} = II{4-0}; +class Enc_2a736a : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_b8513b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_b5e54d : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } -class Enc_8dbdfe : OpcodeHexagon { - bits <8> Ii; - let Inst{13-13} = Ii{7-7}; - let Inst{7-3} = Ii{6-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_50e578 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_90cd8b : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_bd0b33 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; +class Enc_b5b643 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; } -class Enc_8b8927 : OpcodeHexagon { +class Enc_2516bf : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_8d04c3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2ad23d : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_85daf5 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_e570b0 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_41dcc3 : OpcodeHexagon { bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3126d7 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; bits <5> Vv32; - let Inst{4-0} = Vv32{4-0}; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; } -class Enc_c7cd90 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_1cd70f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_12dd8f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_8d5d98 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_fc563d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_c84567 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_334c2b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3c46e8 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_129701 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_790d6e : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_880793 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_a265b7 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_6b1bc4 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_b2ffce : OpcodeHexagon { + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_fde0e3 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_b3bac4 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_e7c9de : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; +} +class Enc_5c3a80 : OpcodeHexagon { + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_8f7cc3 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{10-8} = Qtt8{2-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} +class Enc_f106e0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <5> Vt32; + let Inst{13-9} = Vt32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; +} +class Enc_7db2f8 : OpcodeHexagon { + bits <5> Vu32; + let Inst{13-9} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_405228 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <3> n1; - let Inst{28-28} = n1{2-2}; - let Inst{24-23} = n1{1-0}; +class Enc_37c406 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <4> Vdd16; + let Inst{7-4} = Vdd16{3-0}; } -class Enc_81ac1d : OpcodeHexagon { - bits <24> Ii; - let Inst{24-16} = Ii{23-15}; - let Inst{13-1} = Ii{14-2}; +class Enc_72a92d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; } -class Enc_395cc4 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; +class Enc_d7e8ba : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_ce4c54 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3a81ac : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_a51a9a : OpcodeHexagon { - bits <8> Ii; - let Inst{12-8} = Ii{7-3}; - let Inst{4-2} = Ii{2-0}; +class Enc_6c4697 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_d44e31 : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_b0e553 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5883d0 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; } -class Enc_f77fbc : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; +class Enc_9a895f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_f3adb6 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b5d5a7 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; } -class Enc_d2216a : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_5b76ab : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_85bf58 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_17a474 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_71bb9b : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; +class Enc_9a9d62 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_52a5dd : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_3a527f : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_5e2823 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_c39a8b : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; } -class Enc_28a2dc : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_908985 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; + let Inst{20-16} = Rx32{4-0}; } -class Enc_5138b3 : OpcodeHexagon { +class Enc_e8ddd5 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6a4549 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; } -class Enc_84d359 : OpcodeHexagon { - bits <4> Ii; - let Inst{3-0} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; +class Enc_932b58 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; } -class Enc_e07374 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_124cac : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; } -class Enc_e0820b : OpcodeHexagon { +class Enc_aceeef : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_2c3281 : OpcodeHexagon { + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_a4ae28 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; + let Inst{12-8} = Vv32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_c1652e : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_9aae4a : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qd8; + let Inst{2-0} = Qd8{2-0}; +} +class Enc_dcfcbb : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{7-3} = Vd32{4-0}; } -class Enc_323f2d : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; +class Enc_a7ca29 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; } -class Enc_1a9974 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{4-0} = Rtt32{4-0}; +class Enc_dd5f9f : OpcodeHexagon { + bits <3> Qtt8; + let Inst{2-0} = Qtt8{2-0}; + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; } -class Enc_5de85f : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; +class Enc_7dc746 : OpcodeHexagon { + bits <3> Quu8; + let Inst{10-8} = Quu8{2-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; } -class Enc_dd766a : OpcodeHexagon { +class Enc_fa5efc : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_aac08c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_9a8c1f : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; + let Inst{7-3} = Vdd32{4-0}; } -class Enc_0b51ce : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_a9eee0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; } -class Enc_b4e6cf : OpcodeHexagon { +class Enc_9ce456 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_44215c : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_96f0fd : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qdd8; + let Inst{2-0} = Qdd8{2-0}; } -class Enc_0aa344 : OpcodeHexagon { - bits <5> Gss32; - let Inst{20-16} = Gss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_a662ae : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; } -class Enc_a21d47 : OpcodeHexagon { - bits <6> Ii; - let Inst{10-5} = Ii{5-0}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_ec09c9 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; } -class Enc_cc449f : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_400b42 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; } -class Enc_645d54 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_a5ed8a : OpcodeHexagon { bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_667b39 : OpcodeHexagon { - bits <5> Css32; - let Inst{20-16} = Css32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_134437 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qt4; + let Inst{23-22} = Qt4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; } -class Enc_927852 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_bfbf03 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; } -class Enc_163a3c : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_7222b7 : OpcodeHexagon { bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; } -class Enc_a75aa6 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_f3f408 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_a255dc : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2ebe3b : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_b087ac : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_8d8a30 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } -class Enc_691712 : OpcodeHexagon { +class Enc_58a8bf : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; bits <2> Pv4; let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_b1e1fb : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-23} = n1{3-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_1f19b5 : OpcodeHexagon { - bits <5> Ii; - let Inst{9-5} = Ii{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_b8c967 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_fb6577 : OpcodeHexagon { - bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_2bae10 : OpcodeHexagon { - bits <4> Ii; - let Inst{10-8} = Ii{3-1}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_c4dc92 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_f8c1c4 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_03833b : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_c9e3bc : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; } -class Enc_dbd70c : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_27b757 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; } -class Enc_f6fe0b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{24-22} = n1{4-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; +class Enc_865390 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_9e2e1c : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; +class Enc_1ef990 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_8df4be : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-5} = Ii{9-1}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_66bce1 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> Rd16; - let Inst{11-8} = Rd16{3-0}; +class Enc_b62ef7 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_b8309d : OpcodeHexagon { - bits <9> Ii; - let Inst{8-3} = Ii{8-3}; - bits <3> Rtt8; - let Inst{2-0} = Rtt8{2-0}; +class Enc_d15d19 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_5e8512 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; +class Enc_f77fbc : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; } -class Enc_4f677b : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; +class Enc_f7430e : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; } -class Enc_3d920a : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_784502 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_e83554 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; +class Enc_372c9d : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_ed48be : OpcodeHexagon { - bits <2> Ii; - let Inst{6-5} = Ii{1-0}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; +class Enc_1aaec1 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_f8c1c4 : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; +class Enc_cf1927 : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_1aa186 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_2ea740 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; } -class Enc_134437 : OpcodeHexagon { - bits <2> Qs4; - let Inst{9-8} = Qs4{1-0}; - bits <2> Qt4; - let Inst{23-22} = Qt4{1-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; +class Enc_0b51ce : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_f3f408 : OpcodeHexagon { +class Enc_4dff07 : OpcodeHexagon { + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_ff3442 : OpcodeHexagon { bits <4> Ii; let Inst{13-13} = Ii{3-3}; let Inst{10-8} = Ii{2-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; +} +class Enc_6c9ee0 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_44661f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_e7581c : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } -class Enc_97d666 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; +class Enc_45364e : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_f82eaf : OpcodeHexagon { - bits <8> Ii; - let Inst{10-5} = Ii{7-2}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; +class Enc_f8ecf9 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{20-16} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; } -class Enc_69d63b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; +class Enc_a90628 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; } -class Enc_f79415 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_b43b67 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qx4; + let Inst{6-5} = Qx4{1-0}; } -class Enc_ce6828 : OpcodeHexagon { - bits <14> Ii; - let Inst{26-25} = Ii{13-12}; - let Inst{13-13} = Ii{11-11}; - let Inst{7-0} = Ii{10-3}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_c1d806 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qe4; + let Inst{6-5} = Qe4{1-0}; } -class Enc_800e04 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{25-22} = n1{4-1}; - let Inst{13-13} = n1{0-0}; +class Enc_e0820b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_ad1831 : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_71bb9b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; } -class Enc_0fa531 : OpcodeHexagon { - bits <15> Ii; - let Inst{21-21} = Ii{14-14}; - let Inst{13-13} = Ii{13-13}; - let Inst{11-1} = Ii{12-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_3fc427 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; } -class Enc_7eaeb6 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_a30110 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_0b2e5b : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_7b7ba8 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_f55a0c : OpcodeHexagon { - bits <6> Ii; - let Inst{11-8} = Ii{5-2}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; +class Enc_895bd9 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; } -class Enc_f20719 : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; - bits <6> II; - let Inst{13-13} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_c4dc92 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_eafd18 : OpcodeHexagon { - bits <5> II; - let Inst{12-8} = II{4-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; +class Enc_0f8bab : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; } -class Enc_7b523d : OpcodeHexagon { +class Enc_adf111 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_b087ac : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_5138b3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_8c2412 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_770858 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_989021 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_24a7dc : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; bits <5> Vv32; let Inst{23-19} = Vv32{4-0}; bits <3> Rt8; let Inst{18-16} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_aad80c : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_d6990d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; bits <5> Vxx32; let Inst{4-0} = Vxx32{4-0}; } -class Enc_47ef61 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; +class Enc_0e41fa : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } class Enc_cc857d : OpcodeHexagon { bits <5> Vuu32; @@ -3394,85 +3780,225 @@ class Enc_cc857d : OpcodeHexagon { bits <5> Vx32; let Inst{4-0} = Vx32{4-0}; } -class Enc_7fa7f6 : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; +class Enc_a7341a : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; } -class Enc_0f8bab : OpcodeHexagon { +class Enc_95441f : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; bits <2> Qd4; let Inst{1-0} = Qd4{1-0}; } -class Enc_7eb485 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_eaa9f8 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; } -class Enc_864a5a : OpcodeHexagon { - bits <9> Ii; - let Inst{12-8} = Ii{8-4}; - let Inst{4-3} = Ii{3-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_8b8927 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; } -class Enc_c2b48e : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_158beb : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; } -class Enc_8c6530 : OpcodeHexagon { +class Enc_28dcbb : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_4e4a80 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_217147 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_569cfe : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_263841 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; } -class Enc_448f7f : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_245865 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_cd4705 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_7b523d : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_1178da : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_4b39e4 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_310ba1 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_01d3d0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; } -class Enc_da8d43 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-13} = Ii{5-5}; - let Inst{7-3} = Ii{4-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_5e8512 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; } -class Enc_a6ce9c : OpcodeHexagon { - bits <6> Ii; - let Inst{3-0} = Ii{5-2}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; +class Enc_31db33 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_6f83e7 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_cb785b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_ad9bef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_2f2f04 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_d483b9 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_1bd127 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vdddd32; + let Inst{4-0} = Vdddd32{4-0}; +} +class Enc_d7bc34 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vyyyy32; + let Inst{4-0} = Vyyyy32{4-0}; } class Enc_3b7631 : OpcodeHexagon { bits <5> Vu32; @@ -3482,20 +4008,67 @@ class Enc_3b7631 : OpcodeHexagon { bits <3> Rx8; let Inst{18-16} = Rx8{2-0}; } -class Enc_eca7c8 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; +class Enc_bddee3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vyyyy32; + let Inst{4-0} = Vyyyy32{4-0}; + bits <3> Rx8; + let Inst{18-16} = Rx8{2-0}; +} +class Enc_dd766a : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_16c48b : OpcodeHexagon { bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; } -class Enc_4b39e4 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; +class Enc_9be1de : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_a641d0 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_3d6d37 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_3dac0b : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; bits <5> Vv32; @@ -3503,3 +4076,117 @@ class Enc_4b39e4 : OpcodeHexagon { bits <5> Vdd32; let Inst{4-0} = Vdd32{4-0}; } +class Enc_500cb0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_efaed8 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; +} +class Enc_802dc0 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_ef601b : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} +class Enc_6baed4 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_691712 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_403871 : OpcodeHexagon { + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2d829e : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_ca3887 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_9e9047 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_7d1542 : OpcodeHexagon { + bits <7> Ss128; + let Inst{22-16} = Ss128{6-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8f7633 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <7> Sd128; + let Inst{6-0} = Sd128{6-0}; +} +class Enc_46f33d : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_d0fe02 : OpcodeHexagon { + bits <5> Rxx32; + let Inst{20-16} = Rxx32{4-0}; + bits <0> sgp10; +} +class Enc_e32517 : OpcodeHexagon { + bits <7> Sss128; + let Inst{22-16} = Sss128{6-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_a705fc : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <7> Sdd128; + let Inst{6-0} = Sdd128{6-0}; +} +class Enc_e6abcf : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_b00112 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_598f6c : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index a49051888c77c..ccc3f98d8378c 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -5,14 +5,14 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// def A2_abs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32)", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -23,7 +23,7 @@ def A2_absp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = abs($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -32,7 +32,7 @@ def A2_abssat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32):sat", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -44,15 +44,15 @@ def A2_add : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; let isCommutable = 1; let isPredicable = 1; } @@ -60,7 +60,7 @@ def A2_addh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -72,7 +72,7 @@ def A2_addh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -84,7 +84,7 @@ def A2_addh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -96,7 +96,7 @@ def A2_addh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -108,7 +108,7 @@ def A2_addh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -121,7 +121,7 @@ def A2_addh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -134,7 +134,7 @@ def A2_addh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -147,7 +147,7 @@ def A2_addh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -160,7 +160,7 @@ def A2_addh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -172,7 +172,7 @@ def A2_addh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -184,7 +184,7 @@ def A2_addh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -197,7 +197,7 @@ def A2_addh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -210,13 +210,13 @@ def A2_addi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { let Inst{31-28} = 0b1011; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isPredicable = 1; let isAdd = 1; let isExtendable = 1; @@ -229,7 +229,7 @@ def A2_addp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -240,7 +240,7 @@ def A2_addpsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -252,7 +252,7 @@ def A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110010; @@ -267,14 +267,14 @@ def A2_addsp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rs32,$Rtt32)", -tc_679309b8, TypeALU64> { +tc_01d44cb2, TypeALU64> { let isPseudo = 1; } def A2_addsph : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:hi", -tc_679309b8, TypeALU64>, Enc_a56825 { +tc_01d44cb2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -284,7 +284,7 @@ def A2_addspl : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:lo", -tc_679309b8, TypeALU64>, Enc_a56825 { +tc_01d44cb2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -294,15 +294,15 @@ def A2_and : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = and($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_and"; let CextOpcode = "A2_and"; let InputType = "reg"; -let BaseOpcode = "A2_and"; let isCommutable = 1; let isPredicable = 1; } @@ -310,7 +310,7 @@ def A2_andir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = and($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011000; let hasNewValue = 1; let opNewValue = 0; @@ -326,7 +326,7 @@ def A2_andp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = and($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -336,7 +336,7 @@ def A2_aslh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = aslh($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000000; let hasNewValue = 1; @@ -348,7 +348,7 @@ def A2_asrh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = asrh($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000001; let hasNewValue = 1; @@ -360,7 +360,7 @@ def A2_combine_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.h)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011100; @@ -372,7 +372,7 @@ def A2_combine_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.l)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011101; @@ -384,7 +384,7 @@ def A2_combine_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.h)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011110; @@ -396,7 +396,7 @@ def A2_combine_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.l)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011111; @@ -408,7 +408,7 @@ def A2_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, s8_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_5a2711e5, TypeALU32_2op>, Enc_18c338 { +tc_713b66bf, TypeALU32_2op>, Enc_18c338 { let Inst{31-23} = 0b011111000; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -423,19 +423,19 @@ def A2_combinew : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = combine($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_be32a5, PredNewRel { +tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101000; -let InputType = "reg"; let BaseOpcode = "A2_combinew"; +let InputType = "reg"; let isPredicable = 1; } def A2_max : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = max($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -447,7 +447,7 @@ def A2_maxp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = max($Rss32,$Rtt32)", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -457,7 +457,7 @@ def A2_maxu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = maxu($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -469,7 +469,7 @@ def A2_maxup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = maxu($Rss32,$Rtt32)", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -479,7 +479,7 @@ def A2_min : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = min($Rt32,$Rs32)", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -491,7 +491,7 @@ def A2_minp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = min($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -501,7 +501,7 @@ def A2_minu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = minu($Rt32,$Rs32)", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -513,7 +513,7 @@ def A2_minup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = minu($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -523,7 +523,7 @@ def A2_neg : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32)", -tc_57890846, TypeALU32_2op> { +tc_c57d9f39, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -533,7 +533,7 @@ def A2_negp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = neg($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000100; } @@ -541,7 +541,7 @@ def A2_negsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32):sat", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -553,7 +553,7 @@ def A2_nop : HInst< (outs), (ins), "nop", -tc_2eabeebe, TypeALU32_2op>, Enc_e3b0c4 { +tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0111111100000000; } @@ -561,7 +561,7 @@ def A2_not : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = not($Rs32)", -tc_57890846, TypeALU32_2op> { +tc_c57d9f39, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -571,7 +571,7 @@ def A2_notp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = not($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000100; } @@ -579,15 +579,15 @@ def A2_or : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = or($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001001; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_or"; let CextOpcode = "A2_or"; let InputType = "reg"; -let BaseOpcode = "A2_or"; let isCommutable = 1; let isPredicable = 1; } @@ -595,7 +595,7 @@ def A2_orir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = or($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011010; let hasNewValue = 1; let opNewValue = 0; @@ -611,7 +611,7 @@ def A2_orp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = or($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -621,7 +621,7 @@ def A2_paddf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; @@ -629,15 +629,15 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -646,24 +646,24 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101001; let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -674,7 +674,7 @@ def A2_paddifnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101001; let isPredicated = 1; @@ -682,9 +682,9 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -695,15 +695,15 @@ def A2_paddit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -714,16 +714,16 @@ def A2_padditnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -734,22 +734,22 @@ def A2_paddt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -757,15 +757,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_pandf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -779,7 +779,7 @@ def A2_pandfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -794,7 +794,7 @@ def A2_pandt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -807,7 +807,7 @@ def A2_pandtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -821,7 +821,7 @@ def A2_porf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -835,7 +835,7 @@ def A2_porfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -850,7 +850,7 @@ def A2_port : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -863,7 +863,7 @@ def A2_portnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -877,7 +877,7 @@ def A2_psubf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -891,7 +891,7 @@ def A2_psubfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -906,7 +906,7 @@ def A2_psubt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -919,7 +919,7 @@ def A2_psubtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -933,7 +933,7 @@ def A2_pxorf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -947,7 +947,7 @@ def A2_pxorfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -962,7 +962,7 @@ def A2_pxort : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -975,7 +975,7 @@ def A2_pxortnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -989,7 +989,7 @@ def A2_roundsat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = round($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_90cd8b { +tc_d61dfdc3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1001,7 +1001,7 @@ def A2_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = sat($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1012,7 +1012,7 @@ def A2_satb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1023,7 +1023,7 @@ def A2_sath : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sath($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1034,7 +1034,7 @@ def A2_satub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satub($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1045,7 +1045,7 @@ def A2_satuh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satuh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1056,22 +1056,22 @@ def A2_sub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011001; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_sub"; let CextOpcode = "A2_sub"; let InputType = "reg"; -let BaseOpcode = "A2_sub"; let isPredicable = 1; } def A2_subh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1083,7 +1083,7 @@ def A2_subh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1095,7 +1095,7 @@ def A2_subh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1107,7 +1107,7 @@ def A2_subh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1119,7 +1119,7 @@ def A2_subh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1132,7 +1132,7 @@ def A2_subh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1145,7 +1145,7 @@ def A2_subh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1158,7 +1158,7 @@ def A2_subh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1171,7 +1171,7 @@ def A2_subh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1183,7 +1183,7 @@ def A2_subh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1195,7 +1195,7 @@ def A2_subh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1208,7 +1208,7 @@ def A2_subh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1221,7 +1221,7 @@ def A2_subp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = sub($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -1230,7 +1230,7 @@ def A2_subri : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = sub(#$Ii,$Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { let Inst{31-22} = 0b0111011001; let hasNewValue = 1; let opNewValue = 0; @@ -1246,7 +1246,7 @@ def A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110110; @@ -1260,7 +1260,7 @@ def A2_svaddh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110000; @@ -1273,7 +1273,7 @@ def A2_svaddhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110001; @@ -1288,7 +1288,7 @@ def A2_svadduhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vadduh($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110011; @@ -1303,7 +1303,7 @@ def A2_svavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32)", -tc_1c80410a, TypeALU32_3op>, Enc_5ab2be { +tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111000; @@ -1317,7 +1317,7 @@ def A2_svavghs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32):rnd", -tc_d08ee0f4, TypeALU32_3op>, Enc_5ab2be { +tc_84a7500d, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111001; @@ -1331,7 +1331,7 @@ def A2_svnavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vnavgh($Rt32,$Rs32)", -tc_1c80410a, TypeALU32_3op>, Enc_bd6011 { +tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111011; @@ -1344,7 +1344,7 @@ def A2_svsubh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110100; @@ -1356,7 +1356,7 @@ def A2_svsubhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110101; @@ -1370,7 +1370,7 @@ def A2_svsubuhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubuh($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110111; @@ -1384,7 +1384,7 @@ def A2_swiz : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = swiz($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -1394,7 +1394,7 @@ def A2_sxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxtb($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000101; let hasNewValue = 1; @@ -1406,7 +1406,7 @@ def A2_sxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxth($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000111; let hasNewValue = 1; @@ -1418,7 +1418,7 @@ def A2_sxtw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = sxtw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100010; } @@ -1426,20 +1426,20 @@ def A2_tfr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = $Rs32", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000011; let hasNewValue = 1; let opNewValue = 0; -let InputType = "reg"; let BaseOpcode = "A2_tfr"; +let InputType = "reg"; let isPredicable = 1; } def A2_tfrcrr : HInst< (outs IntRegs:$Rd32), (ins CtrRegs:$Cs32), "$Rd32 = $Cs32", -tc_b9272d6c, TypeCR>, Enc_0cb018 { +tc_7476d766, TypeCR>, Enc_0cb018 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101010000; let hasNewValue = 1; @@ -1449,14 +1449,14 @@ def A2_tfrf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = $Rs32", -tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1464,15 +1464,15 @@ def A2_tfrfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = $Rs32", -tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1480,7 +1480,7 @@ def A2_tfrih : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.h = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_51436c { +tc_713b66bf, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110010; let hasNewValue = 1; @@ -1491,7 +1491,7 @@ def A2_tfril : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.l = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_51436c { +tc_713b66bf, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110001; let hasNewValue = 1; @@ -1502,7 +1502,7 @@ def A2_tfrp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let BaseOpcode = "A2_tfrp"; let isPredicable = 1; let isPseudo = 1; @@ -1511,7 +1511,7 @@ def A2_tfrpf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4) $Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let BaseOpcode = "A2_tfrp"; @@ -1521,7 +1521,7 @@ def A2_tfrpfnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4.new) $Rdd32 = $Rss32", -tc_1ae57e39, TypeALU32_2op>, PredNewRel { +tc_86173609, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let isPredicatedNew = 1; @@ -1532,7 +1532,7 @@ def A2_tfrpi : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii), "$Rdd32 = #$Ii", -tc_5a2711e5, TypeALU64> { +tc_713b66bf, TypeALU64> { let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; @@ -1542,7 +1542,7 @@ def A2_tfrpt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4) $Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let BaseOpcode = "A2_tfrp"; let isPseudo = 1; @@ -1551,7 +1551,7 @@ def A2_tfrptnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4.new) $Rdd32 = $Rss32", -tc_1ae57e39, TypeALU32_2op>, PredNewRel { +tc_86173609, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedNew = 1; let BaseOpcode = "A2_tfrp"; @@ -1561,7 +1561,7 @@ def A2_tfrrcr : HInst< (outs CtrRegs:$Cd32), (ins IntRegs:$Rs32), "$Cd32 = $Rs32", -tc_434c8e1e, TypeCR>, Enc_bd811a { +tc_49fdfd4b, TypeCR>, Enc_bd811a { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100010001; let hasNewValue = 1; @@ -1571,14 +1571,14 @@ def A2_tfrsi : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii), "$Rd32 = #$Ii", -tc_57890846, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { let Inst{21-21} = 0b0; let Inst{31-24} = 0b01111000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isPredicable = 1; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -1593,13 +1593,13 @@ def A2_tfrt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = $Rs32", -tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1607,14 +1607,14 @@ def A2_tfrtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = $Rs32", -tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1622,7 +1622,7 @@ def A2_vabsh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1631,7 +1631,7 @@ def A2_vabshsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1641,7 +1641,7 @@ def A2_vabsw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1650,7 +1650,7 @@ def A2_vabswsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1660,7 +1660,7 @@ def A2_vaddb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddb($Rss32,$Rtt32)", -tc_946df596, TypeMAPPING> { +tc_5da50c4b, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1668,7 +1668,7 @@ def A2_vaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1677,7 +1677,7 @@ def A2_vaddhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1688,7 +1688,7 @@ def A2_vaddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1697,7 +1697,7 @@ def A2_vaddubs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1708,7 +1708,7 @@ def A2_vadduhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vadduh($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1719,7 +1719,7 @@ def A2_vaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1728,7 +1728,7 @@ def A2_vaddws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1739,7 +1739,7 @@ def A2_vavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1749,7 +1749,7 @@ def A2_vavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):crnd", -tc_002cb246, TypeALU64>, Enc_a56825 { +tc_0dfac0a7, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1759,7 +1759,7 @@ def A2_vavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1769,7 +1769,7 @@ def A2_vavgub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1779,7 +1779,7 @@ def A2_vavgubr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1789,7 +1789,7 @@ def A2_vavguh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1799,7 +1799,7 @@ def A2_vavguhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1809,7 +1809,7 @@ def A2_vavguw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1819,7 +1819,7 @@ def A2_vavguwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1829,7 +1829,7 @@ def A2_vavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1839,7 +1839,7 @@ def A2_vavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):crnd", -tc_002cb246, TypeALU64>, Enc_a56825 { +tc_0dfac0a7, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1849,7 +1849,7 @@ def A2_vavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1859,7 +1859,7 @@ def A2_vcmpbeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1868,7 +1868,7 @@ def A2_vcmpbgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1877,7 +1877,7 @@ def A2_vcmpheq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1886,7 +1886,7 @@ def A2_vcmphgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1895,7 +1895,7 @@ def A2_vcmphgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1904,7 +1904,7 @@ def A2_vcmpweq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1913,7 +1913,7 @@ def A2_vcmpwgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1922,7 +1922,7 @@ def A2_vcmpwgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1931,7 +1931,7 @@ def A2_vconj : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vconj($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -1941,7 +1941,7 @@ def A2_vmaxb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxb($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1951,7 +1951,7 @@ def A2_vmaxh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1961,7 +1961,7 @@ def A2_vmaxub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxub($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1971,7 +1971,7 @@ def A2_vmaxuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1981,7 +1981,7 @@ def A2_vmaxuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -1991,7 +1991,7 @@ def A2_vmaxw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2001,7 +2001,7 @@ def A2_vminb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminb($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2011,7 +2011,7 @@ def A2_vminh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2021,7 +2021,7 @@ def A2_vminub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminub($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2031,7 +2031,7 @@ def A2_vminuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2041,7 +2041,7 @@ def A2_vminuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2051,7 +2051,7 @@ def A2_vminw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2061,7 +2061,7 @@ def A2_vnavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32)", -tc_6132ba3d, TypeALU64>, Enc_ea23e4 { +tc_f098b237, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2071,7 +2071,7 @@ def A2_vnavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2082,7 +2082,7 @@ def A2_vnavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2093,7 +2093,7 @@ def A2_vnavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32)", -tc_6132ba3d, TypeALU64>, Enc_ea23e4 { +tc_f098b237, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2103,7 +2103,7 @@ def A2_vnavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2114,7 +2114,7 @@ def A2_vnavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2125,7 +2125,7 @@ def A2_vraddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vraddub($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2135,7 +2135,7 @@ def A2_vraddub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vraddub($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2146,7 +2146,7 @@ def A2_vrsadub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrsadub($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2156,7 +2156,7 @@ def A2_vrsadub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrsadub($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2167,7 +2167,7 @@ def A2_vsubb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vsubb($Rss32,$Rtt32)", -tc_946df596, TypeMAPPING> { +tc_5da50c4b, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -2175,7 +2175,7 @@ def A2_vsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2184,7 +2184,7 @@ def A2_vsubhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2195,7 +2195,7 @@ def A2_vsubub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2204,7 +2204,7 @@ def A2_vsububs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2215,7 +2215,7 @@ def A2_vsubuhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubuh($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2226,7 +2226,7 @@ def A2_vsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2235,7 +2235,7 @@ def A2_vsubws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2246,14 +2246,14 @@ def A2_xor : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = xor($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001011; let hasNewValue = 1; let opNewValue = 0; -let InputType = "reg"; let BaseOpcode = "A2_xor"; +let InputType = "reg"; let isCommutable = 1; let isPredicable = 1; } @@ -2261,7 +2261,7 @@ def A2_xorp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = xor($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2271,7 +2271,7 @@ def A2_zxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let hasNewValue = 1; let opNewValue = 0; let BaseOpcode = "A2_zxtb"; @@ -2283,7 +2283,7 @@ def A2_zxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxth($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000110; let hasNewValue = 1; @@ -2295,7 +2295,7 @@ def A4_addp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", -tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { +tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010110; @@ -2306,7 +2306,7 @@ def A4_andn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = and($Rt32,~$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001100; @@ -2318,7 +2318,7 @@ def A4_andnp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = and($Rtt32,~$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2327,7 +2327,7 @@ def A4_bitsplit : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = bitsplit($Rs32,$Rt32)", -tc_4414d8b1, TypeALU64>, Enc_be32a5 { +tc_f34c1c21, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100001; @@ -2337,7 +2337,7 @@ def A4_bitspliti : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rdd32 = bitsplit($Rs32,#$Ii)", -tc_4414d8b1, TypeS_2op>, Enc_311abd { +tc_f34c1c21, TypeS_2op>, Enc_311abd { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -2347,14 +2347,14 @@ def A4_boundscheck : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rs32,$Rtt32)", -tc_85d5d03f, TypeALU64> { +tc_4a55d03c, TypeALU64> { let isPseudo = 1; } def A4_boundscheck_hi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2363,7 +2363,7 @@ def A4_boundscheck_lo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2372,7 +2372,7 @@ def A4_cmpbeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2385,7 +2385,7 @@ def A4_cmpbeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmpb.eq($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2398,7 +2398,7 @@ def A4_cmpbgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2410,7 +2410,7 @@ def A4_cmpbgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmpb.gt($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2422,7 +2422,7 @@ def A4_cmpbgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gtu($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2434,7 +2434,7 @@ def A4_cmpbgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmpb.gtu($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2451,7 +2451,7 @@ def A4_cmpheq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2464,7 +2464,7 @@ def A4_cmpheqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.eq($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2482,7 +2482,7 @@ def A4_cmphgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2494,7 +2494,7 @@ def A4_cmphgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.gt($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2511,7 +2511,7 @@ def A4_cmphgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gtu($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2523,7 +2523,7 @@ def A4_cmphgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmph.gtu($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2540,7 +2540,7 @@ def A4_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_5a2711e5, TypeALU32_2op>, Enc_f0cca7 { +tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 { let Inst{31-21} = 0b01111100100; let isExtendable = 1; let opExtendable = 2; @@ -2552,7 +2552,7 @@ def A4_combineir : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rdd32 = combine(#$Ii,$Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { +tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011001; let isExtendable = 1; @@ -2565,7 +2565,7 @@ def A4_combineri : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rdd32 = combine($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { +tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011000; let isExtendable = 1; @@ -2578,7 +2578,7 @@ def A4_cround_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = cround($Rs32,#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -2590,7 +2590,7 @@ def A4_cround_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cround($Rs32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -2602,14 +2602,14 @@ def A4_ext : HInst< (outs), (ins u26_6Imm:$Ii), "immext(#$Ii)", -tc_862b3e70, TypeEXTENDER>, Enc_2b518f { +tc_112d30d6, TypeEXTENDER>, Enc_2b518f { let Inst{31-28} = 0b0000; } def A4_modwrapu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = modwrap($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2621,7 +2621,7 @@ def A4_orn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = or($Rt32,~$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001101; @@ -2633,7 +2633,7 @@ def A4_ornp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = or($Rtt32,~$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2642,7 +2642,7 @@ def A4_paslhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = aslh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000000; @@ -2656,7 +2656,7 @@ def A4_paslhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = aslh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000000; @@ -2671,7 +2671,7 @@ def A4_paslht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = aslh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000000; @@ -2684,7 +2684,7 @@ def A4_paslhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = aslh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000000; @@ -2698,7 +2698,7 @@ def A4_pasrhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = asrh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000001; @@ -2712,7 +2712,7 @@ def A4_pasrhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = asrh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000001; @@ -2727,7 +2727,7 @@ def A4_pasrht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = asrh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000001; @@ -2740,7 +2740,7 @@ def A4_pasrhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = asrh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000001; @@ -2754,7 +2754,7 @@ def A4_psxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000101; @@ -2768,7 +2768,7 @@ def A4_psxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000101; @@ -2783,7 +2783,7 @@ def A4_psxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000101; @@ -2796,7 +2796,7 @@ def A4_psxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000101; @@ -2810,7 +2810,7 @@ def A4_psxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000111; @@ -2824,7 +2824,7 @@ def A4_psxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000111; @@ -2839,7 +2839,7 @@ def A4_psxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000111; @@ -2852,7 +2852,7 @@ def A4_psxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000111; @@ -2866,7 +2866,7 @@ def A4_pzxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000100; @@ -2880,7 +2880,7 @@ def A4_pzxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000100; @@ -2895,7 +2895,7 @@ def A4_pzxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000100; @@ -2908,7 +2908,7 @@ def A4_pzxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000100; @@ -2922,7 +2922,7 @@ def A4_pzxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000110; @@ -2936,7 +2936,7 @@ def A4_pzxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000110; @@ -2951,7 +2951,7 @@ def A4_pzxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000110; @@ -2964,7 +2964,7 @@ def A4_pzxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000110; @@ -2978,7 +2978,7 @@ def A4_rcmpeq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmp.eq($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011010; @@ -2992,7 +2992,7 @@ def A4_rcmpeqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = cmp.eq($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011010; let hasNewValue = 1; @@ -3009,7 +3009,7 @@ def A4_rcmpneq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = !cmp.eq($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011011; @@ -3023,7 +3023,7 @@ def A4_rcmpneqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = !cmp.eq($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011011; let hasNewValue = 1; @@ -3040,7 +3040,7 @@ def A4_round_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3052,7 +3052,7 @@ def A4_round_ri_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii):sat", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3065,7 +3065,7 @@ def A4_round_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3077,7 +3077,7 @@ def A4_round_rr_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32):sat", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3090,7 +3090,7 @@ def A4_subp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", -tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { +tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010111; @@ -3101,7 +3101,7 @@ def A4_tfrcpp : HInst< (outs DoubleRegs:$Rdd32), (ins CtrRegs64:$Css32), "$Rdd32 = $Css32", -tc_b9272d6c, TypeCR>, Enc_667b39 { +tc_7476d766, TypeCR>, Enc_667b39 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101000000; } @@ -3109,7 +3109,7 @@ def A4_tfrpcp : HInst< (outs CtrRegs64:$Cdd32), (ins DoubleRegs:$Rss32), "$Cdd32 = $Rss32", -tc_434c8e1e, TypeCR>, Enc_0ed752 { +tc_49fdfd4b, TypeCR>, Enc_0ed752 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100011001; } @@ -3117,7 +3117,7 @@ def A4_tlbmatch : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Pd4 = tlbmatch($Rss32,$Rt32)", -tc_4837eefb, TypeALU64>, Enc_03833b { +tc_d68dca5c, TypeALU64>, Enc_03833b { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3127,7 +3127,7 @@ def A4_vcmpbeq_any : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3136,7 +3136,7 @@ def A4_vcmpbeqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u8_0Imm:$Ii), "$Pd4 = vcmpb.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3145,7 +3145,7 @@ def A4_vcmpbgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3154,7 +3154,7 @@ def A4_vcmpbgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpb.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3163,7 +3163,7 @@ def A4_vcmpbgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpb.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3172,7 +3172,7 @@ def A4_vcmpheqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3181,7 +3181,7 @@ def A4_vcmphgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3190,7 +3190,7 @@ def A4_vcmphgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmph.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3199,7 +3199,7 @@ def A4_vcmpweqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3208,7 +3208,7 @@ def A4_vcmpwgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3217,7 +3217,7 @@ def A4_vcmpwgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpw.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3226,7 +3226,7 @@ def A4_vrmaxh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3237,7 +3237,7 @@ def A4_vrmaxuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3248,7 +3248,7 @@ def A4_vrmaxuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3259,7 +3259,7 @@ def A4_vrmaxw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3270,7 +3270,7 @@ def A4_vrminh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3281,7 +3281,7 @@ def A4_vrminuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3292,7 +3292,7 @@ def A4_vrminuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3303,7 +3303,7 @@ def A4_vrminw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3314,7 +3314,7 @@ def A5_ACS : HInst< (outs DoubleRegs:$Rxx32, PredRegs:$Pe4), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", -tc_d1aa9eaa, TypeM>, Enc_831a7d, Requires<[HasV55]> { +tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -3327,7 +3327,7 @@ def A5_vaddhubs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vaddhub($Rss32,$Rtt32):sat", -tc_002cb246, TypeS_3op>, Enc_d2216a { +tc_0dfac0a7, TypeS_3op>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -3340,7 +3340,7 @@ def A6_vcmpbeq_notany : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", -tc_1fc97744, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { +tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3349,18 +3349,57 @@ def A6_vminub_RdP : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Pe4), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", -tc_f9058dd7, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { +tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; let isPredicateLate = 1; let prefersSlot3 = 1; } +def A7_clip : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = clip($Rs32,#$Ii)", +tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A7_croundd_ri : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = cround($Rss32,#$Ii)", +tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10001100111; +let prefersSlot3 = 1; +} +def A7_croundd_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = cround($Rss32,$Rt32)", +tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let prefersSlot3 = 1; +} +def A7_vclip : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vclip($Rss32,#$Ii)", +tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +} def C2_all8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = all8($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011101000; } @@ -3368,7 +3407,7 @@ def C2_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000000; @@ -3377,7 +3416,7 @@ def C2_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,!$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011000; @@ -3386,7 +3425,7 @@ def C2_any8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = any8($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011100000; } @@ -3394,7 +3433,7 @@ def C2_bitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsclr($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111100; @@ -3403,7 +3442,7 @@ def C2_bitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = bitsclr($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_5d6c34 { +tc_a1297125, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101100; } @@ -3411,7 +3450,7 @@ def C2_bitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsset($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111010; @@ -3420,7 +3459,7 @@ def C2_ccombinewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3432,7 +3471,7 @@ def C2_ccombinewnewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3445,7 +3484,7 @@ def C2_ccombinewnewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3457,7 +3496,7 @@ def C2_ccombinewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3468,7 +3507,7 @@ def C2_cmoveif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3476,9 +3515,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3490,16 +3529,16 @@ def C2_cmoveit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3511,7 +3550,7 @@ def C2_cmovenewif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = #$Ii", -tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3520,9 +3559,9 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3534,7 +3573,7 @@ def C2_cmovenewit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = #$Ii", -tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; @@ -3542,9 +3581,9 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3556,7 +3595,7 @@ def C2_cmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.eq($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3569,7 +3608,7 @@ def C2_cmpeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.eq($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010100; let CextOpcode = "C2_cmpeq"; @@ -3585,7 +3624,7 @@ def C2_cmpeqp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3596,7 +3635,7 @@ def C2_cmpgei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmp.ge($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op> { +tc_d33e5eee, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3604,7 +3643,7 @@ def C2_cmpgeui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmp.geu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op> { +tc_d33e5eee, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3612,7 +3651,7 @@ def C2_cmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gt($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3624,7 +3663,7 @@ def C2_cmpgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.gt($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010101; let CextOpcode = "C2_cmpgt"; @@ -3640,7 +3679,7 @@ def C2_cmpgtp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3650,7 +3689,7 @@ def C2_cmpgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gtu($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3662,7 +3701,7 @@ def C2_cmpgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmp.gtu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-21} = 0b01110101100; let CextOpcode = "C2_cmpgtu"; @@ -3678,7 +3717,7 @@ def C2_cmpgtup : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3688,7 +3727,7 @@ def C2_cmplt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.lt($Rs32,$Rt32)", -tc_56f114f4, TypeALU32_3op> { +tc_d33e5eee, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3697,7 +3736,7 @@ def C2_cmpltu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.ltu($Rs32,$Rt32)", -tc_56f114f4, TypeALU32_3op> { +tc_d33e5eee, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3706,7 +3745,7 @@ def C2_mask : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4), "$Rdd32 = mask($Pt4)", -tc_0ae0825c, TypeS_2op>, Enc_78e566 { +tc_9f6cd987, TypeS_2op>, Enc_78e566 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-16} = 0b1000011000000000; @@ -3715,7 +3754,7 @@ def C2_mux : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mux($Pu4,$Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54 { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110100000; @@ -3727,7 +3766,7 @@ def C2_muxii : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), "$Rd32 = mux($Pu4,#$Ii,#$II)", -tc_4c5ba658, TypeALU32_2op>, Enc_830e5d { +tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d { let Inst{31-25} = 0b0111101; let hasNewValue = 1; let opNewValue = 0; @@ -3741,7 +3780,7 @@ def C2_muxir : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = mux($Pu4,$Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100110; let hasNewValue = 1; @@ -3757,7 +3796,7 @@ def C2_muxri : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = mux($Pu4,#$Ii,$Rs32)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100111; let hasNewValue = 1; @@ -3773,7 +3812,7 @@ def C2_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = not($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011110000; } @@ -3781,7 +3820,7 @@ def C2_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001000; @@ -3790,7 +3829,7 @@ def C2_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,!$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111000; @@ -3799,7 +3838,7 @@ def C2_pxfer_map : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = $Ps4", -tc_640086b5, TypeMAPPING> { +tc_651cbe02, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -3807,7 +3846,7 @@ def C2_tfrpr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4), "$Rd32 = $Ps4", -tc_0ae0825c, TypeS_2op>, Enc_f5e933 { +tc_9f6cd987, TypeS_2op>, Enc_f5e933 { let Inst{13-5} = 0b000000000; let Inst{31-18} = 0b10001001010000; let hasNewValue = 1; @@ -3817,7 +3856,7 @@ def C2_tfrrp : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32), "$Pd4 = $Rs32", -tc_cfd8378a, TypeS_2op>, Enc_48b75f { +tc_55b33fda, TypeS_2op>, Enc_48b75f { let Inst{13-2} = 0b000000000000; let Inst{31-21} = 0b10000101010; } @@ -3825,7 +3864,7 @@ def C2_vitpack : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Rd32 = vitpack($Ps4,$Pt4)", -tc_4414d8b1, TypeS_2op>, Enc_527412 { +tc_f34c1c21, TypeS_2op>, Enc_527412 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b10001001000000; @@ -3837,7 +3876,7 @@ def C2_vmux : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", -tc_b4b5c03a, TypeALU64>, Enc_329361 { +tc_6fc5dbea, TypeALU64>, Enc_329361 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010001000; @@ -3846,7 +3885,7 @@ def C2_xor : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = xor($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010000; @@ -3855,7 +3894,7 @@ def C4_addipc : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = add(pc,#$Ii)", -tc_a813cf9a, TypeCR>, Enc_607661 { +tc_3edca78f, TypeCR>, Enc_607661 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0110101001001001; @@ -3871,7 +3910,7 @@ def C4_and_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000100; @@ -3880,7 +3919,7 @@ def C4_and_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011100100; @@ -3889,7 +3928,7 @@ def C4_and_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001100; @@ -3898,7 +3937,7 @@ def C4_and_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011101100; @@ -3907,7 +3946,7 @@ def C4_cmplte : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gt($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3919,7 +3958,7 @@ def C4_cmpltei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.gt($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010101; let CextOpcode = "C4_cmplte"; @@ -3935,7 +3974,7 @@ def C4_cmplteu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gtu($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3947,7 +3986,7 @@ def C4_cmplteui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = !cmp.gtu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-21} = 0b01110101100; let CextOpcode = "C4_cmplteu"; @@ -3963,7 +4002,7 @@ def C4_cmpneq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.eq($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3976,7 +4015,7 @@ def C4_cmpneqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.eq($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010100; let CextOpcode = "C4_cmpneq"; @@ -3992,7 +4031,7 @@ def C4_fastcorner9 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = fastcorner9($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000000; @@ -4001,7 +4040,7 @@ def C4_fastcorner9_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = !fastcorner9($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000100; @@ -4010,7 +4049,7 @@ def C4_nbitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsclr($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111101; @@ -4019,7 +4058,7 @@ def C4_nbitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = !bitsclr($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_5d6c34 { +tc_a1297125, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101101; } @@ -4027,7 +4066,7 @@ def C4_nbitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsset($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111011; @@ -4036,7 +4075,7 @@ def C4_or_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010100; @@ -4045,7 +4084,7 @@ def C4_or_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011110100; @@ -4054,7 +4093,7 @@ def C4_or_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011100; @@ -4063,7 +4102,7 @@ def C4_or_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111100; @@ -4072,7 +4111,7 @@ def F2_conv_d2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_d2df($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4082,7 +4121,7 @@ def F2_conv_d2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_d2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -4094,7 +4133,7 @@ def F2_conv_df2d : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4104,7 +4143,7 @@ def F2_conv_df2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4114,7 +4153,7 @@ def F2_conv_df2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -4126,7 +4165,7 @@ def F2_conv_df2ud : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4136,7 +4175,7 @@ def F2_conv_df2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4146,7 +4185,7 @@ def F2_conv_df2uw : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -4158,7 +4197,7 @@ def F2_conv_df2uw_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000101; let hasNewValue = 1; @@ -4170,7 +4209,7 @@ def F2_conv_df2w : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -4182,7 +4221,7 @@ def F2_conv_df2w_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -4194,7 +4233,7 @@ def F2_conv_sf2d : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4204,7 +4243,7 @@ def F2_conv_sf2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4214,7 +4253,7 @@ def F2_conv_sf2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4224,7 +4263,7 @@ def F2_conv_sf2ud : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4234,7 +4273,7 @@ def F2_conv_sf2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4244,7 +4283,7 @@ def F2_conv_sf2uw : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4256,7 +4295,7 @@ def F2_conv_sf2uw_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4268,7 +4307,7 @@ def F2_conv_sf2w : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4280,7 +4319,7 @@ def F2_conv_sf2w_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4292,7 +4331,7 @@ def F2_conv_ud2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_ud2df($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4302,7 +4341,7 @@ def F2_conv_ud2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_ud2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000001; let hasNewValue = 1; @@ -4314,7 +4353,7 @@ def F2_conv_uw2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_uw2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4324,7 +4363,7 @@ def F2_conv_uw2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_uw2sf($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011001; let hasNewValue = 1; @@ -4336,7 +4375,7 @@ def F2_conv_w2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_w2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4346,7 +4385,7 @@ def F2_conv_w2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_w2sf($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011010; let hasNewValue = 1; @@ -4358,7 +4397,7 @@ def F2_dfadd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = dfadd($Rss32,$Rtt32)", -tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -4369,7 +4408,7 @@ def F2_dfclass : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Pd4 = dfclass($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_1f19b5 { +tc_a1297125, TypeALU64>, Enc_1f19b5 { let Inst{4-2} = 0b100; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b11011100100; @@ -4380,7 +4419,7 @@ def F2_dfcmpeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4392,7 +4431,7 @@ def F2_dfcmpge : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4404,7 +4443,7 @@ def F2_dfcmpgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4416,7 +4455,7 @@ def F2_dfcmpuo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4428,7 +4467,7 @@ def F2_dfimm_n : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):neg", -tc_9e313203, TypeALU64>, Enc_e6c957 { +tc_65279839, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100101; let prefersSlot3 = 1; @@ -4437,16 +4476,84 @@ def F2_dfimm_p : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):pos", -tc_9e313203, TypeALU64>, Enc_e6c957 { +tc_65279839, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100100; let prefersSlot3 = 1; } +def F2_dfmax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmax($Rss32,$Rtt32)", +tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfmin : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmin($Rss32,$Rtt32)", +tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfmpyfix : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmpyfix($Rss32,$Rtt32)", +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let isFP = 1; +let Uses = [USR]; +} +def F2_dfmpyhh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += dfmpyhh($Rss32,$Rtt32)", +tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let isFP = 1; +let Uses = [USR]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def F2_dfmpylh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += dfmpylh($Rss32,$Rtt32)", +tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def F2_dfmpyll : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmpyll($Rss32,$Rtt32)", +tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +} def F2_dfsub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = dfsub($Rss32,$Rtt32)", -tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -4457,7 +4564,7 @@ def F2_sfadd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfadd($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4471,7 +4578,7 @@ def F2_sfclass : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = sfclass($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101111; @@ -4482,7 +4589,7 @@ def F2_sfcmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4494,7 +4601,7 @@ def F2_sfcmpge : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.ge($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4506,7 +4613,7 @@ def F2_sfcmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4518,7 +4625,7 @@ def F2_sfcmpuo : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.uo($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4530,7 +4637,7 @@ def F2_sffixupd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupd($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4542,7 +4649,7 @@ def F2_sffixupn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupn($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4554,7 +4661,7 @@ def F2_sffixupr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sffixupr($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011101; let hasNewValue = 1; @@ -4565,7 +4672,7 @@ def F2_sffma : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32)", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4579,7 +4686,7 @@ def F2_sffma_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32):lib", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4593,7 +4700,7 @@ def F2_sffma_sc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", -tc_4560740b, TypeM>, Enc_437f33 { +tc_9edb7c77, TypeM>, Enc_437f33 { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -4607,7 +4714,7 @@ def F2_sffms : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32)", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4621,7 +4728,7 @@ def F2_sffms_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32):lib", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4635,7 +4742,7 @@ def F2_sfimm_n : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):neg", -tc_9e313203, TypeALU64>, Enc_6c9440 { +tc_65279839, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011001; let hasNewValue = 1; @@ -4646,7 +4753,7 @@ def F2_sfimm_p : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):pos", -tc_9e313203, TypeALU64>, Enc_6c9440 { +tc_65279839, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011000; let hasNewValue = 1; @@ -4657,7 +4764,7 @@ def F2_sfinvsqrta : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32), "$Rd32,$Pe4 = sfinvsqrta($Rs32)", -tc_b8bffe55, TypeS_2op>, Enc_890909 { +tc_7f7f45f5, TypeS_2op>, Enc_890909 { let Inst{13-7} = 0b0000000; let Inst{31-21} = 0b10001011111; let hasNewValue = 1; @@ -4669,7 +4776,7 @@ def F2_sfmax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmax($Rs32,$Rt32)", -tc_88b4f13d, TypeM>, Enc_5ab2be { +tc_c20701f0, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4683,7 +4790,7 @@ def F2_sfmin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmin($Rs32,$Rt32)", -tc_88b4f13d, TypeM>, Enc_5ab2be { +tc_c20701f0, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4697,7 +4804,7 @@ def F2_sfmpy : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmpy($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011010; @@ -4711,7 +4818,7 @@ def F2_sfrecipa : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", -tc_2ff964b4, TypeM>, Enc_a94f3b { +tc_f7569068, TypeM>, Enc_a94f3b { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011111; @@ -4724,7 +4831,7 @@ def F2_sfsub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfsub($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4737,7 +4844,7 @@ def G4_tfrgcpp : HInst< (outs DoubleRegs:$Rdd32), (ins GuestRegs64:$Gss32), "$Rdd32 = $Gss32", -tc_0d8f5752, TypeCR>, Enc_0aa344 { +tc_fae9dfa5, TypeCR>, Enc_0aa344 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101000001; } @@ -4745,7 +4852,7 @@ def G4_tfrgcrr : HInst< (outs IntRegs:$Rd32), (ins GuestRegs:$Gs32), "$Rd32 = $Gs32", -tc_0d8f5752, TypeCR>, Enc_44271f { +tc_fae9dfa5, TypeCR>, Enc_44271f { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101010001; let hasNewValue = 1; @@ -4755,7 +4862,7 @@ def G4_tfrgpcp : HInst< (outs GuestRegs64:$Gdd32), (ins DoubleRegs:$Rss32), "$Gdd32 = $Rss32", -tc_bcf98408, TypeCR>, Enc_ed5027 { +tc_6ae3426b, TypeCR>, Enc_ed5027 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100011000; let hasNewValue = 1; @@ -4765,7 +4872,7 @@ def G4_tfrgrcr : HInst< (outs GuestRegs:$Gd32), (ins IntRegs:$Rs32), "$Gd32 = $Rs32", -tc_bcf98408, TypeCR>, Enc_621fba { +tc_6ae3426b, TypeCR>, Enc_621fba { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100010000; let hasNewValue = 1; @@ -4775,7 +4882,7 @@ def J2_call : HInst< (outs), (ins a30_2Imm:$Ii), "call $Ii", -tc_4ae7b58b, TypeJ>, Enc_81ac1d, PredRel { +tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101101; let isCall = 1; @@ -4797,7 +4904,7 @@ def J2_callf : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if (!$Pu4) call $Ii", -tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { +tc_69bfb303, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4824,7 +4931,7 @@ def J2_callr : HInst< (outs), (ins IntRegs:$Rs32), "callr $Rs32", -tc_3bd75825, TypeJ>, Enc_ecbcc8 { +tc_362b0be2, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010000101; let isCall = 1; @@ -4838,7 +4945,7 @@ def J2_callrf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) callr $Rs32", -tc_1ad90acd, TypeJ>, Enc_88d4d9 { +tc_dc51281d, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001001; @@ -4856,7 +4963,7 @@ def J2_callrt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) callr $Rs32", -tc_1ad90acd, TypeJ>, Enc_88d4d9 { +tc_dc51281d, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001000; @@ -4873,7 +4980,7 @@ def J2_callt : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if ($Pu4) call $Ii", -tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { +tc_69bfb303, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -4899,7 +5006,7 @@ def J2_endloop0 : HInst< (outs), (ins), "endloop0", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC0, SA0]; let Defs = [LC0, P3, PC, USR]; let isBranch = 1; @@ -4910,7 +5017,7 @@ def J2_endloop01 : HInst< (outs), (ins), "endloop01", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC0, LC1, SA0, SA1]; let Defs = [LC0, LC1, P3, PC, USR]; let isPseudo = 1; @@ -4919,7 +5026,7 @@ def J2_endloop1 : HInst< (outs), (ins), "endloop1", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC1, SA1]; let Defs = [LC1, PC]; let isBranch = 1; @@ -4930,7 +5037,7 @@ def J2_jump : HInst< (outs), (ins b30_2Imm:$Ii), "jump $Ii", -tc_ae53734a, TypeJ>, Enc_81ac1d, PredNewRel { +tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101100; let isTerminator = 1; @@ -4938,8 +5045,8 @@ let isBranch = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isBarrier = 1; let isPredicable = 1; let isExtendable = 1; @@ -4952,7 +5059,7 @@ def J2_jumpf : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:nt $Ii", -tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { +tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4965,8 +5072,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -4978,7 +5085,7 @@ def J2_jumpf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if (!$Pu4) jump $Ii", -tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { +tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -4986,7 +5093,7 @@ def J2_jumpfnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:nt $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b1; @@ -5000,8 +5107,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5013,7 +5120,7 @@ def J2_jumpfnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:t $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b1; @@ -5027,8 +5134,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5040,7 +5147,7 @@ def J2_jumpfpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:t $Ii", -tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { +tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b1; @@ -5053,8 +5160,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5066,7 +5173,7 @@ def J2_jumpr : HInst< (outs), (ins IntRegs:$Rs32), "jumpr $Rs32", -tc_d5b7b0c1, TypeJ>, Enc_ecbcc8, PredNewRel { +tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010100; let isTerminator = 1; @@ -5074,8 +5181,8 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isBarrier = 1; let isPredicable = 1; } @@ -5083,7 +5190,7 @@ def J2_jumprf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:nt $Rs32", -tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { +tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011011; @@ -5094,15 +5201,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr $Rs32", -tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { +tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5110,7 +5217,7 @@ def J2_jumprfnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:nt $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011011; @@ -5122,15 +5229,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprfnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:t $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011011; @@ -5142,15 +5249,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprfpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:t $Rs32", -tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { +tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011011; @@ -5161,15 +5268,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprgtez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000101; @@ -5187,7 +5294,7 @@ def J2_jumprgtezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000101; @@ -5205,7 +5312,7 @@ def J2_jumprltez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000111; @@ -5223,7 +5330,7 @@ def J2_jumprltezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000111; @@ -5241,7 +5348,7 @@ def J2_jumprnz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000110; @@ -5259,7 +5366,7 @@ def J2_jumprnzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000110; @@ -5277,7 +5384,7 @@ def J2_jumprt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:nt $Rs32", -tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { +tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011010; @@ -5287,15 +5394,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr $Rs32", -tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { +tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5303,7 +5410,7 @@ def J2_jumprtnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:nt $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011010; @@ -5314,15 +5421,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprtnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:t $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011010; @@ -5333,15 +5440,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprtpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:t $Rs32", -tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { +tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011010; @@ -5351,15 +5458,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000100; @@ -5377,7 +5484,7 @@ def J2_jumprzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000100; @@ -5395,7 +5502,7 @@ def J2_jumpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:nt $Ii", -tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { +tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -5407,8 +5514,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5420,7 +5527,7 @@ def J2_jumpt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if ($Pu4) jump $Ii", -tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { +tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5428,7 +5535,7 @@ def J2_jumptnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:nt $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b0; @@ -5441,8 +5548,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5454,7 +5561,7 @@ def J2_jumptnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:t $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b0; @@ -5467,8 +5574,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5480,7 +5587,7 @@ def J2_jumptpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:t $Ii", -tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { +tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b0; @@ -5492,8 +5599,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5505,7 +5612,7 @@ def J2_loop0i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop0($Ii,#$II)", -tc_a9d88b22, TypeCR>, Enc_4dc228 { +tc_1248597c, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001000; @@ -5522,7 +5629,7 @@ def J2_loop0r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop0($Ii,$Rs32)", -tc_df3319ed, TypeCR>, Enc_864a5a { +tc_9406230a, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5540,7 +5647,7 @@ def J2_loop1i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop1($Ii,#$II)", -tc_a9d88b22, TypeCR>, Enc_4dc228 { +tc_1248597c, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001001; @@ -5557,7 +5664,7 @@ def J2_loop1r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop1($Ii,$Rs32)", -tc_df3319ed, TypeCR>, Enc_864a5a { +tc_9406230a, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5575,7 +5682,7 @@ def J2_pause : HInst< (outs), (ins u8_0Imm:$Ii), "pause(#$Ii)", -tc_8d9d0154, TypeJ>, Enc_a51a9a { +tc_d57d649c, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5586,7 +5693,7 @@ def J2_ploop1si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp1loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001101; @@ -5604,7 +5711,7 @@ def J2_ploop1sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp1loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5623,7 +5730,7 @@ def J2_ploop2si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp2loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001110; @@ -5641,7 +5748,7 @@ def J2_ploop2sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp2loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5660,7 +5767,7 @@ def J2_ploop3si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp3loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001111; @@ -5678,7 +5785,7 @@ def J2_ploop3sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp3loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5697,7 +5804,7 @@ def J2_trap0 : HInst< (outs), (ins u8_0Imm:$Ii), "trap0(#$Ii)", -tc_fc3999b4, TypeJ>, Enc_a51a9a { +tc_45f9d1be, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5709,7 +5816,7 @@ def J2_trap1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u8_0Imm:$Ii), "trap1($Rx32,#$Ii)", -tc_b9e09e03, TypeJ>, Enc_33f8ba { +tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5726,7 +5833,7 @@ def J2_trap1_noregmap : HInst< (outs), (ins u8_0Imm:$Ii), "trap1(#$Ii)", -tc_b9e09e03, TypeMAPPING> { +tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> { let hasSideEffects = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -5735,7 +5842,7 @@ def J4_cmpeq_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5761,7 +5868,7 @@ def J4_cmpeq_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5787,7 +5894,7 @@ def J4_cmpeq_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010001; @@ -5813,7 +5920,7 @@ def J4_cmpeq_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010001; @@ -5839,7 +5946,7 @@ def J4_cmpeq_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010001; @@ -5865,7 +5972,7 @@ def J4_cmpeq_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010001; @@ -5891,7 +5998,7 @@ def J4_cmpeq_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5916,7 +6023,7 @@ def J4_cmpeq_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5941,7 +6048,7 @@ def J4_cmpeq_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010000; @@ -5966,7 +6073,7 @@ def J4_cmpeq_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010000; @@ -5991,7 +6098,7 @@ def J4_cmpeq_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010000; @@ -6016,7 +6123,7 @@ def J4_cmpeq_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010000; @@ -6041,7 +6148,7 @@ def J4_cmpeqi_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6067,7 +6174,7 @@ def J4_cmpeqi_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6093,7 +6200,7 @@ def J4_cmpeqi_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000001; @@ -6119,7 +6226,7 @@ def J4_cmpeqi_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000001; @@ -6145,7 +6252,7 @@ def J4_cmpeqi_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001001; @@ -6171,7 +6278,7 @@ def J4_cmpeqi_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001001; @@ -6197,7 +6304,7 @@ def J4_cmpeqi_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6222,7 +6329,7 @@ def J4_cmpeqi_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6247,7 +6354,7 @@ def J4_cmpeqi_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000000; @@ -6272,7 +6379,7 @@ def J4_cmpeqi_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000000; @@ -6297,7 +6404,7 @@ def J4_cmpeqi_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001000; @@ -6322,7 +6429,7 @@ def J4_cmpeqi_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001000; @@ -6347,7 +6454,7 @@ def J4_cmpeqn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_e90a15, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6373,7 +6480,7 @@ def J4_cmpeqn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_5a18b3, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6399,7 +6506,7 @@ def J4_cmpeqn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_1de724, PredRel { +tc_24f426ab, TypeCJ>, Enc_1de724, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000111; @@ -6425,7 +6532,7 @@ def J4_cmpeqn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14640c, PredRel { +tc_24f426ab, TypeCJ>, Enc_14640c, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000111; @@ -6451,7 +6558,7 @@ def J4_cmpeqn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_668704, PredRel { +tc_24f426ab, TypeCJ>, Enc_668704, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001111; @@ -6477,7 +6584,7 @@ def J4_cmpeqn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_800e04, PredRel { +tc_24f426ab, TypeCJ>, Enc_800e04, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001111; @@ -6503,7 +6610,7 @@ def J4_cmpeqn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_4aca3a, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6528,7 +6635,7 @@ def J4_cmpeqn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_f7ea77, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6553,7 +6660,7 @@ def J4_cmpeqn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_405228, PredRel { +tc_24f426ab, TypeCJ>, Enc_405228, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000110; @@ -6578,7 +6685,7 @@ def J4_cmpeqn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_3a2484, PredRel { +tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000110; @@ -6603,7 +6710,7 @@ def J4_cmpeqn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_736575, PredRel { +tc_24f426ab, TypeCJ>, Enc_736575, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001110; @@ -6628,7 +6735,7 @@ def J4_cmpeqn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_8e583a, PredRel { +tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001110; @@ -6653,7 +6760,7 @@ def J4_cmpgt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6679,7 +6786,7 @@ def J4_cmpgt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6705,7 +6812,7 @@ def J4_cmpgt_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010011; @@ -6731,7 +6838,7 @@ def J4_cmpgt_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010011; @@ -6757,7 +6864,7 @@ def J4_cmpgt_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010011; @@ -6783,7 +6890,7 @@ def J4_cmpgt_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010011; @@ -6809,7 +6916,7 @@ def J4_cmpgt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6834,7 +6941,7 @@ def J4_cmpgt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6859,7 +6966,7 @@ def J4_cmpgt_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010010; @@ -6884,7 +6991,7 @@ def J4_cmpgt_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010010; @@ -6909,7 +7016,7 @@ def J4_cmpgt_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010010; @@ -6934,7 +7041,7 @@ def J4_cmpgt_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010010; @@ -6959,7 +7066,7 @@ def J4_cmpgti_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6985,7 +7092,7 @@ def J4_cmpgti_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7011,7 +7118,7 @@ def J4_cmpgti_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000011; @@ -7037,7 +7144,7 @@ def J4_cmpgti_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000011; @@ -7063,7 +7170,7 @@ def J4_cmpgti_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001011; @@ -7089,7 +7196,7 @@ def J4_cmpgti_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001011; @@ -7115,7 +7222,7 @@ def J4_cmpgti_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7140,7 +7247,7 @@ def J4_cmpgti_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7165,7 +7272,7 @@ def J4_cmpgti_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000010; @@ -7190,7 +7297,7 @@ def J4_cmpgti_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000010; @@ -7215,7 +7322,7 @@ def J4_cmpgti_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001010; @@ -7240,7 +7347,7 @@ def J4_cmpgti_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001010; @@ -7265,7 +7372,7 @@ def J4_cmpgtn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_3694bd, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -7291,7 +7398,7 @@ def J4_cmpgtn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_a6853f, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -7317,7 +7424,7 @@ def J4_cmpgtn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_a42857, PredRel { +tc_24f426ab, TypeCJ>, Enc_a42857, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000111; @@ -7343,7 +7450,7 @@ def J4_cmpgtn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_f6fe0b, PredRel { +tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000111; @@ -7369,7 +7476,7 @@ def J4_cmpgtn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_3e3989, PredRel { +tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001111; @@ -7395,7 +7502,7 @@ def J4_cmpgtn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_b909d2, PredRel { +tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001111; @@ -7421,7 +7528,7 @@ def J4_cmpgtn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_f82302, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -7446,7 +7553,7 @@ def J4_cmpgtn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_6413b6, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -7471,7 +7578,7 @@ def J4_cmpgtn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_b78edd, PredRel { +tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000110; @@ -7496,7 +7603,7 @@ def J4_cmpgtn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_041d7b, PredRel { +tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000110; @@ -7521,7 +7628,7 @@ def J4_cmpgtn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_b1e1fb, PredRel { +tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001110; @@ -7546,7 +7653,7 @@ def J4_cmpgtn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_178717, PredRel { +tc_24f426ab, TypeCJ>, Enc_178717, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001110; @@ -7571,7 +7678,7 @@ def J4_cmpgtu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7597,7 +7704,7 @@ def J4_cmpgtu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7623,7 +7730,7 @@ def J4_cmpgtu_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010101; @@ -7649,7 +7756,7 @@ def J4_cmpgtu_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010101; @@ -7675,7 +7782,7 @@ def J4_cmpgtu_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010101; @@ -7701,7 +7808,7 @@ def J4_cmpgtu_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010101; @@ -7727,7 +7834,7 @@ def J4_cmpgtu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7752,7 +7859,7 @@ def J4_cmpgtu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7777,7 +7884,7 @@ def J4_cmpgtu_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010100; @@ -7802,7 +7909,7 @@ def J4_cmpgtu_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010100; @@ -7827,7 +7934,7 @@ def J4_cmpgtu_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010100; @@ -7852,7 +7959,7 @@ def J4_cmpgtu_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010100; @@ -7877,7 +7984,7 @@ def J4_cmpgtui_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7903,7 +8010,7 @@ def J4_cmpgtui_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7929,7 +8036,7 @@ def J4_cmpgtui_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000101; @@ -7955,7 +8062,7 @@ def J4_cmpgtui_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000101; @@ -7981,7 +8088,7 @@ def J4_cmpgtui_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001101; @@ -8007,7 +8114,7 @@ def J4_cmpgtui_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001101; @@ -8033,7 +8140,7 @@ def J4_cmpgtui_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8058,7 +8165,7 @@ def J4_cmpgtui_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8083,7 +8190,7 @@ def J4_cmpgtui_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000100; @@ -8108,7 +8215,7 @@ def J4_cmpgtui_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000100; @@ -8133,7 +8240,7 @@ def J4_cmpgtui_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001100; @@ -8158,7 +8265,7 @@ def J4_cmpgtui_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001100; @@ -8183,7 +8290,7 @@ def J4_cmplt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8209,7 +8316,7 @@ def J4_cmplt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8235,7 +8342,7 @@ def J4_cmplt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8260,7 +8367,7 @@ def J4_cmplt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8285,7 +8392,7 @@ def J4_cmpltu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8311,7 +8418,7 @@ def J4_cmpltu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8337,7 +8444,7 @@ def J4_cmpltu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8362,7 +8469,7 @@ def J4_cmpltu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8387,7 +8494,7 @@ def J4_hintjumpr : HInst< (outs), (ins IntRegs:$Rs32), "hintjr($Rs32)", -tc_d5b7b0c1, TypeJ>, Enc_ecbcc8 { +tc_60e324ff, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010101; let isTerminator = 1; @@ -8399,7 +8506,7 @@ def J4_jumpseti : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_0Imm:$II, b30_2Imm:$Ii), "$Rd16 = #$II ; jump $Ii", -tc_0663f615, TypeCJ>, Enc_9e4c3f { +tc_5502c366, TypeCJ>, Enc_9e4c3f { let Inst{0-0} = 0b0; let Inst{31-22} = 0b0001011000; let hasNewValue = 1; @@ -8419,7 +8526,7 @@ def J4_jumpsetr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "$Rd16 = $Rs16 ; jump $Ii", -tc_0663f615, TypeCJ>, Enc_66bce1 { +tc_5502c366, TypeCJ>, Enc_66bce1 { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001011100; @@ -8440,7 +8547,7 @@ def J4_tstbit0_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8465,7 +8572,7 @@ def J4_tstbit0_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:t $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8490,7 +8597,7 @@ def J4_tstbit0_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000111; @@ -8515,7 +8622,7 @@ def J4_tstbit0_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000111; @@ -8540,7 +8647,7 @@ def J4_tstbit0_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001111; @@ -8565,7 +8672,7 @@ def J4_tstbit0_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001111; @@ -8590,7 +8697,7 @@ def J4_tstbit0_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8614,7 +8721,7 @@ def J4_tstbit0_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:t $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8638,7 +8745,7 @@ def J4_tstbit0_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000110; @@ -8662,7 +8769,7 @@ def J4_tstbit0_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000110; @@ -8686,7 +8793,7 @@ def J4_tstbit0_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001110; @@ -8710,7 +8817,7 @@ def J4_tstbit0_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001110; @@ -8734,7 +8841,7 @@ def L2_deallocframe : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = deallocframe($Rs32):raw", -tc_15aa71c5, TypeLD>, Enc_3a3d62 { +tc_e9170fb7, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010000000; let accessSize = DoubleWordAccess; @@ -8746,7 +8853,7 @@ def L2_loadalignb_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Ryy32 = memb_fifo($Rs32+#$Ii)", -tc_5ef37dc4, TypeLD>, Enc_a27588 { +tc_fedb7e19, TypeLD>, Enc_a27588 { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8763,7 +8870,7 @@ def L2_loadalignb_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110100; let addrMode = PostInc; @@ -8775,7 +8882,7 @@ def L2_loadalignb_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", -tc_785f65a7, TypeLD>, Enc_74aef2 { +tc_76bb5435, TypeLD>, Enc_74aef2 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8788,7 +8895,7 @@ def L2_loadalignb_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8801,7 +8908,7 @@ def L2_loadalignb_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), "$Ryy32 = memb_fifo($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_6b197f { +tc_1c7522a8, TypeLD>, Enc_6b197f { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010100; let addrMode = PostInc; @@ -8813,7 +8920,7 @@ def L2_loadalignb_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100100; let addrMode = PostInc; @@ -8825,7 +8932,7 @@ def L2_loadalignb_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memb_fifo($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8834,7 +8941,7 @@ def L2_loadalignh_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), "$Ryy32 = memh_fifo($Rs32+#$Ii)", -tc_5ef37dc4, TypeLD>, Enc_5cd7e9 { +tc_fedb7e19, TypeLD>, Enc_5cd7e9 { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8851,7 +8958,7 @@ def L2_loadalignh_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110010; let addrMode = PostInc; @@ -8863,7 +8970,7 @@ def L2_loadalignh_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", -tc_785f65a7, TypeLD>, Enc_9e2e1c { +tc_76bb5435, TypeLD>, Enc_9e2e1c { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8876,7 +8983,7 @@ def L2_loadalignh_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8889,7 +8996,7 @@ def L2_loadalignh_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), "$Ryy32 = memh_fifo($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_bd1cbc { +tc_1c7522a8, TypeLD>, Enc_bd1cbc { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010010; let addrMode = PostInc; @@ -8901,7 +9008,7 @@ def L2_loadalignh_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100010; let addrMode = PostInc; @@ -8913,7 +9020,7 @@ def L2_loadalignh_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memh_fifo($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8922,7 +9029,7 @@ def L2_loadbsw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = membh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214 { +tc_4222e6bf, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -8940,7 +9047,7 @@ def L2_loadbsw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110001; let hasNewValue = 1; @@ -8954,7 +9061,7 @@ def L2_loadbsw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8969,7 +9076,7 @@ def L2_loadbsw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8984,7 +9091,7 @@ def L2_loadbsw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = membh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467 { +tc_075c8dd8, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010001; let hasNewValue = 1; @@ -8998,7 +9105,7 @@ def L2_loadbsw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -9012,7 +9119,7 @@ def L2_loadbsw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = membh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9022,7 +9129,7 @@ def L2_loadbsw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = membh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2d7491 { +tc_4222e6bf, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0111; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -9038,7 +9145,7 @@ def L2_loadbsw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110111; let addrMode = PostInc; @@ -9050,7 +9157,7 @@ def L2_loadbsw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_70b24b { +tc_5ceb2f9e, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -9063,7 +9170,7 @@ def L2_loadbsw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -9076,7 +9183,7 @@ def L2_loadbsw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = membh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_71f1b4 { +tc_075c8dd8, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010111; let addrMode = PostInc; @@ -9088,7 +9195,7 @@ def L2_loadbsw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100111; let addrMode = PostInc; @@ -9100,7 +9207,7 @@ def L2_loadbsw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = membh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9108,7 +9215,7 @@ def L2_loadbzw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memubh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214 { +tc_4222e6bf, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9126,7 +9233,7 @@ def L2_loadbzw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110011; let hasNewValue = 1; @@ -9140,7 +9247,7 @@ def L2_loadbzw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -9155,7 +9262,7 @@ def L2_loadbzw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -9170,7 +9277,7 @@ def L2_loadbzw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memubh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467 { +tc_075c8dd8, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010011; let hasNewValue = 1; @@ -9184,7 +9291,7 @@ def L2_loadbzw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -9198,7 +9305,7 @@ def L2_loadbzw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memubh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9208,7 +9315,7 @@ def L2_loadbzw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = memubh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2d7491 { +tc_4222e6bf, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0101; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -9224,7 +9331,7 @@ def L2_loadbzw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110101; let addrMode = PostInc; @@ -9236,7 +9343,7 @@ def L2_loadbzw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_70b24b { +tc_5ceb2f9e, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -9249,7 +9356,7 @@ def L2_loadbzw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -9262,7 +9369,7 @@ def L2_loadbzw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = memubh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_71f1b4 { +tc_075c8dd8, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010101; let addrMode = PostInc; @@ -9274,7 +9381,7 @@ def L2_loadbzw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100101; let addrMode = PostInc; @@ -9286,7 +9393,7 @@ def L2_loadbzw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memubh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9294,7 +9401,7 @@ def L2_loadrb_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memb($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9302,8 +9409,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9315,7 +9422,7 @@ def L2_loadrb_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111000; let hasNewValue = 1; @@ -9329,7 +9436,7 @@ def L2_loadrb_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e0a47a { +tc_5ceb2f9e, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -9344,7 +9451,7 @@ def L2_loadrb_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -9359,7 +9466,7 @@ def L2_loadrb_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memb($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011000; let hasNewValue = 1; @@ -9367,8 +9474,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_pi"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9376,7 +9483,7 @@ def L2_loadrb_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -9390,7 +9497,7 @@ def L2_loadrb_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memb($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9400,7 +9507,7 @@ def L2_loadrbgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9419,14 +9526,14 @@ def L2_loadrd_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s29_3Imm:$Ii), "$Rdd32 = memd($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9438,7 +9545,7 @@ def L2_loadrd_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111110; let addrMode = PostInc; @@ -9450,7 +9557,7 @@ def L2_loadrd_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_b05839 { +tc_5ceb2f9e, TypeLD>, Enc_b05839 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9463,7 +9570,7 @@ def L2_loadrd_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9476,14 +9583,14 @@ def L2_loadrd_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii), "$Rdd32 = memd($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011110; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_pi"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9491,7 +9598,7 @@ def L2_loadrd_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101110; let addrMode = PostInc; @@ -9503,7 +9610,7 @@ def L2_loadrd_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9511,7 +9618,7 @@ def L2_loadrdgp : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -9528,7 +9635,7 @@ def L2_loadrh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9536,8 +9643,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9549,7 +9656,7 @@ def L2_loadrh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111010; let hasNewValue = 1; @@ -9563,7 +9670,7 @@ def L2_loadrh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9578,7 +9685,7 @@ def L2_loadrh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9593,7 +9700,7 @@ def L2_loadrh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011010; let hasNewValue = 1; @@ -9601,8 +9708,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_pi"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9610,7 +9717,7 @@ def L2_loadrh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -9624,7 +9731,7 @@ def L2_loadrh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9634,7 +9741,7 @@ def L2_loadrhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9653,7 +9760,7 @@ def L2_loadri_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rd32 = memw($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9661,8 +9768,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9674,7 +9781,7 @@ def L2_loadri_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111100; let hasNewValue = 1; @@ -9688,7 +9795,7 @@ def L2_loadri_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_27fd0e { +tc_5ceb2f9e, TypeLD>, Enc_27fd0e { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9703,7 +9810,7 @@ def L2_loadri_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9718,7 +9825,7 @@ def L2_loadri_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rd32 = memw($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011100; let hasNewValue = 1; @@ -9726,8 +9833,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_pi"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9735,7 +9842,7 @@ def L2_loadri_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -9749,7 +9856,7 @@ def L2_loadri_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9759,7 +9866,7 @@ def L2_loadrigp : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9778,7 +9885,7 @@ def L2_loadrub_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memub($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9786,8 +9893,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9799,7 +9906,7 @@ def L2_loadrub_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111001; let hasNewValue = 1; @@ -9813,7 +9920,7 @@ def L2_loadrub_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e0a47a { +tc_5ceb2f9e, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9828,7 +9935,7 @@ def L2_loadrub_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9843,7 +9950,7 @@ def L2_loadrub_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memub($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011001; let hasNewValue = 1; @@ -9851,8 +9958,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_pi"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9860,7 +9967,7 @@ def L2_loadrub_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -9874,7 +9981,7 @@ def L2_loadrub_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memub($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9884,7 +9991,7 @@ def L2_loadrubgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9903,7 +10010,7 @@ def L2_loadruh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memuh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9911,8 +10018,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9924,7 +10031,7 @@ def L2_loadruh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111011; let hasNewValue = 1; @@ -9938,7 +10045,7 @@ def L2_loadruh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9953,7 +10060,7 @@ def L2_loadruh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9968,7 +10075,7 @@ def L2_loadruh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memuh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011011; let hasNewValue = 1; @@ -9976,8 +10083,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_pi"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9985,7 +10092,7 @@ def L2_loadruh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -9999,7 +10106,7 @@ def L2_loadruh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memuh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10009,7 +10116,7 @@ def L2_loadruhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -10028,7 +10135,7 @@ def L2_loadw_locked : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw_locked($Rs32)", -tc_b43e7930, TypeLD>, Enc_5e2823 { +tc_64b00d8a, TypeLD>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010010000; let hasNewValue = 1; @@ -10041,7 +10148,7 @@ def L2_ploadrbf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101000; let isPredicated = 1; @@ -10051,8 +10158,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10063,7 +10170,7 @@ def L2_ploadrbf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10080,7 +10187,7 @@ def L2_ploadrbf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memb($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10090,7 +10197,7 @@ def L2_ploadrbfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111000; let isPredicated = 1; @@ -10101,8 +10208,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10113,7 +10220,7 @@ def L2_ploadrbfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10131,7 +10238,7 @@ def L2_ploadrbfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memb($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10141,7 +10248,7 @@ def L2_ploadrbt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001000; let isPredicated = 1; @@ -10150,8 +10257,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10162,7 +10269,7 @@ def L2_ploadrbt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10178,7 +10285,7 @@ def L2_ploadrbt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memb($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10188,7 +10295,7 @@ def L2_ploadrbtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011000; let isPredicated = 1; @@ -10198,8 +10305,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10210,7 +10317,7 @@ def L2_ploadrbtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10227,7 +10334,7 @@ def L2_ploadrbtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memb($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10237,7 +10344,7 @@ def L2_ploadrdf_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101110; let isPredicated = 1; @@ -10245,8 +10352,8 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10257,7 +10364,7 @@ def L2_ploadrdf_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10272,7 +10379,7 @@ def L2_ploadrdf_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rdd32 = memd($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10280,7 +10387,7 @@ def L2_ploadrdfnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111110; let isPredicated = 1; @@ -10289,8 +10396,8 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10301,7 +10408,7 @@ def L2_ploadrdfnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10317,7 +10424,7 @@ def L2_ploadrdfnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rdd32 = memd($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10325,15 +10432,15 @@ def L2_ploadrdt_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001110; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10344,7 +10451,7 @@ def L2_ploadrdt_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10358,7 +10465,7 @@ def L2_ploadrdt_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rdd32 = memd($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10366,7 +10473,7 @@ def L2_ploadrdtnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011110; let isPredicated = 1; @@ -10374,8 +10481,8 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10386,7 +10493,7 @@ def L2_ploadrdtnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10401,7 +10508,7 @@ def L2_ploadrdtnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rdd32 = memd($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10409,7 +10516,7 @@ def L2_ploadrhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101010; let isPredicated = 1; @@ -10419,8 +10526,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10431,7 +10538,7 @@ def L2_ploadrhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10448,7 +10555,7 @@ def L2_ploadrhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10458,7 +10565,7 @@ def L2_ploadrhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111010; let isPredicated = 1; @@ -10469,8 +10576,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10481,7 +10588,7 @@ def L2_ploadrhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10499,7 +10606,7 @@ def L2_ploadrhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10509,7 +10616,7 @@ def L2_ploadrht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001010; let isPredicated = 1; @@ -10518,8 +10625,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10530,7 +10637,7 @@ def L2_ploadrht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10546,7 +10653,7 @@ def L2_ploadrht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10556,7 +10663,7 @@ def L2_ploadrhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011010; let isPredicated = 1; @@ -10566,8 +10673,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10578,7 +10685,7 @@ def L2_ploadrhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10595,7 +10702,7 @@ def L2_ploadrhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10605,7 +10712,7 @@ def L2_ploadrif_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101100; let isPredicated = 1; @@ -10615,8 +10722,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10627,7 +10734,7 @@ def L2_ploadrif_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10644,7 +10751,7 @@ def L2_ploadrif_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memw($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10654,7 +10761,7 @@ def L2_ploadrifnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111100; let isPredicated = 1; @@ -10665,8 +10772,8 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10677,7 +10784,7 @@ def L2_ploadrifnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10695,7 +10802,7 @@ def L2_ploadrifnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memw($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10705,7 +10812,7 @@ def L2_ploadrit_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001100; let isPredicated = 1; @@ -10714,8 +10821,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10726,7 +10833,7 @@ def L2_ploadrit_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10742,7 +10849,7 @@ def L2_ploadrit_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memw($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10752,7 +10859,7 @@ def L2_ploadritnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011100; let isPredicated = 1; @@ -10762,8 +10869,8 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10774,7 +10881,7 @@ def L2_ploadritnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10791,7 +10898,7 @@ def L2_ploadritnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memw($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10801,7 +10908,7 @@ def L2_ploadrubf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101001; let isPredicated = 1; @@ -10811,8 +10918,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10823,7 +10930,7 @@ def L2_ploadrubf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10840,7 +10947,7 @@ def L2_ploadrubf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memub($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10850,7 +10957,7 @@ def L2_ploadrubfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111001; let isPredicated = 1; @@ -10861,8 +10968,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10873,7 +10980,7 @@ def L2_ploadrubfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10891,7 +10998,7 @@ def L2_ploadrubfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memub($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10901,7 +11008,7 @@ def L2_ploadrubt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001001; let isPredicated = 1; @@ -10910,8 +11017,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10922,7 +11029,7 @@ def L2_ploadrubt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10938,7 +11045,7 @@ def L2_ploadrubt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memub($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10948,7 +11055,7 @@ def L2_ploadrubtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011001; let isPredicated = 1; @@ -10958,8 +11065,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10970,7 +11077,7 @@ def L2_ploadrubtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10987,7 +11094,7 @@ def L2_ploadrubtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memub($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10997,7 +11104,7 @@ def L2_ploadruhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101011; let isPredicated = 1; @@ -11007,8 +11114,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11019,7 +11126,7 @@ def L2_ploadruhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11036,7 +11143,7 @@ def L2_ploadruhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memuh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11046,7 +11153,7 @@ def L2_ploadruhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111011; let isPredicated = 1; @@ -11057,8 +11164,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11069,7 +11176,7 @@ def L2_ploadruhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11087,7 +11194,7 @@ def L2_ploadruhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memuh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11097,7 +11204,7 @@ def L2_ploadruht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001011; let isPredicated = 1; @@ -11106,8 +11213,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11118,7 +11225,7 @@ def L2_ploadruht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11134,7 +11241,7 @@ def L2_ploadruht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memuh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11144,7 +11251,7 @@ def L2_ploadruhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011011; let isPredicated = 1; @@ -11154,8 +11261,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11166,7 +11273,7 @@ def L2_ploadruhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11183,7 +11290,7 @@ def L2_ploadruhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memuh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11193,7 +11300,7 @@ def L4_add_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -11212,7 +11319,7 @@ def L4_add_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11220,7 +11327,7 @@ def L4_add_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -11239,7 +11346,7 @@ def L4_add_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11247,7 +11354,7 @@ def L4_add_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -11266,7 +11373,7 @@ def L4_add_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11274,7 +11381,7 @@ def L4_and_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -11293,7 +11400,7 @@ def L4_and_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11301,7 +11408,7 @@ def L4_and_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -11320,7 +11427,7 @@ def L4_and_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11328,7 +11435,7 @@ def L4_and_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -11347,7 +11454,7 @@ def L4_and_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11355,7 +11462,7 @@ def L4_iadd_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11374,7 +11481,7 @@ def L4_iadd_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11382,7 +11489,7 @@ def L4_iadd_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11401,7 +11508,7 @@ def L4_iadd_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11409,7 +11516,7 @@ def L4_iadd_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11428,7 +11535,7 @@ def L4_iadd_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11436,7 +11543,7 @@ def L4_iand_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11455,7 +11562,7 @@ def L4_iand_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11463,7 +11570,7 @@ def L4_iand_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11482,7 +11589,7 @@ def L4_iand_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11490,7 +11597,7 @@ def L4_iand_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11509,7 +11616,7 @@ def L4_iand_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11517,7 +11624,7 @@ def L4_ior_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11536,7 +11643,7 @@ def L4_ior_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11544,7 +11651,7 @@ def L4_ior_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11563,7 +11670,7 @@ def L4_ior_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11571,7 +11678,7 @@ def L4_ior_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11590,7 +11697,7 @@ def L4_ior_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11598,7 +11705,7 @@ def L4_isub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11617,7 +11724,7 @@ def L4_isub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11625,7 +11732,7 @@ def L4_isub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11644,7 +11751,7 @@ def L4_isub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11652,7 +11759,7 @@ def L4_isub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11671,7 +11778,7 @@ def L4_isub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11679,7 +11786,7 @@ def L4_loadalignb_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memb_fifo($Re32=#$II)", -tc_7a91e76a, TypeLD>, Enc_f394d3 { +tc_ac65613f, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010100; @@ -11699,7 +11806,7 @@ def L4_loadalignb_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", -tc_a5d4aeec, TypeLD>, Enc_04c959 { +tc_a32e03e7, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100100; let addrMode = BaseLongOffset; @@ -11719,7 +11826,7 @@ def L4_loadalignh_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memh_fifo($Re32=#$II)", -tc_7a91e76a, TypeLD>, Enc_f394d3 { +tc_ac65613f, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010010; @@ -11739,7 +11846,7 @@ def L4_loadalignh_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", -tc_a5d4aeec, TypeLD>, Enc_04c959 { +tc_a32e03e7, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100010; let addrMode = BaseLongOffset; @@ -11759,7 +11866,7 @@ def L4_loadbsw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = membh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010001; @@ -11780,7 +11887,7 @@ def L4_loadbsw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = membh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b { +tc_abfd9a6d, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -11801,7 +11908,7 @@ def L4_loadbsw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = membh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010111; @@ -11820,7 +11927,7 @@ def L4_loadbsw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = membh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe { +tc_abfd9a6d, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100111; let addrMode = BaseLongOffset; @@ -11839,7 +11946,7 @@ def L4_loadbzw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memubh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010011; @@ -11860,7 +11967,7 @@ def L4_loadbzw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memubh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b { +tc_abfd9a6d, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -11881,7 +11988,7 @@ def L4_loadbzw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memubh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010101; @@ -11900,7 +12007,7 @@ def L4_loadbzw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memubh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe { +tc_abfd9a6d, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100101; let addrMode = BaseLongOffset; @@ -11919,7 +12026,7 @@ def L4_loadd_locked : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd_locked($Rs32)", -tc_b43e7930, TypeLD>, Enc_3a3d62 { +tc_64b00d8a, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b010000000; let Inst{31-21} = 0b10010010000; let accessSize = DoubleWordAccess; @@ -11930,7 +12037,7 @@ def L4_loadrb_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memb($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011000; @@ -11951,7 +12058,7 @@ def L4_loadrb_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010000; let hasNewValue = 1; @@ -11959,16 +12066,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; let isPredicable = 1; } def L4_loadrb_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memb($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -11990,7 +12097,7 @@ def L4_loadrd_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memd($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011110; @@ -12009,22 +12116,22 @@ def L4_loadrd_rr : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010110; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; let isPredicable = 1; } def L4_loadrd_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memd($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101110; let addrMode = BaseLongOffset; @@ -12044,7 +12151,7 @@ def L4_loadrh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011010; @@ -12065,7 +12172,7 @@ def L4_loadrh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010010; let hasNewValue = 1; @@ -12073,16 +12180,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; let isPredicable = 1; } def L4_loadrh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -12104,7 +12211,7 @@ def L4_loadri_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memw($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011100; @@ -12125,7 +12232,7 @@ def L4_loadri_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010100; let hasNewValue = 1; @@ -12133,16 +12240,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; let isPredicable = 1; } def L4_loadri_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memw($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -12164,7 +12271,7 @@ def L4_loadrub_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memub($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011001; @@ -12185,7 +12292,7 @@ def L4_loadrub_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010001; let hasNewValue = 1; @@ -12193,16 +12300,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; let isPredicable = 1; } def L4_loadrub_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memub($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -12224,7 +12331,7 @@ def L4_loadruh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memuh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011011; @@ -12245,7 +12352,7 @@ def L4_loadruh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010011; let hasNewValue = 1; @@ -12253,16 +12360,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; let isPredicable = 1; } def L4_loadruh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memuh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -12284,7 +12391,7 @@ def L4_or_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -12303,7 +12410,7 @@ def L4_or_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12311,7 +12418,7 @@ def L4_or_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -12330,7 +12437,7 @@ def L4_or_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12338,7 +12445,7 @@ def L4_or_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -12357,7 +12464,7 @@ def L4_or_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12365,7 +12472,7 @@ def L4_ploadrbf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111000; @@ -12377,8 +12484,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12390,7 +12497,7 @@ def L4_ploadrbf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12399,15 +12506,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111000; @@ -12420,8 +12527,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12433,7 +12540,7 @@ def L4_ploadrbfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12443,15 +12550,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111000; @@ -12462,8 +12569,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12475,7 +12582,7 @@ def L4_ploadrbt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000000; let isPredicated = 1; let hasNewValue = 1; @@ -12483,15 +12590,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111000; @@ -12503,8 +12610,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12516,7 +12623,7 @@ def L4_ploadrbtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010000; let isPredicated = 1; let hasNewValue = 1; @@ -12525,15 +12632,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrdf_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rdd32 = memd(#$Ii)", -tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111110; @@ -12543,8 +12650,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12556,22 +12663,22 @@ def L4_ploadrdf_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110001110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdfnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111110; @@ -12582,8 +12689,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12595,7 +12702,7 @@ def L4_ploadrdfnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110011110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12603,15 +12710,15 @@ let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdt_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rdd32 = memd(#$Ii)", -tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111110; @@ -12620,8 +12727,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12633,21 +12740,21 @@ def L4_ploadrdt_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110000110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdtnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111110; @@ -12657,8 +12764,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12670,22 +12777,22 @@ def L4_ploadrdtnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110010110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111010; @@ -12697,8 +12804,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12710,7 +12817,7 @@ def L4_ploadrhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12719,15 +12826,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111010; @@ -12740,8 +12847,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12753,7 +12860,7 @@ def L4_ploadrhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12763,15 +12870,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111010; @@ -12782,8 +12889,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12795,7 +12902,7 @@ def L4_ploadrht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000010; let isPredicated = 1; let hasNewValue = 1; @@ -12803,15 +12910,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111010; @@ -12823,8 +12930,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12836,7 +12943,7 @@ def L4_ploadrhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010010; let isPredicated = 1; let hasNewValue = 1; @@ -12845,15 +12952,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrif_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memw(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111100; @@ -12865,8 +12972,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12878,7 +12985,7 @@ def L4_ploadrif_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12887,15 +12994,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrifnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111100; @@ -12908,8 +13015,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12921,7 +13028,7 @@ def L4_ploadrifnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12931,15 +13038,15 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrit_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memw(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111100; @@ -12950,8 +13057,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12963,7 +13070,7 @@ def L4_ploadrit_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000100; let isPredicated = 1; let hasNewValue = 1; @@ -12971,15 +13078,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadritnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memw(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111100; @@ -12991,8 +13098,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13004,7 +13111,7 @@ def L4_ploadritnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010100; let isPredicated = 1; let hasNewValue = 1; @@ -13013,15 +13120,15 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrubf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111001; @@ -13033,8 +13140,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13046,7 +13153,7 @@ def L4_ploadrubf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13055,15 +13162,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111001; @@ -13076,8 +13183,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13089,7 +13196,7 @@ def L4_ploadrubfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13099,15 +13206,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111001; @@ -13118,8 +13225,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13131,7 +13238,7 @@ def L4_ploadrubt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000001; let isPredicated = 1; let hasNewValue = 1; @@ -13139,15 +13246,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111001; @@ -13159,8 +13266,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13172,7 +13279,7 @@ def L4_ploadrubtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010001; let isPredicated = 1; let hasNewValue = 1; @@ -13181,15 +13288,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadruhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memuh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111011; @@ -13201,8 +13308,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13214,7 +13321,7 @@ def L4_ploadruhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13223,15 +13330,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111011; @@ -13244,8 +13351,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13257,7 +13364,7 @@ def L4_ploadruhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13267,15 +13374,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memuh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111011; @@ -13286,8 +13393,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13299,7 +13406,7 @@ def L4_ploadruht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000011; let isPredicated = 1; let hasNewValue = 1; @@ -13307,15 +13414,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111011; @@ -13327,8 +13434,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13340,7 +13447,7 @@ def L4_ploadruhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010011; let isPredicated = 1; let hasNewValue = 1; @@ -13349,15 +13456,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_return : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = dealloc_return($Rs32):raw", -tc_675e4897, TypeLD>, Enc_3a3d62, PredNewRel { +tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010110000; let isTerminator = 1; @@ -13378,7 +13485,7 @@ def L4_return_f : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw", -tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { +tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1100; let Inst{31-21} = 0b10010110000; @@ -13400,7 +13507,7 @@ def L4_return_fnew_pnt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b10010110000; @@ -13423,7 +13530,7 @@ def L4_return_fnew_pt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1110; let Inst{31-21} = 0b10010110000; @@ -13446,7 +13553,7 @@ def L4_return_map_to_raw_f : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4) dealloc_return", -tc_2b8da4c2, TypeMAPPING>, Requires<[HasV65]> { +tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13454,7 +13561,7 @@ def L4_return_map_to_raw_fnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:nt", -tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { +tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13462,7 +13569,7 @@ def L4_return_map_to_raw_fnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:t", -tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { +tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13470,7 +13577,7 @@ def L4_return_map_to_raw_t : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4) dealloc_return", -tc_4d5fa3a1, TypeMAPPING>, Requires<[HasV65]> { +tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13478,7 +13585,7 @@ def L4_return_map_to_raw_tnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:nt", -tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { +tc_1981450d, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13486,7 +13593,7 @@ def L4_return_map_to_raw_tnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:t", -tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { +tc_1981450d, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13494,7 +13601,7 @@ def L4_return_t : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw", -tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { +tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b10010110000; @@ -13515,7 +13622,7 @@ def L4_return_tnew_pnt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b10010110000; @@ -13537,7 +13644,7 @@ def L4_return_tnew_pt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b10010110000; @@ -13559,7 +13666,7 @@ def L4_sub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -13578,7 +13685,7 @@ def L4_sub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13586,7 +13693,7 @@ def L4_sub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -13605,7 +13712,7 @@ def L4_sub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13613,7 +13720,7 @@ def L4_sub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -13632,7 +13739,7 @@ def L4_sub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13640,7 +13747,7 @@ def L6_deallocframe_map_to_raw : HInst< (outs), (ins), "deallocframe", -tc_15aa71c5, TypeMAPPING>, Requires<[HasV65]> { +tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13648,7 +13755,7 @@ def L6_memcpy : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2), "memcpy($Rs32,$Rt32,$Mu2)", -tc_a6b1eca9, TypeLD>, Enc_a75aa6, Requires<[HasV66]> { +tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> { let Inst{7-0} = 0b01000000; let Inst{31-21} = 0b10010010000; let mayLoad = 1; @@ -13659,7 +13766,7 @@ def L6_return_map_to_raw : HInst< (outs), (ins), "dealloc_return", -tc_675e4897, TypeMAPPING>, Requires<[HasV65]> { +tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13667,7 +13774,7 @@ def M2_acci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += add($Rs32,$Rt32)", -tc_f675fee8, TypeM>, Enc_2ae154, ImmRegRel { +tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -13682,7 +13789,7 @@ def M2_accii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 += add($Rs32,#$Ii)", -tc_f675fee8, TypeM>, Enc_c90aca, ImmRegRel { +tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010000; let hasNewValue = 1; @@ -13701,7 +13808,7 @@ def M2_cmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyi($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13712,7 +13819,7 @@ def M2_cmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyr($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13723,7 +13830,7 @@ def M2_cmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13735,7 +13842,7 @@ def M2_cmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13747,7 +13854,7 @@ def M2_cmacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13759,7 +13866,7 @@ def M2_cmacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13771,7 +13878,7 @@ def M2_cmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyi($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13781,7 +13888,7 @@ def M2_cmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyr($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13791,7 +13898,7 @@ def M2_cmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13804,7 +13911,7 @@ def M2_cmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13817,7 +13924,7 @@ def M2_cmpyrsc_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -13830,7 +13937,7 @@ def M2_cmpyrsc_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -13843,7 +13950,7 @@ def M2_cmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13854,7 +13961,7 @@ def M2_cmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -13865,7 +13972,7 @@ def M2_cmpysc_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -13876,7 +13983,7 @@ def M2_cmpysc_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -13887,7 +13994,7 @@ def M2_cnacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13899,7 +14006,7 @@ def M2_cnacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13911,7 +14018,7 @@ def M2_cnacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13923,7 +14030,7 @@ def M2_cnacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13935,7 +14042,7 @@ def M2_dpmpyss_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13946,7 +14053,7 @@ def M2_dpmpyss_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -13957,7 +14064,7 @@ def M2_dpmpyss_rnd_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13969,7 +14076,7 @@ def M2_dpmpyss_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13979,7 +14086,7 @@ def M2_dpmpyuu_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13990,7 +14097,7 @@ def M2_dpmpyuu_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -14001,7 +14108,7 @@ def M2_dpmpyuu_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -14011,7 +14118,7 @@ def M2_hmmpyh_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14024,7 +14131,7 @@ def M2_hmmpyh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14037,7 +14144,7 @@ def M2_hmmpyl_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -14050,7 +14157,7 @@ def M2_hmmpyl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14063,7 +14170,7 @@ def M2_maci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyi($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_2ae154, ImmRegRel { +tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -14078,7 +14185,7 @@ def M2_macsin : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 -= mpyi($Rs32,#$Ii)", -tc_05d3a09b, TypeM>, Enc_c90aca { +tc_a154b476, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001100; let hasNewValue = 1; @@ -14096,7 +14203,7 @@ def M2_macsip : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 += mpyi($Rs32,#$Ii)", -tc_05d3a09b, TypeM>, Enc_c90aca, ImmRegRel { +tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001000; let hasNewValue = 1; @@ -14115,7 +14222,7 @@ def M2_mmachs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -14127,7 +14234,7 @@ def M2_mmachs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -14139,7 +14246,7 @@ def M2_mmachs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -14151,7 +14258,7 @@ def M2_mmachs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -14163,7 +14270,7 @@ def M2_mmacls_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -14175,7 +14282,7 @@ def M2_mmacls_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -14187,7 +14294,7 @@ def M2_mmacls_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -14199,7 +14306,7 @@ def M2_mmacls_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -14211,7 +14318,7 @@ def M2_mmacuhs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -14223,7 +14330,7 @@ def M2_mmacuhs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -14235,7 +14342,7 @@ def M2_mmacuhs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -14247,7 +14354,7 @@ def M2_mmacuhs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -14259,7 +14366,7 @@ def M2_mmaculs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -14271,7 +14378,7 @@ def M2_mmaculs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -14283,7 +14390,7 @@ def M2_mmaculs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -14295,7 +14402,7 @@ def M2_mmaculs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -14307,7 +14414,7 @@ def M2_mmpyh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -14318,7 +14425,7 @@ def M2_mmpyh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -14329,7 +14436,7 @@ def M2_mmpyh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -14340,7 +14447,7 @@ def M2_mmpyh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -14351,7 +14458,7 @@ def M2_mmpyl_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -14362,7 +14469,7 @@ def M2_mmpyl_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -14373,7 +14480,7 @@ def M2_mmpyl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -14384,7 +14491,7 @@ def M2_mmpyl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -14395,7 +14502,7 @@ def M2_mmpyuh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -14406,7 +14513,7 @@ def M2_mmpyuh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -14417,7 +14524,7 @@ def M2_mmpyuh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -14428,7 +14535,7 @@ def M2_mmpyuh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -14439,7 +14546,7 @@ def M2_mmpyul_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -14450,7 +14557,7 @@ def M2_mmpyul_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -14461,7 +14568,7 @@ def M2_mmpyul_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -14472,7 +14579,7 @@ def M2_mmpyul_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -14483,7 +14590,7 @@ def M2_mnaci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyi($Rs32,$Rt32)", -tc_bdceeac1, TypeM>, Enc_2ae154, Requires<[HasV66]> { +tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -14496,7 +14603,7 @@ def M2_mpy_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14509,7 +14616,7 @@ def M2_mpy_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14522,7 +14629,7 @@ def M2_mpy_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14535,7 +14642,7 @@ def M2_mpy_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14548,7 +14655,7 @@ def M2_mpy_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14561,7 +14668,7 @@ def M2_mpy_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14574,7 +14681,7 @@ def M2_mpy_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14587,7 +14694,7 @@ def M2_mpy_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14600,7 +14707,7 @@ def M2_mpy_acc_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14614,7 +14721,7 @@ def M2_mpy_acc_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14628,7 +14735,7 @@ def M2_mpy_acc_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14642,7 +14749,7 @@ def M2_mpy_acc_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14656,7 +14763,7 @@ def M2_mpy_acc_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14670,7 +14777,7 @@ def M2_mpy_acc_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14684,7 +14791,7 @@ def M2_mpy_acc_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14698,7 +14805,7 @@ def M2_mpy_acc_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14712,7 +14819,7 @@ def M2_mpy_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14724,7 +14831,7 @@ def M2_mpy_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14736,7 +14843,7 @@ def M2_mpy_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14748,7 +14855,7 @@ def M2_mpy_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14760,7 +14867,7 @@ def M2_mpy_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14772,7 +14879,7 @@ def M2_mpy_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14784,7 +14891,7 @@ def M2_mpy_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14796,7 +14903,7 @@ def M2_mpy_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14808,7 +14915,7 @@ def M2_mpy_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14821,7 +14928,7 @@ def M2_mpy_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14834,7 +14941,7 @@ def M2_mpy_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14847,7 +14954,7 @@ def M2_mpy_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14860,7 +14967,7 @@ def M2_mpy_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14873,7 +14980,7 @@ def M2_mpy_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14886,7 +14993,7 @@ def M2_mpy_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14899,7 +15006,7 @@ def M2_mpy_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14912,7 +15019,7 @@ def M2_mpy_nac_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14926,7 +15033,7 @@ def M2_mpy_nac_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14940,7 +15047,7 @@ def M2_mpy_nac_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14954,7 +15061,7 @@ def M2_mpy_nac_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14968,7 +15075,7 @@ def M2_mpy_nac_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14982,7 +15089,7 @@ def M2_mpy_nac_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14996,7 +15103,7 @@ def M2_mpy_nac_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -15010,7 +15117,7 @@ def M2_mpy_nac_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -15024,7 +15131,7 @@ def M2_mpy_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15036,7 +15143,7 @@ def M2_mpy_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15048,7 +15155,7 @@ def M2_mpy_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15060,7 +15167,7 @@ def M2_mpy_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15072,7 +15179,7 @@ def M2_mpy_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15084,7 +15191,7 @@ def M2_mpy_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15096,7 +15203,7 @@ def M2_mpy_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15108,7 +15215,7 @@ def M2_mpy_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15120,7 +15227,7 @@ def M2_mpy_sat_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15133,7 +15240,7 @@ def M2_mpy_sat_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15146,7 +15253,7 @@ def M2_mpy_sat_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15159,7 +15266,7 @@ def M2_mpy_sat_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15172,7 +15279,7 @@ def M2_mpy_sat_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15185,7 +15292,7 @@ def M2_mpy_sat_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15198,7 +15305,7 @@ def M2_mpy_sat_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15211,7 +15318,7 @@ def M2_mpy_sat_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15224,7 +15331,7 @@ def M2_mpy_sat_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15237,7 +15344,7 @@ def M2_mpy_sat_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15250,7 +15357,7 @@ def M2_mpy_sat_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15263,7 +15370,7 @@ def M2_mpy_sat_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15276,7 +15383,7 @@ def M2_mpy_sat_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15289,7 +15396,7 @@ def M2_mpy_sat_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15302,7 +15409,7 @@ def M2_mpy_sat_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15315,7 +15422,7 @@ def M2_mpy_sat_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15328,7 +15435,7 @@ def M2_mpy_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -15340,7 +15447,7 @@ def M2_mpy_up_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -15352,7 +15459,7 @@ def M2_mpy_up_s1_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -15365,7 +15472,7 @@ def M2_mpyd_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15376,7 +15483,7 @@ def M2_mpyd_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15387,7 +15494,7 @@ def M2_mpyd_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15398,7 +15505,7 @@ def M2_mpyd_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15409,7 +15516,7 @@ def M2_mpyd_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15420,7 +15527,7 @@ def M2_mpyd_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15431,7 +15538,7 @@ def M2_mpyd_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15442,7 +15549,7 @@ def M2_mpyd_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15453,7 +15560,7 @@ def M2_mpyd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15463,7 +15570,7 @@ def M2_mpyd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15473,7 +15580,7 @@ def M2_mpyd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15483,7 +15590,7 @@ def M2_mpyd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15493,7 +15600,7 @@ def M2_mpyd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15503,7 +15610,7 @@ def M2_mpyd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15513,7 +15620,7 @@ def M2_mpyd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15523,7 +15630,7 @@ def M2_mpyd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15533,7 +15640,7 @@ def M2_mpyd_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15544,7 +15651,7 @@ def M2_mpyd_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15555,7 +15662,7 @@ def M2_mpyd_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15566,7 +15673,7 @@ def M2_mpyd_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15577,7 +15684,7 @@ def M2_mpyd_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15588,7 +15695,7 @@ def M2_mpyd_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15599,7 +15706,7 @@ def M2_mpyd_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15610,7 +15717,7 @@ def M2_mpyd_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15621,7 +15728,7 @@ def M2_mpyd_rnd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15631,7 +15738,7 @@ def M2_mpyd_rnd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15641,7 +15748,7 @@ def M2_mpyd_rnd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15651,7 +15758,7 @@ def M2_mpyd_rnd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15661,7 +15768,7 @@ def M2_mpyd_rnd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15671,7 +15778,7 @@ def M2_mpyd_rnd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15681,7 +15788,7 @@ def M2_mpyd_rnd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15691,7 +15798,7 @@ def M2_mpyd_rnd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15701,7 +15808,7 @@ def M2_mpyi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyi($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be, ImmRegRel { +tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -15715,7 +15822,7 @@ def M2_mpysin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Rd32 = -mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, Enc_b8c967 { +tc_38382228, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000100; let hasNewValue = 1; @@ -15726,7 +15833,7 @@ def M2_mpysip : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = +mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, Enc_b8c967 { +tc_38382228, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000000; let hasNewValue = 1; @@ -15742,7 +15849,7 @@ def M2_mpysmi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, m32_0Imm:$Ii), "$Rd32 = mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, ImmRegRel { +tc_38382228, TypeM>, ImmRegRel { let hasNewValue = 1; let opNewValue = 0; let CextOpcode = "M2_mpyi"; @@ -15758,7 +15865,7 @@ def M2_mpysu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpysu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -15770,7 +15877,7 @@ def M2_mpyu_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15783,7 +15890,7 @@ def M2_mpyu_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15796,7 +15903,7 @@ def M2_mpyu_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15809,7 +15916,7 @@ def M2_mpyu_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15822,7 +15929,7 @@ def M2_mpyu_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15835,7 +15942,7 @@ def M2_mpyu_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15848,7 +15955,7 @@ def M2_mpyu_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15861,7 +15968,7 @@ def M2_mpyu_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15874,7 +15981,7 @@ def M2_mpyu_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15886,7 +15993,7 @@ def M2_mpyu_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15898,7 +16005,7 @@ def M2_mpyu_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15910,7 +16017,7 @@ def M2_mpyu_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15922,7 +16029,7 @@ def M2_mpyu_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15934,7 +16041,7 @@ def M2_mpyu_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15946,7 +16053,7 @@ def M2_mpyu_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15958,7 +16065,7 @@ def M2_mpyu_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15970,7 +16077,7 @@ def M2_mpyu_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15983,7 +16090,7 @@ def M2_mpyu_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15996,7 +16103,7 @@ def M2_mpyu_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16009,7 +16116,7 @@ def M2_mpyu_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16022,7 +16129,7 @@ def M2_mpyu_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16035,7 +16142,7 @@ def M2_mpyu_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16048,7 +16155,7 @@ def M2_mpyu_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16061,7 +16168,7 @@ def M2_mpyu_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16074,7 +16181,7 @@ def M2_mpyu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101010; @@ -16086,7 +16193,7 @@ def M2_mpyud_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16097,7 +16204,7 @@ def M2_mpyud_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16108,7 +16215,7 @@ def M2_mpyud_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16119,7 +16226,7 @@ def M2_mpyud_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16130,7 +16237,7 @@ def M2_mpyud_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16141,7 +16248,7 @@ def M2_mpyud_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16152,7 +16259,7 @@ def M2_mpyud_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16163,7 +16270,7 @@ def M2_mpyud_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16174,7 +16281,7 @@ def M2_mpyud_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16184,7 +16291,7 @@ def M2_mpyud_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16194,7 +16301,7 @@ def M2_mpyud_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16204,7 +16311,7 @@ def M2_mpyud_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16214,7 +16321,7 @@ def M2_mpyud_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16224,7 +16331,7 @@ def M2_mpyud_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16234,7 +16341,7 @@ def M2_mpyud_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16244,7 +16351,7 @@ def M2_mpyud_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16254,7 +16361,7 @@ def M2_mpyud_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16265,7 +16372,7 @@ def M2_mpyud_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16276,7 +16383,7 @@ def M2_mpyud_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16287,7 +16394,7 @@ def M2_mpyud_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16298,7 +16405,7 @@ def M2_mpyud_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16309,7 +16416,7 @@ def M2_mpyud_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16320,7 +16427,7 @@ def M2_mpyud_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16331,7 +16438,7 @@ def M2_mpyud_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16342,7 +16449,7 @@ def M2_mpyui : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyui($Rs32,$Rt32)", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -16352,7 +16459,7 @@ def M2_nacci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= add($Rs32,$Rt32)", -tc_f675fee8, TypeM>, Enc_2ae154 { +tc_2c13e7f5, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -16366,7 +16473,7 @@ def M2_naccii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 -= add($Rs32,#$Ii)", -tc_f675fee8, TypeM>, Enc_c90aca { +tc_2c13e7f5, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010100; let hasNewValue = 1; @@ -16384,7 +16491,7 @@ def M2_subacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), "$Rx32 += sub($Rt32,$Rs32)", -tc_f675fee8, TypeM>, Enc_a568d4 { +tc_2c13e7f5, TypeM>, Enc_a568d4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -16398,7 +16505,7 @@ def M2_vabsdiffh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffh($Rtt32,$Rss32)", -tc_002cb246, TypeM>, Enc_ea23e4 { +tc_0dfac0a7, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -16408,7 +16515,7 @@ def M2_vabsdiffw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffw($Rtt32,$Rss32)", -tc_002cb246, TypeM>, Enc_ea23e4 { +tc_0dfac0a7, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -16418,7 +16525,7 @@ def M2_vcmac_s0_sat_i : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -16430,7 +16537,7 @@ def M2_vcmac_s0_sat_r : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16442,7 +16549,7 @@ def M2_vcmpy_s0_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16453,7 +16560,7 @@ def M2_vcmpy_s0_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -16464,7 +16571,7 @@ def M2_vcmpy_s1_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -16475,7 +16582,7 @@ def M2_vcmpy_s1_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16486,7 +16593,7 @@ def M2_vdmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16498,7 +16605,7 @@ def M2_vdmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16510,7 +16617,7 @@ def M2_vdmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -16523,7 +16630,7 @@ def M2_vdmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001100; @@ -16536,7 +16643,7 @@ def M2_vdmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16547,7 +16654,7 @@ def M2_vdmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16558,7 +16665,7 @@ def M2_vmac2 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -16569,7 +16676,7 @@ def M2_vmac2es : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16580,7 +16687,7 @@ def M2_vmac2es_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16592,7 +16699,7 @@ def M2_vmac2es_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16604,7 +16711,7 @@ def M2_vmac2s_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -16616,7 +16723,7 @@ def M2_vmac2s_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -16628,7 +16735,7 @@ def M2_vmac2su_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -16640,7 +16747,7 @@ def M2_vmac2su_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111111; @@ -16652,7 +16759,7 @@ def M2_vmpy2es_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16663,7 +16770,7 @@ def M2_vmpy2es_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16674,7 +16781,7 @@ def M2_vmpy2s_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16685,7 +16792,7 @@ def M2_vmpy2s_s0pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -16698,7 +16805,7 @@ def M2_vmpy2s_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16709,7 +16816,7 @@ def M2_vmpy2s_s1pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -16722,7 +16829,7 @@ def M2_vmpy2su_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16733,7 +16840,7 @@ def M2_vmpy2su_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16744,7 +16851,7 @@ def M2_vraddh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vraddh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001001; @@ -16756,7 +16863,7 @@ def M2_vradduh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vradduh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -16768,7 +16875,7 @@ def M2_vrcmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16779,7 +16886,7 @@ def M2_vrcmaci_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -16790,7 +16897,7 @@ def M2_vrcmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16801,7 +16908,7 @@ def M2_vrcmacr_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -16812,7 +16919,7 @@ def M2_vrcmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16822,7 +16929,7 @@ def M2_vrcmpyi_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16832,7 +16939,7 @@ def M2_vrcmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16842,7 +16949,7 @@ def M2_vrcmpyr_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -16852,7 +16959,7 @@ def M2_vrcmpys_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", -tc_d773585a, TypeM> { +tc_7f8ae742, TypeM> { let isPseudo = 1; let Constraints = "$Rxx32 = $Rxx32in"; } @@ -16860,7 +16967,7 @@ def M2_vrcmpys_acc_s1_h : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -16872,7 +16979,7 @@ def M2_vrcmpys_acc_s1_l : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -16884,14 +16991,14 @@ def M2_vrcmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let isPseudo = 1; } def M2_vrcmpys_s1_h : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16902,7 +17009,7 @@ def M2_vrcmpys_s1_l : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -16913,7 +17020,7 @@ def M2_vrcmpys_s1rp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -16922,7 +17029,7 @@ def M2_vrcmpys_s1rp_h : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16935,7 +17042,7 @@ def M2_vrcmpys_s1rp_l : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16948,7 +17055,7 @@ def M2_vrmac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16959,7 +17066,7 @@ def M2_vrmpy_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16969,7 +17076,7 @@ def M2_xor_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -16983,7 +17090,7 @@ def M4_and_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16997,7 +17104,7 @@ def M4_and_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17011,7 +17118,7 @@ def M4_and_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17025,7 +17132,7 @@ def M4_and_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17039,7 +17146,7 @@ def M4_cmpyi_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17052,7 +17159,7 @@ def M4_cmpyi_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17065,7 +17172,7 @@ def M4_cmpyr_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17078,7 +17185,7 @@ def M4_cmpyr_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17091,7 +17198,7 @@ def M4_mac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -17106,7 +17213,7 @@ def M4_mpyri_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", -tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel { +tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel { let Inst{31-24} = 0b11011000; let hasNewValue = 1; let opNewValue = 0; @@ -17122,7 +17229,7 @@ def M4_mpyri_addr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", -tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel { +tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel { let Inst{31-23} = 0b110111111; let hasNewValue = 1; let opNewValue = 0; @@ -17139,7 +17246,7 @@ def M4_mpyri_addr_u2 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", -tc_1a2fd869, TypeALU64>, Enc_277737 { +tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> { let Inst{31-23} = 0b110111110; let hasNewValue = 1; let opNewValue = 0; @@ -17149,7 +17256,7 @@ def M4_mpyrr_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", -tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel { +tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel { let Inst{31-23} = 0b110101110; let hasNewValue = 1; let opNewValue = 0; @@ -17166,7 +17273,7 @@ def M4_mpyrr_addr : HInst< (outs IntRegs:$Ry32), (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", -tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel { +tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100011000; @@ -17181,7 +17288,7 @@ def M4_nac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -17196,7 +17303,7 @@ def M4_or_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17210,7 +17317,7 @@ def M4_or_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17224,7 +17331,7 @@ def M4_or_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17238,7 +17345,7 @@ def M4_or_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17252,7 +17359,7 @@ def M4_pmpyw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = pmpyw($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -17262,7 +17369,7 @@ def M4_pmpyw_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= pmpyw($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -17273,7 +17380,7 @@ def M4_vpmpyh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vpmpyh($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -17283,7 +17390,7 @@ def M4_vpmpyh_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= vpmpyh($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111101; @@ -17294,7 +17401,7 @@ def M4_vrmpyeh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17305,7 +17412,7 @@ def M4_vrmpyeh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -17316,7 +17423,7 @@ def M4_vrmpyeh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -17326,7 +17433,7 @@ def M4_vrmpyeh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -17336,7 +17443,7 @@ def M4_vrmpyoh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -17347,7 +17454,7 @@ def M4_vrmpyoh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -17358,7 +17465,7 @@ def M4_vrmpyoh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -17368,7 +17475,7 @@ def M4_vrmpyoh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17378,7 +17485,7 @@ def M4_xor_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17392,7 +17499,7 @@ def M4_xor_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17406,7 +17513,7 @@ def M4_xor_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17420,7 +17527,7 @@ def M4_xor_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 ^= xor($Rss32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_88c16c { +tc_a4e22bbd, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010100; @@ -17431,7 +17538,7 @@ def M5_vdmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17443,7 +17550,7 @@ def M5_vdmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17454,7 +17561,7 @@ def M5_vmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybsu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -17465,7 +17572,7 @@ def M5_vmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -17476,7 +17583,7 @@ def M5_vmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybsu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -17486,7 +17593,7 @@ def M5_vmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -17496,7 +17603,7 @@ def M5_vrmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybsu($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -17507,7 +17614,7 @@ def M5_vrmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybu($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -17518,7 +17625,7 @@ def M5_vrmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybsu($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -17528,7 +17635,7 @@ def M5_vrmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybu($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -17538,7 +17645,7 @@ def M6_vabsdiffb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffb($Rtt32,$Rss32)", -tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { +tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -17548,17 +17655,222 @@ def M6_vabsdiffub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffub($Rtt32,$Rss32)", -tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { +tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; let prefersSlot3 = 1; } +def M7_dcmpyiw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyiw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M7_dcmpyiw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyiw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyiwc : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyiw($Rss32,$Rtt32*)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +} +def M7_dcmpyiwc_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyiw($Rss32,$Rtt32*)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyrw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyrw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +} +def M7_dcmpyrw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyrw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyrwc : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyrw($Rss32,$Rtt32*)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M7_dcmpyrwc_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyrw($Rss32,$Rtt32*)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_vdmpy : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpyw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Requires<[HasV67]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M7_vdmpy_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpyw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Requires<[HasV67]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_wcmpyiw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiw_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiwc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiwc_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrw_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrwc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrwc_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} def PS_loadrbabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17567,8 +17879,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17581,15 +17893,15 @@ def PS_loadrdabs : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17602,7 +17914,7 @@ def PS_loadrhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17611,8 +17923,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17625,7 +17937,7 @@ def PS_loadriabs : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17634,8 +17946,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17648,7 +17960,7 @@ def PS_loadrubabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17657,8 +17969,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17671,7 +17983,7 @@ def PS_loadruhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17680,8 +17992,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17694,15 +18006,15 @@ def PS_storerbabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17716,7 +18028,7 @@ def PS_storerbnewabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17727,8 +18039,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17742,15 +18054,15 @@ def PS_storerdabs : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(#$Ii) = $Rtt32", -tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17763,15 +18075,15 @@ def PS_storerfabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32.h", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17784,15 +18096,15 @@ def PS_storerhabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17806,7 +18118,7 @@ def PS_storerhnewabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17817,8 +18129,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17832,15 +18144,15 @@ def PS_storeriabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17854,7 +18166,7 @@ def PS_storerinewabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17865,8 +18177,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17876,11 +18188,22 @@ let opExtentBits = 18; let opExtentAlign = 2; let opNewValue = 1; } +def PS_trap1 : HInst< +(outs), +(ins u8_0Imm:$Ii), +"trap1(#$Ii)", +tc_53c851ab, TypeJ>, Enc_a51a9a, Requires<[HasPreV65]> { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010010000000; +let isSolo = 1; +} def S2_addasl_rrri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), "$Rd32 = addasl($Rt32,$Rs32,#$Ii)", -tc_f675fee8, TypeS_3op>, Enc_47ef61 { +tc_2c13e7f5, TypeS_3op>, Enc_47ef61 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000100000; let hasNewValue = 1; @@ -17891,7 +18214,7 @@ def S2_allocframe : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u11_3Imm:$Ii), "allocframe($Rx32,#$Ii):raw", -tc_b44ecf75, TypeST>, Enc_22c845 { +tc_934753bb, TypeST>, Enc_22c845 { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10100000100; let hasNewValue = 1; @@ -17907,7 +18230,7 @@ def S2_asl_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asl($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000000000; } @@ -17915,7 +18238,7 @@ def S2_asl_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asl($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17925,7 +18248,7 @@ def S2_asl_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17935,7 +18258,7 @@ def S2_asl_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asl($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17945,7 +18268,7 @@ def S2_asl_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17955,7 +18278,7 @@ def S2_asl_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -17965,7 +18288,7 @@ def S2_asl_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -17976,7 +18299,7 @@ def S2_asl_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asl($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17989,7 +18312,7 @@ def S2_asl_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18002,7 +18325,7 @@ def S2_asl_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asl($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18015,7 +18338,7 @@ def S2_asl_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18028,7 +18351,7 @@ def S2_asl_i_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii):sat", -tc_779080bf, TypeS_2op>, Enc_a05677 { +tc_8a825db2, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -18041,7 +18364,7 @@ def S2_asl_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -18054,7 +18377,7 @@ def S2_asl_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vaslh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -18063,7 +18386,7 @@ def S2_asl_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vaslw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -18072,7 +18395,7 @@ def S2_asl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asl($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18081,7 +18404,7 @@ def S2_asl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18092,7 +18415,7 @@ def S2_asl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18103,7 +18426,7 @@ def S2_asl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18114,7 +18437,7 @@ def S2_asl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18125,7 +18448,7 @@ def S2_asl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18136,7 +18459,7 @@ def S2_asl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18147,7 +18470,7 @@ def S2_asl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18160,7 +18483,7 @@ def S2_asl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18173,7 +18496,7 @@ def S2_asl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18186,7 +18509,7 @@ def S2_asl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18199,7 +18522,7 @@ def S2_asl_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32):sat", -tc_779080bf, TypeS_3op>, Enc_5ab2be { +tc_8a825db2, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -18212,7 +18535,7 @@ def S2_asl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18221,7 +18544,7 @@ def S2_asl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18230,7 +18553,7 @@ def S2_asr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000000000; } @@ -18238,7 +18561,7 @@ def S2_asr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18248,7 +18571,7 @@ def S2_asr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18258,7 +18581,7 @@ def S2_asr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18268,7 +18591,7 @@ def S2_asr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18278,7 +18601,7 @@ def S2_asr_i_p_rnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii):rnd", -tc_002cb246, TypeS_2op>, Enc_5eac98 { +tc_0dfac0a7, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18287,14 +18610,14 @@ def S2_asr_i_p_rnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asrrnd($Rss32,#$Ii)", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let isPseudo = 1; } def S2_asr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -18305,7 +18628,7 @@ def S2_asr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18318,7 +18641,7 @@ def S2_asr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18331,7 +18654,7 @@ def S2_asr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18344,7 +18667,7 @@ def S2_asr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18357,7 +18680,7 @@ def S2_asr_i_r_rnd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii):rnd", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -18369,7 +18692,7 @@ def S2_asr_i_r_rnd_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asrrnd($Rs32,#$Ii)", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -18378,7 +18701,7 @@ def S2_asr_i_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rd32 = vasrw($Rss32,#$Ii)", -tc_4414d8b1, TypeS_2op>, Enc_8dec2e { +tc_f34c1c21, TypeS_2op>, Enc_8dec2e { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -18390,7 +18713,7 @@ def S2_asr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -18399,7 +18722,7 @@ def S2_asr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vasrw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -18408,7 +18731,7 @@ def S2_asr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asr($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18417,7 +18740,7 @@ def S2_asr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18428,7 +18751,7 @@ def S2_asr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18439,7 +18762,7 @@ def S2_asr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18450,7 +18773,7 @@ def S2_asr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18461,7 +18784,7 @@ def S2_asr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18472,7 +18795,7 @@ def S2_asr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18483,7 +18806,7 @@ def S2_asr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18496,7 +18819,7 @@ def S2_asr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18509,7 +18832,7 @@ def S2_asr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18522,7 +18845,7 @@ def S2_asr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18535,7 +18858,7 @@ def S2_asr_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32):sat", -tc_779080bf, TypeS_3op>, Enc_5ab2be { +tc_8a825db2, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -18548,7 +18871,7 @@ def S2_asr_r_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vasrw($Rss32,$Rt32)", -tc_4414d8b1, TypeS_3op>, Enc_3d5b28 { +tc_f34c1c21, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -18560,7 +18883,7 @@ def S2_asr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18569,7 +18892,7 @@ def S2_asr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18578,7 +18901,7 @@ def S2_brev : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = brev($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18589,7 +18912,7 @@ def S2_brevp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = brev($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18598,7 +18921,7 @@ def S2_cabacdecbin : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = decbin($Rss32,$Rtt32)", -tc_76851da1, TypeS_3op>, Enc_a56825 { +tc_db596beb, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -18610,7 +18933,7 @@ def S2_cl0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl0($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18621,7 +18944,7 @@ def S2_cl0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl0($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18632,7 +18955,7 @@ def S2_cl1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl1($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18643,7 +18966,7 @@ def S2_cl1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl1($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18654,7 +18977,7 @@ def S2_clb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = clb($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18665,7 +18988,7 @@ def S2_clbnorm : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = normamt($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18676,7 +18999,7 @@ def S2_clbp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = clb($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18687,7 +19010,7 @@ def S2_clrbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = clrbit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -18698,7 +19021,7 @@ def S2_clrbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = clrbit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -18709,7 +19032,7 @@ def S2_ct0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct0($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18720,7 +19043,7 @@ def S2_ct0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct0($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18731,7 +19054,7 @@ def S2_ct1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct1($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18742,7 +19065,7 @@ def S2_ct1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct1($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18753,7 +19076,7 @@ def S2_deinterleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = deinterleave($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18762,7 +19085,7 @@ def S2_extractu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extractu($Rs32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b388cf { +tc_2c13e7f5, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011010; let hasNewValue = 1; @@ -18773,7 +19096,7 @@ def S2_extractu_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extractu($Rs32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_e07374 { +tc_a08b630b, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -18785,7 +19108,7 @@ def S2_extractup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extractu($Rss32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b84c4c { +tc_2c13e7f5, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10000001; let prefersSlot3 = 1; } @@ -18793,7 +19116,7 @@ def S2_extractup_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extractu($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -18803,7 +19126,7 @@ def S2_insert : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = insert($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op>, Enc_a1e29d { +tc_bb831a7c, TypeS_2op>, Enc_a1e29d { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011110; let hasNewValue = 1; @@ -18815,7 +19138,7 @@ def S2_insert_rp : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rx32 = insert($Rs32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_179b35 { +tc_a4e22bbd, TypeS_3op>, Enc_179b35 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001000000; @@ -18828,7 +19151,7 @@ def S2_insertp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rxx32 = insert($Rss32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op>, Enc_143a3c { +tc_bb831a7c, TypeS_2op>, Enc_143a3c { let Inst{31-24} = 0b10000011; let prefersSlot3 = 1; let Constraints = "$Rxx32 = $Rxx32in"; @@ -18837,7 +19160,7 @@ def S2_insertp_rp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 = insert($Rss32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_88c16c { +tc_a4e22bbd, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010000; @@ -18848,7 +19171,7 @@ def S2_interleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = interleave($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18857,7 +19180,7 @@ def S2_lfsp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = lfs($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -18867,7 +19190,7 @@ def S2_lsl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsl($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18876,7 +19199,7 @@ def S2_lsl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18887,7 +19210,7 @@ def S2_lsl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18898,7 +19221,7 @@ def S2_lsl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18909,7 +19232,7 @@ def S2_lsl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18920,7 +19243,7 @@ def S2_lsl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18931,7 +19254,7 @@ def S2_lsl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsl($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18942,7 +19265,7 @@ def S2_lsl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18955,7 +19278,7 @@ def S2_lsl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18968,7 +19291,7 @@ def S2_lsl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18981,7 +19304,7 @@ def S2_lsl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18994,7 +19317,7 @@ def S2_lsl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -19003,7 +19326,7 @@ def S2_lsl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -19012,7 +19335,7 @@ def S2_lsr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = lsr($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000000000; } @@ -19020,7 +19343,7 @@ def S2_lsr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += lsr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -19030,7 +19353,7 @@ def S2_lsr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -19040,7 +19363,7 @@ def S2_lsr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= lsr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -19050,7 +19373,7 @@ def S2_lsr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -19060,7 +19383,7 @@ def S2_lsr_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -19070,7 +19393,7 @@ def S2_lsr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = lsr($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -19081,7 +19404,7 @@ def S2_lsr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += lsr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -19094,7 +19417,7 @@ def S2_lsr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -19107,7 +19430,7 @@ def S2_lsr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= lsr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -19120,7 +19443,7 @@ def S2_lsr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -19133,7 +19456,7 @@ def S2_lsr_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -19146,7 +19469,7 @@ def S2_lsr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vlsrh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b001; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -19155,7 +19478,7 @@ def S2_lsr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vlsrw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -19164,7 +19487,7 @@ def S2_lsr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsr($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -19173,7 +19496,7 @@ def S2_lsr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -19184,7 +19507,7 @@ def S2_lsr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -19195,7 +19518,7 @@ def S2_lsr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -19206,7 +19529,7 @@ def S2_lsr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -19217,7 +19540,7 @@ def S2_lsr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -19228,7 +19551,7 @@ def S2_lsr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsr($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -19239,7 +19562,7 @@ def S2_lsr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -19252,7 +19575,7 @@ def S2_lsr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -19265,7 +19588,7 @@ def S2_lsr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -19278,7 +19601,7 @@ def S2_lsr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -19291,7 +19614,7 @@ def S2_lsr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -19300,7 +19623,7 @@ def S2_lsr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -19309,7 +19632,7 @@ def S2_mask : HInst< (outs IntRegs:$Rd32), (ins u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = mask(#$Ii,#$II)", -tc_9461ff31, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> { +tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> { let Inst{13-13} = 0b1; let Inst{20-16} = 0b00000; let Inst{31-23} = 0b100011010; @@ -19321,7 +19644,7 @@ def S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_be32a5 { +tc_713b66bf, TypeALU32_3op>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101100; @@ -19331,7 +19654,7 @@ def S2_parityp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = parity($Rss32,$Rtt32)", -tc_002cb246, TypeALU64>, Enc_d2216a { +tc_a08b630b, TypeALU64>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010000000; @@ -19343,7 +19666,7 @@ def S2_pstorerbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100000; let isPredicated = 1; @@ -19351,9 +19674,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19365,7 +19688,7 @@ def S2_pstorerbf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { +tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19383,7 +19706,7 @@ def S2_pstorerbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19391,7 +19714,7 @@ def S2_pstorerbfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { +tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19410,7 +19733,7 @@ def S2_pstorerbnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000100101; @@ -19422,9 +19745,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19436,7 +19759,7 @@ def S2_pstorerbnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { +tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -19449,8 +19772,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19458,7 +19781,7 @@ def S2_pstorerbnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19467,7 +19790,7 @@ def S2_pstorerbnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { +tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -19481,8 +19804,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19490,7 +19813,7 @@ def S2_pstorerbnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000000101; @@ -19501,9 +19824,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19515,7 +19838,7 @@ def S2_pstorerbnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { +tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -19527,8 +19850,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19536,7 +19859,7 @@ def S2_pstorerbnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memb($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19545,7 +19868,7 @@ def S2_pstorerbnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { +tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -19558,8 +19881,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19567,16 +19890,16 @@ def S2_pstorerbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19588,7 +19911,7 @@ def S2_pstorerbt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { +tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19605,7 +19928,7 @@ def S2_pstorerbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memb($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19613,7 +19936,7 @@ def S2_pstorerbtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { +tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19631,7 +19954,7 @@ def S2_pstorerdf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100110; let isPredicated = 1; @@ -19639,9 +19962,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19652,7 +19975,7 @@ def S2_pstorerdf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { +tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19662,15 +19985,15 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32) = $Rtt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19678,7 +20001,7 @@ def S2_pstorerdfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { +tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19689,24 +20012,24 @@ let addrMode = PostInc; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000110; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19717,7 +20040,7 @@ def S2_pstorerdt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { +tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19726,15 +20049,15 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32) = $Rtt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19742,7 +20065,7 @@ def S2_pstorerdtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { +tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19752,15 +20075,15 @@ let addrMode = PostInc; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerff_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100011; let isPredicated = 1; @@ -19768,9 +20091,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19781,7 +20104,7 @@ def S2_pstorerff_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19791,15 +20114,15 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerff_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32.h", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19807,7 +20130,7 @@ def S2_pstorerffnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19818,24 +20141,24 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerft_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000011; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19846,7 +20169,7 @@ def S2_pstorerft_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19855,15 +20178,15 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerft_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32.h", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19871,7 +20194,7 @@ def S2_pstorerftnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19881,15 +20204,15 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100010; let isPredicated = 1; @@ -19897,9 +20220,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19911,7 +20234,7 @@ def S2_pstorerhf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19929,7 +20252,7 @@ def S2_pstorerhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19937,7 +20260,7 @@ def S2_pstorerhfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19956,7 +20279,7 @@ def S2_pstorerhnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000100101; @@ -19968,9 +20291,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19982,7 +20305,7 @@ def S2_pstorerhnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { +tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -19995,8 +20318,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20004,7 +20327,7 @@ def S2_pstorerhnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20013,7 +20336,7 @@ def S2_pstorerhnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { +tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -20027,8 +20350,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20036,7 +20359,7 @@ def S2_pstorerhnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000000101; @@ -20047,9 +20370,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20061,7 +20384,7 @@ def S2_pstorerhnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { +tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -20073,8 +20396,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20082,7 +20405,7 @@ def S2_pstorerhnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memh($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20091,7 +20414,7 @@ def S2_pstorerhnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { +tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -20104,8 +20427,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20113,16 +20436,16 @@ def S2_pstorerht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20134,7 +20457,7 @@ def S2_pstorerht_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20151,7 +20474,7 @@ def S2_pstorerht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20159,7 +20482,7 @@ def S2_pstorerhtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20177,7 +20500,7 @@ def S2_pstorerif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100100; let isPredicated = 1; @@ -20185,9 +20508,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20199,7 +20522,7 @@ def S2_pstorerif_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20217,7 +20540,7 @@ def S2_pstorerif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20225,7 +20548,7 @@ def S2_pstorerifnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20236,8 +20559,8 @@ let addrMode = PostInc; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20245,7 +20568,7 @@ def S2_pstorerinewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000100101; @@ -20257,9 +20580,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20271,7 +20594,7 @@ def S2_pstorerinewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { +tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -20284,8 +20607,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20293,7 +20616,7 @@ def S2_pstorerinewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20302,7 +20625,7 @@ def S2_pstorerinewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { +tc_f529831b, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -20316,8 +20639,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20325,7 +20648,7 @@ def S2_pstorerinewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000000101; @@ -20336,9 +20659,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20350,7 +20673,7 @@ def S2_pstorerinewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { +tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -20362,8 +20685,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20371,7 +20694,7 @@ def S2_pstorerinewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memw($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20380,7 +20703,7 @@ def S2_pstorerinewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { +tc_f529831b, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -20393,8 +20716,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20402,16 +20725,16 @@ def S2_pstorerit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000100; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20423,7 +20746,7 @@ def S2_pstorerit_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20440,7 +20763,7 @@ def S2_pstorerit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memw($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20448,7 +20771,7 @@ def S2_pstoreritnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20466,7 +20789,7 @@ def S2_setbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = setbit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -20477,7 +20800,7 @@ def S2_setbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = setbit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -20488,7 +20811,7 @@ def S2_shuffeb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeb($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20497,7 +20820,7 @@ def S2_shuffeh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20506,7 +20829,7 @@ def S2_shuffob : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffob($Rtt32,$Rss32)", -tc_946df596, TypeS_3op>, Enc_ea23e4 { +tc_5da50c4b, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20515,7 +20838,7 @@ def S2_shuffoh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffoh($Rtt32,$Rss32)", -tc_946df596, TypeS_3op>, Enc_ea23e4 { +tc_5da50c4b, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -20524,15 +20847,15 @@ def S2_storerb_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -20545,7 +20868,7 @@ def S2_storerb_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111000; let addrMode = PostInc; @@ -20559,7 +20882,7 @@ def S2_storerb_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_b15941, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001000; @@ -20575,7 +20898,7 @@ def S2_storerb_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001000; let addrMode = PostInc; @@ -20590,7 +20913,7 @@ def S2_storerb_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "memb($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20598,8 +20921,8 @@ let Inst{31-21} = 0b10101011000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -20608,12 +20931,13 @@ def S2_storerb_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20621,7 +20945,7 @@ def S2_storerb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20629,7 +20953,7 @@ def S2_storerbgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let accessSize = ByteAccess; @@ -20647,7 +20971,7 @@ def S2_storerbnew_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_4df4e9, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -20657,9 +20981,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20672,7 +20996,7 @@ def S2_storerbnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101111101; @@ -20690,7 +21014,7 @@ def S2_storerbnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_96ce4f, AddrModeRel { +tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b00; @@ -20710,7 +21034,7 @@ def S2_storerbnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101001101; @@ -20729,7 +21053,7 @@ def S2_storerbnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "memb($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_c7cd90, AddrModeRel { +tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b000; @@ -20750,7 +21074,7 @@ def S2_storerbnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -20760,6 +21084,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -20767,7 +21092,7 @@ def S2_storerbnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memb($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -20776,7 +21101,7 @@ def S2_storerbnewgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -20798,15 +21123,15 @@ def S2_storerd_io : HInst< (outs), (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+#$Ii) = $Rtt32", -tc_30b9bb4a, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20818,7 +21143,7 @@ def S2_storerd_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2:brev) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111110; let addrMode = PostInc; @@ -20830,7 +21155,7 @@ def S2_storerd_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", -tc_e86aa961, TypeST>, Enc_395cc4 { +tc_b4dc7630, TypeST>, Enc_395cc4 { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001110; @@ -20844,7 +21169,7 @@ def S2_storerd_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++I:circ($Mu2)) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001110; let addrMode = PostInc; @@ -20857,7 +21182,7 @@ def S2_storerd_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii) = $Rtt32", -tc_da97ee82, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20865,8 +21190,8 @@ let Inst{31-21} = 0b10101011110; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20874,7 +21199,7 @@ def S2_storerd_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101110; let addrMode = PostInc; @@ -20886,7 +21211,7 @@ def S2_storerd_zomap : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd($Rs32) = $Rtt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20894,7 +21219,7 @@ def S2_storerdgp : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(gp+#$Ii) = $Rtt32", -tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -20911,15 +21236,15 @@ def S2_storerf_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32.h", -tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20931,7 +21256,7 @@ def S2_storerf_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111011; let addrMode = PostInc; @@ -20943,7 +21268,7 @@ def S2_storerf_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", -tc_e86aa961, TypeST>, Enc_935d9b { +tc_b4dc7630, TypeST>, Enc_935d9b { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001011; @@ -20957,7 +21282,7 @@ def S2_storerf_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001011; let addrMode = PostInc; @@ -20970,7 +21295,7 @@ def S2_storerf_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20978,8 +21303,8 @@ let Inst{31-21} = 0b10101011011; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20987,7 +21312,7 @@ def S2_storerf_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101011; let addrMode = PostInc; @@ -20999,7 +21324,7 @@ def S2_storerf_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32.h", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21007,7 +21332,7 @@ def S2_storerfgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32.h", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -21024,15 +21349,15 @@ def S2_storerh_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -21045,7 +21370,7 @@ def S2_storerh_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111010; let addrMode = PostInc; @@ -21059,7 +21384,7 @@ def S2_storerh_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_935d9b, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001010; @@ -21075,7 +21400,7 @@ def S2_storerh_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001010; let addrMode = PostInc; @@ -21090,7 +21415,7 @@ def S2_storerh_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -21098,8 +21423,8 @@ let Inst{31-21} = 0b10101011010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -21108,12 +21433,13 @@ def S2_storerh_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -21121,7 +21447,7 @@ def S2_storerh_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21129,7 +21455,7 @@ def S2_storerhgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -21147,7 +21473,7 @@ def S2_storerhnew_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_0d8870, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -21157,9 +21483,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -21172,7 +21498,7 @@ def S2_storerhnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101111101; @@ -21190,7 +21516,7 @@ def S2_storerhnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_91b9fe, AddrModeRel { +tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b01; @@ -21210,7 +21536,7 @@ def S2_storerhnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101001101; @@ -21229,7 +21555,7 @@ def S2_storerhnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "memh($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_e26546, AddrModeRel { +tc_92240447, TypeST>, Enc_e26546, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b001; @@ -21250,7 +21576,7 @@ def S2_storerhnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -21260,6 +21586,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -21267,7 +21594,7 @@ def S2_storerhnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memh($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -21276,7 +21603,7 @@ def S2_storerhnewgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -21298,15 +21625,15 @@ def S2_storeri_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -21319,7 +21646,7 @@ def S2_storeri_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111100; let addrMode = PostInc; @@ -21333,7 +21660,7 @@ def S2_storeri_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_79b8c8, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001100; @@ -21349,7 +21676,7 @@ def S2_storeri_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001100; let addrMode = PostInc; @@ -21364,7 +21691,7 @@ def S2_storeri_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "memw($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -21372,8 +21699,8 @@ let Inst{31-21} = 0b10101011100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -21382,12 +21709,13 @@ def S2_storeri_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -21395,7 +21723,7 @@ def S2_storeri_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21403,7 +21731,7 @@ def S2_storerigp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let accessSize = WordAccess; @@ -21421,7 +21749,7 @@ def S2_storerinew_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_690862, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -21431,9 +21759,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -21446,7 +21774,7 @@ def S2_storerinew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101111101; @@ -21464,7 +21792,7 @@ def S2_storerinew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_3f97c8, AddrModeRel { +tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b10; @@ -21484,7 +21812,7 @@ def S2_storerinew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101001101; @@ -21503,7 +21831,7 @@ def S2_storerinew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "memw($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_223005, AddrModeRel { +tc_92240447, TypeST>, Enc_223005, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b010; @@ -21523,7 +21851,7 @@ def S2_storerinew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -21533,6 +21861,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -21540,7 +21869,7 @@ def S2_storerinew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memw($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -21549,7 +21878,7 @@ def S2_storerinewgp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -21571,7 +21900,7 @@ def S2_storew_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw_locked($Rs32,$Pd4) = $Rt32", -tc_5abb5e3f, TypeST>, Enc_c2b48e { +tc_6f42bc60, TypeST>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000101; @@ -21584,7 +21913,7 @@ def S2_svsathb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -21595,7 +21924,7 @@ def S2_svsathub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathub($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -21606,7 +21935,7 @@ def S2_tableidxb : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011100; let hasNewValue = 1; let opNewValue = 0; @@ -21617,7 +21946,7 @@ def S2_tableidxb_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21628,7 +21957,7 @@ def S2_tableidxd : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011111; let hasNewValue = 1; let opNewValue = 0; @@ -21639,7 +21968,7 @@ def S2_tableidxd_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21649,7 +21978,7 @@ def S2_tableidxh : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011101; let hasNewValue = 1; let opNewValue = 0; @@ -21660,7 +21989,7 @@ def S2_tableidxh_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21670,7 +21999,7 @@ def S2_tableidxw : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011110; let hasNewValue = 1; let opNewValue = 0; @@ -21681,7 +22010,7 @@ def S2_tableidxw_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21691,7 +22020,7 @@ def S2_togglebit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = togglebit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -21702,7 +22031,7 @@ def S2_togglebit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = togglebit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -21713,7 +22042,7 @@ def S2_tstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = tstbit($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101000; @@ -21722,7 +22051,7 @@ def S2_tstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = tstbit($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111000; @@ -21731,7 +22060,7 @@ def S2_valignib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", -tc_b4b5c03a, TypeS_3op>, Enc_729ff7 { +tc_6fc5dbea, TypeS_3op>, Enc_729ff7 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000000; } @@ -21739,7 +22068,7 @@ def S2_valignrb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", -tc_b4b5c03a, TypeS_3op>, Enc_8c6530 { +tc_6fc5dbea, TypeS_3op>, Enc_8c6530 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010000; @@ -21748,7 +22077,7 @@ def S2_vcnegh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcnegh($Rss32,$Rt32)", -tc_779080bf, TypeS_3op>, Enc_927852 { +tc_8a825db2, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21759,7 +22088,7 @@ def S2_vcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcrotate($Rss32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_927852 { +tc_0dfac0a7, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21770,7 +22099,7 @@ def S2_vrcnegh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcnegh($Rss32,$Rt32)", -tc_d773585a, TypeS_3op>, Enc_1aa186 { +tc_7f8ae742, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -21781,7 +22110,7 @@ def S2_vrndpackwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_e3d699e3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21792,7 +22121,7 @@ def S2_vrndpackwhs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_90cd8b { +tc_d61dfdc3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21804,7 +22133,7 @@ def S2_vsathb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21815,7 +22144,7 @@ def S2_vsathb_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21824,7 +22153,7 @@ def S2_vsathub : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathub($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21835,7 +22164,7 @@ def S2_vsathub_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathub($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21844,7 +22173,7 @@ def S2_vsatwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21855,7 +22184,7 @@ def S2_vsatwh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21864,7 +22193,7 @@ def S2_vsatwuh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwuh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21875,7 +22204,7 @@ def S2_vsatwuh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwuh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21884,7 +22213,7 @@ def S2_vsplatrb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsplatb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -21896,7 +22225,7 @@ def S2_vsplatrh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplath($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100010; let isReMaterializable = 1; @@ -21906,7 +22235,7 @@ def S2_vspliceib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", -tc_b4b5c03a, TypeS_3op>, Enc_d50cd3 { +tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000100; } @@ -21914,7 +22243,7 @@ def S2_vsplicerb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", -tc_b4b5c03a, TypeS_3op>, Enc_dbd70c { +tc_6fc5dbea, TypeS_3op>, Enc_dbd70c { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010100; @@ -21923,7 +22252,7 @@ def S2_vsxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxtbh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21933,7 +22262,7 @@ def S2_vsxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxthw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21943,7 +22272,7 @@ def S2_vtrunehb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunehb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21953,7 +22282,7 @@ def S2_vtrunewh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunewh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21962,7 +22291,7 @@ def S2_vtrunohb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunohb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21972,7 +22301,7 @@ def S2_vtrunowh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunowh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21981,7 +22310,7 @@ def S2_vzxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxtbh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21991,7 +22320,7 @@ def S2_vzxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxthw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -22001,7 +22330,7 @@ def S4_addaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,add($Ru32,#$Ii))", -tc_f675fee8, TypeALU64>, Enc_8b8d61 { +tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> { let Inst{31-23} = 0b110110110; let hasNewValue = 1; let opNewValue = 0; @@ -22016,7 +22345,7 @@ def S4_addi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,asl($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b100; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22034,7 +22363,7 @@ def S4_addi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b100; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22052,7 +22381,7 @@ def S4_andi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,asl($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b000; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22070,7 +22399,7 @@ def S4_andi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b000; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22088,7 +22417,7 @@ def S4_clbaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rs32),#$Ii)", -tc_002cb246, TypeS_2op>, Enc_9fae8a { +tc_a08b630b, TypeS_2op>, Enc_9fae8a { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10001100001; let hasNewValue = 1; @@ -22099,7 +22428,7 @@ def S4_clbpaddi : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rss32),#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a1640c { +tc_a08b630b, TypeS_2op>, Enc_a1640c { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -22110,7 +22439,7 @@ def S4_clbpnorm : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = normamt($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -22121,7 +22450,7 @@ def S4_extract : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extract($Rs32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b388cf { +tc_2c13e7f5, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011011; let hasNewValue = 1; @@ -22132,7 +22461,7 @@ def S4_extract_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extract($Rs32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_e07374 { +tc_a08b630b, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -22144,7 +22473,7 @@ def S4_extractp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extract($Rss32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b84c4c { +tc_2c13e7f5, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10001010; let prefersSlot3 = 1; } @@ -22152,7 +22481,7 @@ def S4_extractp_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extract($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -22162,7 +22491,7 @@ def S4_lsli : HInst< (outs IntRegs:$Rd32), (ins s6_0Imm:$Ii, IntRegs:$Rt32), "$Rd32 = lsl(#$Ii,$Rt32)", -tc_946df596, TypeS_3op>, Enc_fef969 { +tc_5da50c4b, TypeS_3op>, Enc_fef969 { let Inst{7-6} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -22173,7 +22502,7 @@ def S4_ntstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = !tstbit($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101001; @@ -22182,7 +22511,7 @@ def S4_ntstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !tstbit($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111001; @@ -22191,7 +22520,7 @@ def S4_or_andi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= and($Rs32,#$Ii)", -tc_f429765c, TypeALU64>, Enc_b0e9d8 { +tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101000; let hasNewValue = 1; let opNewValue = 0; @@ -22208,7 +22537,7 @@ def S4_or_andix : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), "$Rx32 = or($Ru32,and($Rx32in,#$Ii))", -tc_f429765c, TypeALU64>, Enc_b4e6cf { +tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> { let Inst{31-22} = 0b1101101001; let hasNewValue = 1; let opNewValue = 0; @@ -22224,7 +22553,7 @@ def S4_or_ori : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= or($Rs32,#$Ii)", -tc_f429765c, TypeALU64>, Enc_b0e9d8 { +tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101010; let hasNewValue = 1; let opNewValue = 0; @@ -22241,7 +22570,7 @@ def S4_ori_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,asl($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b010; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22259,7 +22588,7 @@ def S4_ori_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b010; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22277,7 +22606,7 @@ def S4_parity : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = parity($Rs32,$Rt32)", -tc_002cb246, TypeALU64>, Enc_5ab2be { +tc_a08b630b, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101111; @@ -22289,7 +22618,7 @@ def S4_pstorerbf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22300,8 +22629,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22314,23 +22643,23 @@ def S4_pstorerbf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101000; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22342,8 +22671,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22356,7 +22685,7 @@ def S4_pstorerbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110000; let isPredicated = 1; @@ -22365,9 +22694,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -22379,7 +22708,7 @@ def S4_pstorerbfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22387,16 +22716,16 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22404,7 +22733,7 @@ def S4_pstorerbnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -22418,8 +22747,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22432,7 +22761,7 @@ def S4_pstorerbnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -22443,16 +22772,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -22467,8 +22796,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22481,7 +22810,7 @@ def S4_pstorerbnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000110101; @@ -22494,9 +22823,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22508,7 +22837,7 @@ def S4_pstorerbnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -22520,16 +22849,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22538,7 +22867,7 @@ def S4_pstorerbnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -22551,8 +22880,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22565,7 +22894,7 @@ def S4_pstorerbnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -22575,16 +22904,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -22598,8 +22927,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22612,7 +22941,7 @@ def S4_pstorerbnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000010101; @@ -22624,9 +22953,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22638,7 +22967,7 @@ def S4_pstorerbnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -22649,16 +22978,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22667,7 +22996,7 @@ def S4_pstorerbt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22677,8 +23006,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22691,22 +23020,22 @@ def S4_pstorerbt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100000; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22717,8 +23046,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22731,7 +23060,7 @@ def S4_pstorerbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010000; let isPredicated = 1; @@ -22739,9 +23068,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -22753,23 +23082,23 @@ def S4_pstorerbtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110000; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22777,7 +23106,7 @@ def S4_pstorerdf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd(#$Ii) = $Rtt32", -tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22788,8 +23117,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22801,22 +23130,22 @@ def S4_pstorerdf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110101110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd(#$Ii) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22828,8 +23157,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22841,7 +23170,7 @@ def S4_pstorerdfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110110; let isPredicated = 1; @@ -22850,9 +23179,9 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22863,7 +23192,7 @@ def S4_pstorerdfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110111110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22871,15 +23200,15 @@ let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32) = $Rtt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22887,7 +23216,7 @@ def S4_pstorerdt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd(#$Ii) = $Rtt32", -tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22897,8 +23226,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22910,21 +23239,21 @@ def S4_pstorerdt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110100110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd(#$Ii) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22935,8 +23264,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22948,7 +23277,7 @@ def S4_pstorerdtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010110; let isPredicated = 1; @@ -22956,9 +23285,9 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22969,22 +23298,22 @@ def S4_pstorerdtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110110110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32) = $Rtt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22992,7 +23321,7 @@ def S4_pstorerff_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32.h", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23003,8 +23332,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23016,22 +23345,22 @@ def S4_pstorerff_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101011; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerffnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23043,8 +23372,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23056,7 +23385,7 @@ def S4_pstorerffnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110011; let isPredicated = 1; @@ -23065,9 +23394,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23078,7 +23407,7 @@ def S4_pstorerffnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23086,15 +23415,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerffnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32.h", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23102,7 +23431,7 @@ def S4_pstorerft_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32.h", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23112,8 +23441,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23125,21 +23454,21 @@ def S4_pstorerft_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100011; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerftnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23150,8 +23479,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23163,7 +23492,7 @@ def S4_pstorerftnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010011; let isPredicated = 1; @@ -23171,9 +23500,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23184,22 +23513,22 @@ def S4_pstorerftnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110011; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerftnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32.h", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23207,7 +23536,7 @@ def S4_pstorerhf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23218,8 +23547,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23232,23 +23561,23 @@ def S4_pstorerhf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101010; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23260,8 +23589,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23274,7 +23603,7 @@ def S4_pstorerhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110010; let isPredicated = 1; @@ -23283,9 +23612,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23297,7 +23626,7 @@ def S4_pstorerhfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23305,16 +23634,16 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23322,7 +23651,7 @@ def S4_pstorerhnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -23336,8 +23665,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23350,7 +23679,7 @@ def S4_pstorerhnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -23361,16 +23690,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -23385,8 +23714,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23399,7 +23728,7 @@ def S4_pstorerhnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000110101; @@ -23412,9 +23741,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23426,7 +23755,7 @@ def S4_pstorerhnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -23438,16 +23767,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23456,7 +23785,7 @@ def S4_pstorerhnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -23469,8 +23798,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23483,7 +23812,7 @@ def S4_pstorerhnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -23493,16 +23822,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -23516,8 +23845,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23530,7 +23859,7 @@ def S4_pstorerhnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000010101; @@ -23542,9 +23871,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23556,7 +23885,7 @@ def S4_pstorerhnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -23567,16 +23896,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23585,7 +23914,7 @@ def S4_pstorerht_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23595,8 +23924,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23609,22 +23938,22 @@ def S4_pstorerht_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100010; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23635,8 +23964,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23649,7 +23978,7 @@ def S4_pstorerhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010010; let isPredicated = 1; @@ -23657,9 +23986,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23671,23 +24000,23 @@ def S4_pstorerhtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110010; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23695,7 +24024,7 @@ def S4_pstorerif_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23706,8 +24035,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23720,23 +24049,23 @@ def S4_pstorerif_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101100; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstorerifnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23748,8 +24077,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23762,7 +24091,7 @@ def S4_pstorerifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110100; let isPredicated = 1; @@ -23771,9 +24100,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23785,7 +24114,7 @@ def S4_pstorerifnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23793,16 +24122,16 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstorerifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23810,7 +24139,7 @@ def S4_pstorerinewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23824,8 +24153,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23838,7 +24167,7 @@ def S4_pstorerinewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -23849,16 +24178,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -23873,8 +24202,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23887,7 +24216,7 @@ def S4_pstorerinewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000110101; @@ -23900,9 +24229,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23914,7 +24243,7 @@ def S4_pstorerinewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -23926,16 +24255,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23944,7 +24273,7 @@ def S4_pstorerinewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23957,8 +24286,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23971,7 +24300,7 @@ def S4_pstorerinewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -23981,16 +24310,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -24004,8 +24333,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -24018,7 +24347,7 @@ def S4_pstorerinewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000010101; @@ -24030,9 +24359,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -24044,7 +24373,7 @@ def S4_pstorerinewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -24055,16 +24384,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -24073,7 +24402,7 @@ def S4_pstorerit_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -24083,8 +24412,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24097,22 +24426,22 @@ def S4_pstorerit_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100100; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstoreritnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -24123,8 +24452,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24137,7 +24466,7 @@ def S4_pstoreritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010100; let isPredicated = 1; @@ -24145,9 +24474,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24159,23 +24488,23 @@ def S4_pstoreritnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110100; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstoreritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24183,7 +24512,7 @@ def S4_stored_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd_locked($Rs32,$Pd4) = $Rtt32", -tc_5abb5e3f, TypeST>, Enc_d7dc10 { +tc_6f42bc60, TypeST>, Enc_d7dc10 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000111; @@ -24196,14 +24525,14 @@ def S4_storeirb_io : HInst< (outs), (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "memb($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_8203bb, PredNewRel { +tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel { let Inst{31-21} = 0b00111100000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24215,7 +24544,7 @@ def S4_storeirb_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memb($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24223,16 +24552,16 @@ def S4_storeirbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memb($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { +tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000100; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24243,7 +24572,7 @@ def S4_storeirbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memb($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24251,7 +24580,7 @@ def S4_storeirbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { +tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24259,9 +24588,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24272,7 +24601,7 @@ def S4_storeirbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memb($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24280,15 +24609,15 @@ def S4_storeirbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memb($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { +tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24299,7 +24628,7 @@ def S4_storeirbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memb($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24307,16 +24636,16 @@ def S4_storeirbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { +tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24327,7 +24656,7 @@ def S4_storeirbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memb($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24335,14 +24664,14 @@ def S4_storeirh_io : HInst< (outs), (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "memh($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_a803e0, PredNewRel { +tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel { let Inst{31-21} = 0b00111100001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24354,7 +24683,7 @@ def S4_storeirh_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memh($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24362,16 +24691,16 @@ def S4_storeirhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memh($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { +tc_d03278fd, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24382,7 +24711,7 @@ def S4_storeirhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memh($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24390,7 +24719,7 @@ def S4_storeirhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { +tc_65cbd974, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24398,9 +24727,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24411,7 +24740,7 @@ def S4_storeirhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memh($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24419,15 +24748,15 @@ def S4_storeirht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memh($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { +tc_d03278fd, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000001; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24438,7 +24767,7 @@ def S4_storeirht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memh($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24446,16 +24775,16 @@ def S4_storeirhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { +tc_65cbd974, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001001; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24466,7 +24795,7 @@ def S4_storeirhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memh($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24474,14 +24803,14 @@ def S4_storeiri_io : HInst< (outs), (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "memw($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_f37377, PredNewRel { +tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel { let Inst{31-21} = 0b00111100010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24493,7 +24822,7 @@ def S4_storeiri_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memw($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24501,16 +24830,16 @@ def S4_storeirif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memw($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { +tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24521,7 +24850,7 @@ def S4_storeirif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memw($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24529,7 +24858,7 @@ def S4_storeirifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { +tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24537,9 +24866,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24550,7 +24879,7 @@ def S4_storeirifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memw($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24558,15 +24887,15 @@ def S4_storeirit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memw($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { +tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24577,7 +24906,7 @@ def S4_storeirit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memw($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24585,16 +24914,16 @@ def S4_storeiritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { +tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24605,7 +24934,7 @@ def S4_storeiritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memw($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24613,7 +24942,7 @@ def S4_storerb_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memb($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011000; @@ -24634,15 +24963,15 @@ def S4_storerb_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011000; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -24650,16 +24979,16 @@ def S4_storerb_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memb($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101000; let addrMode = BaseLongOffset; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_ur"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storerb_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24672,7 +25001,7 @@ def S4_storerbnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memb($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b000; let Inst{31-21} = 0b10101011101; @@ -24696,7 +25025,7 @@ def S4_storerbnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0000; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -24705,9 +25034,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -24715,7 +25044,7 @@ def S4_storerbnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memb($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -24726,8 +25055,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S4_storerb_ur"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24740,7 +25069,7 @@ def S4_storerd_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Re32=#$II) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_c7a204 { +tc_bb07f2c5, TypeST>, Enc_c7a204 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011110; @@ -24760,31 +25089,31 @@ def S4_storerd_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_5aee39f7, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011110; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; let isPredicable = 1; } def S4_storerd_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Ru32<<#$Ii+#$II) = $Rtt32", -tc_14b272fa, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101110; let addrMode = BaseLongOffset; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_ur"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_ur"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24796,7 +25125,7 @@ def S4_storerf_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_8bcba4 { +tc_bb07f2c5, TypeST>, Enc_8bcba4 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011011; @@ -24816,31 +25145,31 @@ def S4_storerf_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011011; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; let isPredicable = 1; } def S4_storerf_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32.h", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101011; let addrMode = BaseLongOffset; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S4_storerf_rr"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24852,7 +25181,7 @@ def S4_storerh_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011010; @@ -24873,15 +25202,15 @@ def S4_storerh_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011010; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -24889,16 +25218,16 @@ def S4_storerh_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101010; let addrMode = BaseLongOffset; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_ur"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24911,7 +25240,7 @@ def S4_storerhnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memh($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b001; let Inst{31-21} = 0b10101011101; @@ -24935,7 +25264,7 @@ def S4_storerhnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0001; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -24944,9 +25273,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -24954,7 +25283,7 @@ def S4_storerhnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memh($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -24965,8 +25294,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_ur"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24979,7 +25308,7 @@ def S4_storeri_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memw($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011100; @@ -25000,15 +25329,15 @@ def S4_storeri_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011100; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -25016,16 +25345,16 @@ def S4_storeri_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memw($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101100; let addrMode = BaseLongOffset; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_ur"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -25038,7 +25367,7 @@ def S4_storerinew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memw($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b010; let Inst{31-21} = 0b10101011101; @@ -25062,7 +25391,7 @@ def S4_storerinew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0010; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -25071,9 +25400,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -25081,7 +25410,7 @@ def S4_storerinew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memw($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -25092,8 +25421,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_ur"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -25106,7 +25435,7 @@ def S4_subaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", -tc_f675fee8, TypeALU64>, Enc_8b8d61 { +tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> { let Inst{31-23} = 0b110110111; let hasNewValue = 1; let opNewValue = 0; @@ -25121,7 +25450,7 @@ def S4_subi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b110; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -25139,7 +25468,7 @@ def S4_subi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b110; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -25157,7 +25486,7 @@ def S4_vrcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", -tc_13bfbcf9, TypeS_3op>, Enc_645d54 { +tc_f0cdeccf, TypeS_3op>, Enc_645d54 { let Inst{7-6} = 0b11; let Inst{31-21} = 0b11000011110; let prefersSlot3 = 1; @@ -25166,7 +25495,7 @@ def S4_vrcrotate_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", -tc_9debc299, TypeS_3op>, Enc_b72622 { +tc_a38c45dc, TypeS_3op>, Enc_b72622 { let Inst{7-6} = 0b00; let Inst{31-21} = 0b11001011101; let prefersSlot3 = 1; @@ -25176,7 +25505,7 @@ def S4_vxaddsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25187,7 +25516,7 @@ def S4_vxaddsubhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_0dfac0a7, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -25198,7 +25527,7 @@ def S4_vxaddsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25209,7 +25538,7 @@ def S4_vxsubaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25220,7 +25549,7 @@ def S4_vxsubaddhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_0dfac0a7, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -25231,7 +25560,7 @@ def S4_vxsubaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25242,7 +25571,7 @@ def S5_asrhub_rnd_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):raw", -tc_002cb246, TypeS_2op>, Enc_11a146 { +tc_0dfac0a7, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25255,7 +25584,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25264,7 +25593,7 @@ def S5_asrhub_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):sat", -tc_002cb246, TypeS_2op>, Enc_11a146 { +tc_0dfac0a7, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b101; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25277,7 +25606,7 @@ def S5_popcountp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = popcount($Rss32)", -tc_703e822c, TypeS_2op>, Enc_90cd8b { +tc_d3632d88, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -25288,7 +25617,7 @@ def S5_vasrhrnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):raw", -tc_002cb246, TypeS_2op>, Enc_12b6e9 { +tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000001; @@ -25298,14 +25627,14 @@ def S5_vasrhrnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):rnd", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let isPseudo = 1; } def S6_allocframe_to_raw : HInst< (outs), (ins u11_3Imm:$Ii), "allocframe(#$Ii)", -tc_b44ecf75, TypeMAPPING>, Requires<[HasV65]> { +tc_934753bb, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -25313,7 +25642,7 @@ def S6_rol_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = rol($Rss32,#$Ii)", -tc_1fc97744, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { +tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000000000; } @@ -25321,7 +25650,7 @@ def S6_rol_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25331,7 +25660,7 @@ def S6_rol_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25341,7 +25670,7 @@ def S6_rol_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25351,7 +25680,7 @@ def S6_rol_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25361,7 +25690,7 @@ def S6_rol_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -25371,7 +25700,7 @@ def S6_rol_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = rol($Rs32,#$Ii)", -tc_1fc97744, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { +tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -25382,7 +25711,7 @@ def S6_rol_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25395,7 +25724,7 @@ def S6_rol_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25408,7 +25737,7 @@ def S6_rol_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25421,7 +25750,7 @@ def S6_rol_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25434,7 +25763,7 @@ def S6_rol_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -25447,7 +25776,7 @@ def S6_vsplatrbp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplatb($Rs32)", -tc_a1c00888, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { +tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100010; } @@ -25455,7 +25784,7 @@ def S6_vtrunehb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunehb($Rss32,$Rtt32)", -tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { +tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -25464,7 +25793,7 @@ def S6_vtrunohb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunohb($Rss32,$Rtt32)", -tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { +tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -25473,7 +25802,7 @@ def SA1_addi : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, s32_0Imm:$Ii), "$Rx16 = add($Rx16in,#$Ii)", -tc_0a705168, TypeSUBINSN>, Enc_93af4c { +tc_5b347363, TypeSUBINSN>, Enc_93af4c { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -25490,7 +25819,7 @@ def SA1_addrx : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), "$Rx16 = add($Rx16in,$Rs16)", -tc_0a705168, TypeSUBINSN>, Enc_0527db { +tc_5b347363, TypeSUBINSN>, Enc_0527db { let Inst{12-8} = 0b11000; let hasNewValue = 1; let opNewValue = 0; @@ -25502,7 +25831,7 @@ def SA1_addsp : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_2Imm:$Ii), "$Rd16 = add(r29,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_2df31d { +tc_3d14a17b, TypeSUBINSN>, Enc_2df31d { let Inst{12-10} = 0b011; let hasNewValue = 1; let opNewValue = 0; @@ -25514,7 +25843,7 @@ def SA1_and1 : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#1)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10010; let hasNewValue = 1; let opNewValue = 0; @@ -25525,7 +25854,7 @@ def SA1_clrf : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0) $Rd16 = #0", -tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { +tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25539,7 +25868,7 @@ def SA1_clrfnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0.new) $Rd16 = #0", -tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { +tc_63567288, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25554,7 +25883,7 @@ def SA1_clrt : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0) $Rd16 = #0", -tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { +tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100110; let isPredicated = 1; let hasNewValue = 1; @@ -25567,7 +25896,7 @@ def SA1_clrtnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0.new) $Rd16 = #0", -tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { +tc_63567288, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100100; let isPredicated = 1; let hasNewValue = 1; @@ -25581,7 +25910,7 @@ def SA1_cmpeqi : HInst< (outs), (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), "p0 = cmp.eq($Rs16,#$Ii)", -tc_5b7c0967, TypeSUBINSN>, Enc_63eaeb { +tc_59a7822c, TypeSUBINSN>, Enc_63eaeb { let Inst{3-2} = 0b00; let Inst{12-8} = 0b11001; let AsmVariantName = "NonParsable"; @@ -25592,7 +25921,7 @@ def SA1_combine0i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#0,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b00; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25604,7 +25933,7 @@ def SA1_combine1i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#1,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b01; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25616,7 +25945,7 @@ def SA1_combine2i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#2,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b10; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25628,7 +25957,7 @@ def SA1_combine3i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#3,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b11; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25640,7 +25969,7 @@ def SA1_combinerz : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine($Rs16,#0)", -tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { +tc_3d14a17b, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b1; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25652,7 +25981,7 @@ def SA1_combinezr : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine(#0,$Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { +tc_3d14a17b, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b0; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25664,7 +25993,7 @@ def SA1_dec : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, n1Const:$n1), "$Rd16 = add($Rs16,#$n1)", -tc_0a705168, TypeSUBINSN>, Enc_ee5ed0 { +tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 { let Inst{12-8} = 0b10011; let hasNewValue = 1; let opNewValue = 0; @@ -25675,7 +26004,7 @@ def SA1_inc : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = add($Rs16,#1)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10001; let hasNewValue = 1; let opNewValue = 0; @@ -25686,7 +26015,7 @@ def SA1_seti : HInst< (outs GeneralSubRegs:$Rd16), (ins u32_0Imm:$Ii), "$Rd16 = #$Ii", -tc_9fc3dae0, TypeSUBINSN>, Enc_e39bb2 { +tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 { let Inst{12-10} = 0b010; let hasNewValue = 1; let opNewValue = 0; @@ -25702,7 +26031,7 @@ def SA1_setin1 : HInst< (outs GeneralSubRegs:$Rd16), (ins n1Const:$n1), "$Rd16 = #$n1", -tc_9fc3dae0, TypeSUBINSN>, Enc_7a0ea6 { +tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 { let Inst{12-4} = 0b110100000; let hasNewValue = 1; let opNewValue = 0; @@ -25713,7 +26042,7 @@ def SA1_sxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxtb($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10101; let hasNewValue = 1; let opNewValue = 0; @@ -25724,7 +26053,7 @@ def SA1_sxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxth($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10100; let hasNewValue = 1; let opNewValue = 0; @@ -25735,7 +26064,7 @@ def SA1_tfr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = $Rs16", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10000; let hasNewValue = 1; let opNewValue = 0; @@ -25746,7 +26075,7 @@ def SA1_zxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#255)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10111; let hasNewValue = 1; let opNewValue = 0; @@ -25757,7 +26086,7 @@ def SA1_zxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = zxth($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10110; let hasNewValue = 1; let opNewValue = 0; @@ -25768,7 +26097,7 @@ def SL1_loadri_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "$Rd16 = memw($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_53dca9 { +tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 { let Inst{12-12} = 0b0; let hasNewValue = 1; let opNewValue = 0; @@ -25782,7 +26111,7 @@ def SL1_loadrub_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "$Rd16 = memub($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_c175d0 { +tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 { let Inst{12-12} = 0b1; let hasNewValue = 1; let opNewValue = 0; @@ -25796,20 +26125,20 @@ def SL2_deallocframe : HInst< (outs), (ins), "deallocframe", -tc_39dfefe8, TypeSUBINSN>, Enc_e3b0c4 { +tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111100000000; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayLoad = 1; let Uses = [FRAMEKEY, R30]; -let Defs = [R30, R29, R31]; +let Defs = [R29, R30, R31]; let DecoderNamespace = "SUBINSN_L2"; } def SL2_jumpr31 : HInst< (outs), (ins), "jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000000; let isTerminator = 1; let isIndirectBranch = 1; @@ -25824,7 +26153,7 @@ def SL2_jumpr31_f : HInst< (outs), (ins), "if (!p0) jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25842,7 +26171,7 @@ def SL2_jumpr31_fnew : HInst< (outs), (ins), "if (!p0.new) jumpr:nt r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25861,7 +26190,7 @@ def SL2_jumpr31_t : HInst< (outs), (ins), "if (p0) jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000100; let isPredicated = 1; let isTerminator = 1; @@ -25878,7 +26207,7 @@ def SL2_jumpr31_tnew : HInst< (outs), (ins), "if (p0.new) jumpr:nt r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000110; let isPredicated = 1; let isTerminator = 1; @@ -25896,7 +26225,7 @@ def SL2_loadrb_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), "$Rd16 = memb($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2fbf3c { +tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c { let Inst{12-11} = 0b10; let hasNewValue = 1; let opNewValue = 0; @@ -25910,7 +26239,7 @@ def SL2_loadrd_sp : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u5_3Imm:$Ii), "$Rdd8 = memd(r29+#$Ii)", -tc_c4db48cb, TypeSUBINSN>, Enc_86a14b { +tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b { let Inst{12-8} = 0b11110; let hasNewValue = 1; let opNewValue = 0; @@ -25925,7 +26254,7 @@ def SL2_loadrh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memh($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { +tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -25939,7 +26268,7 @@ def SL2_loadri_sp : HInst< (outs GeneralSubRegs:$Rd16), (ins u5_2Imm:$Ii), "$Rd16 = memw(r29+#$Ii)", -tc_c4db48cb, TypeSUBINSN>, Enc_51635c { +tc_8a6d0d94, TypeSUBINSN>, Enc_51635c { let Inst{12-9} = 0b1110; let hasNewValue = 1; let opNewValue = 0; @@ -25954,7 +26283,7 @@ def SL2_loadruh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memuh($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { +tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b01; let hasNewValue = 1; let opNewValue = 0; @@ -25968,7 +26297,7 @@ def SL2_return : HInst< (outs), (ins), "dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000000; let isTerminator = 1; let isIndirectBranch = 1; @@ -25979,14 +26308,14 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let DecoderNamespace = "SUBINSN_L2"; } def SL2_return_f : HInst< (outs), (ins), "if (!p0) dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25999,7 +26328,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26007,7 +26336,7 @@ def SL2_return_fnew : HInst< (outs), (ins), "if (!p0.new) dealloc_return:nt", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -26021,7 +26350,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26029,7 +26358,7 @@ def SL2_return_t : HInst< (outs), (ins), "if (p0) dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000100; let isPredicated = 1; let isTerminator = 1; @@ -26041,7 +26370,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26049,7 +26378,7 @@ def SL2_return_tnew : HInst< (outs), (ins), "if (p0.new) dealloc_return:nt", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000110; let isPredicated = 1; let isTerminator = 1; @@ -26062,7 +26391,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26070,7 +26399,7 @@ def SS1_storeb_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), "memb($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_b38ffc { +tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc { let Inst{12-12} = 0b1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26082,7 +26411,7 @@ def SS1_storew_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_f55a0c { +tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c { let Inst{12-12} = 0b0; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26094,22 +26423,22 @@ def SS2_allocframe : HInst< (outs), (ins u5_3Imm:$Ii), "allocframe(#$Ii)", -tc_49a8207d, TypeSUBINSN>, Enc_6f70ca { +tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca { let Inst{3-0} = 0b0000; let Inst{12-9} = 0b1110; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayStore = 1; -let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31]; -let Defs = [R30, R29]; +let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31]; +let Defs = [R29, R30]; let DecoderNamespace = "SUBINSN_S2"; } def SS2_storebi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #0", -tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { +tc_44d5a428, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10010; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26121,7 +26450,7 @@ def SS2_storebi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #1", -tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { +tc_44d5a428, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10011; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26133,7 +26462,7 @@ def SS2_stored_sp : HInst< (outs), (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), "memd(r29+#$Ii) = $Rtt8", -tc_0371abea, TypeSUBINSN>, Enc_b8309d { +tc_0655b949, TypeSUBINSN>, Enc_b8309d { let Inst{12-9} = 0b0101; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; @@ -26146,7 +26475,7 @@ def SS2_storeh_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), "memh($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_625deb { +tc_ae5babd7, TypeSUBINSN>, Enc_625deb { let Inst{12-11} = 0b00; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; @@ -26158,7 +26487,7 @@ def SS2_storew_sp : HInst< (outs), (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw(r29+#$Ii) = $Rt16", -tc_0371abea, TypeSUBINSN>, Enc_87c142 { +tc_0655b949, TypeSUBINSN>, Enc_87c142 { let Inst{12-9} = 0b0100; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26171,7 +26500,7 @@ def SS2_storewi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #0", -tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { +tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10000; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26183,7 +26512,7 @@ def SS2_storewi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #1", -tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { +tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10001; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26198,6 +26527,7 @@ def V6_MAP_equb : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26207,6 +26537,7 @@ def V6_MAP_equb_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26218,6 +26549,7 @@ def V6_MAP_equb_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26228,6 +26560,7 @@ def V6_MAP_equb_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26240,6 +26573,7 @@ def V6_MAP_equh : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26249,6 +26583,7 @@ def V6_MAP_equh_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26260,6 +26595,7 @@ def V6_MAP_equh_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26270,6 +26606,7 @@ def V6_MAP_equh_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26282,6 +26619,7 @@ def V6_MAP_equw : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26291,6 +26629,7 @@ def V6_MAP_equw_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26302,6 +26641,7 @@ def V6_MAP_equw_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26312,6 +26652,7 @@ def V6_MAP_equw_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26327,6 +26668,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b10010010000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isSolo = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26338,6 +26680,7 @@ def V6_extractw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26349,6 +26692,7 @@ def V6_hi : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -26359,6 +26703,7 @@ def V6_ld0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26370,6 +26715,7 @@ def V6_ldcnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26381,6 +26727,7 @@ def V6_ldcnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26392,6 +26739,7 @@ def V6_ldcp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26403,6 +26751,7 @@ def V6_ldcpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26414,6 +26763,7 @@ def V6_ldnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26425,6 +26775,7 @@ def V6_ldnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26436,6 +26787,7 @@ def V6_ldnt0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26458,6 +26810,7 @@ def V6_ldp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26469,6 +26822,7 @@ def V6_ldpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26480,6 +26834,7 @@ def V6_ldtnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26491,6 +26846,7 @@ def V6_ldtnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26502,6 +26858,7 @@ def V6_ldtp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26513,6 +26870,7 @@ def V6_ldtpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26524,6 +26882,7 @@ def V6_ldu0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26535,6 +26894,7 @@ def V6_lo : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -26542,22 +26902,24 @@ def V6_lvsplatb : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.b = vsplat($Rt32)", -tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { +tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_lvsplath : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.h = vsplat($Rt32)", -tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { +tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_lvsplatw : HInst< @@ -26569,6 +26931,7 @@ let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_and : HInst< @@ -26582,6 +26945,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_and_n : HInst< @@ -26595,6 +26959,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_not : HInst< @@ -26607,6 +26972,7 @@ let Inst{13-10} = 0b0000; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_or : HInst< @@ -26620,6 +26986,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_or_n : HInst< @@ -26633,6 +27000,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_scalar2 : HInst< @@ -26644,6 +27012,7 @@ let Inst{13-2} = 0b000000010001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_scalar2v2 : HInst< @@ -26655,6 +27024,7 @@ let Inst{13-2} = 0b000000010011; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_xor : HInst< @@ -26668,6 +27038,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_shuffeqh : HInst< @@ -26681,6 +27052,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_shuffeqw : HInst< @@ -26694,6 +27066,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_st0 : HInst< @@ -26701,6 +27074,7 @@ def V6_st0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26710,6 +27084,7 @@ def V6_stn0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32) = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26720,6 +27095,7 @@ def V6_stnnt0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32):nt = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26730,6 +27106,7 @@ def V6_stnp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26739,6 +27116,7 @@ def V6_stnpnt0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26748,6 +27126,7 @@ def V6_stnq0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26757,6 +27136,7 @@ def V6_stnqnt0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26766,6 +27146,7 @@ def V6_stnt0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26775,6 +27156,7 @@ def V6_stp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26784,6 +27166,7 @@ def V6_stpnt0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26793,6 +27176,7 @@ def V6_stq0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26802,6 +27186,7 @@ def V6_stqnt0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26811,6 +27196,7 @@ def V6_stu0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26820,6 +27206,7 @@ def V6_stunp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26829,6 +27216,7 @@ def V6_stup0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26846,6 +27234,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26863,6 +27252,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -26881,6 +27271,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26899,6 +27290,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -26919,6 +27311,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26940,6 +27333,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26961,6 +27355,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26982,6 +27377,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27002,6 +27398,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27022,6 +27419,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27043,6 +27441,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27063,6 +27462,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27083,6 +27483,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27104,6 +27505,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -27124,6 +27526,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27144,6 +27547,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27163,6 +27567,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27184,6 +27589,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27206,6 +27612,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27228,6 +27635,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27250,6 +27658,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27271,6 +27680,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27292,6 +27702,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27314,6 +27725,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27335,6 +27747,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27356,6 +27769,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27378,6 +27792,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27399,6 +27814,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27420,6 +27836,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27440,6 +27857,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27461,6 +27879,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27483,6 +27902,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27503,6 +27923,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27523,6 +27944,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27543,6 +27965,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27564,6 +27987,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27585,6 +28009,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27606,6 +28031,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27626,6 +28052,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27646,6 +28073,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27667,6 +28095,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27687,6 +28116,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27707,6 +28137,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27727,6 +28158,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27747,6 +28179,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27768,6 +28201,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -27787,6 +28221,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27806,6 +28241,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27825,6 +28261,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27845,6 +28282,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27865,6 +28303,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27885,6 +28324,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27904,6 +28344,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27923,6 +28364,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27943,6 +28385,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27962,6 +28405,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27981,6 +28425,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27997,6 +28442,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let isPredicable = 1; @@ -28013,6 +28459,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; @@ -28029,6 +28476,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; @@ -28045,6 +28493,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; @@ -28060,6 +28509,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let isPredicable = 1; @@ -28075,6 +28525,7 @@ let Inst{12-5} = 0b00000111; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let isPredicable = 1; @@ -28091,6 +28542,7 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; @@ -28106,6 +28558,7 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; @@ -28121,6 +28574,7 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; @@ -28136,6 +28590,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28153,6 +28608,7 @@ let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28173,6 +28629,7 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28193,6 +28650,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28213,6 +28671,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28232,6 +28691,7 @@ let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28251,6 +28711,7 @@ let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28271,6 +28732,7 @@ let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28290,6 +28752,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28309,6 +28772,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28328,6 +28792,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28345,6 +28810,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28362,6 +28828,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; @@ -28377,6 +28844,7 @@ let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -28390,6 +28858,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28403,6 +28872,7 @@ let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28417,6 +28887,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28435,6 +28906,7 @@ let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28456,6 +28928,7 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28477,6 +28950,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28498,6 +28972,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28518,6 +28993,7 @@ let Inst{31-21} = 0b00101001011; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28538,6 +29014,7 @@ let Inst{31-21} = 0b00101011011; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28559,6 +29036,7 @@ let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28579,6 +29057,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28599,6 +29078,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28619,6 +29099,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28637,6 +29118,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28655,6 +29137,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28671,6 +29154,7 @@ let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28685,6 +29169,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28699,6 +29184,7 @@ let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28714,6 +29200,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28731,6 +29218,7 @@ let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28749,6 +29237,7 @@ let Inst{31-21} = 0b00101000111; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28766,6 +29255,7 @@ let Inst{31-21} = 0b00101001111; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28783,6 +29273,7 @@ let Inst{31-21} = 0b00101011111; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28799,6 +29290,7 @@ let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28813,6 +29305,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28827,6 +29320,7 @@ let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28842,6 +29336,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28858,7 +29353,9 @@ let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28874,6 +29371,7 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28890,6 +29388,7 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28906,6 +29405,7 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; @@ -28921,6 +29421,7 @@ let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -28934,6 +29435,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28947,6 +29449,7 @@ let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28961,6 +29464,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28975,6 +29479,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28989,6 +29494,7 @@ let Inst{12-0} = 0b0000000101000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29004,6 +29510,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsb_alt : HInst< @@ -29013,6 +29520,7 @@ def V6_vabsb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29027,6 +29535,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsb_sat_alt : HInst< @@ -29036,6 +29545,7 @@ def V6_vabsb_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29050,6 +29560,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffh_alt : HInst< @@ -29059,6 +29570,7 @@ def V6_vabsdiffh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29073,6 +29585,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffub_alt : HInst< @@ -29082,6 +29595,7 @@ def V6_vabsdiffub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29096,6 +29610,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffuh_alt : HInst< @@ -29105,6 +29620,7 @@ def V6_vabsdiffuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29119,6 +29635,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffw_alt : HInst< @@ -29128,6 +29645,7 @@ def V6_vabsdiffw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29142,6 +29660,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsh_alt : HInst< @@ -29151,6 +29670,7 @@ def V6_vabsh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29165,6 +29685,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsh_sat_alt : HInst< @@ -29174,6 +29695,7 @@ def V6_vabsh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29185,6 +29707,7 @@ def V6_vabsub_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29196,6 +29719,7 @@ def V6_vabsuh_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29207,6 +29731,7 @@ def V6_vabsuw_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29221,6 +29746,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsw_alt : HInst< @@ -29230,6 +29756,7 @@ def V6_vabsw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29244,6 +29771,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsw_sat_alt : HInst< @@ -29253,6 +29781,7 @@ def V6_vabsw_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29267,6 +29796,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddb_alt : HInst< @@ -29276,6 +29806,7 @@ def V6_vaddb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29290,6 +29821,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddb_dv_alt : HInst< @@ -29299,6 +29831,7 @@ def V6_vaddb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29315,6 +29848,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29326,6 +29860,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29343,6 +29878,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29354,6 +29890,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29369,6 +29906,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddbsat_alt : HInst< @@ -29378,6 +29916,7 @@ def V6_vaddbsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29392,6 +29931,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddbsat_dv_alt : HInst< @@ -29401,6 +29941,7 @@ def V6_vaddbsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29415,6 +29956,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -29422,7 +29964,7 @@ def V6_vaddcarryo : HInst< (outs HvxVR:$Vd32, HvxQR:$Qe4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry", -tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { +tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101101; @@ -29430,6 +29972,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddcarrysat : HInst< @@ -29442,6 +29985,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddclbh : HInst< @@ -29454,6 +29998,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddclbw : HInst< @@ -29466,6 +30011,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh : HInst< @@ -29478,6 +30024,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh_alt : HInst< @@ -29487,6 +30034,7 @@ def V6_vaddh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29501,6 +30049,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh_dv_alt : HInst< @@ -29510,6 +30059,7 @@ def V6_vaddh_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29526,6 +30076,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29537,6 +30088,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29554,6 +30106,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29565,6 +30118,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29580,6 +30134,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhsat_alt : HInst< @@ -29589,6 +30144,7 @@ def V6_vaddhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29603,6 +30159,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhsat_dv_alt : HInst< @@ -29612,6 +30169,7 @@ def V6_vaddhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29626,6 +30184,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhw_acc : HInst< @@ -29639,6 +30198,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29650,6 +30210,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29662,6 +30223,7 @@ def V6_vaddhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29676,6 +30238,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubh_acc : HInst< @@ -29689,6 +30252,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29700,6 +30264,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29712,6 +30277,7 @@ def V6_vaddubh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29726,6 +30292,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubsat_alt : HInst< @@ -29735,6 +30302,7 @@ def V6_vaddubsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29749,6 +30317,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubsat_dv_alt : HInst< @@ -29758,6 +30327,7 @@ def V6_vaddubsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29772,6 +30342,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat : HInst< @@ -29784,6 +30355,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat_alt : HInst< @@ -29793,6 +30365,7 @@ def V6_vadduhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29807,6 +30380,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat_dv_alt : HInst< @@ -29816,6 +30390,7 @@ def V6_vadduhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29830,6 +30405,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhw_acc : HInst< @@ -29843,6 +30419,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29854,6 +30431,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29866,6 +30444,7 @@ def V6_vadduhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29880,6 +30459,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduwsat_alt : HInst< @@ -29889,6 +30469,7 @@ def V6_vadduwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29903,6 +30484,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduwsat_dv_alt : HInst< @@ -29912,6 +30494,7 @@ def V6_vadduwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29926,6 +30509,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddw_alt : HInst< @@ -29935,6 +30519,7 @@ def V6_vaddw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29949,6 +30534,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddw_dv_alt : HInst< @@ -29958,6 +30544,7 @@ def V6_vaddw_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29974,6 +30561,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29985,6 +30573,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30002,6 +30591,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30013,6 +30603,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30028,6 +30619,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddwsat_alt : HInst< @@ -30037,6 +30629,7 @@ def V6_vaddwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30051,6 +30644,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddwsat_dv_alt : HInst< @@ -30060,6 +30654,7 @@ def V6_vaddwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30074,6 +30669,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_valignbi : HInst< @@ -30085,6 +30681,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vand : HInst< @@ -30097,31 +30694,34 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandnqrt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand(!$Qu4,$Rt32)", -tc_ac4046bc, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> { +tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-10} = 0b0001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandnqrt_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand(!$Qu4,$Rt32)", -tc_2e8f5f6e, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> { +tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30133,6 +30733,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30145,6 +30746,7 @@ def V6_vandnqrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30159,6 +30761,7 @@ let Inst{13-10} = 0b0000; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandqrt_acc : HInst< @@ -30172,6 +30775,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30183,6 +30787,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30195,6 +30800,7 @@ def V6_vandqrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30210,6 +30816,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvqv : HInst< @@ -30223,6 +30830,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvrt : HInst< @@ -30235,6 +30843,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvrt_acc : HInst< @@ -30246,6 +30855,7 @@ let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30255,6 +30865,7 @@ def V6_vandvrt_acc_alt : HInst< "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30267,6 +30878,7 @@ def V6_vandvrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30281,6 +30893,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslh_acc : HInst< @@ -30294,6 +30907,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30305,6 +30919,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30317,6 +30932,7 @@ def V6_vaslh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30331,6 +30947,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslhv_alt : HInst< @@ -30340,6 +30957,7 @@ def V6_vaslhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30354,6 +30972,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslw_acc : HInst< @@ -30367,6 +30986,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30378,6 +30998,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30390,6 +31011,7 @@ def V6_vaslw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30404,6 +31026,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslwv_alt : HInst< @@ -30413,6 +31036,7 @@ def V6_vaslwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30427,6 +31051,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011010101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -30437,6 +31062,7 @@ def V6_vasr_into_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30452,6 +31078,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrh_acc : HInst< @@ -30465,6 +31092,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30476,6 +31104,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30488,6 +31117,7 @@ def V6_vasrh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30502,18 +31132,9 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhbrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhbsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30524,6 +31145,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrhubrndsat : HInst< @@ -30536,18 +31158,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhubsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30558,18 +31171,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), @@ -30580,6 +31184,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrhv_alt : HInst< @@ -30589,6 +31194,7 @@ def V6_vasrhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30603,6 +31209,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruhubsat : HInst< @@ -30615,6 +31222,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruwuhrndsat : HInst< @@ -30627,6 +31235,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruwuhsat : HInst< @@ -30639,6 +31248,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrw : HInst< @@ -30651,6 +31261,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrw_acc : HInst< @@ -30664,6 +31275,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30675,6 +31287,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30687,6 +31300,7 @@ def V6_vasrw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30701,18 +31315,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwh_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30723,18 +31328,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30745,18 +31341,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwuhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30767,6 +31354,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrwuhsat : HInst< @@ -30779,18 +31367,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwuhsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), @@ -30801,6 +31380,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrwv_alt : HInst< @@ -30810,6 +31390,7 @@ def V6_vasrwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30824,6 +31405,7 @@ let Inst{13-13} = 0b1; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vassignp : HInst< @@ -30833,6 +31415,7 @@ def V6_vassignp : HInst< CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -30846,6 +31429,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgb_alt : HInst< @@ -30855,6 +31439,7 @@ def V6_vavgb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30869,6 +31454,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgbrnd_alt : HInst< @@ -30878,6 +31464,7 @@ def V6_vavgbrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30892,6 +31479,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgh_alt : HInst< @@ -30901,6 +31489,7 @@ def V6_vavgh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30915,6 +31504,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavghrnd_alt : HInst< @@ -30924,6 +31514,7 @@ def V6_vavghrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30938,6 +31529,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgub_alt : HInst< @@ -30947,6 +31539,7 @@ def V6_vavgub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30961,6 +31554,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgubrnd_alt : HInst< @@ -30970,6 +31564,7 @@ def V6_vavgubrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30984,6 +31579,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguh_alt : HInst< @@ -30993,6 +31589,7 @@ def V6_vavguh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31007,6 +31604,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguhrnd_alt : HInst< @@ -31016,6 +31614,7 @@ def V6_vavguhrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31030,6 +31629,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguw_alt : HInst< @@ -31039,6 +31639,7 @@ def V6_vavguw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31053,6 +31654,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguwrnd_alt : HInst< @@ -31062,6 +31664,7 @@ def V6_vavguwrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31076,6 +31679,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgw_alt : HInst< @@ -31085,6 +31689,7 @@ def V6_vavgw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31099,6 +31704,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgwrnd_alt : HInst< @@ -31108,6 +31714,7 @@ def V6_vavgwrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31123,6 +31730,7 @@ let Inst{31-21} = 0b00011010011; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0h : HInst< @@ -31135,6 +31743,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0h_alt : HInst< @@ -31144,6 +31753,7 @@ def V6_vcl0h_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31158,6 +31768,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0w_alt : HInst< @@ -31167,6 +31778,7 @@ def V6_vcl0w_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31182,6 +31794,7 @@ let Inst{31-16} = 0b0001101000000000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcombine : HInst< @@ -31194,6 +31807,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isRegSequence = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -31204,6 +31818,7 @@ def V6_vd0 : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31215,6 +31830,7 @@ def V6_vdd0 : HInst< tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31231,6 +31847,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } @@ -31244,6 +31861,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w : HInst< @@ -31256,6 +31874,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w_alt : HInst< @@ -31265,6 +31884,7 @@ def V6_vdealb4w_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31276,6 +31896,7 @@ def V6_vdealb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31290,6 +31911,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealh_alt : HInst< @@ -31299,6 +31921,7 @@ def V6_vdealh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31313,6 +31936,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdelta : HInst< @@ -31325,6 +31949,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus : HInst< @@ -31337,6 +31962,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus_acc : HInst< @@ -31350,6 +31976,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31361,6 +31988,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31373,6 +32001,7 @@ def V6_vdmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31387,6 +32016,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus_dv_acc : HInst< @@ -31400,6 +32030,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31411,6 +32042,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31423,6 +32055,7 @@ def V6_vdmpybus_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31437,6 +32070,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhb_acc : HInst< @@ -31450,6 +32084,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31461,6 +32096,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31473,6 +32109,7 @@ def V6_vdmpyhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31487,6 +32124,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhb_dv_acc : HInst< @@ -31500,6 +32138,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31511,6 +32150,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31523,6 +32163,7 @@ def V6_vdmpyhb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31537,6 +32178,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhisat_acc : HInst< @@ -31550,6 +32192,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31561,6 +32204,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31573,6 +32217,7 @@ def V6_vdmpyhisat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31587,6 +32232,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsat_acc : HInst< @@ -31600,6 +32246,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31611,6 +32258,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31623,6 +32271,7 @@ def V6_vdmpyhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31637,6 +32286,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsuisat_acc : HInst< @@ -31650,6 +32300,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31661,6 +32312,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31673,6 +32325,7 @@ def V6_vdmpyhsuisat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31687,6 +32340,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsusat_acc : HInst< @@ -31700,6 +32354,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31711,6 +32366,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31723,6 +32379,7 @@ def V6_vdmpyhsusat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31737,6 +32394,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhvsat_acc : HInst< @@ -31750,6 +32408,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31761,6 +32420,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31773,6 +32433,7 @@ def V6_vdmpyhvsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31787,6 +32448,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdsaduh_acc : HInst< @@ -31800,6 +32462,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31811,6 +32474,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31823,6 +32487,7 @@ def V6_vdsaduh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31837,6 +32502,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqb_and : HInst< @@ -31847,6 +32513,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31859,6 +32526,7 @@ let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31870,6 +32538,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31883,6 +32552,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqh_and : HInst< @@ -31893,6 +32563,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31905,6 +32576,7 @@ let Inst{7-2} = 0b010001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31916,6 +32588,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31929,6 +32602,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqw_and : HInst< @@ -31939,6 +32613,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31951,6 +32626,7 @@ let Inst{7-2} = 0b010010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31962,6 +32638,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31976,6 +32653,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -31992,6 +32670,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32001,13 +32680,14 @@ def V6_vgathermhw : HInst< (outs), (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_05058f6f, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> { +tc_05058f6f, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32017,13 +32697,14 @@ def V6_vgathermhwq : HInst< (outs), (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_fd7610da, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> { +tc_fd7610da, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> { let Inst{12-7} = 0b001100; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32040,6 +32721,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = WordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32056,6 +32738,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = WordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32071,6 +32754,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtb_and : HInst< @@ -32081,6 +32765,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32093,6 +32778,7 @@ let Inst{7-2} = 0b010100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32104,6 +32790,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32117,6 +32804,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgth_and : HInst< @@ -32127,6 +32815,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32139,6 +32828,7 @@ let Inst{7-2} = 0b010101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32150,6 +32840,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32163,6 +32854,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtub_and : HInst< @@ -32173,6 +32865,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32185,6 +32878,7 @@ let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32196,6 +32890,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32209,6 +32904,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtuh_and : HInst< @@ -32219,6 +32915,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32231,6 +32928,7 @@ let Inst{7-2} = 0b011001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32242,6 +32940,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32255,6 +32954,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtuw_and : HInst< @@ -32265,6 +32965,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32277,6 +32978,7 @@ let Inst{7-2} = 0b011010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32288,6 +32990,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32301,6 +33004,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtw_and : HInst< @@ -32311,6 +33015,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32323,6 +33028,7 @@ let Inst{7-2} = 0b010110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32334,6 +33040,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32344,6 +33051,7 @@ def V6_vhist : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vhistq : HInst< @@ -32354,6 +33062,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vinsertwr : HInst< @@ -32365,6 +33074,7 @@ let Inst{13-5} = 0b100000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32378,6 +33088,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlalignbi : HInst< @@ -32389,6 +33100,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrb : HInst< @@ -32401,6 +33113,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrh : HInst< @@ -32413,6 +33126,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrh_alt : HInst< @@ -32422,6 +33136,7 @@ def V6_vlsrh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32436,6 +33151,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrhv_alt : HInst< @@ -32445,6 +33161,7 @@ def V6_vlsrhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32459,6 +33176,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrw_alt : HInst< @@ -32468,6 +33186,7 @@ def V6_vlsrw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32482,6 +33201,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrwv_alt : HInst< @@ -32491,6 +33211,7 @@ def V6_vlsrwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32505,6 +33226,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb : HInst< @@ -32517,6 +33239,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb_nm : HInst< @@ -32529,6 +33252,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb_oracc : HInst< @@ -32542,6 +33266,7 @@ let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32555,6 +33280,7 @@ let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32567,6 +33293,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh : HInst< @@ -32579,6 +33306,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh_nm : HInst< @@ -32591,6 +33319,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh_oracc : HInst< @@ -32604,6 +33333,7 @@ let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32617,6 +33347,7 @@ let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32629,6 +33360,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxb : HInst< @@ -32641,6 +33373,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxb_alt : HInst< @@ -32650,6 +33383,7 @@ def V6_vmaxb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32664,6 +33398,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxh_alt : HInst< @@ -32673,6 +33408,7 @@ def V6_vmaxh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32687,6 +33423,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxub_alt : HInst< @@ -32696,6 +33433,7 @@ def V6_vmaxub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32710,6 +33448,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxuh_alt : HInst< @@ -32719,6 +33458,7 @@ def V6_vmaxuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32733,6 +33473,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxw_alt : HInst< @@ -32742,6 +33483,7 @@ def V6_vmaxw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32756,6 +33498,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminb_alt : HInst< @@ -32765,6 +33508,7 @@ def V6_vminb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32779,6 +33523,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminh_alt : HInst< @@ -32788,6 +33533,7 @@ def V6_vminh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32802,6 +33548,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminub_alt : HInst< @@ -32811,6 +33558,7 @@ def V6_vminub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32825,6 +33573,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminuh_alt : HInst< @@ -32834,6 +33583,7 @@ def V6_vminuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32848,6 +33598,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminw_alt : HInst< @@ -32857,6 +33608,7 @@ def V6_vminw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32871,6 +33623,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabus_acc : HInst< @@ -32884,6 +33637,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32895,6 +33649,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32907,6 +33662,7 @@ def V6_vmpabus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32921,6 +33677,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabusv_alt : HInst< @@ -32930,6 +33687,7 @@ def V6_vmpabusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32944,6 +33702,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabuu_acc : HInst< @@ -32957,6 +33716,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32968,6 +33728,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32980,6 +33741,7 @@ def V6_vmpabuu_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32994,6 +33756,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabuuv_alt : HInst< @@ -33003,6 +33766,7 @@ def V6_vmpabuuv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33017,6 +33781,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpahb_acc : HInst< @@ -33030,6 +33795,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33041,6 +33807,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33053,6 +33820,7 @@ def V6_vmpahb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33067,6 +33835,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33080,6 +33849,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpauhb_acc : HInst< @@ -33093,6 +33863,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33104,6 +33875,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33116,6 +33888,7 @@ def V6_vmpauhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33130,6 +33903,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33143,6 +33917,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33156,6 +33931,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybus_acc : HInst< @@ -33169,6 +33945,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33180,6 +33957,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33192,6 +33970,7 @@ def V6_vmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33206,6 +33985,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybusv_acc : HInst< @@ -33219,6 +33999,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33230,6 +34011,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33242,6 +34024,7 @@ def V6_vmpybusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33256,6 +34039,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybv_acc : HInst< @@ -33269,6 +34053,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33280,6 +34065,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33292,6 +34078,7 @@ def V6_vmpybv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33306,6 +34093,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyewuh_64 : HInst< @@ -33318,6 +34106,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyewuh_alt : HInst< @@ -33327,6 +34116,7 @@ def V6_vmpyewuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33341,6 +34131,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyh_acc : HInst< @@ -33354,6 +34145,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33365,6 +34157,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33377,6 +34170,7 @@ def V6_vmpyh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33392,6 +34186,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33403,6 +34198,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33418,6 +34214,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhsrs_alt : HInst< @@ -33427,6 +34224,7 @@ def V6_vmpyhsrs_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33441,6 +34239,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhss_alt : HInst< @@ -33450,6 +34249,7 @@ def V6_vmpyhss_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33464,6 +34264,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhus_acc : HInst< @@ -33477,6 +34278,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33488,6 +34290,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33500,6 +34303,7 @@ def V6_vmpyhus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33514,6 +34318,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhv_acc : HInst< @@ -33527,6 +34332,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33538,6 +34344,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33550,6 +34357,7 @@ def V6_vmpyhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33564,6 +34372,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhvsrs_alt : HInst< @@ -33573,6 +34382,7 @@ def V6_vmpyhvsrs_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33587,6 +34397,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiewh_acc : HInst< @@ -33600,6 +34411,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33611,6 +34423,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33626,6 +34439,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiewuh_acc : HInst< @@ -33639,6 +34453,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33650,6 +34465,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33662,6 +34478,7 @@ def V6_vmpyiewuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33676,6 +34493,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyih_acc : HInst< @@ -33689,6 +34507,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33700,6 +34519,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33712,6 +34532,7 @@ def V6_vmpyih_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33726,6 +34547,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyihb_acc : HInst< @@ -33739,6 +34561,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33750,6 +34573,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33762,6 +34586,7 @@ def V6_vmpyihb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33776,6 +34601,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiowh_alt : HInst< @@ -33785,6 +34611,7 @@ def V6_vmpyiowh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33799,6 +34626,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwb_acc : HInst< @@ -33812,6 +34640,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33823,6 +34652,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33835,6 +34665,7 @@ def V6_vmpyiwb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33849,6 +34680,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwh_acc : HInst< @@ -33862,6 +34694,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33873,6 +34706,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33885,6 +34719,7 @@ def V6_vmpyiwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33899,6 +34734,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwub_acc : HInst< @@ -33912,6 +34748,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33923,6 +34760,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33935,6 +34773,7 @@ def V6_vmpyiwub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33949,6 +34788,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyowh_64_acc : HInst< @@ -33962,6 +34802,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33972,6 +34813,7 @@ def V6_vmpyowh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33986,6 +34828,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyowh_rnd_alt : HInst< @@ -33995,6 +34838,7 @@ def V6_vmpyowh_rnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34010,6 +34854,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34021,6 +34866,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; @@ -34036,6 +34882,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34047,6 +34894,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; @@ -34061,6 +34909,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyub_acc : HInst< @@ -34074,6 +34923,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34085,6 +34935,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34097,6 +34948,7 @@ def V6_vmpyub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34111,6 +34963,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyubv_acc : HInst< @@ -34124,6 +34977,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34135,6 +34989,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34147,6 +35002,7 @@ def V6_vmpyubv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34161,6 +35017,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuh_acc : HInst< @@ -34174,6 +35031,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34185,6 +35043,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34197,6 +35056,7 @@ def V6_vmpyuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34211,6 +35071,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuhe_acc : HInst< @@ -34224,6 +35085,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34237,6 +35099,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuhv_acc : HInst< @@ -34250,6 +35113,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34261,6 +35125,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34273,6 +35138,7 @@ def V6_vmpyuhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34287,6 +35153,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgb : HInst< @@ -34299,6 +35166,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgb_alt : HInst< @@ -34308,6 +35176,7 @@ def V6_vnavgb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34322,6 +35191,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgh_alt : HInst< @@ -34331,6 +35201,7 @@ def V6_vnavgh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34345,6 +35216,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgub_alt : HInst< @@ -34354,6 +35226,7 @@ def V6_vnavgub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34368,6 +35241,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgw_alt : HInst< @@ -34377,6 +35251,7 @@ def V6_vnavgw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34393,6 +35268,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vncmov : HInst< @@ -34407,6 +35283,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamth : HInst< @@ -34419,6 +35296,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamth_alt : HInst< @@ -34428,6 +35306,7 @@ def V6_vnormamth_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34442,6 +35321,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamtw_alt : HInst< @@ -34451,6 +35331,7 @@ def V6_vnormamtw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34465,6 +35346,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vor : HInst< @@ -34477,6 +35359,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeb : HInst< @@ -34489,6 +35372,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeb_alt : HInst< @@ -34498,6 +35382,7 @@ def V6_vpackeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34512,6 +35397,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeh_alt : HInst< @@ -34521,6 +35407,7 @@ def V6_vpackeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34535,6 +35422,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackhb_sat_alt : HInst< @@ -34544,6 +35432,7 @@ def V6_vpackhb_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34558,6 +35447,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackhub_sat_alt : HInst< @@ -34567,6 +35457,7 @@ def V6_vpackhub_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34581,6 +35472,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackob_alt : HInst< @@ -34590,6 +35482,7 @@ def V6_vpackob_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34604,6 +35497,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackoh_alt : HInst< @@ -34613,6 +35507,7 @@ def V6_vpackoh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34627,6 +35522,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackwh_sat_alt : HInst< @@ -34636,6 +35532,7 @@ def V6_vpackwh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34650,6 +35547,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackwuh_sat_alt : HInst< @@ -34659,6 +35557,7 @@ def V6_vpackwuh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34673,6 +35572,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpopcounth_alt : HInst< @@ -34682,6 +35582,7 @@ def V6_vpopcounth_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34696,6 +35597,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vprefixqh : HInst< @@ -34708,6 +35610,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vprefixqw : HInst< @@ -34720,6 +35623,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrdelta : HInst< @@ -34732,6 +35636,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybub_rtt : HInst< @@ -34744,6 +35649,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybub_rtt_acc : HInst< @@ -34757,6 +35663,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34768,6 +35675,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34780,6 +35688,7 @@ def V6_vrmpybub_rtt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34794,6 +35703,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybus_acc : HInst< @@ -34807,6 +35717,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34818,6 +35729,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34830,6 +35742,7 @@ def V6_vrmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34844,6 +35757,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybusi_acc : HInst< @@ -34857,6 +35771,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34868,6 +35783,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34880,6 +35796,7 @@ def V6_vrmpybusi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34894,6 +35811,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybusv_acc : HInst< @@ -34907,6 +35825,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34918,6 +35837,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34930,6 +35850,7 @@ def V6_vrmpybusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34944,6 +35865,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybv_acc : HInst< @@ -34957,6 +35879,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34968,6 +35891,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34980,6 +35904,7 @@ def V6_vrmpybv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34994,6 +35919,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyub_acc : HInst< @@ -35007,6 +35933,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -35018,6 +35945,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35030,6 +35958,7 @@ def V6_vrmpyub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35044,6 +35973,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyub_rtt_acc : HInst< @@ -35057,6 +35987,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35068,6 +35999,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35080,6 +36012,7 @@ def V6_vrmpyub_rtt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35094,6 +36027,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyubi_acc : HInst< @@ -35107,6 +36041,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35118,6 +36053,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35130,6 +36066,7 @@ def V6_vrmpyubi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35144,6 +36081,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyubv_acc : HInst< @@ -35157,6 +36095,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -35168,6 +36107,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35180,6 +36120,7 @@ def V6_vrmpyubv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35194,6 +36135,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzbb_rt_acc : HInst< @@ -35207,6 +36149,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35220,6 +36163,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35234,6 +36178,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35247,6 +36192,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzbub_rt_acc : HInst< @@ -35260,6 +36206,7 @@ let Inst{31-19} = 0b0001100111010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35273,6 +36220,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35287,6 +36235,7 @@ let Inst{31-19} = 0b0001100111011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35300,6 +36249,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzcb_rt_acc : HInst< @@ -35313,6 +36263,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35326,6 +36277,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35340,6 +36292,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35353,6 +36306,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzcbs_rt_acc : HInst< @@ -35366,6 +36320,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35379,6 +36334,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35393,6 +36349,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35406,6 +36363,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyznb_rt_acc : HInst< @@ -35419,6 +36377,7 @@ let Inst{31-19} = 0b0001100111010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35432,6 +36391,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35446,6 +36406,7 @@ let Inst{31-19} = 0b0001100111011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35459,6 +36420,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrotr : HInst< @@ -35471,6 +36433,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011010100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrotr_alt : HInst< @@ -35480,6 +36443,7 @@ def V6_vrotr_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35494,6 +36458,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundhb_alt : HInst< @@ -35503,6 +36468,7 @@ def V6_vroundhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35517,6 +36483,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundhub_alt : HInst< @@ -35526,6 +36493,7 @@ def V6_vroundhub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35540,6 +36508,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrounduhub_alt : HInst< @@ -35549,6 +36518,7 @@ def V6_vrounduhub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35563,6 +36533,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrounduwuh_alt : HInst< @@ -35572,6 +36543,7 @@ def V6_vrounduwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35586,6 +36558,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundwh_alt : HInst< @@ -35595,6 +36568,7 @@ def V6_vroundwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35609,6 +36583,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundwuh_alt : HInst< @@ -35618,6 +36593,7 @@ def V6_vroundwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35632,6 +36608,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrsadubi_acc : HInst< @@ -35645,6 +36622,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35656,6 +36634,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35668,6 +36647,7 @@ def V6_vrsadubi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35682,18 +36662,20 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsathub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsat($Vu32.h,$Vv32.h)", -tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { +tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsathub_alt : HInst< @@ -35703,6 +36685,7 @@ def V6_vsathub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35717,6 +36700,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsatuwuh_alt : HInst< @@ -35726,6 +36710,7 @@ def V6_vsatuwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35734,12 +36719,13 @@ def V6_vsatwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsat($Vu32.w,$Vv32.w)", -tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { +tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsatwh_alt : HInst< @@ -35749,6 +36735,7 @@ def V6_vsatwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35763,6 +36750,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsb_alt : HInst< @@ -35772,6 +36760,7 @@ def V6_vsb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35784,6 +36773,7 @@ tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35796,6 +36786,7 @@ let Inst{7-5} = 0b101; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35805,6 +36796,7 @@ def V6_vscattermh_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35814,6 +36806,7 @@ def V6_vscattermh_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35826,6 +36819,7 @@ tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { let Inst{7-7} = 0b1; let Inst{31-21} = 0b00101111100; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35834,6 +36828,7 @@ def V6_vscattermhq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35846,6 +36841,7 @@ tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { let Inst{7-5} = 0b010; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35858,6 +36854,7 @@ let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35869,6 +36866,7 @@ tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> { let Inst{7-7} = 0b0; let Inst{31-21} = 0b00101111101; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35880,6 +36878,7 @@ tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101111001; let accessSize = WordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35892,6 +36891,7 @@ let Inst{7-5} = 0b100; let Inst{31-21} = 0b00101111001; let accessSize = WordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35901,6 +36901,7 @@ def V6_vscattermw_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35910,6 +36911,7 @@ def V6_vscattermw_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35920,6 +36922,7 @@ def V6_vscattermwh_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35929,6 +36932,7 @@ def V6_vscattermwh_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35938,6 +36942,7 @@ def V6_vscattermwhq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35950,6 +36955,7 @@ tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { let Inst{7-7} = 0b0; let Inst{31-21} = 0b00101111100; let accessSize = WordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35958,6 +36964,7 @@ def V6_vscattermwq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35972,6 +36979,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsh_alt : HInst< @@ -35981,6 +36989,7 @@ def V6_vsh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35995,6 +37004,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufeh_alt : HInst< @@ -36004,6 +37014,7 @@ def V6_vshufeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36020,6 +37031,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } @@ -36033,6 +37045,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffb_alt : HInst< @@ -36042,6 +37055,7 @@ def V6_vshuffb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36056,6 +37070,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffeb_alt : HInst< @@ -36065,6 +37080,7 @@ def V6_vshuffeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36079,6 +37095,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffh_alt : HInst< @@ -36088,6 +37105,7 @@ def V6_vshuffh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36102,6 +37120,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffob_alt : HInst< @@ -36111,6 +37130,7 @@ def V6_vshuffob_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36125,6 +37145,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeb : HInst< @@ -36137,6 +37158,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeb_alt : HInst< @@ -36146,6 +37168,7 @@ def V6_vshufoeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36160,6 +37183,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeh_alt : HInst< @@ -36169,6 +37193,7 @@ def V6_vshufoeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36183,6 +37208,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoh_alt : HInst< @@ -36192,6 +37218,7 @@ def V6_vshufoh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36206,6 +37233,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubb_alt : HInst< @@ -36215,6 +37243,7 @@ def V6_vsubb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36229,6 +37258,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubb_dv_alt : HInst< @@ -36238,6 +37268,7 @@ def V6_vsubb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36253,6 +37284,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36263,6 +37295,7 @@ def V6_vsubbnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36279,6 +37312,7 @@ let Inst{21-16} = 0b000001; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36289,6 +37323,7 @@ def V6_vsubbq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36304,6 +37339,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubbsat_alt : HInst< @@ -36313,6 +37349,7 @@ def V6_vsubbsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36327,6 +37364,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubbsat_dv_alt : HInst< @@ -36336,6 +37374,7 @@ def V6_vsubbsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36350,6 +37389,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -36357,7 +37397,7 @@ def V6_vsubcarryo : HInst< (outs HvxVR:$Vd32, HvxQR:$Qe4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry", -tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { +tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101101; @@ -36365,6 +37405,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh : HInst< @@ -36377,6 +37418,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh_alt : HInst< @@ -36386,6 +37428,7 @@ def V6_vsubh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36400,6 +37443,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh_dv_alt : HInst< @@ -36409,6 +37453,7 @@ def V6_vsubh_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36424,6 +37469,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36434,6 +37480,7 @@ def V6_vsubhnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36450,6 +37497,7 @@ let Inst{21-16} = 0b000001; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36460,6 +37508,7 @@ def V6_vsubhq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36475,6 +37524,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhsat_alt : HInst< @@ -36484,6 +37534,7 @@ def V6_vsubhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36498,6 +37549,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhsat_dv_alt : HInst< @@ -36507,6 +37559,7 @@ def V6_vsubhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36521,6 +37574,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhw_alt : HInst< @@ -36530,6 +37584,7 @@ def V6_vsubhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36544,6 +37599,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububh_alt : HInst< @@ -36553,6 +37609,7 @@ def V6_vsububh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36567,6 +37624,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububsat_alt : HInst< @@ -36576,6 +37634,7 @@ def V6_vsububsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36590,6 +37649,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububsat_dv_alt : HInst< @@ -36599,6 +37659,7 @@ def V6_vsububsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36613,6 +37674,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat : HInst< @@ -36625,6 +37687,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat_alt : HInst< @@ -36634,6 +37697,7 @@ def V6_vsubuhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36648,6 +37712,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat_dv_alt : HInst< @@ -36657,6 +37722,7 @@ def V6_vsubuhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36671,6 +37737,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhw_alt : HInst< @@ -36680,6 +37747,7 @@ def V6_vsubuhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36694,6 +37762,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuwsat_alt : HInst< @@ -36703,6 +37772,7 @@ def V6_vsubuwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36717,6 +37787,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuwsat_dv_alt : HInst< @@ -36726,6 +37797,7 @@ def V6_vsubuwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36740,6 +37812,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubw_alt : HInst< @@ -36749,6 +37822,7 @@ def V6_vsubw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36763,6 +37837,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubw_dv_alt : HInst< @@ -36772,6 +37847,7 @@ def V6_vsubw_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36787,6 +37863,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36797,6 +37874,7 @@ def V6_vsubwnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36813,6 +37891,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36823,6 +37902,7 @@ def V6_vsubwq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36838,6 +37918,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubwsat_alt : HInst< @@ -36847,6 +37928,7 @@ def V6_vsubwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36861,6 +37943,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubwsat_dv_alt : HInst< @@ -36870,6 +37953,7 @@ def V6_vsubwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36884,6 +37968,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyb : HInst< @@ -36896,6 +37981,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyb_acc : HInst< @@ -36909,6 +37995,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -36920,6 +38007,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36932,6 +38020,7 @@ def V6_vtmpyb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36946,6 +38035,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpybus_acc : HInst< @@ -36959,6 +38049,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -36970,6 +38061,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36982,6 +38074,7 @@ def V6_vtmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36996,6 +38089,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyhb_acc : HInst< @@ -37009,6 +38103,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37020,6 +38115,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37032,6 +38128,7 @@ def V6_vtmpyhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37045,6 +38142,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37060,6 +38158,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackb_alt : HInst< @@ -37069,6 +38168,7 @@ def V6_vunpackb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37083,6 +38183,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackh_alt : HInst< @@ -37092,6 +38193,7 @@ def V6_vunpackh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37107,6 +38209,7 @@ let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37118,6 +38221,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; @@ -37133,6 +38237,7 @@ let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37144,6 +38249,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37159,6 +38265,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackub_alt : HInst< @@ -37168,6 +38275,7 @@ def V6_vunpackub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37182,6 +38290,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackuh_alt : HInst< @@ -37191,6 +38300,7 @@ def V6_vunpackuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37202,6 +38312,7 @@ def V6_vwhist128 : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128m : HInst< @@ -37212,6 +38323,7 @@ tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> { let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128q : HInst< @@ -37222,6 +38334,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128qm : HInst< @@ -37233,6 +38346,7 @@ let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256 : HInst< @@ -37242,6 +38356,7 @@ def V6_vwhist256 : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256_sat : HInst< @@ -37251,6 +38366,7 @@ def V6_vwhist256_sat : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256q : HInst< @@ -37261,6 +38377,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256q_sat : HInst< @@ -37271,6 +38388,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vxor : HInst< @@ -37283,6 +38401,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzb : HInst< @@ -37295,6 +38414,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzb_alt : HInst< @@ -37304,6 +38424,7 @@ def V6_vzb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37318,6 +38439,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzh_alt : HInst< @@ -37327,6 +38449,7 @@ def V6_vzh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37340,6 +38463,7 @@ let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101100000; let addrMode = BaseImmOffset; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37353,6 +38477,7 @@ let Inst{7-0} = 0b00000000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101101000; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37366,6 +38491,7 @@ tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> { let Inst{12-0} = 0b0000000000001; let Inst{31-21} = 0b00101101000; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37380,6 +38506,7 @@ let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b00101100100; let isPredicated = 1; let addrMode = BaseImmOffset; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37394,6 +38521,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101101100; let isPredicated = 1; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37408,6 +38536,7 @@ let Inst{10-0} = 0b00000000001; let Inst{31-21} = 0b00101101100; let isPredicated = 1; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37422,6 +38551,7 @@ let Inst{13-5} = 0b000001001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_zld0 : HInst< @@ -37429,6 +38559,7 @@ def V6_zld0 : HInst< (ins IntRegs:$Rt32), "z = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37438,6 +38569,7 @@ def V6_zldp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) z = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37446,7 +38578,7 @@ def Y2_barrier : HInst< (outs), (ins), "barrier", -tc_8c99de45, TypeST>, Enc_e3b0c4 { +tc_77f94a5e, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100000000000; let isSoloAX = 1; @@ -37456,7 +38588,7 @@ def Y2_break : HInst< (outs), (ins), "brkpt", -tc_9ad9998f, TypeCR>, Enc_e3b0c4 { +tc_55255f2b, TypeCR>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0110110000100000; let isSolo = 1; @@ -37465,7 +38597,7 @@ def Y2_dccleana : HInst< (outs), (ins IntRegs:$Rs32), "dccleana($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000000; let isRestrictSlot1AOK = 1; @@ -37475,7 +38607,7 @@ def Y2_dccleaninva : HInst< (outs), (ins IntRegs:$Rs32), "dccleaninva($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000010; let isRestrictSlot1AOK = 1; @@ -37485,7 +38617,7 @@ def Y2_dcfetch : HInst< (outs), (ins IntRegs:$Rs32), "dcfetch($Rs32)", -tc_d63f638c, TypeMAPPING> { +tc_d45ba9cd, TypeMAPPING> { let hasSideEffects = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -37494,7 +38626,7 @@ def Y2_dcfetchbo : HInst< (outs), (ins IntRegs:$Rs32, u11_3Imm:$Ii), "dcfetch($Rs32+#$Ii)", -tc_9ca930f7, TypeLD>, Enc_2d829e { +tc_2237d952, TypeLD>, Enc_2d829e { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10010100000; let addrMode = BaseImmOffset; @@ -37505,7 +38637,7 @@ def Y2_dcinva : HInst< (outs), (ins IntRegs:$Rs32), "dcinva($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000001; let isRestrictSlot1AOK = 1; @@ -37515,7 +38647,7 @@ def Y2_dczeroa : HInst< (outs), (ins IntRegs:$Rs32), "dczeroa($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000110; let isRestrictSlot1AOK = 1; @@ -37526,7 +38658,7 @@ def Y2_icinva : HInst< (outs), (ins IntRegs:$Rs32), "icinva($Rs32)", -tc_5d7f5414, TypeJ>, Enc_ecbcc8 { +tc_0ba0d5da, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010110110; let isSolo = 1; @@ -37535,7 +38667,7 @@ def Y2_isync : HInst< (outs), (ins), "isync", -tc_8b121f4a, TypeJ>, Enc_e3b0c4 { +tc_9b34f5e0, TypeJ>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000010; let Inst{31-16} = 0b0101011111000000; let isSolo = 1; @@ -37544,7 +38676,7 @@ def Y2_syncht : HInst< (outs), (ins), "syncht", -tc_8c99de45, TypeST>, Enc_e3b0c4 { +tc_77f94a5e, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100001000000; let isSolo = 1; @@ -37553,7 +38685,7 @@ def Y2_wait : HInst< (outs), (ins IntRegs:$Rs32), "wait($Rs32)", -tc_174516e8, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> { +tc_d7718fbe, TypeCR>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100100010; let isSolo = 1; @@ -37562,7 +38694,7 @@ def Y4_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "l2fetch($Rs32,$Rt32)", -tc_fe211424, TypeST>, Enc_ca3887 { +tc_a3070909, TypeST>, Enc_ca3887 { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110000; @@ -37574,7 +38706,7 @@ def Y4_trace : HInst< (outs), (ins IntRegs:$Rs32), "trace($Rs32)", -tc_6b25e783, TypeCR>, Enc_ecbcc8 { +tc_d7718fbe, TypeCR>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100010010; let isSoloAX = 1; @@ -37583,7 +38715,7 @@ def Y5_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "l2fetch($Rs32,$Rtt32)", -tc_fe211424, TypeST>, Enc_e6abcf { +tc_a3070909, TypeST>, Enc_e6abcf { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; @@ -37591,11 +38723,37 @@ let isSoloAX = 1; let mayStore = 1; let hasSideEffects = 1; } +def Y6_diag : HInst< +(outs), +(ins IntRegs:$Rs32), +"diag($Rs32)", +tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> { +let Inst{13-0} = 0b00000000100000; +let Inst{31-21} = 0b01100010010; +} +def Y6_diag0 : HInst< +(outs), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"diag0($Rss32,$Rtt32)", +tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> { +let Inst{7-0} = 0b01000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100010010; +} +def Y6_diag1 : HInst< +(outs), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"diag1($Rss32,$Rtt32)", +tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> { +let Inst{7-0} = 0b01100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100010010; +} def dep_A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat:deprecated", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -37608,7 +38766,7 @@ def dep_A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat:deprecated", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -37621,8 +38779,476 @@ def dep_S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32):deprecated", -tc_946df596, TypeALU64>, Enc_be32a5 { +tc_5da50c4b, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100000; } +def dup_A2_add : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32)", +tc_388f9897, TypeALU32_3op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_addi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,#$Ii)", +tc_388f9897, TypeALU32_ADDI>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def dup_A2_andir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = and($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def dup_A2_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, s8_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_A2_sxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxtb($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_sxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxth($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_tfr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = $Rs32", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_tfrsi : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii), +"$Rd32 = #$Ii", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def dup_A2_zxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxtb($Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_zxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxth($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A4_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def dup_A4_combineir : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rdd32 = combine(#$Ii,$Rs32)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_A4_combineri : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rdd32 = combine($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_C2_cmoveif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = #$Ii", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmoveit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = #$Ii", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmovenewif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = #$Ii", +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmovenewit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = #$Ii", +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmpeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.eq($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def dup_L2_deallocframe : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = deallocframe($Rs32):raw", +tc_aee6250c, TypeLD>, Requires<[HasV67]> { +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [FRAMEKEY]; +let Defs = [R29]; +let isPseudo = 1; +} +def dup_L2_loadrb_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memb($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_L2_loadrd_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s29_3Imm:$Ii), +"$Rdd32 = memd($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def dup_L2_loadrh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memh($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_L2_loadri_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rd32 = memw($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def dup_L2_loadrub_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memub($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_L2_loadruh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memuh($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_S2_allocframe : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u11_3Imm:$Ii), +"allocframe($Rx32,#$Ii):raw", +tc_74a42bda, TypeST>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31]; +let Defs = [R30]; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def dup_S2_storerb_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_S2_storerd_io : HInst< +(outs), +(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+#$Ii) = $Rtt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def dup_S2_storerh_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_S2_storeri_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def dup_S4_storeirb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"memb($Rs32+#$Ii) = #$II", +tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_S4_storeiri_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"memw($Rs32+#$Ii) = #$II", +tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} diff --git a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td index 61a1df5eb94bb..0143d6f44d88e 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td +++ b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -1,2750 +1,2680 @@ -//===-------------------------------------------------------*- tablegen -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// // V5 Scalar Instructions. -def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1), - (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2), - (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2), - (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1), - (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1), - (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1), - (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1), - (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2), - (C4_cmplte IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2), - (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1), - (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_abssat IntRegs:$src1), - (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_cmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_cmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2), - (C2_cmpgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (C2_cmpgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2), - (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2), - (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1), - (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2), - (A4_cmpheq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), - (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2), - (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1), - (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_not PredRegs:$src1), - (C2_not PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1), - (C2_tfrpr PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2), - (A4_cmpbgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; + (C2_tfrpr (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2), - (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2), + (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2), + (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_bitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_bitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_nbitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_nbitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), + (C2_tfrpr (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), + (C2_tfrpr (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmpneq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmplte IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmplteu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_xor (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_not PredRegs:$src1), + (C2_tfrpr (C2_not (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1), + (C2_tfrpr (C2_pxfer_map (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_any8 PredRegs:$src1), + (C2_tfrpr (C2_any8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_all8 PredRegs:$src1), + (C2_tfrpr (C2_all8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2), + (C2_vitpack (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (C2_mux (C2_tfrrp PredRegs:$src1), IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3), + (C2_muxii (C2_tfrrp PredRegs:$src1), s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (C2_muxir (C2_tfrrp PredRegs:$src1), IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), + (C2_muxri (C2_tfrrp PredRegs:$src1), s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (C2_vmux (C2_tfrrp PredRegs:$src1), DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_mask PredRegs:$src1), + (C2_mask (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2), - (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2), - (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2), - (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1), - (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1), - (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_all8 PredRegs:$src1), - (C2_all8 PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2), - (C2_bitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysip IntRegs:$src1, u32_0ImmPred_timm:$src2), - (M2_mpysip IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysin IntRegs:$src1, u8_0ImmPred_timm:$src2), - (M2_mpysin IntRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpheq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmphgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmphgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_boundscheck IntRegs:$src1, DoubleRegs:$src2), - (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1), + (C2_tfrpr (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1), + (C2_tfrpr (C2_tfrrp IntRegs:$src1))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C4_fastcorner9 PredRegs:$src1, PredRegs:$src2), - (C4_fastcorner9 PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2), - (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2), - (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2), - (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (C4_fastcorner9 (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C4_fastcorner9_not (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1), - (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1), - (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2), - (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2), - (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), - (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2), - (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2), - (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1), - (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1), - (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1), - (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1), - (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_any8 PredRegs:$src1), - (C2_any8 PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2), - (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1), - (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1), - (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2), (M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2), (M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2), - (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1), - (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2), - (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2), - (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2), - (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2), - (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2), - (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_negsat IntRegs:$src1), - (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2), - (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1), - (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2), - (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2), (M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2), (M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2), - (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_tfrpcp DoubleRegs:$src1), - (A4_tfrpcp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1), - (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_zxth IntRegs:$src1), - (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), (M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), (M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1), - (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2), - (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2), - (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), - (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2), - (C2_xor PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1), - (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1), - (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1), - (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxth IntRegs:$src1), - (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1), - (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1), - (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1), - (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2), - (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2), - (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1), - (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), - (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2), - (S2_tstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3), - (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2), + (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2), (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2), - (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1), - (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2), - (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2), + (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2), + (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3), + (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3), + (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2), (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2), (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2), (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1), - (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), - (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2), - (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1), - (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1), - (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2), (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1), - (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2), - (C2_andn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), (M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2), - (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2), - (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_combineii s8_0ImmPred_timm:$src1, u32_0ImmPred_timm:$src2), - (A4_combineii s8_0ImmPred_timm:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2), - (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2), - (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1), - (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2), - (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2), - (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2), (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2), - (C4_nbitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2), - (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2), - (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1), - (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1), - (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2), (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1), - (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2), - (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2), - (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1), - (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2), + (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4), + (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3), + (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2), + (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2), + (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2), + (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2), + (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2), + (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2), + (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2), + (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_aslh IntRegs:$src1), + (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_asrh IntRegs:$src1), + (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2), + (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negsat IntRegs:$src1), + (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abs IntRegs:$src1), + (A2_abs IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abssat IntRegs:$src1), + (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1), + (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1), + (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1), + (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2), + (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2), + (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2), + (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2), (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2), (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfr IntRegs:$src1), + (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1), + (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1), + (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1), + (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1), + (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxth IntRegs:$src1), + (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxth IntRegs:$src1), + (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2), + (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2), + (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2), + (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2), + (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2), + (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2), + (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2), + (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2), + (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2), + (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2), + (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2), + (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2), + (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2), + (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2), + (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), + (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2), - (F2_sfcmpge IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2), - (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2), - (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2), - (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; + (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2), + (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1), + (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1), + (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1), + (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1), (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1), - (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2), - (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_tfrcpp CtrRegs64:$src1), - (A4_tfrcpp CtrRegs64:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2), - (A4_cmphgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_sath IntRegs:$src1), (A2_sath IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satuh IntRegs:$src1), + (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satub IntRegs:$src1), + (A2_satub IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_satb IntRegs:$src1), (A2_satb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4), - (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2), + (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2), (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2), (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_asrh IntRegs:$src1), - (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2), - (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2), - (C2_or PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2), - (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2), - (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfinvsqrta IntRegs:$src1), - (F2_sfinvsqrta IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1), - (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2), + (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2), + (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2), + (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2), (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2), - (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_aslh IntRegs:$src1), - (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1), - (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2), - (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1), - (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), - (C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1), - (C2_pxfer_map PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2), - (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3), - (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrcrr CtrRegs:$src1), - (A2_tfrcrr CtrRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2), - (C2_orn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2), - (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_mask PredRegs:$src1), - (C2_mask PredRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2), - (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2), - (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2), + (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2), + (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2), + (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1), + (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1), + (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1), + (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1), + (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2), (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrrcr IntRegs:$src1), - (A2_tfrrcr IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2), - (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2), + (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2), + (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2), + (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2), (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2), (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1), - (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2), - (C2_cmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1), - (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1), - (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2), + (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2), + (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2), + (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2), + (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), + (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpge IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2), + (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2), + (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2), - (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3), - (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1), - (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2), - (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; + (C2_tfrpr (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1), + (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1), + (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2), + (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2), + (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1), + (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1), + (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1), + (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1), + (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1), + (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1), + (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1), + (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1), + (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1), + (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1), + (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1), + (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1), + (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1), + (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1), (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1), + (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1), (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1), + (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1), + (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1), + (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1), + (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1), + (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1), (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1), - (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2), - (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2), - (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1), + (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1), + (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1), + (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1), + (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1), + (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1), + (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1), + (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2), (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2), - (C2_vitpack PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2), - (C4_nbitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2), - (C2_and PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1), - (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), - (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1), - (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2), - (C4_cmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clb IntRegs:$src1), - (S2_clb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2), - (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1), - (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1), - (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2), - (A4_cmphgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1), - (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3), - (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), - (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2), - (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfrecipa IntRegs:$src1, IntRegs:$src2), - (F2_sfrecipa IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2), - (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2), - (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2), - (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2), - (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2), - (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2), - (C2_cmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1), - (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1), - (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_satuh IntRegs:$src1), - (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_satub IntRegs:$src1), - (A2_satub IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2), - (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2), - (C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2), - (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2), - (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1), - (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1), - (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1), - (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2), - (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3), - (C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_swiz IntRegs:$src1), - (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2), - (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1), - (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2), - (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), - (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1), - (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfr IntRegs:$src1), - (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2), - (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2), - (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_brev IntRegs:$src1), - (S2_brev IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1), - (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4), - (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1), - (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2), - (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2), - (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1), - (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1), - (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1), - (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1), - (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1), - (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2), - (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1), - (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1), - (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2), - (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), - (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1), - (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1), - (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2), - (C4_cmplteu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2), (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2), - (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2), - (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2), - (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2), (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2), - (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2), - (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2), (S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3), + (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), + (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), + (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1), + (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1), + (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), + (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2), + (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), + (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), + (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4), + (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), + (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), + (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3), + (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2), + (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2), + (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (S2_tstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2), + (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2), + (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2), + (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2), (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1), - (C2_tfrrp IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1), + (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1), + (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1), + (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1), + (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1), + (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1), + (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1), + (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1), + (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1), + (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2), (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_abs IntRegs:$src1), - (A2_abs IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2), - (A4_cmpbeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1), - (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1), + (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1), + (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1), + (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1), + (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1), (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1), - (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2), - (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2), - (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2), - (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2), + (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_swiz IntRegs:$src1), + (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1), + (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1), + (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1), + (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1), + (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2), (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3), - (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), - (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2), - (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2), - (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1), - (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1), + (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2), (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1), - (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2), - (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1), - (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2), - (C2_bitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2), - (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), - (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; - -// V55 Scalar Instructions. - -def: Pat<(int_hexagon_A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV55]>; +def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1), + (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2), + (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1), + (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2), + (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clb IntRegs:$src1), + (S2_clb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1), + (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1), + (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1), + (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1), + (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1), + (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_brev IntRegs:$src1), + (S2_brev IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1), + (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1), + (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1), + (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1), + (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1), + (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1), + (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1), + (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dczeroa IntRegs:$src1), + (Y2_dczeroa IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dccleana IntRegs:$src1), + (Y2_dccleana IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dccleaninva IntRegs:$src1), + (Y2_dccleaninva IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dcinva IntRegs:$src1), + (Y2_dcinva IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y4_l2fetch IntRegs:$src1, IntRegs:$src2), + (Y4_l2fetch IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2), + (Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; // V60 Scalar Instructions. -def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), (S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; // V62 Scalar Instructions. -def: Pat<(int_hexagon_S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2), - (S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; -def: Pat<(int_hexagon_V6_ldntnt0 IntRegs:$src1), - (V6_ldntnt0 IntRegs:$src1)>, Requires<[HasV62]>; -def: Pat<(int_hexagon_M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2), - (M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; -def: Pat<(int_hexagon_S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2), - (S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; def: Pat<(int_hexagon_M6_vabsdiffb DoubleRegs:$src1, DoubleRegs:$src2), (M6_vabsdiffb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; -def: Pat<(int_hexagon_A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2), - (A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2), + (M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; def: Pat<(int_hexagon_S6_vsplatrbp IntRegs:$src1), (S6_vsplatrbp IntRegs:$src1)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2), + (S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2), + (S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; // V65 Scalar Instructions. def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), - (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>; + (C2_tfrpr (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV65]>; // V66 Scalar Instructions. -def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; -def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; def: Pat<(int_hexagon_S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2), (S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV66]>; +// V67 Scalar Instructions. + +def: Pat<(int_hexagon_M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_vdmpy DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_vdmpy_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2), + (A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmax DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfmax DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; + // V60 HVX Instructions. -def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2), - (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2), - (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybusi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2), - (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2), - (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2), - (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2), - (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2), - (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2), - (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybusv HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybusv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2), - (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2), - (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2), (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2), (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtran2x2_map_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2), - (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2), (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2), (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2), - (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2), - (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lo HvxWR:$src1), - (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1), - (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldu0 IntRegs:$src1), - (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldu0_128B IntRegs:$src1), - (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2), - (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsh HvxVR:$src1), - (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1), - (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2), - (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vzb HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsb HvxVR:$src1), (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1), (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2), - (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2), - (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1), - (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1), - (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2), - (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1), - (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1), - (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhb HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2), - (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2), - (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2), - (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2), - (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2), - (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vzh HvxVR:$src1), (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1), (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2), - (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2), - (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2), - (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2), - (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2), - (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2), - (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2), - (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2), - (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2), - (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1), - (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1), - (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2), - (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1), - (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1), - (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2), - (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vzb HvxVR:$src1), - (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1), - (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsh HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2), (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpybus_dv_128B HvxWR:$src1, IntRegs:$src2), (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2), - (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vtmpyb HvxWR:$src1, IntRegs:$src2), (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vtmpyb_128B HvxWR:$src1, IntRegs:$src2), (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2), - (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2), - (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vrmpyubv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaslw HvxVR:$src1, IntRegs:$src2), (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaslw_128B HvxVR:$src1, IntRegs:$src2), (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1), - (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1), - (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2), - (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2), - (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2), - (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2), - (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2), - (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2), - (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2), - (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2), - (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2), - (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2), - (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2), - (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2), - (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vasrwhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2), - (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2), - (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2), - (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffh HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2), - (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1), - (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1), - (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1), - (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1), - (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2), - (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2), - (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2), - (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_hi HvxWR:$src1), - (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1), - (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vasrwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2), - (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2), - (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2), - (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2), + (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2), + (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsubw HvxVR:$src1, HvxVR:$src2), (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsubw_128B HvxVR:$src1, HvxVR:$src2), (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsubw_dv HvxWR:$src1, HvxWR:$src2), (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsubw_dv_128B HvxWR:$src1, HvxWR:$src2), (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2), - (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2), - (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2), - (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsubhsat HvxVR:$src1, HvxVR:$src2), (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsubhsat_128B HvxVR:$src1, HvxVR:$src2), (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1), - (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1), - (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2), (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddwsat_dv_128B HvxWR:$src1, HvxWR:$src2), (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2), - (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2), - (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1), - (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1), - (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2), - (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffub HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffw HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vd0 ), + (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vd0_128B ), + (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsubhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2), - (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2), - (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2), - (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2), - (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2), - (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2), - (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1), - (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1), - (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2), - (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2), - (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2), (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2), (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2), - (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1), - (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1), - (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2), - (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2), (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2), (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpybus_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2), - (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ld0 IntRegs:$src1), - (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ld0_128B IntRegs:$src1), - (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1), - (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1), - (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldnt0 IntRegs:$src1), - (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldnt0_128B IntRegs:$src1), - (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2), - (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2), - (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1), - (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1), - (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1), - (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1), - (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2), - (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2), - (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2), - (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyiowh HvxVR:$src1, HvxVR:$src2), (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyiowh_128B HvxVR:$src1, HvxVR:$src2), (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2), - (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2), - (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2), - (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1), - (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1), - (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2), - (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2), - (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2), - (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vd0 ), - (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vd0_128B ), - (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2), - (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpybus HvxVR:$src1, IntRegs:$src2), (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpybus_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vassign HvxVR:$src1), - (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1), - (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhb_dv_128B HvxWR:$src1, IntRegs:$src2), - (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1), - (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1), - (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1), - (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1), - (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpahb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2), - (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2), - (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyihb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2), - (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2), - (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyiwb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnot HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_veqw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffub HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2), - (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_veqw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), @@ -2753,584 +2683,664 @@ def: Pat<(int_hexagon_V6_vgth HvxVR:$src1, HvxVR:$src2), (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vgth_128B HvxVR:$src1, HvxVR:$src2), (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vgtb HvxVR:$src1, HvxVR:$src2), (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vgtb_128B HvxVR:$src1, HvxVR:$src2), (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2), - (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnot HvxVR:$src1), - (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1), - (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vgtb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2), (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2), (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2), - (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1), - (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1), - (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2), - (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2), - (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1), - (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1), - (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2), - (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2), - (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2), + (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2), + (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2), + (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1), + (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1), + (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1), (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1), (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1), - (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1), - (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassign HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2), - (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2), - (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2), - (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2), - (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2), - (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2), - (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybusi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2), - (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2), - (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2), - (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2), - (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffw HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_hi HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lo HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; // V62 HVX Instructions. -def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2), - (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldcnpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2), - (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vlsrb HvxVR:$src1, IntRegs:$src2), (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vlsrb_128B HvxVR:$src1, IntRegs:$src2), (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldtp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldtp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2), - (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2), - (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1), - (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1), - (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1), - (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1), - (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldtpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldnpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2), - (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldtnp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldtnp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vrounduhub HvxVR:$src1, HvxVR:$src2), (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vrounduhub_128B HvxVR:$src1, HvxVR:$src2), (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldcp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldcp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vadduwsat HvxVR:$src1, HvxVR:$src2), (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vadduwsat_128B HvxVR:$src1, HvxVR:$src2), (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldtnpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddbsat HvxVR:$src1, HvxVR:$src2), (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddbsat_128B HvxVR:$src1, HvxVR:$src2), (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2), - (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2), - (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2), - (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2), + (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2), + (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2), (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2), (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddbsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldnp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldnp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2), - (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2), + (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2), + (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_pred_scalar2v2 IntRegs:$src1), (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_pred_scalar2v2_128B IntRegs:$src1), (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2), + (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2), + (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2), + (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddclbw HvxVR:$src1, HvxVR:$src2), (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddclbw_128B HvxVR:$src1, HvxVR:$src2), (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2), - (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldcpnt0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_ldcnp0 PredRegs:$src1, IntRegs:$src2), - (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_ldcnp0_128B PredRegs:$src1, IntRegs:$src2), - (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vlutvwh_oracci_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; // V65 HVX Instructions. +def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), - (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), - (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdd0 ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdd0_128B ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), + (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), + (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), + (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), + (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), + (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), - (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), - (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), - (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), - (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), - (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), - (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), - (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), - (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), - (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), - (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), - (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), - (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), - (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdd0 ), - (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdd0_128B ), - (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), - (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), - (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), - (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), + (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), + (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), + (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), + (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; // V66 HVX Instructions. -def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; def: Pat<(int_hexagon_V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX64B]>; def: Pat<(int_hexagon_V6_vasr_into_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsatdw HvxVR:$src1, HvxVR:$src2), (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsatdw_128B HvxVR:$src1, HvxVR:$src2), (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2), - (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepMappings.td b/llvm/lib/Target/Hexagon/HexagonDepMappings.td index 22ee495b25e67..3fca1aee9a60e 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepMappings.td +++ b/llvm/lib/Target/Hexagon/HexagonDepMappings.td @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>; @@ -94,6 +94,8 @@ def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= $Rt32", (L4_sub_memopw_ def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>; def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>; def M2_mpyuiAlias : InstAlias<"$Rd32 = mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>; +def M7_vdmpyAlias : InstAlias<"$Rdd32 = vdmpyw($Rss32,$Rtt32)", (M7_dcmpyrwc DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def M7_vdmpy_accAlias : InstAlias<"$Rxx32 += vdmpyw($Rss32,$Rtt32)", (M7_dcmpyrwc_acc DoubleRegs:$Rxx32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; @@ -253,16 +255,9 @@ def V6_vaslwv_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Vv32)", (V6_vaslwv HvxV def V6_vasr_into_altAlias : InstAlias<"$Vxx32 = vasrinto($Vu32,$Vv32)", (V6_vasr_into HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; def V6_vasrh_acc_altAlias : InstAlias<"$Vx32 += vasrh($Vu32,$Rt32)", (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; def V6_vasrh_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; def V6_vasrhv_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; def V6_vasrw_acc_altAlias : InstAlias<"$Vx32 += vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; def V6_vasrw_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrwh_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; def V6_vasrwv_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; def V6_vavgb_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32)", (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; def V6_vavgbrnd_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32):rnd", (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepMask.h b/llvm/lib/Target/Hexagon/HexagonDepMask.h new file mode 100644 index 0000000000000..742fe2d14d5bc --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonDepMask.h @@ -0,0 +1,2821 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H + +// clang-format off +HexagonInstruction InstructionEncodings[] = { +{ /*Tag:A2_addi*/ + /*Rd32=add(Rs32,#s16)*/ + 0xf0000000, + 0xb0000000, + 0x0fe03fe0, + 0 }, +{ /*Tag:A2_andir*/ + /*Rd32=and(Rs32,#s10)*/ + 0xffc00000, + 0x76000000, + 0x00203fe0, + 0 }, +{ /*Tag:A2_combineii*/ + /*Rdd32=combine(#s8,#S8)*/ + 0xff800000, + 0x7c000000, + 0x00001fe0, + 0 }, +{ /*Tag:A2_orir*/ + /*Rd32=or(Rs32,#s10)*/ + 0xffc00000, + 0x76800000, + 0x00203fe0, + 0 }, +{ /*Tag:A2_paddif*/ + /*if (!Pu4) Rd32=add(Rs32,#s8)*/ + 0xff802000, + 0x74800000, + 0x00001fe0, + 0 }, +{ /*Tag:A2_paddifnew*/ + /*if (!Pu4.new) Rd32=add(Rs32,#s8)*/ + 0xff802000, + 0x74802000, + 0x00001fe0, + 0 }, +{ /*Tag:A2_paddit*/ + /*if (Pu4) Rd32=add(Rs32,#s8)*/ + 0xff802000, + 0x74000000, + 0x00001fe0, + 0 }, +{ /*Tag:A2_padditnew*/ + /*if (Pu4.new) Rd32=add(Rs32,#s8)*/ + 0xff802000, + 0x74002000, + 0x00001fe0, + 0 }, +{ /*Tag:A2_subri*/ + /*Rd32=sub(#s10,Rs32)*/ + 0xffc00000, + 0x76400000, + 0x00203fe0, + 0 }, +{ /*Tag:A2_tfrsi*/ + /*Rd32=#s16*/ + 0xff000000, + 0x78000000, + 0x00df3fe0, + 0 }, +{ /*Tag:A4_cmpbgtui*/ + /*Pd4=cmpb.gtu(Rs32,#u7)*/ + 0xff601018, + 0xdd400000, + 0x00000fe0, + 0 }, +{ /*Tag:A4_cmpheqi*/ + /*Pd4=cmph.eq(Rs32,#s8)*/ + 0xff600018, + 0xdd000008, + 0x00001fe0, + 0 }, +{ /*Tag:A4_cmphgti*/ + /*Pd4=cmph.gt(Rs32,#s8)*/ + 0xff600018, + 0xdd200008, + 0x00001fe0, + 0 }, +{ /*Tag:A4_cmphgtui*/ + /*Pd4=cmph.gtu(Rs32,#u7)*/ + 0xff601018, + 0xdd400008, + 0x00000fe0, + 0 }, +{ /*Tag:A4_combineii*/ + /*Rdd32=combine(#s8,#U6)*/ + 0xff800000, + 0x7c800000, + 0x001f2000, + 0 }, +{ /*Tag:A4_combineir*/ + /*Rdd32=combine(#s8,Rs32)*/ + 0xff602000, + 0x73202000, + 0x00001fe0, + 0 }, +{ /*Tag:A4_combineri*/ + /*Rdd32=combine(Rs32,#s8)*/ + 0xff602000, + 0x73002000, + 0x00001fe0, + 0 }, +{ /*Tag:A4_rcmpeqi*/ + /*Rd32=cmp.eq(Rs32,#s8)*/ + 0xff602000, + 0x73402000, + 0x00001fe0, + 0 }, +{ /*Tag:A4_rcmpneqi*/ + /*Rd32=!cmp.eq(Rs32,#s8)*/ + 0xff602000, + 0x73602000, + 0x00001fe0, + 0 }, +{ /*Tag:C2_cmoveif*/ + /*if (!Pu4) Rd32=#s12*/ + 0xff902000, + 0x7e800000, + 0x000f1fe0, + 0 }, +{ /*Tag:C2_cmoveit*/ + /*if (Pu4) Rd32=#s12*/ + 0xff902000, + 0x7e000000, + 0x000f1fe0, + 0 }, +{ /*Tag:C2_cmovenewif*/ + /*if (!Pu4.new) Rd32=#s12*/ + 0xff902000, + 0x7e802000, + 0x000f1fe0, + 0 }, +{ /*Tag:C2_cmovenewit*/ + /*if (Pu4.new) Rd32=#s12*/ + 0xff902000, + 0x7e002000, + 0x000f1fe0, + 0 }, +{ /*Tag:C2_cmpeqi*/ + /*Pd4=cmp.eq(Rs32,#s10)*/ + 0xffc0001c, + 0x75000000, + 0x00203fe0, + 0 }, +{ /*Tag:C2_cmpgti*/ + /*Pd4=cmp.gt(Rs32,#s10)*/ + 0xffc0001c, + 0x75400000, + 0x00203fe0, + 0 }, +{ /*Tag:C2_cmpgtui*/ + /*Pd4=cmp.gtu(Rs32,#u9)*/ + 0xffe0001c, + 0x75800000, + 0x00003fe0, + 0 }, +{ /*Tag:C2_muxii*/ + /*Rd32=mux(Pu4,#s8,#S8)*/ + 0xfe000000, + 0x7a000000, + 0x00001fe0, + 0 }, +{ /*Tag:C2_muxir*/ + /*Rd32=mux(Pu4,Rs32,#s8)*/ + 0xff802000, + 0x73000000, + 0x00001fe0, + 0 }, +{ /*Tag:C2_muxri*/ + /*Rd32=mux(Pu4,#s8,Rs32)*/ + 0xff802000, + 0x73800000, + 0x00001fe0, + 0 }, +{ /*Tag:C4_addipc*/ + /*Rd32=add(pc,#u6)*/ + 0xffff0000, + 0x6a490000, + 0x00001f80, + 0 }, +{ /*Tag:C4_cmpltei*/ + /*Pd4=!cmp.gt(Rs32,#s10)*/ + 0xffc0001c, + 0x75400010, + 0x00203fe0, + 0 }, +{ /*Tag:C4_cmplteui*/ + /*Pd4=!cmp.gtu(Rs32,#u9)*/ + 0xffe0001c, + 0x75800010, + 0x00003fe0, + 0 }, +{ /*Tag:C4_cmpneqi*/ + /*Pd4=!cmp.eq(Rs32,#s10)*/ + 0xffc0001c, + 0x75000010, + 0x00203fe0, + 0 }, +{ /*Tag:J2_call*/ + /*call #r22:2*/ + 0xfe000001, + 0x5a000000, + 0x01ff3ffe, + 0 }, +{ /*Tag:J2_callf*/ + /*if (!Pu4) call #r15:2*/ + 0xff200800, + 0x5d200000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_callt*/ + /*if (Pu4) call #r15:2*/ + 0xff200800, + 0x5d000000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jump*/ + /*jump #r22:2*/ + 0xfe000000, + 0x58000000, + 0x01ff3ffe, + 0 }, +{ /*Tag:J2_jumpf*/ + /*if (!Pu4) jump:nt #r15:2*/ + 0xff201800, + 0x5c200000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumpfnew*/ + /*if (!Pu4.new) jump:nt #r15:2*/ + 0xff201800, + 0x5c200800, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumpfnewpt*/ + /*if (!Pu4.new) jump:t #r15:2*/ + 0xff201800, + 0x5c201800, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumpfpt*/ + /*if (!Pu4) jump:t #r15:2*/ + 0xff201800, + 0x5c201000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumpt*/ + /*if (Pu4) jump:nt #r15:2*/ + 0xff201800, + 0x5c000000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumptnew*/ + /*if (Pu4.new) jump:nt #r15:2*/ + 0xff201800, + 0x5c000800, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumptnewpt*/ + /*if (Pu4.new) jump:t #r15:2*/ + 0xff201800, + 0x5c001800, + 0x00df20fe, + 0 }, +{ /*Tag:J2_jumptpt*/ + /*if (Pu4) jump:t #r15:2*/ + 0xff201800, + 0x5c001000, + 0x00df20fe, + 0 }, +{ /*Tag:J2_loop0i*/ + /*loop0(#r7:2,#U10)*/ + 0xffe00000, + 0x69000000, + 0x00001f18, + 0 }, +{ /*Tag:J2_loop0r*/ + /*loop0(#r7:2,Rs32)*/ + 0xffe00000, + 0x60000000, + 0x00001f18, + 0 }, +{ /*Tag:J2_loop1i*/ + /*loop1(#r7:2,#U10)*/ + 0xffe00000, + 0x69200000, + 0x00001f18, + 0 }, +{ /*Tag:J2_loop1r*/ + /*loop1(#r7:2,Rs32)*/ + 0xffe00000, + 0x60200000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop1si*/ + /*p3=sp1loop0(#r7:2,#U10)*/ + 0xffe00000, + 0x69a00000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop1sr*/ + /*p3=sp1loop0(#r7:2,Rs32)*/ + 0xffe00000, + 0x60a00000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop2si*/ + /*p3=sp2loop0(#r7:2,#U10)*/ + 0xffe00000, + 0x69c00000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop2sr*/ + /*p3=sp2loop0(#r7:2,Rs32)*/ + 0xffe00000, + 0x60c00000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop3si*/ + /*p3=sp3loop0(#r7:2,#U10)*/ + 0xffe00000, + 0x69e00000, + 0x00001f18, + 0 }, +{ /*Tag:J2_ploop3sr*/ + /*p3=sp3loop0(#r7:2,Rs32)*/ + 0xffe00000, + 0x60e00000, + 0x00001f18, + 0 }, +{ /*Tag:J4_cmpeq_f_jumpnv_nt*/ + /*if (!cmp.eq(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x20400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_f_jumpnv_t*/ + /*if (!cmp.eq(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x20402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_fp0_jump_nt*/ + /*p0=cmp.eq(Rs16,Rt16); if (!p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_fp0_jump_t*/ + /*p0=cmp.eq(Rs16,Rt16); if (!p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x14402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_fp1_jump_nt*/ + /*p1=cmp.eq(Rs16,Rt16); if (!p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14401000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_fp1_jump_t*/ + /*p1=cmp.eq(Rs16,Rt16); if (!p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x14403000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_t_jumpnv_nt*/ + /*if (cmp.eq(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x20000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_t_jumpnv_t*/ + /*if (cmp.eq(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x20002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_tp0_jump_nt*/ + /*p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_tp0_jump_t*/ + /*p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x14002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_tp1_jump_nt*/ + /*p1=cmp.eq(Rs16,Rt16); if (p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14001000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeq_tp1_jump_t*/ + /*p1=cmp.eq(Rs16,Rt16); if (p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x14003000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_f_jumpnv_nt*/ + /*if (!cmp.eq(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x24400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_f_jumpnv_t*/ + /*if (!cmp.eq(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x24402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_fp0_jump_nt*/ + /*p0=cmp.eq(Rs16,#U5); if (!p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x10400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_fp0_jump_t*/ + /*p0=cmp.eq(Rs16,#U5); if (!p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x10402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_fp1_jump_nt*/ + /*p1=cmp.eq(Rs16,#U5); if (!p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x12400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_fp1_jump_t*/ + /*p1=cmp.eq(Rs16,#U5); if (!p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x12402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_t_jumpnv_nt*/ + /*if (cmp.eq(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x24000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_t_jumpnv_t*/ + /*if (cmp.eq(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x24002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_tp0_jump_nt*/ + /*p0=cmp.eq(Rs16,#U5); if (p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x10000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_tp0_jump_t*/ + /*p0=cmp.eq(Rs16,#U5); if (p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x10002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_tp1_jump_nt*/ + /*p1=cmp.eq(Rs16,#U5); if (p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x12000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqi_tp1_jump_t*/ + /*p1=cmp.eq(Rs16,#U5); if (p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x12002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_f_jumpnv_nt*/ + /*if (!cmp.eq(Ns8.new,#-1)) jump:nt #r9:2*/ + 0xffc02000, + 0x26400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_f_jumpnv_t*/ + /*if (!cmp.eq(Ns8.new,#-1)) jump:t #r9:2*/ + 0xffc02000, + 0x26402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_fp0_jump_nt*/ + /*p0=cmp.eq(Rs16,#-1); if (!p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_fp0_jump_t*/ + /*p0=cmp.eq(Rs16,#-1); if (!p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_fp1_jump_nt*/ + /*p1=cmp.eq(Rs16,#-1); if (!p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_fp1_jump_t*/ + /*p1=cmp.eq(Rs16,#-1); if (!p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_t_jumpnv_nt*/ + /*if (cmp.eq(Ns8.new,#-1)) jump:nt #r9:2*/ + 0xffc02000, + 0x26000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_t_jumpnv_t*/ + /*if (cmp.eq(Ns8.new,#-1)) jump:t #r9:2*/ + 0xffc02000, + 0x26002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_tp0_jump_nt*/ + /*p0=cmp.eq(Rs16,#-1); if (p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_tp0_jump_t*/ + /*p0=cmp.eq(Rs16,#-1); if (p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_tp1_jump_nt*/ + /*p1=cmp.eq(Rs16,#-1); if (p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpeqn1_tp1_jump_t*/ + /*p1=cmp.eq(Rs16,#-1); if (p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_f_jumpnv_nt*/ + /*if (!cmp.gt(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x20c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_f_jumpnv_t*/ + /*if (!cmp.gt(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x20c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_fp0_jump_nt*/ + /*p0=cmp.gt(Rs16,Rt16); if (!p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_fp0_jump_t*/ + /*p0=cmp.gt(Rs16,Rt16); if (!p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x14c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_fp1_jump_nt*/ + /*p1=cmp.gt(Rs16,Rt16); if (!p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14c01000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_fp1_jump_t*/ + /*p1=cmp.gt(Rs16,Rt16); if (!p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x14c03000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_t_jumpnv_nt*/ + /*if (cmp.gt(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x20800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_t_jumpnv_t*/ + /*if (cmp.gt(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x20802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_tp0_jump_nt*/ + /*p0=cmp.gt(Rs16,Rt16); if (p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_tp0_jump_t*/ + /*p0=cmp.gt(Rs16,Rt16); if (p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x14802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_tp1_jump_nt*/ + /*p1=cmp.gt(Rs16,Rt16); if (p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x14801000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgt_tp1_jump_t*/ + /*p1=cmp.gt(Rs16,Rt16); if (p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x14803000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_f_jumpnv_nt*/ + /*if (!cmp.gt(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x24c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_f_jumpnv_t*/ + /*if (!cmp.gt(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x24c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_fp0_jump_nt*/ + /*p0=cmp.gt(Rs16,#U5); if (!p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x10c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_fp0_jump_t*/ + /*p0=cmp.gt(Rs16,#U5); if (!p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x10c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_fp1_jump_nt*/ + /*p1=cmp.gt(Rs16,#U5); if (!p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x12c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_fp1_jump_t*/ + /*p1=cmp.gt(Rs16,#U5); if (!p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x12c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_t_jumpnv_nt*/ + /*if (cmp.gt(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x24800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_t_jumpnv_t*/ + /*if (cmp.gt(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x24802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_tp0_jump_nt*/ + /*p0=cmp.gt(Rs16,#U5); if (p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x10800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_tp0_jump_t*/ + /*p0=cmp.gt(Rs16,#U5); if (p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x10802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_tp1_jump_nt*/ + /*p1=cmp.gt(Rs16,#U5); if (p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x12800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgti_tp1_jump_t*/ + /*p1=cmp.gt(Rs16,#U5); if (p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x12802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_f_jumpnv_nt*/ + /*if (!cmp.gt(Ns8.new,#-1)) jump:nt #r9:2*/ + 0xffc02000, + 0x26c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_f_jumpnv_t*/ + /*if (!cmp.gt(Ns8.new,#-1)) jump:t #r9:2*/ + 0xffc02000, + 0x26c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_fp0_jump_nt*/ + /*p0=cmp.gt(Rs16,#-1); if (!p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11c00100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_fp0_jump_t*/ + /*p0=cmp.gt(Rs16,#-1); if (!p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11c02100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_fp1_jump_nt*/ + /*p1=cmp.gt(Rs16,#-1); if (!p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13c00100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_fp1_jump_t*/ + /*p1=cmp.gt(Rs16,#-1); if (!p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13c02100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_t_jumpnv_nt*/ + /*if (cmp.gt(Ns8.new,#-1)) jump:nt #r9:2*/ + 0xffc02000, + 0x26800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_t_jumpnv_t*/ + /*if (cmp.gt(Ns8.new,#-1)) jump:t #r9:2*/ + 0xffc02000, + 0x26802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_tp0_jump_nt*/ + /*p0=cmp.gt(Rs16,#-1); if (p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11800100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_tp0_jump_t*/ + /*p0=cmp.gt(Rs16,#-1); if (p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11802100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_tp1_jump_nt*/ + /*p1=cmp.gt(Rs16,#-1); if (p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13800100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtn1_tp1_jump_t*/ + /*p1=cmp.gt(Rs16,#-1); if (p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13802100, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_f_jumpnv_nt*/ + /*if (!cmp.gtu(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x21400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_f_jumpnv_t*/ + /*if (!cmp.gtu(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x21402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_fp0_jump_nt*/ + /*p0=cmp.gtu(Rs16,Rt16); if (!p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x15400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_fp0_jump_t*/ + /*p0=cmp.gtu(Rs16,Rt16); if (!p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x15402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_fp1_jump_nt*/ + /*p1=cmp.gtu(Rs16,Rt16); if (!p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x15401000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_fp1_jump_t*/ + /*p1=cmp.gtu(Rs16,Rt16); if (!p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x15403000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_t_jumpnv_nt*/ + /*if (cmp.gtu(Ns8.new,Rt32)) jump:nt #r9:2*/ + 0xffc02000, + 0x21000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_t_jumpnv_t*/ + /*if (cmp.gtu(Ns8.new,Rt32)) jump:t #r9:2*/ + 0xffc02000, + 0x21002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_tp0_jump_nt*/ + /*p0=cmp.gtu(Rs16,Rt16); if (p0.new) jump:nt #r9:2*/ + 0xffc03000, + 0x15000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_tp0_jump_t*/ + /*p0=cmp.gtu(Rs16,Rt16); if (p0.new) jump:t #r9:2*/ + 0xffc03000, + 0x15002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_tp1_jump_nt*/ + /*p1=cmp.gtu(Rs16,Rt16); if (p1.new) jump:nt #r9:2*/ + 0xffc03000, + 0x15001000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtu_tp1_jump_t*/ + /*p1=cmp.gtu(Rs16,Rt16); if (p1.new) jump:t #r9:2*/ + 0xffc03000, + 0x15003000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_f_jumpnv_nt*/ + /*if (!cmp.gtu(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x25400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_f_jumpnv_t*/ + /*if (!cmp.gtu(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x25402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_fp0_jump_nt*/ + /*p0=cmp.gtu(Rs16,#U5); if (!p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x11400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_fp0_jump_t*/ + /*p0=cmp.gtu(Rs16,#U5); if (!p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x11402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_fp1_jump_nt*/ + /*p1=cmp.gtu(Rs16,#U5); if (!p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x13400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_fp1_jump_t*/ + /*p1=cmp.gtu(Rs16,#U5); if (!p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x13402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_t_jumpnv_nt*/ + /*if (cmp.gtu(Ns8.new,#U5)) jump:nt #r9:2*/ + 0xffc02000, + 0x25000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_t_jumpnv_t*/ + /*if (cmp.gtu(Ns8.new,#U5)) jump:t #r9:2*/ + 0xffc02000, + 0x25002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_tp0_jump_nt*/ + /*p0=cmp.gtu(Rs16,#U5); if (p0.new) jump:nt #r9:2*/ + 0xffc02000, + 0x11000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_tp0_jump_t*/ + /*p0=cmp.gtu(Rs16,#U5); if (p0.new) jump:t #r9:2*/ + 0xffc02000, + 0x11002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_tp1_jump_nt*/ + /*p1=cmp.gtu(Rs16,#U5); if (p1.new) jump:nt #r9:2*/ + 0xffc02000, + 0x13000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpgtui_tp1_jump_t*/ + /*p1=cmp.gtu(Rs16,#U5); if (p1.new) jump:t #r9:2*/ + 0xffc02000, + 0x13002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmplt_f_jumpnv_nt*/ + /*if (!cmp.gt(Rt32,Ns8.new)) jump:nt #r9:2*/ + 0xffc02000, + 0x21c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmplt_f_jumpnv_t*/ + /*if (!cmp.gt(Rt32,Ns8.new)) jump:t #r9:2*/ + 0xffc02000, + 0x21c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmplt_t_jumpnv_nt*/ + /*if (cmp.gt(Rt32,Ns8.new)) jump:nt #r9:2*/ + 0xffc02000, + 0x21800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmplt_t_jumpnv_t*/ + /*if (cmp.gt(Rt32,Ns8.new)) jump:t #r9:2*/ + 0xffc02000, + 0x21802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpltu_f_jumpnv_nt*/ + /*if (!cmp.gtu(Rt32,Ns8.new)) jump:nt #r9:2*/ + 0xffc02000, + 0x22400000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpltu_f_jumpnv_t*/ + /*if (!cmp.gtu(Rt32,Ns8.new)) jump:t #r9:2*/ + 0xffc02000, + 0x22402000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpltu_t_jumpnv_nt*/ + /*if (cmp.gtu(Rt32,Ns8.new)) jump:nt #r9:2*/ + 0xffc02000, + 0x22000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_cmpltu_t_jumpnv_t*/ + /*if (cmp.gtu(Rt32,Ns8.new)) jump:t #r9:2*/ + 0xffc02000, + 0x22002000, + 0x003000fe, + 0 }, +{ /*Tag:J4_jumpseti*/ + /*Rd16=#U6 ; jump #r9:2*/ + 0xff000000, + 0x16000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_jumpsetr*/ + /*Rd16=Rs16 ; jump #r9:2*/ + 0xff000000, + 0x17000000, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_f_jumpnv_nt*/ + /*if (!tstbit(Ns8.new,#0)) jump:nt #r9:2*/ + 0xffc02000, + 0x25c00000, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_f_jumpnv_t*/ + /*if (!tstbit(Ns8.new,#0)) jump:t #r9:2*/ + 0xffc02000, + 0x25c02000, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_fp0_jump_nt*/ + /*p0=tstbit(Rs16,#0); if (!p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11c00300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_fp0_jump_t*/ + /*p0=tstbit(Rs16,#0); if (!p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11c02300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_fp1_jump_nt*/ + /*p1=tstbit(Rs16,#0); if (!p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13c00300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_fp1_jump_t*/ + /*p1=tstbit(Rs16,#0); if (!p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13c02300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_t_jumpnv_nt*/ + /*if (tstbit(Ns8.new,#0)) jump:nt #r9:2*/ + 0xffc02000, + 0x25800000, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_t_jumpnv_t*/ + /*if (tstbit(Ns8.new,#0)) jump:t #r9:2*/ + 0xffc02000, + 0x25802000, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_tp0_jump_nt*/ + /*p0=tstbit(Rs16,#0); if (p0.new) jump:nt #r9:2*/ + 0xffc02300, + 0x11800300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_tp0_jump_t*/ + /*p0=tstbit(Rs16,#0); if (p0.new) jump:t #r9:2*/ + 0xffc02300, + 0x11802300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_tp1_jump_nt*/ + /*p1=tstbit(Rs16,#0); if (p1.new) jump:nt #r9:2*/ + 0xffc02300, + 0x13800300, + 0x003000fe, + 0 }, +{ /*Tag:J4_tstbit0_tp1_jump_t*/ + /*p1=tstbit(Rs16,#0); if (p1.new) jump:t #r9:2*/ + 0xffc02300, + 0x13802300, + 0x003000fe, + 0 }, +{ /*Tag:L2_loadalignb_io*/ + /*Ryy32=memb_fifo(Rs32+#s11:0)*/ + 0xf9e00000, + 0x90800000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadalignh_io*/ + /*Ryy32=memh_fifo(Rs32+#s11:1)*/ + 0xf9e00000, + 0x90400000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadbsw2_io*/ + /*Rd32=membh(Rs32+#s11:1)*/ + 0xf9e00000, + 0x90200000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadbsw4_io*/ + /*Rdd32=membh(Rs32+#s11:2)*/ + 0xf9e00000, + 0x90e00000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadbzw2_io*/ + /*Rd32=memubh(Rs32+#s11:1)*/ + 0xf9e00000, + 0x90600000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadbzw4_io*/ + /*Rdd32=memubh(Rs32+#s11:2)*/ + 0xf9e00000, + 0x90a00000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrb_io*/ + /*Rd32=memb(Rs32+#s11:0)*/ + 0xf9e00000, + 0x91000000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrbgp*/ + /*Rd32=memb(gp+#u16:0)*/ + 0xf9e00000, + 0x49000000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_loadrd_io*/ + /*Rdd32=memd(Rs32+#s11:3)*/ + 0xf9e00000, + 0x91c00000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrdgp*/ + /*Rdd32=memd(gp+#u16:3)*/ + 0xf9e00000, + 0x49c00000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_loadrh_io*/ + /*Rd32=memh(Rs32+#s11:1)*/ + 0xf9e00000, + 0x91400000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrhgp*/ + /*Rd32=memh(gp+#u16:1)*/ + 0xf9e00000, + 0x49400000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_loadri_io*/ + /*Rd32=memw(Rs32+#s11:2)*/ + 0xf9e00000, + 0x91800000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrigp*/ + /*Rd32=memw(gp+#u16:2)*/ + 0xf9e00000, + 0x49800000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_loadrub_io*/ + /*Rd32=memub(Rs32+#s11:0)*/ + 0xf9e00000, + 0x91200000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadrubgp*/ + /*Rd32=memub(gp+#u16:0)*/ + 0xf9e00000, + 0x49200000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_loadruh_io*/ + /*Rd32=memuh(Rs32+#s11:1)*/ + 0xf9e00000, + 0x91600000, + 0x06003fe0, + 0 }, +{ /*Tag:L2_loadruhgp*/ + /*Rd32=memuh(gp+#u16:1)*/ + 0xf9e00000, + 0x49600000, + 0x061f3fe0, + 0 }, +{ /*Tag:L2_ploadrbf_io*/ + /*if (!Pt4) Rd32=memb(Rs32+#u6:0)*/ + 0xffe02000, + 0x45000000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrbfnew_io*/ + /*if (!Pt4.new) Rd32=memb(Rs32+#u6:0)*/ + 0xffe02000, + 0x47000000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrbt_io*/ + /*if (Pt4) Rd32=memb(Rs32+#u6:0)*/ + 0xffe02000, + 0x41000000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrbtnew_io*/ + /*if (Pt4.new) Rd32=memb(Rs32+#u6:0)*/ + 0xffe02000, + 0x43000000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrdf_io*/ + /*if (!Pt4) Rdd32=memd(Rs32+#u6:3)*/ + 0xffe02000, + 0x45c00000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrdfnew_io*/ + /*if (!Pt4.new) Rdd32=memd(Rs32+#u6:3)*/ + 0xffe02000, + 0x47c00000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrdt_io*/ + /*if (Pt4) Rdd32=memd(Rs32+#u6:3)*/ + 0xffe02000, + 0x41c00000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrdtnew_io*/ + /*if (Pt4.new) Rdd32=memd(Rs32+#u6:3)*/ + 0xffe02000, + 0x43c00000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrhf_io*/ + /*if (!Pt4) Rd32=memh(Rs32+#u6:1)*/ + 0xffe02000, + 0x45400000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrhfnew_io*/ + /*if (!Pt4.new) Rd32=memh(Rs32+#u6:1)*/ + 0xffe02000, + 0x47400000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrht_io*/ + /*if (Pt4) Rd32=memh(Rs32+#u6:1)*/ + 0xffe02000, + 0x41400000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrhtnew_io*/ + /*if (Pt4.new) Rd32=memh(Rs32+#u6:1)*/ + 0xffe02000, + 0x43400000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrif_io*/ + /*if (!Pt4) Rd32=memw(Rs32+#u6:2)*/ + 0xffe02000, + 0x45800000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrifnew_io*/ + /*if (!Pt4.new) Rd32=memw(Rs32+#u6:2)*/ + 0xffe02000, + 0x47800000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrit_io*/ + /*if (Pt4) Rd32=memw(Rs32+#u6:2)*/ + 0xffe02000, + 0x41800000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadritnew_io*/ + /*if (Pt4.new) Rd32=memw(Rs32+#u6:2)*/ + 0xffe02000, + 0x43800000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrubf_io*/ + /*if (!Pt4) Rd32=memub(Rs32+#u6:0)*/ + 0xffe02000, + 0x45200000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrubfnew_io*/ + /*if (!Pt4.new) Rd32=memub(Rs32+#u6:0)*/ + 0xffe02000, + 0x47200000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrubt_io*/ + /*if (Pt4) Rd32=memub(Rs32+#u6:0)*/ + 0xffe02000, + 0x41200000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadrubtnew_io*/ + /*if (Pt4.new) Rd32=memub(Rs32+#u6:0)*/ + 0xffe02000, + 0x43200000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadruhf_io*/ + /*if (!Pt4) Rd32=memuh(Rs32+#u6:1)*/ + 0xffe02000, + 0x45600000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadruhfnew_io*/ + /*if (!Pt4.new) Rd32=memuh(Rs32+#u6:1)*/ + 0xffe02000, + 0x47600000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadruht_io*/ + /*if (Pt4) Rd32=memuh(Rs32+#u6:1)*/ + 0xffe02000, + 0x41600000, + 0x000007e0, + 0 }, +{ /*Tag:L2_ploadruhtnew_io*/ + /*if (Pt4.new) Rd32=memuh(Rs32+#u6:1)*/ + 0xffe02000, + 0x43600000, + 0x000007e0, + 0 }, +{ /*Tag:L4_add_memopb_io*/ + /*memb(Rs32+#u6:0)+=Rt32*/ + 0xff602060, + 0x3e000000, + 0x00001f80, + 0 }, +{ /*Tag:L4_add_memoph_io*/ + /*memh(Rs32+#u6:1)+=Rt32*/ + 0xff602060, + 0x3e200000, + 0x00001f80, + 0 }, +{ /*Tag:L4_add_memopw_io*/ + /*memw(Rs32+#u6:2)+=Rt32*/ + 0xff602060, + 0x3e400000, + 0x00001f80, + 0 }, +{ /*Tag:L4_and_memopb_io*/ + /*memb(Rs32+#u6:0)&=Rt32*/ + 0xff602060, + 0x3e000040, + 0x00001f80, + 0 }, +{ /*Tag:L4_and_memoph_io*/ + /*memh(Rs32+#u6:1)&=Rt32*/ + 0xff602060, + 0x3e200040, + 0x00001f80, + 0 }, +{ /*Tag:L4_and_memopw_io*/ + /*memw(Rs32+#u6:2)&=Rt32*/ + 0xff602060, + 0x3e400040, + 0x00001f80, + 0 }, +{ /*Tag:L4_iadd_memopb_io*/ + /*memb(Rs32+#u6:0)+=#U5*/ + 0xff602060, + 0x3f000000, + 0x00001f80, + 0 }, +{ /*Tag:L4_iadd_memoph_io*/ + /*memh(Rs32+#u6:1)+=#U5*/ + 0xff602060, + 0x3f200000, + 0x00001f80, + 0 }, +{ /*Tag:L4_iadd_memopw_io*/ + /*memw(Rs32+#u6:2)+=#U5*/ + 0xff602060, + 0x3f400000, + 0x00001f80, + 0 }, +{ /*Tag:L4_iand_memopb_io*/ + /*memb(Rs32+#u6:0)=clrbit(#U5)*/ + 0xff602060, + 0x3f000040, + 0x00001f80, + 0 }, +{ /*Tag:L4_iand_memoph_io*/ + /*memh(Rs32+#u6:1)=clrbit(#U5)*/ + 0xff602060, + 0x3f200040, + 0x00001f80, + 0 }, +{ /*Tag:L4_iand_memopw_io*/ + /*memw(Rs32+#u6:2)=clrbit(#U5)*/ + 0xff602060, + 0x3f400040, + 0x00001f80, + 0 }, +{ /*Tag:L4_ior_memopb_io*/ + /*memb(Rs32+#u6:0)=setbit(#U5)*/ + 0xff602060, + 0x3f000060, + 0x00001f80, + 0 }, +{ /*Tag:L4_ior_memoph_io*/ + /*memh(Rs32+#u6:1)=setbit(#U5)*/ + 0xff602060, + 0x3f200060, + 0x00001f80, + 0 }, +{ /*Tag:L4_ior_memopw_io*/ + /*memw(Rs32+#u6:2)=setbit(#U5)*/ + 0xff602060, + 0x3f400060, + 0x00001f80, + 0 }, +{ /*Tag:L4_isub_memopb_io*/ + /*memb(Rs32+#u6:0)-=#U5*/ + 0xff602060, + 0x3f000020, + 0x00001f80, + 0 }, +{ /*Tag:L4_isub_memoph_io*/ + /*memh(Rs32+#u6:1)-=#U5*/ + 0xff602060, + 0x3f200020, + 0x00001f80, + 0 }, +{ /*Tag:L4_isub_memopw_io*/ + /*memw(Rs32+#u6:2)-=#U5*/ + 0xff602060, + 0x3f400020, + 0x00001f80, + 0 }, +{ /*Tag:L4_loadalignb_ap*/ + /*Ryy32=memb_fifo(Re32=#U6)*/ + 0xffe03000, + 0x9a801000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadalignb_ur*/ + /*Ryy32=memb_fifo(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9c801000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadalignh_ap*/ + /*Ryy32=memh_fifo(Re32=#U6)*/ + 0xffe03000, + 0x9a401000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadalignh_ur*/ + /*Ryy32=memh_fifo(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9c401000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbsw2_ap*/ + /*Rd32=membh(Re32=#U6)*/ + 0xffe03000, + 0x9a201000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbsw2_ur*/ + /*Rd32=membh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9c201000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbsw4_ap*/ + /*Rdd32=membh(Re32=#U6)*/ + 0xffe03000, + 0x9ae01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbsw4_ur*/ + /*Rdd32=membh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9ce01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbzw2_ap*/ + /*Rd32=memubh(Re32=#U6)*/ + 0xffe03000, + 0x9a601000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbzw2_ur*/ + /*Rd32=memubh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9c601000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbzw4_ap*/ + /*Rdd32=memubh(Re32=#U6)*/ + 0xffe03000, + 0x9aa01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadbzw4_ur*/ + /*Rdd32=memubh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9ca01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrb_ap*/ + /*Rd32=memb(Re32=#U6)*/ + 0xffe03000, + 0x9b001000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrb_ur*/ + /*Rd32=memb(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9d001000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrd_ap*/ + /*Rdd32=memd(Re32=#U6)*/ + 0xffe03000, + 0x9bc01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrd_ur*/ + /*Rdd32=memd(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9dc01000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrh_ap*/ + /*Rd32=memh(Re32=#U6)*/ + 0xffe03000, + 0x9b401000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrh_ur*/ + /*Rd32=memh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9d401000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadri_ap*/ + /*Rd32=memw(Re32=#U6)*/ + 0xffe03000, + 0x9b801000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadri_ur*/ + /*Rd32=memw(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9d801000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrub_ap*/ + /*Rd32=memub(Re32=#U6)*/ + 0xffe03000, + 0x9b201000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadrub_ur*/ + /*Rd32=memub(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9d201000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadruh_ap*/ + /*Rd32=memuh(Re32=#U6)*/ + 0xffe03000, + 0x9b601000, + 0x00000f60, + 0 }, +{ /*Tag:L4_loadruh_ur*/ + /*Rd32=memuh(Rt32<<#u2+#U6)*/ + 0xffe01000, + 0x9d601000, + 0x00000f60, + 0 }, +{ /*Tag:L4_or_memopb_io*/ + /*memb(Rs32+#u6:0)|=Rt32*/ + 0xff602060, + 0x3e000060, + 0x00001f80, + 0 }, +{ /*Tag:L4_or_memoph_io*/ + /*memh(Rs32+#u6:1)|=Rt32*/ + 0xff602060, + 0x3e200060, + 0x00001f80, + 0 }, +{ /*Tag:L4_or_memopw_io*/ + /*memw(Rs32+#u6:2)|=Rt32*/ + 0xff602060, + 0x3e400060, + 0x00001f80, + 0 }, +{ /*Tag:L4_ploadrbf_abs*/ + /*if (!Pt4) Rd32=memb(#u6)*/ + 0xffe03880, + 0x9f002880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrbfnew_abs*/ + /*if (!Pt4.new) Rd32=memb(#u6)*/ + 0xffe03880, + 0x9f003880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrbt_abs*/ + /*if (Pt4) Rd32=memb(#u6)*/ + 0xffe03880, + 0x9f002080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrbtnew_abs*/ + /*if (Pt4.new) Rd32=memb(#u6)*/ + 0xffe03880, + 0x9f003080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrdf_abs*/ + /*if (!Pt4) Rdd32=memd(#u6)*/ + 0xffe03880, + 0x9fc02880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrdfnew_abs*/ + /*if (!Pt4.new) Rdd32=memd(#u6)*/ + 0xffe03880, + 0x9fc03880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrdt_abs*/ + /*if (Pt4) Rdd32=memd(#u6)*/ + 0xffe03880, + 0x9fc02080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrdtnew_abs*/ + /*if (Pt4.new) Rdd32=memd(#u6)*/ + 0xffe03880, + 0x9fc03080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrhf_abs*/ + /*if (!Pt4) Rd32=memh(#u6)*/ + 0xffe03880, + 0x9f402880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrhfnew_abs*/ + /*if (!Pt4.new) Rd32=memh(#u6)*/ + 0xffe03880, + 0x9f403880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrht_abs*/ + /*if (Pt4) Rd32=memh(#u6)*/ + 0xffe03880, + 0x9f402080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrhtnew_abs*/ + /*if (Pt4.new) Rd32=memh(#u6)*/ + 0xffe03880, + 0x9f403080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrif_abs*/ + /*if (!Pt4) Rd32=memw(#u6)*/ + 0xffe03880, + 0x9f802880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrifnew_abs*/ + /*if (!Pt4.new) Rd32=memw(#u6)*/ + 0xffe03880, + 0x9f803880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrit_abs*/ + /*if (Pt4) Rd32=memw(#u6)*/ + 0xffe03880, + 0x9f802080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadritnew_abs*/ + /*if (Pt4.new) Rd32=memw(#u6)*/ + 0xffe03880, + 0x9f803080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrubf_abs*/ + /*if (!Pt4) Rd32=memub(#u6)*/ + 0xffe03880, + 0x9f202880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrubfnew_abs*/ + /*if (!Pt4.new) Rd32=memub(#u6)*/ + 0xffe03880, + 0x9f203880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrubt_abs*/ + /*if (Pt4) Rd32=memub(#u6)*/ + 0xffe03880, + 0x9f202080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadrubtnew_abs*/ + /*if (Pt4.new) Rd32=memub(#u6)*/ + 0xffe03880, + 0x9f203080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadruhf_abs*/ + /*if (!Pt4) Rd32=memuh(#u6)*/ + 0xffe03880, + 0x9f602880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadruhfnew_abs*/ + /*if (!Pt4.new) Rd32=memuh(#u6)*/ + 0xffe03880, + 0x9f603880, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadruht_abs*/ + /*if (Pt4) Rd32=memuh(#u6)*/ + 0xffe03880, + 0x9f602080, + 0x001f0100, + 0 }, +{ /*Tag:L4_ploadruhtnew_abs*/ + /*if (Pt4.new) Rd32=memuh(#u6)*/ + 0xffe03880, + 0x9f603080, + 0x001f0100, + 0 }, +{ /*Tag:L4_sub_memopb_io*/ + /*memb(Rs32+#u6:0)-=Rt32*/ + 0xff602060, + 0x3e000020, + 0x00001f80, + 0 }, +{ /*Tag:L4_sub_memoph_io*/ + /*memh(Rs32+#u6:1)-=Rt32*/ + 0xff602060, + 0x3e200020, + 0x00001f80, + 0 }, +{ /*Tag:L4_sub_memopw_io*/ + /*memw(Rs32+#u6:2)-=Rt32*/ + 0xff602060, + 0x3e400020, + 0x00001f80, + 0 }, +{ /*Tag:M2_accii*/ + /*Rx32+=add(Rs32,#s8)*/ + 0xff802000, + 0xe2000000, + 0x00001fe0, + 0 }, +{ /*Tag:M2_macsin*/ + /*Rx32-=mpyi(Rs32,#u8)*/ + 0xff802000, + 0xe1800000, + 0x00001fe0, + 0 }, +{ /*Tag:M2_macsip*/ + /*Rx32+=mpyi(Rs32,#u8)*/ + 0xff802000, + 0xe1000000, + 0x00001fe0, + 0 }, +{ /*Tag:M2_mpysip*/ + /*Rd32=+mpyi(Rs32,#u8)*/ + 0xff802000, + 0xe0000000, + 0x00001fe0, + 0 }, +{ /*Tag:M2_naccii*/ + /*Rx32-=add(Rs32,#s8)*/ + 0xff802000, + 0xe2800000, + 0x00001fe0, + 0 }, +{ /*Tag:M4_mpyri_addi*/ + /*Rd32=add(#u6,mpyi(Rs32,#U6))*/ + 0xff000000, + 0xd8000000, + 0x006020e0, + 0 }, +{ /*Tag:M4_mpyri_addr*/ + /*Rd32=add(Ru32,mpyi(Rs32,#u6))*/ + 0xff800000, + 0xdf800000, + 0x006020e0, + 0 }, +{ /*Tag:M4_mpyrr_addi*/ + /*Rd32=add(#u6,mpyi(Rs32,Rt32))*/ + 0xff800000, + 0xd7000000, + 0x006020e0, + 0 }, +{ /*Tag:PS_loadrbabs*/ + /*Rd32=memb(#u16:0)*/ + 0xf9e00000, + 0x49000000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_loadrdabs*/ + /*Rdd32=memd(#u16:3)*/ + 0xf9e00000, + 0x49c00000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_loadrhabs*/ + /*Rd32=memh(#u16:1)*/ + 0xf9e00000, + 0x49400000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_loadriabs*/ + /*Rd32=memw(#u16:2)*/ + 0xf9e00000, + 0x49800000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_loadrubabs*/ + /*Rd32=memub(#u16:0)*/ + 0xf9e00000, + 0x49200000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_loadruhabs*/ + /*Rd32=memuh(#u16:1)*/ + 0xf9e00000, + 0x49600000, + 0x061f3fe0, + 0 }, +{ /*Tag:PS_storerbabs*/ + /*memb(#u16:0)=Rt32*/ + 0xf9e00000, + 0x48000000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerbnewabs*/ + /*memb(#u16:0)=Nt8.new*/ + 0xf9e01800, + 0x48a00000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerdabs*/ + /*memd(#u16:3)=Rtt32*/ + 0xf9e00000, + 0x48c00000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerfabs*/ + /*memh(#u16:1)=Rt32.h*/ + 0xf9e00000, + 0x48600000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerhabs*/ + /*memh(#u16:1)=Rt32*/ + 0xf9e00000, + 0x48400000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerhnewabs*/ + /*memh(#u16:1)=Nt8.new*/ + 0xf9e01800, + 0x48a00800, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storeriabs*/ + /*memw(#u16:2)=Rt32*/ + 0xf9e00000, + 0x48800000, + 0x061f20ff, + 0 }, +{ /*Tag:PS_storerinewabs*/ + /*memw(#u16:2)=Nt8.new*/ + 0xf9e01800, + 0x48a01000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_pstorerbf_io*/ + /*if (!Pv4) memb(Rs32+#u6:0)=Rt32*/ + 0xffe00004, + 0x44000000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerbnewf_io*/ + /*if (!Pv4) memb(Rs32+#u6:0)=Nt8.new*/ + 0xffe01804, + 0x44a00000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerbnewt_io*/ + /*if (Pv4) memb(Rs32+#u6:0)=Nt8.new*/ + 0xffe01804, + 0x40a00000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerbt_io*/ + /*if (Pv4) memb(Rs32+#u6:0)=Rt32*/ + 0xffe00004, + 0x40000000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerdf_io*/ + /*if (!Pv4) memd(Rs32+#u6:3)=Rtt32*/ + 0xffe00004, + 0x44c00000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerdt_io*/ + /*if (Pv4) memd(Rs32+#u6:3)=Rtt32*/ + 0xffe00004, + 0x40c00000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerff_io*/ + /*if (!Pv4) memh(Rs32+#u6:1)=Rt32.h*/ + 0xffe00004, + 0x44600000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerft_io*/ + /*if (Pv4) memh(Rs32+#u6:1)=Rt32.h*/ + 0xffe00004, + 0x40600000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerhf_io*/ + /*if (!Pv4) memh(Rs32+#u6:1)=Rt32*/ + 0xffe00004, + 0x44400000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerhnewf_io*/ + /*if (!Pv4) memh(Rs32+#u6:1)=Nt8.new*/ + 0xffe01804, + 0x44a00800, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerhnewt_io*/ + /*if (Pv4) memh(Rs32+#u6:1)=Nt8.new*/ + 0xffe01804, + 0x40a00800, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerht_io*/ + /*if (Pv4) memh(Rs32+#u6:1)=Rt32*/ + 0xffe00004, + 0x40400000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerif_io*/ + /*if (!Pv4) memw(Rs32+#u6:2)=Rt32*/ + 0xffe00004, + 0x44800000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerinewf_io*/ + /*if (!Pv4) memw(Rs32+#u6:2)=Nt8.new*/ + 0xffe01804, + 0x44a01000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerinewt_io*/ + /*if (Pv4) memw(Rs32+#u6:2)=Nt8.new*/ + 0xffe01804, + 0x40a01000, + 0x000020f8, + 0 }, +{ /*Tag:S2_pstorerit_io*/ + /*if (Pv4) memw(Rs32+#u6:2)=Rt32*/ + 0xffe00004, + 0x40800000, + 0x000020f8, + 0 }, +{ /*Tag:S2_storerb_io*/ + /*memb(Rs32+#s11:0)=Rt32*/ + 0xf9e00000, + 0xa1000000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerbgp*/ + /*memb(gp+#u16:0)=Rt32*/ + 0xf9e00000, + 0x48000000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerbnew_io*/ + /*memb(Rs32+#s11:0)=Nt8.new*/ + 0xf9e01800, + 0xa1a00000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerbnewgp*/ + /*memb(gp+#u16:0)=Nt8.new*/ + 0xf9e01800, + 0x48a00000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerd_io*/ + /*memd(Rs32+#s11:3)=Rtt32*/ + 0xf9e00000, + 0xa1c00000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerdgp*/ + /*memd(gp+#u16:3)=Rtt32*/ + 0xf9e00000, + 0x48c00000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerf_io*/ + /*memh(Rs32+#s11:1)=Rt32.h*/ + 0xf9e00000, + 0xa1600000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerfgp*/ + /*memh(gp+#u16:1)=Rt32.h*/ + 0xf9e00000, + 0x48600000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerh_io*/ + /*memh(Rs32+#s11:1)=Rt32*/ + 0xf9e00000, + 0xa1400000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerhgp*/ + /*memh(gp+#u16:1)=Rt32*/ + 0xf9e00000, + 0x48400000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerhnew_io*/ + /*memh(Rs32+#s11:1)=Nt8.new*/ + 0xf9e01800, + 0xa1a00800, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerhnewgp*/ + /*memh(gp+#u16:1)=Nt8.new*/ + 0xf9e01800, + 0x48a00800, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storeri_io*/ + /*memw(Rs32+#s11:2)=Rt32*/ + 0xf9e00000, + 0xa1800000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerigp*/ + /*memw(gp+#u16:2)=Rt32*/ + 0xf9e00000, + 0x48800000, + 0x061f20ff, + 0 }, +{ /*Tag:S2_storerinew_io*/ + /*memw(Rs32+#s11:2)=Nt8.new*/ + 0xf9e01800, + 0xa1a01000, + 0x060020ff, + 0 }, +{ /*Tag:S2_storerinewgp*/ + /*memw(gp+#u16:2)=Nt8.new*/ + 0xf9e01800, + 0x48a01000, + 0x061f20ff, + 0 }, +{ /*Tag:S4_addaddi*/ + /*Rd32=add(Rs32,add(Ru32,#s6))*/ + 0xff800000, + 0xdb000000, + 0x006020e0, + 0 }, +{ /*Tag:S4_addi_asl_ri*/ + /*Rx32=add(#u8,asl(Rx32,#U5))*/ + 0xff000016, + 0xde000004, + 0x00e020e8, + 0 }, +{ /*Tag:S4_addi_lsr_ri*/ + /*Rx32=add(#u8,lsr(Rx32,#U5))*/ + 0xff000016, + 0xde000014, + 0x00e020e8, + 0 }, +{ /*Tag:S4_andi_asl_ri*/ + /*Rx32=and(#u8,asl(Rx32,#U5))*/ + 0xff000016, + 0xde000000, + 0x00e020e8, + 0 }, +{ /*Tag:S4_andi_lsr_ri*/ + /*Rx32=and(#u8,lsr(Rx32,#U5))*/ + 0xff000016, + 0xde000010, + 0x00e020e8, + 0 }, +{ /*Tag:S4_or_andi*/ + /*Rx32|=and(Rs32,#s10)*/ + 0xffc00000, + 0xda000000, + 0x00203fe0, + 0 }, +{ /*Tag:S4_or_andix*/ + /*Rx32=or(Ru32,and(Rx32,#s10))*/ + 0xffc00000, + 0xda400000, + 0x00203fe0, + 0 }, +{ /*Tag:S4_or_ori*/ + /*Rx32|=or(Rs32,#s10)*/ + 0xffc00000, + 0xda800000, + 0x00203fe0, + 0 }, +{ /*Tag:S4_ori_asl_ri*/ + /*Rx32=or(#u8,asl(Rx32,#U5))*/ + 0xff000016, + 0xde000002, + 0x00e020e8, + 0 }, +{ /*Tag:S4_ori_lsr_ri*/ + /*Rx32=or(#u8,lsr(Rx32,#U5))*/ + 0xff000016, + 0xde000012, + 0x00e020e8, + 0 }, +{ /*Tag:S4_pstorerbf_abs*/ + /*if (!Pv4) memb(#u6)=Rt32*/ + 0xffe02084, + 0xaf000084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbfnew_abs*/ + /*if (!Pv4.new) memb(#u6)=Rt32*/ + 0xffe02084, + 0xaf002084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbfnew_io*/ + /*if (!Pv4.new) memb(Rs32+#u6:0)=Rt32*/ + 0xffe00004, + 0x46000000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerbnewf_abs*/ + /*if (!Pv4) memb(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa00084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbnewfnew_abs*/ + /*if (!Pv4.new) memb(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa02084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbnewfnew_io*/ + /*if (!Pv4.new) memb(Rs32+#u6:0)=Nt8.new*/ + 0xffe01804, + 0x46a00000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerbnewt_abs*/ + /*if (Pv4) memb(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa00080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbnewtnew_abs*/ + /*if (Pv4.new) memb(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa02080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbnewtnew_io*/ + /*if (Pv4.new) memb(Rs32+#u6:0)=Nt8.new*/ + 0xffe01804, + 0x42a00000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerbt_abs*/ + /*if (Pv4) memb(#u6)=Rt32*/ + 0xffe02084, + 0xaf000080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbtnew_abs*/ + /*if (Pv4.new) memb(#u6)=Rt32*/ + 0xffe02084, + 0xaf002080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerbtnew_io*/ + /*if (Pv4.new) memb(Rs32+#u6:0)=Rt32*/ + 0xffe00004, + 0x42000000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerdf_abs*/ + /*if (!Pv4) memd(#u6)=Rtt32*/ + 0xffe02084, + 0xafc00084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerdfnew_abs*/ + /*if (!Pv4.new) memd(#u6)=Rtt32*/ + 0xffe02084, + 0xafc02084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerdfnew_io*/ + /*if (!Pv4.new) memd(Rs32+#u6:3)=Rtt32*/ + 0xffe00004, + 0x46c00000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerdt_abs*/ + /*if (Pv4) memd(#u6)=Rtt32*/ + 0xffe02084, + 0xafc00080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerdtnew_abs*/ + /*if (Pv4.new) memd(#u6)=Rtt32*/ + 0xffe02084, + 0xafc02080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerdtnew_io*/ + /*if (Pv4.new) memd(Rs32+#u6:3)=Rtt32*/ + 0xffe00004, + 0x42c00000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerff_abs*/ + /*if (!Pv4) memh(#u6)=Rt32.h*/ + 0xffe02084, + 0xaf600084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerffnew_abs*/ + /*if (!Pv4.new) memh(#u6)=Rt32.h*/ + 0xffe02084, + 0xaf602084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerffnew_io*/ + /*if (!Pv4.new) memh(Rs32+#u6:1)=Rt32.h*/ + 0xffe00004, + 0x46600000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerft_abs*/ + /*if (Pv4) memh(#u6)=Rt32.h*/ + 0xffe02084, + 0xaf600080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerftnew_abs*/ + /*if (Pv4.new) memh(#u6)=Rt32.h*/ + 0xffe02084, + 0xaf602080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerftnew_io*/ + /*if (Pv4.new) memh(Rs32+#u6:1)=Rt32.h*/ + 0xffe00004, + 0x42600000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerhf_abs*/ + /*if (!Pv4) memh(#u6)=Rt32*/ + 0xffe02084, + 0xaf400084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhfnew_abs*/ + /*if (!Pv4.new) memh(#u6)=Rt32*/ + 0xffe02084, + 0xaf402084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhfnew_io*/ + /*if (!Pv4.new) memh(Rs32+#u6:1)=Rt32*/ + 0xffe00004, + 0x46400000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerhnewf_abs*/ + /*if (!Pv4) memh(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa00884, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhnewfnew_abs*/ + /*if (!Pv4.new) memh(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa02884, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhnewfnew_io*/ + /*if (!Pv4.new) memh(Rs32+#u6:1)=Nt8.new*/ + 0xffe01804, + 0x46a00800, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerhnewt_abs*/ + /*if (Pv4) memh(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa00880, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhnewtnew_abs*/ + /*if (Pv4.new) memh(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa02880, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhnewtnew_io*/ + /*if (Pv4.new) memh(Rs32+#u6:1)=Nt8.new*/ + 0xffe01804, + 0x42a00800, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerht_abs*/ + /*if (Pv4) memh(#u6)=Rt32*/ + 0xffe02084, + 0xaf400080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhtnew_abs*/ + /*if (Pv4.new) memh(#u6)=Rt32*/ + 0xffe02084, + 0xaf402080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerhtnew_io*/ + /*if (Pv4.new) memh(Rs32+#u6:1)=Rt32*/ + 0xffe00004, + 0x42400000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerif_abs*/ + /*if (!Pv4) memw(#u6)=Rt32*/ + 0xffe02084, + 0xaf800084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerifnew_abs*/ + /*if (!Pv4.new) memw(#u6)=Rt32*/ + 0xffe02084, + 0xaf802084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerifnew_io*/ + /*if (!Pv4.new) memw(Rs32+#u6:2)=Rt32*/ + 0xffe00004, + 0x46800000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerinewf_abs*/ + /*if (!Pv4) memw(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa01084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerinewfnew_abs*/ + /*if (!Pv4.new) memw(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa03084, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerinewfnew_io*/ + /*if (!Pv4.new) memw(Rs32+#u6:2)=Nt8.new*/ + 0xffe01804, + 0x46a01000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerinewt_abs*/ + /*if (Pv4) memw(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa01080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerinewtnew_abs*/ + /*if (Pv4.new) memw(#u6)=Nt8.new*/ + 0xffe03884, + 0xafa03080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstorerinewtnew_io*/ + /*if (Pv4.new) memw(Rs32+#u6:2)=Nt8.new*/ + 0xffe01804, + 0x42a01000, + 0x000020f8, + 0 }, +{ /*Tag:S4_pstorerit_abs*/ + /*if (Pv4) memw(#u6)=Rt32*/ + 0xffe02084, + 0xaf800080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstoreritnew_abs*/ + /*if (Pv4.new) memw(#u6)=Rt32*/ + 0xffe02084, + 0xaf802080, + 0x00030078, + 0 }, +{ /*Tag:S4_pstoreritnew_io*/ + /*if (Pv4.new) memw(Rs32+#u6:2)=Rt32*/ + 0xffe00004, + 0x42800000, + 0x000020f8, + 0 }, +{ /*Tag:S4_storeirb_io*/ + /*memb(Rs32+#u6:0)=#S8*/ + 0xfe600000, + 0x3c000000, + 0x0000207f, + 0 }, +{ /*Tag:S4_storeirbf_io*/ + /*if (!Pv4) memb(Rs32+#u6:0)=#S6*/ + 0xffe00000, + 0x38800000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirbfnew_io*/ + /*if (!Pv4.new) memb(Rs32+#u6:0)=#S6*/ + 0xffe00000, + 0x39800000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirbt_io*/ + /*if (Pv4) memb(Rs32+#u6:0)=#S6*/ + 0xffe00000, + 0x38000000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirbtnew_io*/ + /*if (Pv4.new) memb(Rs32+#u6:0)=#S6*/ + 0xffe00000, + 0x39000000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirh_io*/ + /*memh(Rs32+#u6:1)=#S8*/ + 0xfe600000, + 0x3c200000, + 0x0000207f, + 0 }, +{ /*Tag:S4_storeirhf_io*/ + /*if (!Pv4) memh(Rs32+#u6:1)=#S6*/ + 0xffe00000, + 0x38a00000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirhfnew_io*/ + /*if (!Pv4.new) memh(Rs32+#u6:1)=#S6*/ + 0xffe00000, + 0x39a00000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirht_io*/ + /*if (Pv4) memh(Rs32+#u6:1)=#S6*/ + 0xffe00000, + 0x38200000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirhtnew_io*/ + /*if (Pv4.new) memh(Rs32+#u6:1)=#S6*/ + 0xffe00000, + 0x39200000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeiri_io*/ + /*memw(Rs32+#u6:2)=#S8*/ + 0xfe600000, + 0x3c400000, + 0x0000207f, + 0 }, +{ /*Tag:S4_storeirif_io*/ + /*if (!Pv4) memw(Rs32+#u6:2)=#S6*/ + 0xffe00000, + 0x38c00000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirifnew_io*/ + /*if (!Pv4.new) memw(Rs32+#u6:2)=#S6*/ + 0xffe00000, + 0x39c00000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeirit_io*/ + /*if (Pv4) memw(Rs32+#u6:2)=#S6*/ + 0xffe00000, + 0x38400000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storeiritnew_io*/ + /*if (Pv4.new) memw(Rs32+#u6:2)=#S6*/ + 0xffe00000, + 0x39400000, + 0x0000201f, + 0 }, +{ /*Tag:S4_storerb_ap*/ + /*memb(Re32=#U6)=Rt32*/ + 0xffe02080, + 0xab000080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerb_ur*/ + /*memb(Ru32<<#u2+#U6)=Rt32*/ + 0xffe00080, + 0xad000080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerbnew_ap*/ + /*memb(Re32=#U6)=Nt8.new*/ + 0xffe03880, + 0xaba00080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerbnew_ur*/ + /*memb(Ru32<<#u2+#U6)=Nt8.new*/ + 0xffe01880, + 0xada00080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerd_ap*/ + /*memd(Re32=#U6)=Rtt32*/ + 0xffe02080, + 0xabc00080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerd_ur*/ + /*memd(Ru32<<#u2+#U6)=Rtt32*/ + 0xffe00080, + 0xadc00080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerf_ap*/ + /*memh(Re32=#U6)=Rt32.h*/ + 0xffe02080, + 0xab600080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerf_ur*/ + /*memh(Ru32<<#u2+#U6)=Rt32.h*/ + 0xffe00080, + 0xad600080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerh_ap*/ + /*memh(Re32=#U6)=Rt32*/ + 0xffe02080, + 0xab400080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerh_ur*/ + /*memh(Ru32<<#u2+#U6)=Rt32*/ + 0xffe00080, + 0xad400080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerhnew_ap*/ + /*memh(Re32=#U6)=Nt8.new*/ + 0xffe03880, + 0xaba00880, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerhnew_ur*/ + /*memh(Ru32<<#u2+#U6)=Nt8.new*/ + 0xffe01880, + 0xada00880, + 0x0000003f, + 0 }, +{ /*Tag:S4_storeri_ap*/ + /*memw(Re32=#U6)=Rt32*/ + 0xffe02080, + 0xab800080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storeri_ur*/ + /*memw(Ru32<<#u2+#U6)=Rt32*/ + 0xffe00080, + 0xad800080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerinew_ap*/ + /*memw(Re32=#U6)=Nt8.new*/ + 0xffe03880, + 0xaba01080, + 0x0000003f, + 0 }, +{ /*Tag:S4_storerinew_ur*/ + /*memw(Ru32<<#u2+#U6)=Nt8.new*/ + 0xffe01880, + 0xada01080, + 0x0000003f, + 0 }, +{ /*Tag:S4_subaddi*/ + /*Rd32=add(Rs32,sub(#s6,Ru32))*/ + 0xff800000, + 0xdb800000, + 0x006020e0, + 0 }, +{ /*Tag:S4_subi_asl_ri*/ + /*Rx32=sub(#u8,asl(Rx32,#U5))*/ + 0xff000016, + 0xde000006, + 0x00e020e8, + 0 }, +{ /*Tag:S4_subi_lsr_ri*/ + /*Rx32=sub(#u8,lsr(Rx32,#U5))*/ + 0xff000016, + 0xde000016, + 0x00e020e8, + 0 }, +{ /*Tag:SA1_addi*/ + /*Rx16=add(Rx16,#s7)*/ + 0xf8002000, + 0x20002000, + 0x07f00000, + 1 }, +{ /*Tag:SA1_addi*/ + /*Rx16=add(Rx16,#s7)*/ + 0xf8002000, + 0x40000000, + 0x07f00000, + 1 }, +{ /*Tag:SA1_addi*/ + /*Rx16=add(Rx16,#s7)*/ + 0xf8002000, + 0x40002000, + 0x07f00000, + 1 }, +{ /*Tag:SA1_addi*/ + /*Rx16=add(Rx16,#s7)*/ + 0xf8002000, + 0x60000000, + 0x07f00000, + 1 }, +{ /*Tag:SA1_addi*/ + /*Rx16=add(Rx16,#s7)*/ + 0xf8002000, + 0x60002000, + 0x07f00000, + 1 }, +{ /*Tag:SA1_seti*/ + /*Rd16=#u6*/ + 0xfc002000, + 0x28002000, + 0x03f00000, + 1 }, +{ /*Tag:SA1_seti*/ + /*Rd16=#u6*/ + 0xfc002000, + 0x48000000, + 0x03f00000, + 1 }, +{ /*Tag:SA1_seti*/ + /*Rd16=#u6*/ + 0xfc002000, + 0x48002000, + 0x03f00000, + 1 }, +{ /*Tag:SA1_seti*/ + /*Rd16=#u6*/ + 0xfc002000, + 0x68000000, + 0x03f00000, + 1 }, +{ /*Tag:SA1_seti*/ + /*Rd16=#u6*/ + 0xfc002000, + 0x68002000, + 0x03f00000, + 1 }, +{ /*Tag:dup_A2_addi*/ + /*Rd32=add(Rs32,#s16)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_A2_andir*/ + /*Rd32=and(Rs32,#s10)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_A2_combineii*/ + /*Rdd32=combine(#s8,#S8)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_A2_tfrsi*/ + /*Rd32=#s16*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_A4_combineii*/ + /*Rdd32=combine(#s8,#U6)*/ + 0x00000000, + 0x00000000, + 0x00002404, + 0 }, +{ /*Tag:dup_A4_combineir*/ + /*Rdd32=combine(#s8,Rs32)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_A4_combineri*/ + /*Rdd32=combine(Rs32,#s8)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_C2_cmoveif*/ + /*if (!Pu4) Rd32=#s12*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_C2_cmoveit*/ + /*if (Pu4) Rd32=#s12*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_C2_cmovenewif*/ + /*if (!Pu4.new) Rd32=#s12*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_C2_cmovenewit*/ + /*if (Pu4.new) Rd32=#s12*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_C2_cmpeqi*/ + /*Pd4=cmp.eq(Rs32,#s10)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadrb_io*/ + /*Rd32=memb(Rs32+#s11:0)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadrd_io*/ + /*Rdd32=memd(Rs32+#s11:3)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadrh_io*/ + /*Rd32=memh(Rs32+#s11:1)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadri_io*/ + /*Rd32=memw(Rs32+#s11:2)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadrub_io*/ + /*Rd32=memub(Rs32+#s11:0)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_L2_loadruh_io*/ + /*Rd32=memuh(Rs32+#s11:1)*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_S2_storerb_io*/ + /*memb(Rs32+#s11:0)=Rt32*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_S2_storerd_io*/ + /*memd(Rs32+#s11:3)=Rtt32*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_S2_storerh_io*/ + /*memh(Rs32+#s11:1)=Rt32*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_S2_storeri_io*/ + /*memw(Rs32+#s11:2)=Rt32*/ + 0x00000000, + 0x00000000, + 0x00000000, + 0 }, +{ /*Tag:dup_S4_storeirb_io*/ + /*memb(Rs32+#u6:0)=#S8*/ + 0x00000000, + 0x00000000, + 0x00002404, + 0 }, +{ /*Tag:dup_S4_storeiri_io*/ + /*memw(Rs32+#u6:2)=#S8*/ + 0x00000000, + 0x00000000, + 0x00002404, + 0 } +}; +// clang-format off + +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H diff --git a/llvm/lib/Target/Hexagon/HexagonDepOperands.td b/llvm/lib/Target/Hexagon/HexagonDepOperands.td index 8a94d96522ccc..6ef668d307643 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepOperands.td +++ b/llvm/lib/Target/Hexagon/HexagonDepOperands.td @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// multiclass ImmOpPred<code pred, ValueType vt = i32> { @@ -13,120 +13,120 @@ multiclass ImmOpPred<code pred, ValueType vt = i32> { def _timm : PatLeaf<(vt timm), pred>; } -def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } -defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; -def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; } -def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; } -defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>; -def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } -def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; -def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } -defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; -def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } -def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; +def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; } +defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; } def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; } defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>; +def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } +def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; +def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } +def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; +def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } +def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; } def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>; -def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } -def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; -def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } -def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; +def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } +def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; +def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } +def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; +def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } +def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; +def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; } +def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>; +def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; } def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>; -def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } -def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; -def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } -defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; -def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } -def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; -def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } -def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; -def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; } -def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>; +def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; +def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } +defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; } def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; } defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>; -def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } -defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; +def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } +defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; } def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; } defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } +defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; +def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; } +defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>; +def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } +defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; +def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } +def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; +def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } +def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; +def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } +def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; +def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } +def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; +def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } +def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } +def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; +def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } +def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; +def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } +def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; } def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>; def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; } def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; } defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>; -def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } -def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; -def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; } -defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; -def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } -def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } -defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; -def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; } -def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>; -def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } -def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; -def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } -defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; -def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } -def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; } def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>; +def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } +def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; +def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } +def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; +def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } +def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; } def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>; -def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } -def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; -def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } -def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; -def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } -def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; -def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } -defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; -def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } -def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; -def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } -def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; -def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } -defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; -def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } -defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; -def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } -def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; -def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } -def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; +def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } +defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; +def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } +defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; +def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; } +def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h b/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h index b6be74f848bb0..dba39232433d0 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h +++ b/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h @@ -5,137 +5,147 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -#ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H -#define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H #include "HexagonInstrInfo.h" namespace llvm { -inline bool is_TC3x(unsigned SchedClass) { +inline bool is_TC1(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_05d3a09b: - case Hexagon::Sched::tc_0d8f5752: - case Hexagon::Sched::tc_13bfbcf9: - case Hexagon::Sched::tc_174516e8: - case Hexagon::Sched::tc_1a2fd869: - case Hexagon::Sched::tc_1c4528a2: - case Hexagon::Sched::tc_32779c6f: - case Hexagon::Sched::tc_5b54b33f: - case Hexagon::Sched::tc_6b25e783: - case Hexagon::Sched::tc_76851da1: - case Hexagon::Sched::tc_9debc299: - case Hexagon::Sched::tc_a9d88b22: - case Hexagon::Sched::tc_bafaade3: - case Hexagon::Sched::tc_bcf98408: - case Hexagon::Sched::tc_bdceeac1: - case Hexagon::Sched::tc_c8ce0b5c: - case Hexagon::Sched::tc_d1aa9eaa: - case Hexagon::Sched::tc_d773585a: - case Hexagon::Sched::tc_df3319ed: + case Hexagon::Sched::tc_112d30d6: + case Hexagon::Sched::tc_151bf368: + case Hexagon::Sched::tc_1c2c7a4a: + case Hexagon::Sched::tc_1d41f8b7: + case Hexagon::Sched::tc_23708a21: + case Hexagon::Sched::tc_24f426ab: + case Hexagon::Sched::tc_2f573607: + case Hexagon::Sched::tc_388f9897: + case Hexagon::Sched::tc_3d14a17b: + case Hexagon::Sched::tc_3fbf1042: + case Hexagon::Sched::tc_407e96f9: + case Hexagon::Sched::tc_42ff66ba: + case Hexagon::Sched::tc_4a55d03c: + case Hexagon::Sched::tc_5502c366: + case Hexagon::Sched::tc_55b33fda: + case Hexagon::Sched::tc_56a124a7: + case Hexagon::Sched::tc_57a55b54: + case Hexagon::Sched::tc_59a7822c: + case Hexagon::Sched::tc_5b347363: + case Hexagon::Sched::tc_5da50c4b: + case Hexagon::Sched::tc_60e324ff: + case Hexagon::Sched::tc_651cbe02: + case Hexagon::Sched::tc_6fc5dbea: + case Hexagon::Sched::tc_711c805f: + case Hexagon::Sched::tc_713b66bf: + case Hexagon::Sched::tc_9124c04f: + case Hexagon::Sched::tc_9c52f549: + case Hexagon::Sched::tc_9e27f2f9: + case Hexagon::Sched::tc_9f6cd987: + case Hexagon::Sched::tc_a1297125: + case Hexagon::Sched::tc_a7a13fac: + case Hexagon::Sched::tc_b837298f: + case Hexagon::Sched::tc_c57d9f39: + case Hexagon::Sched::tc_d33e5eee: + case Hexagon::Sched::tc_decdde8a: + case Hexagon::Sched::tc_ed03645c: + case Hexagon::Sched::tc_eeda4109: + case Hexagon::Sched::tc_ef921005: + case Hexagon::Sched::tc_f999c66e: return true; default: return false; } } -inline bool is_TC2early(unsigned SchedClass) { +inline bool is_TC2(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_b4407292: - case Hexagon::Sched::tc_fc3999b4: + case Hexagon::Sched::tc_01d44cb2: + case Hexagon::Sched::tc_0dfac0a7: + case Hexagon::Sched::tc_1fcb8495: + case Hexagon::Sched::tc_20131976: + case Hexagon::Sched::tc_2c13e7f5: + case Hexagon::Sched::tc_3edca78f: + case Hexagon::Sched::tc_5e4cf0e8: + case Hexagon::Sched::tc_65279839: + case Hexagon::Sched::tc_7401744f: + case Hexagon::Sched::tc_84a7500d: + case Hexagon::Sched::tc_8a825db2: + case Hexagon::Sched::tc_8b5bd4f5: + case Hexagon::Sched::tc_95a33176: + case Hexagon::Sched::tc_9b3c0462: + case Hexagon::Sched::tc_a08b630b: + case Hexagon::Sched::tc_a4e22bbd: + case Hexagon::Sched::tc_a7bdb22c: + case Hexagon::Sched::tc_bb831a7c: + case Hexagon::Sched::tc_c20701f0: + case Hexagon::Sched::tc_d3632d88: + case Hexagon::Sched::tc_d61dfdc3: + case Hexagon::Sched::tc_e3d699e3: + case Hexagon::Sched::tc_f098b237: + case Hexagon::Sched::tc_f34c1c21: return true; default: return false; } } -inline bool is_TC4x(unsigned SchedClass) { +inline bool is_TC3x(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_2f7c551d: - case Hexagon::Sched::tc_2ff964b4: - case Hexagon::Sched::tc_3a867367: - case Hexagon::Sched::tc_3b470976: - case Hexagon::Sched::tc_4560740b: - case Hexagon::Sched::tc_a58fd5cc: - case Hexagon::Sched::tc_b8bffe55: + case Hexagon::Sched::tc_01e1be3b: + case Hexagon::Sched::tc_1248597c: + case Hexagon::Sched::tc_197dce51: + case Hexagon::Sched::tc_28e55c6f: + case Hexagon::Sched::tc_2c3e17fc: + case Hexagon::Sched::tc_38382228: + case Hexagon::Sched::tc_38e0bae9: + case Hexagon::Sched::tc_4abdbdc6: + case Hexagon::Sched::tc_503ce0f3: + case Hexagon::Sched::tc_556f6577: + case Hexagon::Sched::tc_5a4b5e58: + case Hexagon::Sched::tc_6ae3426b: + case Hexagon::Sched::tc_6d861a95: + case Hexagon::Sched::tc_788b1d09: + case Hexagon::Sched::tc_7f8ae742: + case Hexagon::Sched::tc_9406230a: + case Hexagon::Sched::tc_a154b476: + case Hexagon::Sched::tc_a38c45dc: + case Hexagon::Sched::tc_c21d7447: + case Hexagon::Sched::tc_d7718fbe: + case Hexagon::Sched::tc_db596beb: + case Hexagon::Sched::tc_f0cdeccf: + case Hexagon::Sched::tc_fae9dfa5: return true; default: return false; } } -inline bool is_TC2(unsigned SchedClass) { +inline bool is_TC2early(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_002cb246: - case Hexagon::Sched::tc_14b5c689: - case Hexagon::Sched::tc_1c80410a: - case Hexagon::Sched::tc_4414d8b1: - case Hexagon::Sched::tc_6132ba3d: - case Hexagon::Sched::tc_61830035: - case Hexagon::Sched::tc_679309b8: - case Hexagon::Sched::tc_703e822c: - case Hexagon::Sched::tc_779080bf: - case Hexagon::Sched::tc_784490da: - case Hexagon::Sched::tc_88b4f13d: - case Hexagon::Sched::tc_9461ff31: - case Hexagon::Sched::tc_9e313203: - case Hexagon::Sched::tc_a813cf9a: - case Hexagon::Sched::tc_bfec0f01: - case Hexagon::Sched::tc_cf8126ae: - case Hexagon::Sched::tc_d08ee0f4: - case Hexagon::Sched::tc_e4a7f9f0: - case Hexagon::Sched::tc_f429765c: - case Hexagon::Sched::tc_f675fee8: - case Hexagon::Sched::tc_f9058dd7: + case Hexagon::Sched::tc_45f9d1be: + case Hexagon::Sched::tc_a4ee89db: return true; default: return false; } } -inline bool is_TC1(unsigned SchedClass) { +inline bool is_TC4x(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_0663f615: - case Hexagon::Sched::tc_0a705168: - case Hexagon::Sched::tc_0ae0825c: - case Hexagon::Sched::tc_1b6f7cec: - case Hexagon::Sched::tc_1fc97744: - case Hexagon::Sched::tc_20cdee80: - case Hexagon::Sched::tc_2332b92e: - case Hexagon::Sched::tc_2eabeebe: - case Hexagon::Sched::tc_3d495a39: - case Hexagon::Sched::tc_4c5ba658: - case Hexagon::Sched::tc_56336eb0: - case Hexagon::Sched::tc_56f114f4: - case Hexagon::Sched::tc_57890846: - case Hexagon::Sched::tc_5a2711e5: - case Hexagon::Sched::tc_5b7c0967: - case Hexagon::Sched::tc_640086b5: - case Hexagon::Sched::tc_643b4717: - case Hexagon::Sched::tc_85c9c08f: - case Hexagon::Sched::tc_85d5d03f: - case Hexagon::Sched::tc_862b3e70: - case Hexagon::Sched::tc_946df596: - case Hexagon::Sched::tc_9c3ecd83: - case Hexagon::Sched::tc_9fc3dae0: - case Hexagon::Sched::tc_a1123dda: - case Hexagon::Sched::tc_a1c00888: - case Hexagon::Sched::tc_ae53734a: - case Hexagon::Sched::tc_b31c2e97: - case Hexagon::Sched::tc_b4b5c03a: - case Hexagon::Sched::tc_b51dc29a: - case Hexagon::Sched::tc_cd374165: - case Hexagon::Sched::tc_cfd8378a: - case Hexagon::Sched::tc_d5b7b0c1: - case Hexagon::Sched::tc_d9d43ecb: - case Hexagon::Sched::tc_db2bce9c: - case Hexagon::Sched::tc_de4df740: - case Hexagon::Sched::tc_de554571: - case Hexagon::Sched::tc_e78647bd: + case Hexagon::Sched::tc_02fe1c65: + case Hexagon::Sched::tc_0a195f2c: + case Hexagon::Sched::tc_7f7f45f5: + case Hexagon::Sched::tc_9783714b: + case Hexagon::Sched::tc_9e72dc89: + case Hexagon::Sched::tc_9edb7c77: + case Hexagon::Sched::tc_f0e8e832: + case Hexagon::Sched::tc_f7569068: return true; default: return false; @@ -143,4 +153,4 @@ inline bool is_TC1(unsigned SchedClass) { } } // namespace llvm -#endif
\ No newline at end of file +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index d0285a7aa3776..a431af17e6d08 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -1017,18 +1017,20 @@ void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB, PredB->removeSuccessor(SuccB); PredB->splice(PredB->end(), SuccB, SuccB->begin(), SuccB->end()); PredB->transferSuccessorsAndUpdatePHIs(SuccB); + MachineBasicBlock *OldLayoutSuccessor = SuccB->getNextNode(); removeBlock(SuccB); if (!TermOk) - PredB->updateTerminator(); + PredB->updateTerminator(OldLayoutSuccessor); } void HexagonEarlyIfConversion::simplifyFlowGraph(const FlowPattern &FP) { + MachineBasicBlock *OldLayoutSuccessor = FP.SplitB->getNextNode(); if (FP.TrueB) removeBlock(FP.TrueB); if (FP.FalseB) removeBlock(FP.FalseB); - FP.SplitB->updateTerminator(); + FP.SplitB->updateTerminator(OldLayoutSuccessor); if (FP.SplitB->succ_size() != 1) return; diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index d21de8ccb5ab1..97a4b351af669 100644 --- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -20,7 +20,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/Support/MathExtras.h" -#include "llvm/PassSupport.h" +#include "llvm/Pass.h" using namespace llvm; @@ -114,7 +114,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) { // First pass - compute the offset of each basic block. for (const MachineBasicBlock &MBB : MF) { - if (MBB.getAlignment() != Align::None()) { + if (MBB.getAlignment() != Align(1)) { // Although we don't know the exact layout of the final code, we need // to account for alignment padding somehow. This heuristic pads each // aligned basic block according to the alignment value. diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index aff8e57b0a940..010b7171ce172 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -261,20 +261,20 @@ static unsigned getMax32BitSubRegister(unsigned Reg, } /// Returns the callee saved register with the largest id in the vector. -static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI, +static unsigned getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo &TRI) { - static_assert(Hexagon::R1 > 0, - "Assume physical registers are encoded as positive integers"); - if (CSI.empty()) - return 0; - - unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI); - for (unsigned I = 1, E = CSI.size(); I < E; ++I) { - unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI); - if (Reg > Max) - Max = Reg; - } - return Max; + static_assert(Hexagon::R1 > 0, + "Assume physical registers are encoded as positive integers"); + if (CSI.empty()) + return 0; + + unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI); + for (unsigned I = 1, E = CSI.size(); I < E; ++I) { + unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI); + if (Reg > Max) + Max = Reg; + } + return Max; } /// Checks if the basic block contains any instruction that needs a stack @@ -395,6 +395,9 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const { static unsigned ShrinkCounter = 0; + if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() && + MF.getFunction().isVarArg()) + return; if (ShrinkLimit.getPosition()) { if (ShrinkCounter >= ShrinkLimit) return; @@ -588,7 +591,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, auto &HII = *HST.getInstrInfo(); auto &HRI = *HST.getRegisterInfo(); - unsigned MaxAlign = std::max(MFI.getMaxAlignment(), getStackAlignment()); + Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign()); // Calculate the total stack frame size. // Get the number of bytes to allocate from the FrameInfo. @@ -600,7 +603,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign); MFI.setStackSize(FrameSize); - bool AlignStack = (MaxAlign > getStackAlignment()); + bool AlignStack = (MaxAlign > getStackAlign()); // Get the number of bytes to allocate from the FrameInfo. unsigned NumBytes = MFI.getStackSize(); @@ -622,12 +625,124 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, DebugLoc dl = MBB.findDebugLoc(InsertPt); + if (MF.getFunction().isVarArg() && + MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) { + // Calculate the size of register saved area. + int NumVarArgRegs = 6 - FirstVarArgSavedReg; + int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) + ? NumVarArgRegs * 4 + : NumVarArgRegs * 4 + 4; + if (RegisterSavedAreaSizePlusPadding > 0) { + // Decrement the stack pointer by size of register saved area plus + // padding if any. + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) + .addReg(SP) + .addImm(-RegisterSavedAreaSizePlusPadding) + .setMIFlag(MachineInstr::FrameSetup); + + int NumBytes = 0; + // Copy all the named arguments below register saved area. + auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>(); + for (int i = HMFI.getFirstNamedArgFrameIndex(), + e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) { + uint64_t ObjSize = MFI.getObjectSize(i); + Align ObjAlign = MFI.getObjectAlign(i); + + // Determine the kind of load/store that should be used. + unsigned LDOpc, STOpc; + uint64_t OpcodeChecker = ObjAlign.value(); + + // Handle cases where alignment of an object is > its size. + if (ObjAlign > ObjSize) { + if (ObjSize <= 1) + OpcodeChecker = 1; + else if (ObjSize <= 2) + OpcodeChecker = 2; + else if (ObjSize <= 4) + OpcodeChecker = 4; + else if (ObjSize > 4) + OpcodeChecker = 8; + } + + switch (OpcodeChecker) { + case 1: + LDOpc = Hexagon::L2_loadrb_io; + STOpc = Hexagon::S2_storerb_io; + break; + case 2: + LDOpc = Hexagon::L2_loadrh_io; + STOpc = Hexagon::S2_storerh_io; + break; + case 4: + LDOpc = Hexagon::L2_loadri_io; + STOpc = Hexagon::S2_storeri_io; + break; + case 8: + default: + LDOpc = Hexagon::L2_loadrd_io; + STOpc = Hexagon::S2_storerd_io; + break; + } + + unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3 + : Hexagon::R6; + int LoadStoreCount = ObjSize / OpcodeChecker; + + if (ObjSize % OpcodeChecker) + ++LoadStoreCount; + + // Get the start location of the load. NumBytes is basically the + // offset from the stack pointer of previous function, which would be + // the caller in this case, as this function has variable argument + // list. + if (NumBytes != 0) + NumBytes = alignTo(NumBytes, ObjAlign); + + int Count = 0; + while (Count < LoadStoreCount) { + // Load the value of the named argument on stack. + BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed) + .addReg(SP) + .addImm(RegisterSavedAreaSizePlusPadding + + ObjAlign.value() * Count + NumBytes) + .setMIFlag(MachineInstr::FrameSetup); + + // Store it below the register saved area plus padding. + BuildMI(MBB, InsertPt, dl, HII.get(STOpc)) + .addReg(SP) + .addImm(ObjAlign.value() * Count + NumBytes) + .addReg(RegUsed) + .setMIFlag(MachineInstr::FrameSetup); + + Count++; + } + NumBytes += MFI.getObjectSize(i); + } + + // Make NumBytes 8 byte aligned + NumBytes = alignTo(NumBytes, 8); + + // If the number of registers having variable arguments is odd, + // leave 4 bytes of padding to get to the location where first + // variable argument which was passed through register was copied. + NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4; + + for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) { + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io)) + .addReg(SP) + .addImm(NumBytes + 4 * i) + .addReg(Hexagon::R0 + j) + .setMIFlag(MachineInstr::FrameSetup); + } + } + } + if (hasFP(MF)) { insertAllocframe(MBB, InsertPt, NumBytes); if (AlignStack) { BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP) .addReg(SP) - .addImm(-int64_t(MaxAlign)); + .addImm(-int64_t(MaxAlign.value())); } // If the stack-checking is enabled, and we spilled the callee-saved // registers inline (i.e. did not use a spill function), then call @@ -655,7 +770,16 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { if (!hasFP(MF)) { MachineFrameInfo &MFI = MF.getFrameInfo(); - if (unsigned NumBytes = MFI.getStackSize()) { + unsigned NumBytes = MFI.getStackSize(); + if (MF.getFunction().isVarArg() && + MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) { + // On Hexagon Linux, deallocate the stack for the register saved area. + int NumVarArgRegs = 6 - FirstVarArgSavedReg; + int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ? + (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4); + NumBytes += RegisterSavedAreaSizePlusPadding; + } + if (NumBytes) { BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) .addReg(SP) .addImm(NumBytes); @@ -710,24 +834,49 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { NeedsDeallocframe = false; } - if (!NeedsDeallocframe) - return; - // If the returning instruction is PS_jmpret, replace it with dealloc_return, - // otherwise just add deallocframe. The function could be returning via a - // tail call. - if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) { - BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) + if (!MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() || + !MF.getFunction().isVarArg()) { + if (!NeedsDeallocframe) + return; + // If the returning instruction is PS_jmpret, replace it with + // dealloc_return, otherwise just add deallocframe. The function + // could be returning via a tail call. + if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) { + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) .addDef(Hexagon::D15) .addReg(Hexagon::R30); - return; - } - unsigned NewOpc = Hexagon::L4_return; - MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc)) + return; + } + unsigned NewOpc = Hexagon::L4_return; + MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc)) .addDef(Hexagon::D15) .addReg(Hexagon::R30); - // Transfer the function live-out registers. - NewI->copyImplicitOps(MF, *RetI); - MBB.erase(RetI); + // Transfer the function live-out registers. + NewI->copyImplicitOps(MF, *RetI); + MBB.erase(RetI); + } else { + // L2_deallocframe instruction after it. + // Calculate the size of register saved area. + int NumVarArgRegs = 6 - FirstVarArgSavedReg; + int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ? + (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4); + + MachineBasicBlock::iterator Term = MBB.getFirstTerminator(); + MachineBasicBlock::iterator I = (Term == MBB.begin()) ? MBB.end() + : std::prev(Term); + if (I == MBB.end() || + (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT && + I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC && + I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 && + I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC)) + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) + .addDef(Hexagon::D15) + .addReg(Hexagon::R30); + if (RegisterSavedAreaSizePlusPadding != 0) + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP) + .addReg(SP) + .addImm(RegisterSavedAreaSizePlusPadding); + } } void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, @@ -744,7 +893,7 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, // Create a dummy memory operand to avoid allocframe from being treated as // a volatile memory reference. auto *MMO = MF.getMachineMemOperand(MachinePointerInfo::getStack(MF, 0), - MachineMemOperand::MOStore, 4, 4); + MachineMemOperand::MOStore, 4, Align(4)); DebugLoc dl = MBB.findDebugLoc(InsertPt); unsigned SP = HRI.getStackRegister(); @@ -907,9 +1056,9 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB, // | +-- Old SP (before allocframe) // +-- New FP (after allocframe) // - // MCCFIInstruction::createDefCfa subtracts the offset from the register. + // MCCFIInstruction::cfiDefCfa adds the offset from the register. // MCCFIInstruction::createOffset takes the offset without sign change. - auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8); + auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8); BuildMI(MBB, At, DL, CFID) .addCFIIndex(MF.addFrameInst(DefCfa)); // R31 (return addr) = CFA - 4 @@ -954,7 +1103,7 @@ void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB, // Instead, get the offset (relative to the FP) directly. Offset = MFI.getObjectOffset(F->getFrameIdx()); } else { - unsigned FrameReg; + Register FrameReg; Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg); } // Subtract 8 to make room for R30 and R31, which are added above. @@ -1108,7 +1257,8 @@ static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, } int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, unsigned &FrameReg) const { + int FI, + Register &FrameReg) const { auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); @@ -1119,9 +1269,9 @@ int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>(); unsigned FrameSize = MFI.getStackSize(); - unsigned SP = HRI.getStackRegister(); - unsigned FP = HRI.getFrameRegister(); - unsigned AP = HMFI.getStackAlignBasePhysReg(); + Register SP = HRI.getStackRegister(); + Register FP = HRI.getFrameRegister(); + Register AP = HMFI.getStackAlignBasePhysReg(); // It may happen that AP will be absent even HasAlloca && HasExtraAlign // is true. HasExtraAlign may be set because of vector spills, without // aligned locals or aligned outgoing function arguments. Since vector @@ -1358,7 +1508,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized( // via AP, which may not be available at the particular place in the program. MachineFrameInfo &MFI = MF.getFrameInfo(); bool HasAlloca = MFI.hasVarSizedObjects(); - bool NeedsAlign = (MFI.getMaxAlignment() > getStackAlignment()); + bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign()); if (!HasAlloca || !NeedsAlign) return; @@ -1371,8 +1521,8 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized( unsigned S = MFI.getObjectSize(i); // Reduce the alignment to at most 8. This will require unaligned vector // stores if they happen here. - unsigned A = std::max(MFI.getObjectAlignment(i), 8U); - MFI.setObjectAlignment(i, 8); + Align A = std::max(MFI.getObjectAlign(i), Align(8)); + MFI.setObjectAlignment(i, Align(8)); LFS = alignTo(LFS+S, A); MFI.mapLocalFrameObject(i, -static_cast<int64_t>(LFS)); DealignSlots.insert(i); @@ -1398,12 +1548,11 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized( if (auto *FS = dyn_cast_or_null<FixedStackPseudoSourceValue>(PV)) { int FI = FS->getFrameIndex(); if (DealignSlots.count(FI)) { - unsigned A = MFI.getObjectAlignment(FI); - auto *NewMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), - MMO->getFlags(), MMO->getSize(), A, - MMO->getAAInfo(), MMO->getRanges(), - MMO->getSyncScopeID(), MMO->getOrdering(), - MMO->getFailureOrdering()); + auto *NewMMO = MF.getMachineMemOperand( + MMO->getPointerInfo(), MMO->getFlags(), MMO->getSize(), + MFI.getObjectAlign(FI), MMO->getAAInfo(), MMO->getRanges(), + MMO->getSyncScopeID(), MMO->getOrdering(), + MMO->getFailureOrdering()); new_memops.push_back(NewMMO); KeepOld = false; continue; @@ -1562,9 +1711,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); unsigned Size = TRI->getSpillSize(*RC); int Off = MinOffset - Size; - unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment()); - assert(isPowerOf2_32(Align)); - Off &= -Align; + Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign()); + Off &= -Alignment.value(); int FI = MFI.CreateFixedSpillStackObject(Size, Off); MinOffset = std::min(MinOffset, Off); CSI.push_back(CalleeSavedInfo(R, FI)); @@ -1787,11 +1935,11 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, bool NeedsAligna = needsAligna(MF); unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); - unsigned HasAlign = MFI.getObjectAlignment(FI); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); + Align HasAlign = MFI.getObjectAlign(FI); unsigned StoreOpc; - auto UseAligned = [&] (unsigned NeedAlign, unsigned HasAlign) { + auto UseAligned = [&](Align NeedAlign, Align HasAlign) { return !NeedsAligna && (NeedAlign <= HasAlign); }; @@ -1839,11 +1987,11 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, bool NeedsAligna = needsAligna(MF); unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); - unsigned HasAlign = MFI.getObjectAlignment(FI); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); + Align HasAlign = MFI.getObjectAlign(FI); unsigned LoadOpc; - auto UseAligned = [&] (unsigned NeedAlign, unsigned HasAlign) { + auto UseAligned = [&](Align NeedAlign, Align HasAlign) { return !NeedsAligna && (NeedAlign <= HasAlign); }; @@ -1883,8 +2031,8 @@ bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B, bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); - unsigned HasAlign = MFI.getObjectAlignment(FI); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); + Align HasAlign = MFI.getObjectAlign(FI); bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign); unsigned StoreOpc = UseAligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai; @@ -1913,8 +2061,8 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, Register DstR = MI->getOperand(0).getReg(); int FI = MI->getOperand(1).getIndex(); - unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); - unsigned HasAlign = MFI.getObjectAlignment(FI); + Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); + Align HasAlign = MFI.getObjectAlign(FI); bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign); unsigned LoadOpc = UseAligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai; @@ -2016,7 +2164,8 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, Num = 2; // Vector predicate spills also need a vector register. break; } - unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC); + unsigned S = HRI.getSpillSize(*RC); + Align A = HRI.getSpillAlign(*RC); for (unsigned i = 0; i < Num; i++) { int NewFI = MFI.CreateSpillStackObject(S, A); RS->addScavengingFrameIndex(NewFI); @@ -2473,6 +2622,8 @@ void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, /// checks are performed, which may still lead to the inline code. bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const { + if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) + return true; if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn()) return true; if (!hasFP(MF)) diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h index 27265dd537949..87d385e1ce3c4 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -29,8 +29,10 @@ class TargetRegisterClass; class HexagonFrameLowering : public TargetFrameLowering { public: + // First register which could possibly hold a variable argument. + int FirstVarArgSavedReg; explicit HexagonFrameLowering() - : TargetFrameLowering(StackGrowsDown, Align(8), 0, Align::None(), true) {} + : TargetFrameLowering(StackGrowsDown, Align(8), 0, Align(1), true) {} // All of the prolog/epilog functionality, including saving and restoring // callee-saved registers is handled in emitPrologue. This is to have the @@ -43,14 +45,17 @@ public: bool enableCalleeSaveSkip(const MachineFunction &MF) const override; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override { + MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override { return true; } - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override { + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override { return true; } @@ -78,7 +83,7 @@ public: } int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; bool hasFP(const MachineFunction &MF) const override; const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) diff --git a/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp b/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp index 342ca21525c5e..d9307190ae169 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp @@ -221,15 +221,16 @@ bool HexagonGenExtract::convert(Instruction *In) { } bool HexagonGenExtract::visitBlock(BasicBlock *B) { + bool Changed = false; + // Depth-first, bottom-up traversal. for (auto *DTN : children<DomTreeNode*>(DT->getNode(B))) - visitBlock(DTN->getBlock()); + Changed |= visitBlock(DTN->getBlock()); // Allow limiting the number of generated extracts for debugging purposes. bool HasCutoff = ExtractCutoff.getPosition(); unsigned Cutoff = ExtractCutoff; - bool Changed = false; BasicBlock::iterator I = std::prev(B->end()), NextI, Begin = B->begin(); while (true) { if (HasCutoff && (ExtractCount >= Cutoff)) diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 1cf1500bc8329..4833935f8d24b 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -467,7 +467,7 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, if (!PredI->isCompare()) return false; - unsigned CmpReg1 = 0, CmpReg2 = 0; + Register CmpReg1, CmpReg2; int CmpImm = 0, CmpMask = 0; bool CmpAnalyzed = TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm); @@ -640,7 +640,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, if (!TB || (FB && TB != Header && FB != Header)) return nullptr; - // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch + // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch // to put imm(0), followed by P in the vector Cond. // If TB is not the header, it means that the "not-taken" path must lead // to the header. @@ -651,7 +651,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, MachineInstr *CondI = MRI->getVRegDef(PredReg); unsigned CondOpc = CondI->getOpcode(); - unsigned CmpReg1 = 0, CmpReg2 = 0; + Register CmpReg1, CmpReg2; int Mask = 0, ImmValue = 0; bool AnalyzedCmp = TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue); @@ -1455,7 +1455,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow( for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); I != E; ++I) { MachineInstr *MI = &*I; - unsigned CmpReg1 = 0, CmpReg2 = 0; + Register CmpReg1, CmpReg2; int CmpMask = 0, CmpValue = 0; if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue)) @@ -1657,7 +1657,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { MachineBasicBlock *TB = nullptr, *FB = nullptr; SmallVector<MachineOperand,2> Cond; - // AnalyzeBranch returns true if it fails to analyze branch. + // analyzeBranch returns true if it fails to analyze branch. bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed || Cond.empty()) return false; @@ -1693,7 +1693,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { // Expecting a predicate register as a condition. It won't be a hardware // predicate register at this point yet, just a vreg. - // HexagonInstrInfo::AnalyzeBranch for negated branches inserts imm(0) + // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0) // into Cond, followed by the predicate register. For non-negated branches // it's just the register. unsigned CSz = Cond.size(); diff --git a/llvm/lib/Target/Hexagon/HexagonIICScalar.td b/llvm/lib/Target/Hexagon/HexagonIICScalar.td index d37cc3a2cc3ef..e9239ab5ad22a 100644 --- a/llvm/lib/Target/Hexagon/HexagonIICScalar.td +++ b/llvm/lib/Target/Hexagon/HexagonIICScalar.td @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // These itinerary class descriptions are based on the instruction timing -// classes as per V62. Curretnly, they are just extracted from +// classes as per V62. Currently, they are just extracted from // HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py. class PseudoItin { diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 9cf5b257a00ab..b4b389a7b9568 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -734,8 +734,8 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) { MachineFrameInfo &MFI = MF->getFrameInfo(); const HexagonFrameLowering *HFI = HST->getFrameLowering(); int FX = cast<FrameIndexSDNode>(N)->getIndex(); - unsigned StkA = HFI->getStackAlignment(); - unsigned MaxA = MFI.getMaxAlignment(); + Align StkA = HFI->getStackAlign(); + Align MaxA = MFI.getMaxAlign(); SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32); SDLoc DL(N); SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); @@ -787,10 +787,18 @@ void HexagonDAGToDAGISel::SelectVAlign(SDNode *N) { MVT::i64, Ops); // Shift right by "(Addr & 0x3) * 8" bytes. + SDNode *C; SDValue M0 = CurDAG->getTargetConstant(0x18, dl, MVT::i32); SDValue M1 = CurDAG->getTargetConstant(0x03, dl, MVT::i32); - SDNode *C = CurDAG->getMachineNode(Hexagon::S4_andi_asl_ri, dl, MVT::i32, - M0, N->getOperand(2), M1); + if (HST->useCompound()) { + C = CurDAG->getMachineNode(Hexagon::S4_andi_asl_ri, dl, MVT::i32, + M0, N->getOperand(2), M1); + } else { + SDNode *T = CurDAG->getMachineNode(Hexagon::S2_asl_i_r, dl, MVT::i32, + N->getOperand(2), M1); + C = CurDAG->getMachineNode(Hexagon::A2_andir, dl, MVT::i32, + SDValue(T, 0), M0); + } SDNode *S = CurDAG->getMachineNode(Hexagon::S2_lsr_r_p, dl, MVT::i64, SDValue(R, 0), SDValue(C, 0)); SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy, @@ -1179,7 +1187,7 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) { Ops[i] = U->getOperand(i); EVT BVT = Ops[I1N].getValueType(); - SDLoc dl(U); + const SDLoc &dl(U); SDValue C0 = DAG.getConstant(0, dl, BVT); SDValue C1 = DAG.getConstant(1, dl, BVT); SDValue If0, If1; @@ -1197,8 +1205,15 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) { Ops[I1N] = C1; If1 = DAG.getNode(UseOpc, dl, UVT, Ops); } - SDValue Sel = DAG.getNode(ISD::SELECT, dl, UVT, OpI1, If1, If0); - DAG.ReplaceAllUsesWith(U, Sel.getNode()); + // We're generating a SELECT way after legalization, so keep the types + // simple. + unsigned UW = UVT.getSizeInBits(); + EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; + SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, + DAG.getBitcast(SVT, If1), + DAG.getBitcast(SVT, If0)); + SDValue Ret = DAG.getBitcast(UVT, Sel); + DAG.ReplaceAllUsesWith(U, Ret.getNode()); } } } @@ -1260,7 +1275,7 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { } } -void HexagonDAGToDAGISel::EmitFunctionEntryCode() { +void HexagonDAGToDAGISel::emitFunctionEntryCode() { auto &HST = MF->getSubtarget<HexagonSubtarget>(); auto &HFI = *HST.getFrameLowering(); if (!HFI.needsAligna(*MF)) @@ -1269,9 +1284,9 @@ void HexagonDAGToDAGISel::EmitFunctionEntryCode() { MachineFrameInfo &MFI = MF->getFrameInfo(); MachineBasicBlock *EntryBB = &MF->front(); unsigned AR = FuncInfo->CreateReg(MVT::i32); - unsigned EntryMaxA = MFI.getMaxAlignment(); + Align EntryMaxA = MFI.getMaxAlign(); BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR) - .addImm(EntryMaxA); + .addImm(EntryMaxA.value()); MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR); } @@ -1281,7 +1296,7 @@ void HexagonDAGToDAGISel::updateAligna() { return; auto *AlignaI = const_cast<MachineInstr*>(HFI.getAlignaInstr(*MF)); assert(AlignaI != nullptr); - unsigned MaxA = MF->getFrameInfo().getMaxAlignment(); + unsigned MaxA = MF->getFrameInfo().getMaxAlign().value(); if (AlignaI->getOperand(1).getImm() < MaxA) AlignaI->getOperand(1).setImm(MaxA); } @@ -1300,28 +1315,28 @@ bool HexagonDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) { } inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) { - return SelectGlobalAddress(N, R, false, 0); + return SelectGlobalAddress(N, R, false, Align(1)); } inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) { - return SelectGlobalAddress(N, R, true, 0); + return SelectGlobalAddress(N, R, true, Align(1)); } inline bool HexagonDAGToDAGISel::SelectAnyImm(SDValue &N, SDValue &R) { - return SelectAnyImmediate(N, R, 0); + return SelectAnyImmediate(N, R, Align(1)); } inline bool HexagonDAGToDAGISel::SelectAnyImm0(SDValue &N, SDValue &R) { - return SelectAnyImmediate(N, R, 0); + return SelectAnyImmediate(N, R, Align(1)); } inline bool HexagonDAGToDAGISel::SelectAnyImm1(SDValue &N, SDValue &R) { - return SelectAnyImmediate(N, R, 1); + return SelectAnyImmediate(N, R, Align(2)); } inline bool HexagonDAGToDAGISel::SelectAnyImm2(SDValue &N, SDValue &R) { - return SelectAnyImmediate(N, R, 2); + return SelectAnyImmediate(N, R, Align(4)); } inline bool HexagonDAGToDAGISel::SelectAnyImm3(SDValue &N, SDValue &R) { - return SelectAnyImmediate(N, R, 3); + return SelectAnyImmediate(N, R, Align(8)); } inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) { @@ -1333,17 +1348,13 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) { } bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, - uint32_t LogAlign) { - auto IsAligned = [LogAlign] (uint64_t V) -> bool { - return alignTo(V, (uint64_t)1 << LogAlign) == V; - }; - + Align Alignment) { switch (N.getOpcode()) { case ISD::Constant: { if (N.getValueType() != MVT::i32) return false; int32_t V = cast<const ConstantSDNode>(N)->getZExtValue(); - if (!IsAligned(V)) + if (!isAligned(Alignment, V)) return false; R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType()); return true; @@ -1351,37 +1362,34 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, case HexagonISD::JT: case HexagonISD::CP: // These are assumed to always be aligned at least 8-byte boundary. - if (LogAlign > 3) + if (Alignment > Align(8)) return false; R = N.getOperand(0); return true; case ISD::ExternalSymbol: // Symbols may be aligned at any boundary. - if (LogAlign > 0) + if (Alignment > Align(1)) return false; R = N; return true; case ISD::BlockAddress: // Block address is always aligned at least 4-byte boundary. - if (LogAlign > 2 || !IsAligned(cast<BlockAddressSDNode>(N)->getOffset())) + if (Alignment > Align(4) || + !isAligned(Alignment, cast<BlockAddressSDNode>(N)->getOffset())) return false; R = N; return true; } - if (SelectGlobalAddress(N, R, false, LogAlign) || - SelectGlobalAddress(N, R, true, LogAlign)) + if (SelectGlobalAddress(N, R, false, Alignment) || + SelectGlobalAddress(N, R, true, Alignment)) return true; return false; } bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R, - bool UseGP, uint32_t LogAlign) { - auto IsAligned = [LogAlign] (uint64_t V) -> bool { - return alignTo(V, (uint64_t)1 << LogAlign) == V; - }; - + bool UseGP, Align Alignment) { switch (N.getOpcode()) { case ISD::ADD: { SDValue N0 = N.getOperand(0); @@ -1392,10 +1400,9 @@ bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R, if (!UseGP && GAOpc != HexagonISD::CONST32) return false; if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) { - SDValue Addr = N0.getOperand(0); - // For the purpose of alignment, sextvalue and zextvalue are the same. - if (!IsAligned(Const->getZExtValue())) + if (!isAligned(Alignment, Const->getZExtValue())) return false; + SDValue Addr = N0.getOperand(0); if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) { if (GA->getOpcode() == ISD::TargetGlobalAddress) { uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 6c77d88033593..1e50385a7b4be 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -25,7 +25,6 @@ namespace llvm { class MachineFunction; class HexagonInstrInfo; class HexagonRegisterInfo; -class HexagonTargetLowering; class HexagonDAGToDAGISel : public SelectionDAGISel { const HexagonSubtarget *HST; @@ -51,7 +50,7 @@ public: return true; } void PreprocessISelDAG() override; - void EmitFunctionEntryCode() override; + void emitFunctionEntryCode() override; void Select(SDNode *N) override; @@ -60,9 +59,8 @@ public: inline bool SelectAddrGP(SDValue &N, SDValue &R); inline bool SelectAnyImm(SDValue &N, SDValue &R); inline bool SelectAnyInt(SDValue &N, SDValue &R); - bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign); - bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, - uint32_t LogAlign); + bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment); + bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment); bool SelectAddrFI(SDValue &N, SDValue &R); bool DetectUseSxtw(SDValue &N, SDValue &R); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 7e143a3494005..c0f92042e5dae 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -1199,7 +1199,7 @@ OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb, ResultStack &Results) { DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';}); MVT ByteTy = getSingleVT(MVT::i8); - MVT BoolTy = MVT::getVectorVT(MVT::i1, 8*HwLen); // XXX + MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen); const SDLoc &dl(Results.InpNode); SDValue B = getVectorConstant(Bytes, dl); Results.push(Hexagon::V6_vd0, ByteTy, {}); @@ -2201,30 +2201,30 @@ void HexagonDAGToDAGISel::SelectHVXDualOutput(SDNode *N) { SDNode *Result; switch (IID) { case Intrinsic::hexagon_V6_vaddcarry: { - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), - N->getOperand(3) }; - SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); + std::array<SDValue, 3> Ops = { + {N->getOperand(1), N->getOperand(2), N->getOperand(3)}}; + SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); break; } case Intrinsic::hexagon_V6_vaddcarry_128B: { - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), - N->getOperand(3) }; - SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); + std::array<SDValue, 3> Ops = { + {N->getOperand(1), N->getOperand(2), N->getOperand(3)}}; + SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); break; } case Intrinsic::hexagon_V6_vsubcarry: { - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), - N->getOperand(3) }; - SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); + std::array<SDValue, 3> Ops = { + {N->getOperand(1), N->getOperand(2), N->getOperand(3)}}; + SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops); break; } case Intrinsic::hexagon_V6_vsubcarry_128B: { - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), - N->getOperand(3) }; - SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); + std::array<SDValue, 3> Ops = { + {N->getOperand(1), N->getOperand(2), N->getOperand(3)}}; + SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops); break; } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index e11ecdc7d035f..768fea639cf9c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -109,6 +109,11 @@ static cl::opt<bool> AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads")); +static cl::opt<bool> + DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden, + cl::init(false), + cl::desc("Disable minimum alignment of 1 for " + "arguments passed by value on stack")); namespace { @@ -167,10 +172,10 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); - return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*isVolatile=*/false, /*AlwaysInline=*/false, - /*isTailCall=*/false, - MachinePointerInfo(), MachinePointerInfo()); + return DAG.getMemcpy( + Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); } bool @@ -387,19 +392,22 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, MachineFrameInfo &MFI = MF.getFrameInfo(); auto PtrVT = getPointerTy(MF.getDataLayout()); - unsigned NumParams = CLI.CS.getInstruction() - ? CLI.CS.getFunctionType()->getNumParams() - : 0; + unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0; if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); + // Linux ABI treats var-arg calls the same way as regular ones. + bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg; + // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(), + HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(), NumParams); if (Subtarget.useHVXOps()) CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX); + else if (DisableArgsMinAlignment) + CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_Legacy); else CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); @@ -429,7 +437,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT); bool NeedsArgAlign = false; - unsigned LargestAlignSeen = 0; + Align LargestAlignSeen; // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; @@ -466,8 +474,8 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, StackPtr.getValueType()); MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); if (ArgAlign) - LargestAlignSeen = std::max(LargestAlignSeen, - (unsigned)VA.getLocVT().getStoreSizeInBits() >> 3); + LargestAlignSeen = std::max( + LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8)); if (Flags.isByVal()) { // The argument is a struct passed by value. According to LLVM, "Arg" // is a pointer. @@ -490,7 +498,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (NeedsArgAlign && Subtarget.hasV60Ops()) { LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); - unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); + Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass)); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); MFI.ensureMaxAlignment(LargestAlignSeen); } @@ -726,7 +734,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, auto &HFI = *Subtarget.getFrameLowering(); // "Zero" means natural stack alignment. if (A == 0) - A = HFI.getStackAlignment(); + A = HFI.getStackAlign().value(); LLVM_DEBUG({ dbgs () << __func__ << " Align: " << A << " Size: "; @@ -750,13 +758,19 @@ SDValue HexagonTargetLowering::LowerFormalArguments( MachineFrameInfo &MFI = MF.getFrameInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); + // Linux ABI treats var-arg calls the same way as regular ones. + bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg; + // Assign locations to all of the incoming arguments. SmallVector<CCValAssign, 16> ArgLocs; - HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(), + HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, + *DAG.getContext(), MF.getFunction().getFunctionType()->getNumParams()); if (Subtarget.useHVXOps()) CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX); + else if (DisableArgsMinAlignment) + CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy); else CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); @@ -766,8 +780,24 @@ SDValue HexagonTargetLowering::LowerFormalArguments( // caller's stack is passed only when the struct size is smaller than (and // equal to) 8 bytes. If not, no address will be passed into callee and // callee return the result direclty through R0/R1. + auto NextSingleReg = [] (const TargetRegisterClass &RC, unsigned Reg) { + switch (RC.getID()) { + case Hexagon::IntRegsRegClassID: + return Reg - Hexagon::R0 + 1; + case Hexagon::DoubleRegsRegClassID: + return (Reg - Hexagon::D0 + 1) * 2; + case Hexagon::HvxVRRegClassID: + return Reg - Hexagon::V0 + 1; + case Hexagon::HvxWRRegClassID: + return (Reg - Hexagon::W0 + 1) * 2; + } + llvm_unreachable("Unexpected register class"); + }; + auto &HFL = const_cast<HexagonFrameLowering&>(*Subtarget.getFrameLowering()); auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>(); + HFL.FirstVarArgSavedReg = 0; + HMFI.setFirstNamedArgFrameIndex(-int(MFI.getNumFixedObjects())); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; @@ -811,6 +841,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments( } InVals.push_back(Copy); MRI.addLiveIn(VA.getLocReg(), VReg); + HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); } else { assert(VA.isMemLoc() && "Argument should be passed in memory"); @@ -838,8 +869,48 @@ SDValue HexagonTargetLowering::LowerFormalArguments( } } + if (IsVarArg && Subtarget.isEnvironmentMusl()) { + for (int i = HFL.FirstVarArgSavedReg; i < 6; i++) + MRI.addLiveIn(Hexagon::R0+i); + } + + if (IsVarArg && Subtarget.isEnvironmentMusl()) { + HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1); + HMFI.setLastNamedArgFrameIndex(-int(MFI.getNumFixedObjects())); + + // Create Frame index for the start of register saved area. + int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg; + bool RequiresPadding = (NumVarArgRegs & 1); + int RegSaveAreaSizePlusPadding = RequiresPadding + ? (NumVarArgRegs + 1) * 4 + : NumVarArgRegs * 4; + + if (RegSaveAreaSizePlusPadding > 0) { + // The offset to saved register area should be 8 byte aligned. + int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset(); + if (!(RegAreaStart % 8)) + RegAreaStart = (RegAreaStart + 7) & -8; - if (IsVarArg) { + int RegSaveAreaFrameIndex = + MFI.CreateFixedObject(RegSaveAreaSizePlusPadding, RegAreaStart, true); + HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex); + + // This will point to the next argument passed via stack. + int Offset = RegAreaStart + RegSaveAreaSizePlusPadding; + int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true); + HMFI.setVarArgsFrameIndex(FI); + } else { + // This will point to the next argument passed via stack, when + // there is no saved register area. + int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset(); + int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true); + HMFI.setRegSavedAreaStartFrameIndex(FI); + HMFI.setVarArgsFrameIndex(FI); + } + } + + + if (IsVarArg && !Subtarget.isEnvironmentMusl()) { // This will point to the next argument passed via stack. int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset(); int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true); @@ -857,8 +928,81 @@ HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>(); SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1), - MachinePointerInfo(SV)); + + if (!Subtarget.isEnvironmentMusl()) { + return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1), + MachinePointerInfo(SV)); + } + auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>(); + auto &HFL = *Subtarget.getFrameLowering(); + SDLoc DL(Op); + SmallVector<SDValue, 8> MemOps; + + // Get frame index of va_list. + SDValue FIN = Op.getOperand(1); + + // If first Vararg register is odd, add 4 bytes to start of + // saved register area to point to the first register location. + // This is because the saved register area has to be 8 byte aligned. + // Incase of an odd start register, there will be 4 bytes of padding in + // the beginning of saved register area. If all registers area used up, + // the following condition will handle it correctly. + SDValue SavedRegAreaStartFrameIndex = + DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32); + + auto PtrVT = getPointerTy(DAG.getDataLayout()); + + if (HFL.FirstVarArgSavedReg & 1) + SavedRegAreaStartFrameIndex = + DAG.getNode(ISD::ADD, DL, PtrVT, + DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), + MVT::i32), + DAG.getIntPtrConstant(4, DL)); + + // Store the saved register area start pointer. + SDValue Store = + DAG.getStore(Op.getOperand(0), DL, + SavedRegAreaStartFrameIndex, + FIN, MachinePointerInfo(SV)); + MemOps.push_back(Store); + + // Store saved register area end pointer. + FIN = DAG.getNode(ISD::ADD, DL, PtrVT, + FIN, DAG.getIntPtrConstant(4, DL)); + Store = DAG.getStore(Op.getOperand(0), DL, + DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(), + PtrVT), + FIN, MachinePointerInfo(SV, 4)); + MemOps.push_back(Store); + + // Store overflow area pointer. + FIN = DAG.getNode(ISD::ADD, DL, PtrVT, + FIN, DAG.getIntPtrConstant(4, DL)); + Store = DAG.getStore(Op.getOperand(0), DL, + DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(), + PtrVT), + FIN, MachinePointerInfo(SV, 8)); + MemOps.push_back(Store); + + return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); +} + +SDValue +HexagonTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { + // Assert that the linux ABI is enabled for the current compilation. + assert(Subtarget.isEnvironmentMusl() && "Linux ABI should be enabled"); + SDValue Chain = Op.getOperand(0); + SDValue DestPtr = Op.getOperand(1); + SDValue SrcPtr = Op.getOperand(2); + const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); + const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); + SDLoc DL(Op); + // Size of the va_list is 12 bytes as it has 3 pointers. Therefore, + // we need to memcopy 12 bytes from va_list to another similar list. + return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr, + DAG.getIntPtrConstant(12, DL), Align(4), + /*isVolatile*/ false, false, false, + MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV)); } SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { @@ -943,57 +1087,40 @@ HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { return SDValue(); } -static Constant *convert_i1_to_i8(const Constant *ConstVal) { - SmallVector<Constant *, 128> NewConst; - const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal); - if (!CV) - return nullptr; - - LLVMContext &Ctx = ConstVal->getContext(); - IRBuilder<> IRB(Ctx); - unsigned NumVectorElements = CV->getNumOperands(); - assert(isPowerOf2_32(NumVectorElements) && - "conversion only supported for pow2 VectorSize!"); - - for (unsigned i = 0; i < NumVectorElements / 8; ++i) { - uint8_t x = 0; - for (unsigned j = 0; j < 8; ++j) { - uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue(); - x |= y << (7 - j); - } - assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!"); - NewConst.push_back(IRB.getInt8(x)); - } - return ConstantVector::get(NewConst); -} - SDValue HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { EVT ValTy = Op.getValueType(); ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op); Constant *CVal = nullptr; bool isVTi1Type = false; - if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) { - Type *CValTy = ConstVal->getType(); - if (CValTy->isVectorTy() && - CValTy->getVectorElementType()->isIntegerTy(1)) { - CVal = convert_i1_to_i8(ConstVal); - isVTi1Type = (CVal != nullptr); + if (auto *CV = dyn_cast<ConstantVector>(CPN->getConstVal())) { + if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) { + IRBuilder<> IRB(CV->getContext()); + SmallVector<Constant*, 128> NewConst; + unsigned VecLen = CV->getNumOperands(); + assert(isPowerOf2_32(VecLen) && + "conversion only supported for pow2 VectorSize"); + for (unsigned i = 0; i < VecLen; ++i) + NewConst.push_back(IRB.getInt8(CV->getOperand(i)->isZeroValue())); + + CVal = ConstantVector::get(NewConst); + isVTi1Type = true; } } - unsigned Align = CPN->getAlignment(); + Align Alignment = CPN->getAlign(); bool IsPositionIndependent = isPositionIndependent(); unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0; unsigned Offset = 0; SDValue T; if (CPN->isMachineConstantPoolEntry()) - T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset, - TF); + T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Alignment, + Offset, TF); else if (isVTi1Type) - T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF); + T = DAG.getTargetConstantPool(CVal, ValTy, Alignment, Offset, TF); else - T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF); + T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Alignment, Offset, + TF); assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && "Inconsistent target flag encountered"); @@ -1375,7 +1502,10 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::VAEND, MVT::Other, Expand); setOperationAction(ISD::VAARG, MVT::Other, Expand); - setOperationAction(ISD::VACOPY, MVT::Other, Expand); + if (Subtarget.isEnvironmentMusl()) + setOperationAction(ISD::VACOPY, MVT::Other, Custom); + else + setOperationAction(ISD::VACOPY, MVT::Other, Expand); setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); @@ -1621,6 +1751,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FADD, MVT::f64, Legal); setOperationAction(ISD::FSUB, MVT::f64, Legal); } + if (Subtarget.hasV67Ops()) { + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); + setOperationAction(ISD::FMUL, MVT::f64, Legal); + } setTargetDAGCombine(ISD::VSELECT); @@ -1855,8 +1990,7 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // The offset value comes through Modifier register. For now, assume the // offset is 0. Info.offset = 0; - Info.align = - MaybeAlign(DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont))); + Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont)); Info.flags = MachineMemOperand::MOLoad; return true; } @@ -2139,13 +2273,16 @@ HexagonTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { const SDLoc &dl(Op); // Handle conversion from i8 to v8i1. - if (ResTy == MVT::v8i1) { - SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV); - SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32); - return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG); + if (InpTy == MVT::i8) { + if (ResTy == MVT::v8i1) { + SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV); + SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32); + return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG); + } + return SDValue(); } - return SDValue(); + return Op; } bool @@ -2779,10 +2916,10 @@ HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) MachineMemOperand *WideMMO = nullptr; if (MachineMemOperand *MMO = LN->getMemOperand()) { MachineFunction &MF = DAG.getMachineFunction(); - WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(), - 2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(), - MMO->getSyncScopeID(), MMO->getOrdering(), - MMO->getFailureOrdering()); + WideMMO = MF.getMachineMemOperand( + MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen, Align(LoadLen), + MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(), + MMO->getOrdering(), MMO->getFailureOrdering()); } SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO); @@ -2928,6 +3065,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); + case ISD::VACOPY: return LowerVACOPY(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); @@ -2946,6 +3084,12 @@ void HexagonTargetLowering::LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { + if (isHvxOperation(N)) { + LowerHvxOperationWrapper(N, Results, DAG); + if (!Results.empty()) + return; + } + // We are only custom-lowering stores to verify the alignment of the // address if it is a compile-time constant. Since a store can be modified // during type-legalization (the value being stored may need legalization), @@ -2959,6 +3103,12 @@ void HexagonTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { + if (isHvxOperation(N)) { + ReplaceHvxNodeResults(N, Results, DAG); + if (!Results.empty()) + return; + } + const SDLoc &dl(N); switch (N->getOpcode()) { case ISD::SRL: @@ -3079,8 +3229,8 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( switch (VT.getSizeInBits()) { default: return {0u, nullptr}; - case 512: - case 1024: + case 64: + case 128: return {0u, &Hexagon::HvxQRRegClass}; } break; @@ -3127,12 +3277,12 @@ bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL, // The type Ty passed here would then be "void". Skip the alignment // checks, but do not return false right away, since that confuses // LSR into crashing. - unsigned A = DL.getABITypeAlignment(Ty); + Align A = DL.getABITypeAlign(Ty); // The base offset must be a multiple of the alignment. - if ((AM.BaseOffs % A) != 0) + if (!isAligned(A, AM.BaseOffs)) return false; // The shifted offset must fit in 11 bits. - if (!isInt<11>(AM.BaseOffs >> Log2_32(A))) + if (!isInt<11>(AM.BaseOffs >> Log2(A))) return false; } @@ -3232,30 +3382,36 @@ bool HexagonTargetLowering::IsEligibleForTailCallOptimization( /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it /// does not need to be loaded. It returns EVT::Other if the type should be /// determined using generic target-independent logic. -EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size, - unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, - bool MemcpyStrSrc, const AttributeList &FuncAttributes) const { - - auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool { - return (GivenA % MinA) == 0; - }; - - if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8))) +EVT HexagonTargetLowering::getOptimalMemOpType( + const MemOp &Op, const AttributeList &FuncAttributes) const { + if (Op.size() >= 8 && Op.isAligned(Align(8))) return MVT::i64; - if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4))) + if (Op.size() >= 4 && Op.isAligned(Align(4))) return MVT::i32; - if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2))) + if (Op.size() >= 2 && Op.isAligned(Align(2))) return MVT::i16; - return MVT::Other; } +bool HexagonTargetLowering::allowsMemoryAccess( + LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, + Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { + MVT SVT = VT.getSimpleVT(); + if (Subtarget.isHVXVectorType(SVT, true)) + return allowsHvxMemoryAccess(SVT, Flags, Fast); + return TargetLoweringBase::allowsMemoryAccess( + Context, DL, VT, AddrSpace, Alignment, Flags, Fast); +} + bool HexagonTargetLowering::allowsMisalignedMemoryAccesses( - EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags, - bool *Fast) const { + EVT VT, unsigned AddrSpace, unsigned Alignment, + MachineMemOperand::Flags Flags, bool *Fast) const { + MVT SVT = VT.getSimpleVT(); + if (Subtarget.isHVXVectorType(SVT, true)) + return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast); if (Fast) *Fast = false; - return Subtarget.isHVXVectorType(VT.getSimpleVT()); + return false; } std::pair<const TargetRegisterClass*, uint8_t> @@ -3357,9 +3513,5 @@ bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { TargetLowering::AtomicExpansionKind HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR( AtomicCmpXchgInst *AI) const { - const DataLayout &DL = AI->getModule()->getDataLayout(); - unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType()); - if (Size >= 4 && Size <= 8) - return AtomicExpansionKind::LLSC; - return AtomicExpansionKind::None; + return AtomicExpansionKind::LLSC; } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index e79646de62874..7d6e6b6185c87 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -235,19 +235,20 @@ namespace HexagonISD { /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. - unsigned + Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { return Hexagon::R0; } /// If a physical register, this returns the register that receives the /// exception typeid on entry to a landing pad. - unsigned + Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { return Hexagon::R1; } SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; @@ -301,12 +302,16 @@ namespace HexagonISD { /// the immediate into a register. bool isLegalICmpImmediate(int64_t Imm) const override; - EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, - unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, - const AttributeList &FuncAttributes) const override; + EVT getOptimalMemOpType(const MemOp &Op, + const AttributeList &FuncAttributes) const override; + + bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, + unsigned AddrSpace, Align Alignment, + MachineMemOperand::Flags Flags, + bool *Fast) const override; bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, - unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) + unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override; /// Returns relocation base for the given PIC jumptable. @@ -404,8 +409,15 @@ namespace HexagonISD { VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const; SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const; + bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags, + bool *Fast) const; + bool allowsHvxMisalignedMemoryAccesses(MVT VecTy, + MachineMemOperand::Flags Flags, + bool *Fast) const; + bool isHvxSingleTy(MVT Ty) const; bool isHvxPairTy(MVT Ty) const; + bool isHvxBoolTy(MVT Ty) const; SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy, SelectionDAG &DAG) const; SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const; @@ -437,6 +449,8 @@ namespace HexagonISD { const SDLoc &dl, SelectionDAG &DAG) const; SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy, bool ZeroExt, SelectionDAG &DAG) const; + SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy, + SelectionDAG &DAG) const; SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const; @@ -444,7 +458,7 @@ namespace HexagonISD { SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const; - + SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const; @@ -454,6 +468,9 @@ namespace HexagonISD { SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const; SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerHvxStore(SDValue Op, SelectionDAG &DAG) const; + SDValue HvxVecPredBitcastComputation(SDValue Op, SelectionDAG &DAG) const; SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const; SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const; @@ -463,8 +480,12 @@ namespace HexagonISD { const override; bool isHvxOperation(SDValue Op) const; + bool isHvxOperation(SDNode *N) const; SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const; - + void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG) const; + void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG) const; SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; }; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 204950f9010e9..7cda915fffe91 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -9,6 +9,7 @@ #include "HexagonISelLowering.h" #include "HexagonRegisterInfo.h" #include "HexagonSubtarget.h" +#include "llvm/IR/IntrinsicsHexagon.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -39,7 +40,6 @@ HexagonTargetLowering::initializeHVXLowering() { addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); - addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); } else if (Subtarget.useHVX128BOps()) { addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); @@ -50,7 +50,6 @@ HexagonTargetLowering::initializeHVXLowering() { addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass); - addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); } // Set up operation actions. @@ -66,8 +65,18 @@ HexagonTargetLowering::initializeHVXLowering() { AddPromotedToType(Opc, FromTy, ToTy); }; - setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); - setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); + // Handle bitcasts of vector predicates to scalars (e.g. v32i1 to i32). + // Note: v16i1 -> i16 is handled in type legalization instead of op + // legalization. + setOperationAction(ISD::BITCAST, MVT::i16, Custom); + setOperationAction(ISD::BITCAST, MVT::i32, Custom); + setOperationAction(ISD::BITCAST, MVT::i64, Custom); + setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); + setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); + setOperationAction(ISD::BITCAST, MVT::i128, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); + setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); for (MVT T : LegalV) { setIndexedLoadAction(ISD::POST_INC, T, Legal); @@ -194,12 +203,13 @@ HexagonTargetLowering::initializeHVXLowering() { setOperationAction(ISD::XOR, BoolV, Legal); } - if (Use64b) + if (Use64b) { for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); - else + } else { for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); + } setTargetDAGCombine(ISD::VSELECT); } @@ -283,6 +293,37 @@ HexagonTargetLowering::isHvxPairTy(MVT Ty) const { Ty.getSizeInBits() == 16 * Subtarget.getVectorLength(); } +bool +HexagonTargetLowering::isHvxBoolTy(MVT Ty) const { + return Subtarget.isHVXVectorType(Ty, true) && + Ty.getVectorElementType() == MVT::i1; +} + +bool HexagonTargetLowering::allowsHvxMemoryAccess( + MVT VecTy, MachineMemOperand::Flags Flags, bool *Fast) const { + // Bool vectors are excluded by default, but make it explicit to + // emphasize that bool vectors cannot be loaded or stored. + // Also, disallow double vector stores (to prevent unnecessary + // store widening in DAG combiner). + if (VecTy.getSizeInBits() > 8*Subtarget.getVectorLength()) + return false; + if (!Subtarget.isHVXVectorType(VecTy, /*IncludeBool=*/false)) + return false; + if (Fast) + *Fast = true; + return true; +} + +bool HexagonTargetLowering::allowsHvxMisalignedMemoryAccesses( + MVT VecTy, MachineMemOperand::Flags Flags, bool *Fast) const { + if (!Subtarget.isHVXVectorType(VecTy)) + return false; + // XXX Should this be false? vmemu are a bit slower than vmem. + if (Fast) + *Fast = true; + return true; +} + SDValue HexagonTargetLowering::convertToByteIndex(SDValue ElemIdx, MVT ElemTy, SelectionDAG &DAG) const { @@ -402,10 +443,11 @@ HexagonTargetLowering::buildHvxVectorReg(ArrayRef<SDValue> Values, ArrayRef<Constant*> Tmp((Constant**)Consts.begin(), (Constant**)Consts.end()); Constant *CV = ConstantVector::get(Tmp); - unsigned Align = HwLen; - SDValue CP = LowerConstantPool(DAG.getConstantPool(CV, VecTy, Align), DAG); + Align Alignment(HwLen); + SDValue CP = + LowerConstantPool(DAG.getConstantPool(CV, VecTy, Alignment), DAG); return DAG.getLoad(VecTy, dl, DAG.getEntryNode(), CP, - MachinePointerInfo::getConstantPool(MF), Align); + MachinePointerInfo::getConstantPool(MF), Alignment); } // A special case is a situation where the vector is built entirely from @@ -1023,6 +1065,63 @@ HexagonTargetLowering::extendHvxVectorPred(SDValue VecV, const SDLoc &dl, } SDValue +HexagonTargetLowering::compressHvxPred(SDValue VecQ, const SDLoc &dl, + MVT ResTy, SelectionDAG &DAG) const { + // Given a predicate register VecQ, transfer bits VecQ[0..HwLen-1] + // (i.e. the entire predicate register) to bits [0..HwLen-1] of a + // vector register. The remaining bits of the vector register are + // unspecified. + + MachineFunction &MF = DAG.getMachineFunction(); + unsigned HwLen = Subtarget.getVectorLength(); + MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen); + MVT PredTy = ty(VecQ); + unsigned PredLen = PredTy.getVectorNumElements(); + assert(HwLen % PredLen == 0); + MVT VecTy = MVT::getVectorVT(MVT::getIntegerVT(8*HwLen/PredLen), PredLen); + + Type *Int8Ty = Type::getInt8Ty(*DAG.getContext()); + SmallVector<Constant*, 128> Tmp; + // Create an array of bytes (hex): 01,02,04,08,10,20,40,80, 01,02,04,08,... + // These are bytes with the LSB rotated left with respect to their index. + for (unsigned i = 0; i != HwLen/8; ++i) { + for (unsigned j = 0; j != 8; ++j) + Tmp.push_back(ConstantInt::get(Int8Ty, 1ull << j)); + } + Constant *CV = ConstantVector::get(Tmp); + Align Alignment(HwLen); + SDValue CP = + LowerConstantPool(DAG.getConstantPool(CV, ByteTy, Alignment), DAG); + SDValue Bytes = + DAG.getLoad(ByteTy, dl, DAG.getEntryNode(), CP, + MachinePointerInfo::getConstantPool(MF), Alignment); + + // Select the bytes that correspond to true bits in the vector predicate. + SDValue Sel = DAG.getSelect(dl, VecTy, VecQ, DAG.getBitcast(VecTy, Bytes), + getZero(dl, VecTy, DAG)); + // Calculate the OR of all bytes in each group of 8. That will compress + // all the individual bits into a single byte. + // First, OR groups of 4, via vrmpy with 0x01010101. + SDValue All1 = + DAG.getSplatBuildVector(MVT::v4i8, dl, DAG.getConstant(1, dl, MVT::i32)); + SDValue Vrmpy = getInstr(Hexagon::V6_vrmpyub, dl, ByteTy, {Sel, All1}, DAG); + // Then rotate the accumulated vector by 4 bytes, and do the final OR. + SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, + {Vrmpy, Vrmpy, DAG.getTargetConstant(4, dl, MVT::i32)}, DAG); + SDValue Vor = DAG.getNode(ISD::OR, dl, ByteTy, {Vrmpy, Rot}); + + // Pick every 8th byte and coalesce them at the beginning of the output. + // For symmetry, coalesce every 1+8th byte after that, then every 2+8th + // byte and so on. + SmallVector<int,128> Mask; + for (unsigned i = 0; i != HwLen; ++i) + Mask.push_back((8*i) % HwLen + i/(HwLen/8)); + SDValue Collect = + DAG.getVectorShuffle(ByteTy, dl, Vor, DAG.getUNDEF(ByteTy), Mask); + return DAG.getBitcast(ResTy, Collect); +} + +SDValue HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const { const SDLoc &dl(Op); @@ -1431,6 +1530,53 @@ HexagonTargetLowering::LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const { } SDValue +HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const { + SDValue ValQ = Op.getOperand(0); + MVT ResTy = ty(Op); + MVT VecTy = ty(ValQ); + const SDLoc &dl(Op); + + if (isHvxBoolTy(VecTy) && ResTy.isScalarInteger()) { + unsigned HwLen = Subtarget.getVectorLength(); + MVT WordTy = MVT::getVectorVT(MVT::i32, HwLen/4); + SDValue VQ = compressHvxPred(ValQ, dl, WordTy, DAG); + unsigned BitWidth = ResTy.getSizeInBits(); + + if (BitWidth < 64) { + SDValue W0 = extractHvxElementReg(VQ, DAG.getConstant(0, dl, MVT::i32), + dl, MVT::i32, DAG); + if (BitWidth == 32) + return W0; + assert(BitWidth < 32u); + return DAG.getZExtOrTrunc(W0, dl, ResTy); + } + + // The result is >= 64 bits. The only options are 64 or 128. + assert(BitWidth == 64 || BitWidth == 128); + SmallVector<SDValue,4> Words; + for (unsigned i = 0; i != BitWidth/32; ++i) { + SDValue W = extractHvxElementReg( + VQ, DAG.getConstant(i, dl, MVT::i32), dl, MVT::i32, DAG); + Words.push_back(W); + } + SmallVector<SDValue,2> Combines; + assert(Words.size() % 2 == 0); + for (unsigned i = 0, e = Words.size(); i < e; i += 2) { + SDValue C = DAG.getNode( + HexagonISD::COMBINE, dl, MVT::i64, {Words[i+1], Words[i]}); + Combines.push_back(C); + } + + if (BitWidth == 64) + return Combines[0]; + + return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines); + } + + return Op; +} + +SDValue HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const { // Sign- and zero-extends are legal. assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG); @@ -1446,6 +1592,28 @@ HexagonTargetLowering::LowerHvxShift(SDValue Op, SelectionDAG &DAG) const { } SDValue +HexagonTargetLowering::LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const { + const SDLoc &dl(Op); + MVT ResTy = ty(Op); + + unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + bool Use64b = Subtarget.useHVX64BOps(); + unsigned IntPredCast = Use64b ? Intrinsic::hexagon_V6_pred_typecast + : Intrinsic::hexagon_V6_pred_typecast_128B; + if (IntNo == IntPredCast) { + SDValue Vs = Op.getOperand(1); + MVT OpTy = ty(Vs); + if (isHvxBoolTy(ResTy) && isHvxBoolTy(OpTy)) { + if (ResTy == OpTy) + return Vs; + return DAG.getNode(HexagonISD::TYPECAST, dl, ResTy, Vs); + } + } + + return Op; +} + +SDValue HexagonTargetLowering::SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const { assert(!Op.isMachineOpcode()); SmallVector<SDValue,2> OpsL, OpsH; @@ -1566,7 +1734,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); - + case ISD::BITCAST: return LowerHvxBitcast(Op, DAG); case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG); case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG); case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG); @@ -1580,6 +1748,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG); case ISD::SETCC: case ISD::INTRINSIC_VOID: return Op; + case ISD::INTRINSIC_WO_CHAIN: return LowerHvxIntrinsic(Op, DAG); // Unaligned loads will be handled by the default lowering. case ISD::LOAD: return SDValue(); } @@ -1589,6 +1758,28 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { llvm_unreachable("Unhandled HVX operation"); } +void +HexagonTargetLowering::LowerHvxOperationWrapper(SDNode *N, + SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { +} + +void +HexagonTargetLowering::ReplaceHvxNodeResults(SDNode *N, + SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { + unsigned Opc = N->getOpcode(); + switch (Opc) { + case ISD::BITCAST: + if (isHvxBoolTy(ty(N->getOperand(0)))) { + SDValue Op(N, 0); + SDValue C = LowerHvxBitcast(Op, DAG); + Results.push_back(C); + } + break; + default: + break; + } +} + SDValue HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { @@ -1621,3 +1812,16 @@ HexagonTargetLowering::isHvxOperation(SDValue Op) const { return Subtarget.isHVXVectorType(ty(V), true); }); } + +bool +HexagonTargetLowering::isHvxOperation(SDNode *N) const { + // If the type of any result, or any operand type are HVX vector types, + // this is an HVX operation. + auto IsHvxTy = [this] (EVT Ty) { + return Ty.isSimple() && Subtarget.isHVXVectorType(Ty.getSimpleVT(), true); + }; + auto IsHvxOp = [this] (SDValue Op) { + return Subtarget.isHVXVectorType(ty(Op), true); + }; + return llvm::any_of(N->values(), IsHvxTy) || llvm::any_of(N->ops(), IsHvxOp); +} diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index f156de6710593..ef2b3040931d8 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -37,6 +37,8 @@ def HVXVectorAccess : MemAccessSize<5>; // Instruction Class Declaration + //===----------------------------------------------------------------------===// +// "Parse" bits are explicitly NOT defined in the opcode space to prevent +// TableGen from using them for generation of the decoder tables. class OpcodeHexagon { field bits<32> Inst = ?; // Default to an invalid insn. bits<4> IClass = 0; // ICLASS @@ -164,6 +166,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bit CVINew = 0; let TSFlags{62} = CVINew; + bit isCVI = 0; + let TSFlags{63} = isCVI; + // Fields used for relation models. bit isNonTemporal = 0; string isNT = ""; // set to "true" for non-temporal vector stores. @@ -226,9 +231,105 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], OpcodeHexagon; //===----------------------------------------------------------------------===// +// Special Instructions - +//===----------------------------------------------------------------------===// + +// The 'invalid_decode' instruction is used by the disassembler to +// show an instruction that didn't decode correctly. This feature +// is only leveraged in a special disassembler mode that's activated +// by a command line flag. +def tc_invalid : InstrItinClass; +class Enc_invalid : OpcodeHexagon { +} +def invalid_decode : HInst< +(outs ), +(ins ), +"<invalid>", +tc_invalid, TypeALU32_2op>, Enc_invalid { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b0000000000000000; +let isCodeGenOnly = 1; +} + +//===----------------------------------------------------------------------===// +// Duplex Instruction Class Declaration +//===----------------------------------------------------------------------===// + +class OpcodeDuplex { + field bits<32> Inst = ?; // Default to an invalid insn. + bits<4> IClass = 0; // ICLASS + bits<13> ISubHi = 0; // Low sub-insn + bits<13> ISubLo = 0; // High sub-insn + + let Inst{31-29} = IClass{3-1}; + let Inst{13} = IClass{0}; + let Inst{15-14} = 0; + let Inst{28-16} = ISubHi; + let Inst{12-0} = ISubLo; +} + +class InstDuplex<bits<4> iClass, list<dag> pattern = [], + string cstr = ""> + : Instruction, OpcodeDuplex { + let Namespace = "Hexagon"; + IType Type = TypeDUPLEX; // uses slot 0,1 + let isCodeGenOnly = 1; + let hasSideEffects = 0; + dag OutOperandList = (outs); + dag InOperandList = (ins); + let IClass = iClass; + let Constraints = cstr; + let Itinerary = DUPLEX; + let Size = 4; + + // SoftFail is a field the disassembler can use to provide a way for + // instructions to not match without killing the whole decode process. It is + // mainly used for ARM, but Tablegen expects this field to exist or it fails + // to build the decode table. + field bits<32> SoftFail = 0; + + // *** Must match MCTargetDesc/HexagonBaseInfo.h *** + + let TSFlags{6-0} = Type.Value; + + // Predicated instructions. + bits<1> isPredicated = 0; + let TSFlags{7} = isPredicated; + bits<1> isPredicatedFalse = 0; + let TSFlags{8} = isPredicatedFalse; + bits<1> isPredicatedNew = 0; + let TSFlags{9} = isPredicatedNew; + + // New-value insn helper fields. + bits<1> isNewValue = 0; + let TSFlags{10} = isNewValue; // New-value consumer insn. + bits<1> hasNewValue = 0; + let TSFlags{11} = hasNewValue; // New-value producer insn. + bits<3> opNewValue = 0; + let TSFlags{14-12} = opNewValue; // New-value produced operand. + bits<1> isNVStorable = 0; + let TSFlags{15} = isNVStorable; // Store that can become new-value store. + bits<1> isNVStore = 0; + let TSFlags{16} = isNVStore; // New-value store insn. + + // Immediate extender helper fields. + bits<1> isExtendable = 0; + let TSFlags{17} = isExtendable; // Insn may be extended. + bits<1> isExtended = 0; + let TSFlags{18} = isExtended; // Insn must be extended. + bits<3> opExtendable = 0; + let TSFlags{21-19} = opExtendable; // Which operand may be extended. + bits<1> isExtentSigned = 0; + let TSFlags{22} = isExtentSigned; // Signed or unsigned range. + bits<5> opExtentBits = 0; + let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending. + bits<2> opExtentAlign = 0; + let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending. +} + +//===----------------------------------------------------------------------===// // Instruction Classes Definitions - //===----------------------------------------------------------------------===// -include "HexagonInstrFormatsV5.td" include "HexagonInstrFormatsV60.td" include "HexagonInstrFormatsV65.td" diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td deleted file mode 100644 index 68ef2d2d3a8aa..0000000000000 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td +++ /dev/null @@ -1,86 +0,0 @@ -//==- HexagonInstrFormatsV5.td - Hexagon Instruction Formats --*- tablegen -==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V5 instruction classes in TableGen format. -// -//===----------------------------------------------------------------------===// - -// Duplex Instruction Class Declaration -//===----------------------------------------------------------------------===// - -class OpcodeDuplex { - field bits<32> Inst = ?; // Default to an invalid insn. - bits<4> IClass = 0; // ICLASS - bits<13> ISubHi = 0; // Low sub-insn - bits<13> ISubLo = 0; // High sub-insn - - let Inst{31-29} = IClass{3-1}; - let Inst{13} = IClass{0}; - let Inst{15-14} = 0; - let Inst{28-16} = ISubHi; - let Inst{12-0} = ISubLo; -} - -class InstDuplex<bits<4> iClass, list<dag> pattern = [], - string cstr = ""> - : Instruction, OpcodeDuplex { - let Namespace = "Hexagon"; - IType Type = TypeDUPLEX; // uses slot 0,1 - let isCodeGenOnly = 1; - let hasSideEffects = 0; - dag OutOperandList = (outs); - dag InOperandList = (ins); - let IClass = iClass; - let Constraints = cstr; - let Itinerary = DUPLEX; - let Size = 4; - - // SoftFail is a field the disassembler can use to provide a way for - // instructions to not match without killing the whole decode process. It is - // mainly used for ARM, but Tablegen expects this field to exist or it fails - // to build the decode table. - field bits<32> SoftFail = 0; - - // *** Must match MCTargetDesc/HexagonBaseInfo.h *** - - let TSFlags{6-0} = Type.Value; - - // Predicated instructions. - bits<1> isPredicated = 0; - let TSFlags{7} = isPredicated; - bits<1> isPredicatedFalse = 0; - let TSFlags{8} = isPredicatedFalse; - bits<1> isPredicatedNew = 0; - let TSFlags{9} = isPredicatedNew; - - // New-value insn helper fields. - bits<1> isNewValue = 0; - let TSFlags{10} = isNewValue; // New-value consumer insn. - bits<1> hasNewValue = 0; - let TSFlags{11} = hasNewValue; // New-value producer insn. - bits<3> opNewValue = 0; - let TSFlags{14-12} = opNewValue; // New-value produced operand. - bits<1> isNVStorable = 0; - let TSFlags{15} = isNVStorable; // Store that can become new-value store. - bits<1> isNVStore = 0; - let TSFlags{16} = isNVStore; // New-value store insn. - - // Immediate extender helper fields. - bits<1> isExtendable = 0; - let TSFlags{17} = isExtendable; // Insn may be extended. - bits<1> isExtended = 0; - let TSFlags{18} = isExtended; // Insn must be extended. - bits<3> opExtendable = 0; - let TSFlags{21-19} = opExtendable; // Which operand may be extended. - bits<1> isExtentSigned = 0; - let TSFlags{22} = isExtentSigned; // Signed or unsigned range. - bits<5> opExtentBits = 0; - let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending. - bits<2> opExtentAlign = 0; - let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending. -} diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td index eaecffe9c89e8..246a1d364d41a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td @@ -11,13 +11,13 @@ //===----------------------------------------------------------------------===// //----------------------------------------------------------------------------// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags + // // *** Must match BaseInfo.h *** //----------------------------------------------------------------------------// //----------------------------------------------------------------------------// -// Intruction Classes Definitions + +// Instruction Classes Definitions + //----------------------------------------------------------------------------// class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 39ec8936214e7..d1cd23c3be3e5 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -118,6 +118,12 @@ HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), Subtarget(ST) {} +namespace llvm { +namespace HexagonFUnits { + bool isSlot0Only(unsigned units); +} +} + static bool isIntRegForSubInst(unsigned Reg) { return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); @@ -370,7 +376,7 @@ bool HexagonInstrInfo::hasStoreToStackSlot( /// This function can analyze one/two way branching only and should (mostly) be /// called by target independent side. /// First entry is always the opcode of the branching instruction, except when -/// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a +/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a /// BB with only unconditional jump. Subsequent entries depend upon the opcode, /// e.g. Jump_c p will have /// Cond[0] = Jump_c @@ -784,6 +790,25 @@ bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB, return NumInstrs <= 4; } +static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) { + SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers; + const MachineBasicBlock &B = *MI.getParent(); + Regs.addLiveIns(B); + auto E = MachineBasicBlock::const_iterator(MI.getIterator()); + for (auto I = B.begin(); I != E; ++I) { + Clobbers.clear(); + Regs.stepForward(*I, Clobbers); + } +} + +static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) { + const MachineBasicBlock &B = *MI.getParent(); + Regs.addLiveOuts(B); + auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse(); + for (auto I = B.rbegin(); I != E; ++I) + Regs.stepBackward(*I); +} + void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, @@ -849,11 +874,15 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) { - Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); - Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); + LivePhysRegs LiveAtMI(HRI); + getLiveInRegsAt(LiveAtMI, *I); + Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); + Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); + unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo)); + unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) - .addReg(HiSrc, KillFlag) - .addReg(LoSrc, KillFlag); + .addReg(SrcHi, KillFlag | UndefHi) + .addReg(SrcLo, KillFlag | UndefLo); return; } if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { @@ -882,17 +911,16 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, + MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned SlotAlign = MFI.getObjectAlignment(FI); unsigned KillFlag = getKillRegState(isKill); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, - MFI.getObjectSize(FI), SlotAlign); + MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) @@ -928,17 +956,16 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } void HexagonInstrInfo::loadRegFromStackSlot( - MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned SlotAlign = MFI.getObjectAlignment(FI); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, - MFI.getObjectSize(FI), SlotAlign); + MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) @@ -966,14 +993,6 @@ void HexagonInstrInfo::loadRegFromStackSlot( } } -static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) { - const MachineBasicBlock &B = *MI.getParent(); - Regs.addLiveOuts(B); - auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse(); - for (auto I = B.rbegin(); I != E; ++I) - Regs.stepBackward(*I); -} - /// expandPostRAPseudo - This function is called for all pseudo instructions /// that remain after register allocation. Many pseudo instructions are /// created to help register allocation. This is the place to convert them @@ -985,6 +1004,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MachineFunction &MF = *MBB.getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); + LivePhysRegs LiveIn(HRI), LiveOut(HRI); DebugLoc DL = MI.getDebugLoc(); unsigned Opc = MI.getOpcode(); @@ -1005,10 +1025,9 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) { if (MI.memoperands().empty()) return false; - return all_of(MI.memoperands(), - [NeedAlign] (const MachineMemOperand *MMO) { - return NeedAlign <= MMO->getAlignment(); - }); + return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { + return MMO->getAlign() >= NeedAlign; + }); }; switch (Opc) { @@ -1032,10 +1051,15 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case Hexagon::V6_vassignp: { Register SrcReg = MI.getOperand(1).getReg(); Register DstReg = MI.getOperand(0).getReg(); + Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); + Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); + getLiveInRegsAt(LiveIn, MI); + unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); + unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); unsigned Kill = getKillRegState(MI.getOperand(1).isKill()); BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg) - .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill) - .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill); + .addReg(SrcHi, UndefHi) + .addReg(SrcLo, Kill | UndefLo); MBB.erase(MI); return true; } @@ -1255,9 +1279,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { const MachineOperand &Op1 = MI.getOperand(1); const MachineOperand &Op2 = MI.getOperand(2); const MachineOperand &Op3 = MI.getOperand(3); - LivePhysRegs LiveAtMI(HRI); - getLiveRegsAt(LiveAtMI, MI); - bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); + getLiveOutRegsAt(LiveOut, MI); + bool IsDestLive = !LiveOut.available(MRI, Op0.getReg()); Register PReg = Op1.getReg(); assert(Op1.getSubReg() == 0); unsigned PState = getRegState(Op1); @@ -1289,9 +1312,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MachineOperand &Op1 = MI.getOperand(1); MachineOperand &Op2 = MI.getOperand(2); MachineOperand &Op3 = MI.getOperand(3); - LivePhysRegs LiveAtMI(HRI); - getLiveRegsAt(LiveAtMI, MI); - bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); + getLiveOutRegsAt(LiveOut, MI); + bool IsDestLive = !LiveOut.available(MRI, Op0.getReg()); Register PReg = Op1.getReg(); assert(Op1.getSubReg() == 0); unsigned PState = getRegState(Op1); @@ -1349,7 +1371,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { static const CrashPseudoSourceValue CrashPSV(*this); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo(&CrashPSV), - MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1); + MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, + Align(1)); BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13) .addImm(0xBADC0FEE) // Misaligned load. .addMemOperand(MMO); @@ -1707,6 +1730,10 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI, if (MI.getDesc().isTerminator() || MI.isPosition()) return true; + // INLINEASM_BR can jump to another block + if (MI.getOpcode() == TargetOpcode::INLINEASM_BR) + return true; + if (MI.isInlineAsm() && !ScheduleInlineAsm) return true; @@ -1735,7 +1762,7 @@ unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str, if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(), strlen(MAI.getSeparatorString())) == 0) atInsnStart = true; - if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) { + if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) { Length += MaxInstLength; atInsnStart = false; } @@ -1762,8 +1789,8 @@ HexagonInstrInfo::CreateTargetPostRAHazardRecognizer( /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it /// compares against in CmpValue. Return true if the comparison instruction /// can be analyzed. -bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, - unsigned &SrcReg2, int &Mask, +bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int &Mask, int &Value) const { unsigned Opc = MI.getOpcode(); @@ -2940,12 +2967,16 @@ bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, } /// Get the base register and byte offset of a load/store instr. -bool HexagonInstrInfo::getMemOperandWithOffset( - const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, +bool HexagonInstrInfo::getMemOperandsWithOffsetWidth( + const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, + int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const { - unsigned AccessSize = 0; - BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize); - return BaseOp != nullptr && BaseOp->isReg(); + OffsetIsScalable = false; + const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width); + if (!BaseOp || !BaseOp->isReg()) + return false; + BaseOps.push_back(BaseOp); + return true; } /// Can these instructions execute at the same time in a bundle. @@ -3403,6 +3434,64 @@ unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA, : Hexagon::J4_cmpeqi_tp1_jump_nt; } +// Returns -1 if there is no opcode found. +int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI, + bool ForBigCore) const { + // Static table to switch the opcodes across Tiny Core and Big Core. + // dup_ opcodes are Big core opcodes. + // NOTE: There are special instructions that need to handled later. + // L4_return* instructions, they will only occupy SLOT0 (on big core too). + // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2. + // The compiler need to base the root instruction to L6_return_map_to_raw + // which can go any slot. + static const std::map<unsigned, unsigned> DupMap = { + {Hexagon::A2_add, Hexagon::dup_A2_add}, + {Hexagon::A2_addi, Hexagon::dup_A2_addi}, + {Hexagon::A2_andir, Hexagon::dup_A2_andir}, + {Hexagon::A2_combineii, Hexagon::dup_A2_combineii}, + {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, + {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, + {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, + {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi}, + {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, + {Hexagon::A2_zxth, Hexagon::dup_A2_zxth}, + {Hexagon::A4_combineii, Hexagon::dup_A4_combineii}, + {Hexagon::A4_combineir, Hexagon::dup_A4_combineir}, + {Hexagon::A4_combineri, Hexagon::dup_A4_combineri}, + {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif}, + {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit}, + {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif}, + {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit}, + {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi}, + {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe}, + {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io}, + {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io}, + {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io}, + {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io}, + {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io}, + {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io}, + {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe}, + {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io}, + {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io}, + {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io}, + {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io}, + {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io}, + {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io}, + }; + unsigned OpNum = MI.getOpcode(); + // Conversion to Big core. + if (ForBigCore) { + auto Iter = DupMap.find(OpNum); + if (Iter != DupMap.end()) + return Iter->second; + } else { // Conversion to Tiny core. + for (auto Iter = DupMap.begin(), End = DupMap.end(); Iter != End; ++Iter) + if (Iter->second == OpNum) + return Iter->first; + } + return -1; +} + int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const { enum Hexagon::PredSense inPredSense; inPredSense = invertPredicate ? Hexagon::PredSense_false : @@ -3735,6 +3824,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( // Rd = memw(Rs+#u4:2) // Rd = memub(Rs+#u4:0) case Hexagon::L2_loadri_io: + case Hexagon::dup_L2_loadri_io: DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); // Special case this one from Group L2. @@ -3753,6 +3843,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( } break; case Hexagon::L2_loadrub_io: + case Hexagon::dup_L2_loadrub_io: // Rd = memub(Rs+#u4:0) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -3772,6 +3863,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( // [if ([!]p0[.new])] jumpr r31 case Hexagon::L2_loadrh_io: case Hexagon::L2_loadruh_io: + case Hexagon::dup_L2_loadrh_io: + case Hexagon::dup_L2_loadruh_io: // Rd = memh/memuh(Rs+#u3:1) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -3781,6 +3874,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_L2; break; case Hexagon::L2_loadrb_io: + case Hexagon::dup_L2_loadrb_io: // Rd = memb(Rs+#u3:0) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -3790,6 +3884,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_L2; break; case Hexagon::L2_loadrd_io: + case Hexagon::dup_L2_loadrd_io: // Rdd = memd(r29+#u5:3) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -3806,6 +3901,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: case Hexagon::L4_return: case Hexagon::L2_deallocframe: + case Hexagon::dup_L2_deallocframe: return HexagonII::HSIG_L2; case Hexagon::EH_RETURN_JMPR: case Hexagon::PS_jmpret: @@ -3825,6 +3921,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::SL2_jumpr31_t: case Hexagon::SL2_jumpr31_f: case Hexagon::SL2_jumpr31_tnew: + case Hexagon::SL2_jumpr31_fnew: DstReg = MI.getOperand(1).getReg(); SrcReg = MI.getOperand(0).getReg(); // [if ([!]p0[.new])] jumpr r31 @@ -3850,6 +3947,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( // memw(Rs+#u4:2) = Rt // memb(Rs+#u4:0) = Rt case Hexagon::S2_storeri_io: + case Hexagon::dup_S2_storeri_io: // Special case this one from Group S2. // memw(r29+#u5:2) = Rt Src1Reg = MI.getOperand(0).getReg(); @@ -3866,6 +3964,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S1; break; case Hexagon::S2_storerb_io: + case Hexagon::dup_S2_storerb_io: // memb(Rs+#u4:0) = Rt Src1Reg = MI.getOperand(0).getReg(); Src2Reg = MI.getOperand(2).getReg(); @@ -3883,6 +3982,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( // memb(Rs+#u4) = #U1 // allocframe(#u5:3) case Hexagon::S2_storerh_io: + case Hexagon::dup_S2_storerh_io: // memh(Rs+#u3:1) = Rt Src1Reg = MI.getOperand(0).getReg(); Src2Reg = MI.getOperand(2).getReg(); @@ -3892,6 +3992,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S1; break; case Hexagon::S2_storerd_io: + case Hexagon::dup_S2_storerd_io: // memd(r29+#s6:3) = Rtt Src1Reg = MI.getOperand(0).getReg(); Src2Reg = MI.getOperand(2).getReg(); @@ -3902,6 +4003,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S2; break; case Hexagon::S4_storeiri_io: + case Hexagon::dup_S4_storeiri_io: // memw(Rs+#u4:2) = #U1 Src1Reg = MI.getOperand(0).getReg(); if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() && @@ -3910,6 +4012,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S2; break; case Hexagon::S4_storeirb_io: + case Hexagon::dup_S4_storeirb_io: // memb(Rs+#u4) = #U1 Src1Reg = MI.getOperand(0).getReg(); if (isIntRegForSubInst(Src1Reg) && @@ -3918,6 +4021,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S2; break; case Hexagon::S2_allocframe: + case Hexagon::dup_S2_allocframe: if (MI.getOperand(2).isImm() && isShiftedUInt<5,3>(MI.getOperand(2).getImm())) return HexagonII::HSIG_S1; @@ -3941,6 +4045,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( // Rd = sxth/sxtb/zxtb/zxth(Rs) // Rd = and(Rs,#1) case Hexagon::A2_addi: + case Hexagon::dup_A2_addi: DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); if (isIntRegForSubInst(DstReg)) { @@ -3962,6 +4067,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( } break; case Hexagon::A2_add: + case Hexagon::dup_A2_add: // Rx = add(Rx,Rs) DstReg = MI.getOperand(0).getReg(); Src1Reg = MI.getOperand(1).getReg(); @@ -3971,6 +4077,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::A2_andir: + case Hexagon::dup_A2_andir: // Same as zxtb. // Rd16=and(Rs16,#255) // Rd16=and(Rs16,#1) @@ -3983,6 +4090,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::A2_tfr: + case Hexagon::dup_A2_tfr: // Rd = Rs DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -3990,6 +4098,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::A2_tfrsi: + case Hexagon::dup_A2_tfrsi: // Rd = #u6 // Do not test for #u6 size since the const is getting extended // regardless and compound could be formed. @@ -4002,6 +4111,10 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::C2_cmovenewit: case Hexagon::C2_cmoveif: case Hexagon::C2_cmovenewif: + case Hexagon::dup_C2_cmoveit: + case Hexagon::dup_C2_cmovenewit: + case Hexagon::dup_C2_cmoveif: + case Hexagon::dup_C2_cmovenewif: // if ([!]P0[.new]) Rd = #0 // Actual form: // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16; @@ -4013,6 +4126,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::C2_cmpeqi: + case Hexagon::dup_C2_cmpeqi: // P0 = cmp.eq(Rs,#u2) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4023,6 +4137,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( break; case Hexagon::A2_combineii: case Hexagon::A4_combineii: + case Hexagon::dup_A2_combineii: + case Hexagon::dup_A4_combineii: // Rdd = combine(#u2,#U2) DstReg = MI.getOperand(0).getReg(); if (isDblRegForSubInst(DstReg, HRI) && @@ -4035,6 +4151,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::A4_combineri: + case Hexagon::dup_A4_combineri: + // Rdd = combine(Rs,#0) // Rdd = combine(Rs,#0) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4044,6 +4162,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_A; break; case Hexagon::A4_combineir: + case Hexagon::dup_A4_combineir: // Rdd = combine(#0,Rs) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(2).getReg(); @@ -4056,6 +4175,10 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::A2_sxth: case Hexagon::A2_zxtb: case Hexagon::A2_zxth: + case Hexagon::dup_A2_sxtb: + case Hexagon::dup_A2_sxth: + case Hexagon::dup_A2_zxtb: + case Hexagon::dup_A2_zxth: // Rd = sxth/sxtb/zxtb/zxth(Rs) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4199,6 +4322,61 @@ bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const { addrMode == HexagonII::BaseLongOffset); } +bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const { + // Workaround for the Global Scheduler. Sometimes, it creates + // A4_ext as a Pseudo instruction and calls this function to see if + // it can be added to an existing bundle. Since the instruction doesn't + // belong to any BB yet, we can't use getUnits API. + if (MI.getOpcode() == Hexagon::A4_ext) + return false; + + unsigned FuncUnits = getUnits(MI); + return HexagonFUnits::isSlot0Only(FuncUnits); +} + +bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const { + const uint64_t F = MI.getDesc().TSFlags; + return ((F >> HexagonII::RestrictNoSlot1StorePos) & + HexagonII::RestrictNoSlot1StoreMask); +} + +void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, + bool ToBigInstrs) const { + int Opcode = -1; + if (ToBigInstrs) { // To BigCore Instr. + // Check if the instruction can form a Duplex. + if (getDuplexCandidateGroup(*MII)) + // Get the opcode marked "dup_*" tag. + Opcode = getDuplexOpcode(*MII, ToBigInstrs); + } else // To TinyCore Instr. + Opcode = getDuplexOpcode(*MII, ToBigInstrs); + + // Change the opcode of the instruction. + if (Opcode >= 0) + MII->setDesc(get(Opcode)); +} + +// This function is used to translate instructions to facilitate generating +// Duplexes on TinyCore. +void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF, + bool ToBigInstrs) const { + for (auto &MB : MF) + for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(), + End = MB.instr_end(); + Instr != End; ++Instr) + changeDuplexOpcode(Instr, ToBigInstrs); +} + +// This is a specialized form of above function. +void HexagonInstrInfo::translateInstrsForDup( + MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const { + MachineBasicBlock *MBB = MII->getParent(); + while ((MII != MBB->instr_end()) && MII->isInsideBundle()) { + changeDuplexOpcode(MII, ToBigInstrs); + ++MII; + } +} + unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const { using namespace HexagonII; @@ -4328,7 +4506,7 @@ uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const { return (F >> HexagonII::TypePos) & HexagonII::TypeMask; } -unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const { +InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const { const InstrItineraryData &II = *Subtarget.getInstrItineraryData(); const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass()); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 676f6f0a2a8c0..847b9a6728916 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -109,19 +109,19 @@ public: bool AllowModify) const override; /// Remove the branching code at the end of the specific MBB. - /// This is only invoked in cases where AnalyzeBranch returns success. It + /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. /// The operands to this method are the same as those - /// returned by AnalyzeBranch. This is only invoked in cases where - /// AnalyzeBranch returns success. It returns the number of instructions + /// returned by analyzeBranch. This is only invoked in cases where + /// analyzeBranch returns success. It returns the number of instructions /// inserted. /// /// It is also invoked by tail merging to add unconditional branches in - /// cases where AnalyzeBranch doesn't apply because there was no original + /// cases where analyzeBranch doesn't apply because there was no original /// branch to analyze. At least this much must be implemented, else tail /// merging needs to be disabled. unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, @@ -182,7 +182,7 @@ public: /// is true, the register operand is the last use and must be marked kill. void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -191,7 +191,7 @@ public: /// machine basic block before the specified machine instruction. void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -204,10 +204,11 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; /// Get the base register and byte offset of a load/store instr. - bool getMemOperandWithOffset(const MachineInstr &LdSt, - const MachineOperand *&BaseOp, - int64_t &Offset, - const TargetRegisterInfo *TRI) const override; + bool getMemOperandsWithOffsetWidth( + const MachineInstr &LdSt, + SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, + bool &OffsetIsScalable, unsigned &Width, + const TargetRegisterInfo *TRI) const override; /// Reverses the branch condition of the specified condition list, /// returning false on success and true if it cannot be reversed. @@ -268,8 +269,8 @@ public: /// in SrcReg and SrcReg2 if having two register operands, and the value it /// compares against in CmpValue. Return true if the comparison instruction /// can be analyzed. - bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, - unsigned &SrcReg2, int &Mask, int &Value) const override; + bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int &Mask, int &Value) const override; /// Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via @@ -341,10 +342,10 @@ public: MachineBasicBlock *TargetBB, SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; - bool isBaseImmOffset(const MachineInstr &MI) const; bool isAbsoluteSet(const MachineInstr &MI) const; bool isAccumulator(const MachineInstr &MI) const; bool isAddrModeWithOffset(const MachineInstr &MI) const; + bool isBaseImmOffset(const MachineInstr &MI) const; bool isComplex(const MachineInstr &MI) const; bool isCompoundBranchInstr(const MachineInstr &MI) const; bool isConstExtended(const MachineInstr &MI) const; @@ -387,6 +388,8 @@ public: bool isPredicated(unsigned Opcode) const; bool isPredicateLate(unsigned Opcode) const; bool isPredictedTaken(unsigned Opcode) const; + bool isPureSlot0(const MachineInstr &MI) const; + bool isRestrictNoSlot1Store(const MachineInstr &MI) const; bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const; bool isSignExtendingLoad(const MachineInstr &MI) const; bool isSolo(const MachineInstr &MI) const; @@ -435,6 +438,7 @@ public: getCompoundCandidateGroup(const MachineInstr &MI) const; unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const; + int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const; int getCondOpcode(int Opc, bool sense) const; int getDotCurOp(const MachineInstr &MI) const; int getNonDotCurOp(const MachineInstr &MI) const; @@ -461,7 +465,7 @@ public: short getRegForm(const MachineInstr &MI) const; unsigned getSize(const MachineInstr &MI) const; uint64_t getType(const MachineInstr &MI) const; - unsigned getUnits(const MachineInstr &MI) const; + InstrStage::FuncUnits getUnits(const MachineInstr &MI) const; MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const; @@ -480,6 +484,17 @@ public: void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const; bool getBundleNoShuf(const MachineInstr &MIB) const; + + // When TinyCore with Duplexes is enabled, this function is used to translate + // tiny-instructions to big-instructions and vice versa to get the slot + // consumption. + void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, + bool ToBigInstrs) const; + void translateInstrsForDup(MachineFunction &MF, + bool ToBigInstrs = true) const; + void translateInstrsForDup(MachineBasicBlock::instr_iterator MII, + bool ToBigInstrs) const; + // Addressing mode relations. short changeAddrMode_abs_io(short Opc) const; short changeAddrMode_io_abs(short Opc) const; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 8ae55b2071889..10d0261a95dd4 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -205,12 +205,12 @@ def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred_timm, I32>; multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> { def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[UseHVX]>; def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[UseHVX]>; } @@ -236,6 +236,8 @@ def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>; def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>; def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>; +def: Pat<(int_hexagon_Y2_dcfetch I32:$Rt), (Y2_dcfetchbo I32:$Rt, 0)>; + // // Patterns for optimizing code generations for HVX. @@ -277,76 +279,6 @@ def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), Requires<[UseHVX]>; } -def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), - (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), - (v512i1 (V6_vandvrt (v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), - (v512i1 (V6_vandvrt (v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), - (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), - (v32i16 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), - (v64i8 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), - (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), - (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), - (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -let AddedComplexity = 140 in { -def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai IntRegs:$addr, 0, - (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>, - Requires<[UseHVX]>; - -def : Pat <(v512i1 (load (i32 IntRegs:$addr))), - (v512i1 (V6_vandvrt - (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; - -def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai IntRegs:$addr, 0, - (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>, - Requires<[UseHVX]>; - -def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), - (v1024i1 (V6_vandvrt - (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVX]>; -} - def: Pat<(v64i16 (trunc v64i32:$Vdd)), (v64i16 (V6_vpackwh_sat (v32i32 (V6_hi HvxWR:$Vdd)), diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td index a60c80beb5d66..1245ee7974b55 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -25,59 +25,59 @@ def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >; } -def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), - (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))), + (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), - (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))), + (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), - (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))), + (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), - (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))), + (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), - (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))), + (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), - (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v64i8 (bitconvert (v64i1 HvxQR:$src1))), + (v64i8 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))), + (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))), + (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), - (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v128i1 (bitconvert (v128i8 HvxVR:$src1))), + (v128i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), - (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))), + (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), - (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))), + (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; -def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), - (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; +def : Pat <(v128i8 (bitconvert (v128i1 HvxQR:$src1))), + (v128i8 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; let AddedComplexity = 140 in { -def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), +def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)), (V6_vS32b_ai IntRegs:$addr, 0, - (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), + (v16i32 (V6_vandqrt (v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>; -def : Pat <(v512i1 (load (i32 IntRegs:$addr))), - (v512i1 (V6_vandvrt +def : Pat <(v64i1 (load (i32 IntRegs:$addr))), + (v64i1 (V6_vandvrt (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; -def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), +def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)), (V6_vS32b_ai IntRegs:$addr, 0, - (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), + (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>; -def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), - (v1024i1 (V6_vandvrt +def : Pat <(v128i1 (load (i32 IntRegs:$addr))), + (v128i1 (V6_vandvrt (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; } diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index ffaf71e23690e..2c1e0cadd9ee4 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -20,7 +20,6 @@ #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/ScalarEvolution.h" -#include "llvm/Analysis/ScalarEvolutionExpander.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/ValueTracking.h" @@ -57,6 +56,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" #include <algorithm> #include <array> #include <cassert> diff --git a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp index d1a153920e5e0..188d91355a35e 100644 --- a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -51,7 +51,7 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, RelocationType = MCSymbolRefExpr::VK_None; break; case HexagonII::MO_PCREL: - RelocationType = MCSymbolRefExpr::VK_Hexagon_PCREL; + RelocationType = MCSymbolRefExpr::VK_PCREL; break; case HexagonII::MO_GOT: RelocationType = MCSymbolRefExpr::VK_GOT; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index 2961e16cc9dc2..89ef5c2a891db 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -30,6 +30,9 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo { unsigned StackAlignBaseVReg = 0; // Aligned-stack base register (virtual) unsigned StackAlignBasePhysReg = 0; // (physical) int VarArgsFrameIndex; + int RegSavedAreaStartFrameIndex; + int FirstNamedArgFrameIndex; + int LastNamedArgFrameIndex; bool HasClobberLR = false; bool HasEHReturn = false; std::map<const MachineInstr*, unsigned> PacketInfo; @@ -46,6 +49,15 @@ public: void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; } int getVarArgsFrameIndex() { return VarArgsFrameIndex; } + void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;} + int getRegSavedAreaStartFrameIndex() { return RegSavedAreaStartFrameIndex; } + + void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; } + int getFirstNamedArgFrameIndex() { return FirstNamedArgFrameIndex; } + + void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; } + int getLastNamedArgFrameIndex() { return LastNamedArgFrameIndex; } + void setStartPacket(MachineInstr* MI) { PacketInfo[MI] |= Hexagon::StartPacket; } diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index e3579dfa9ba97..8dc1113194a85 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -291,7 +291,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, // at machine code level, we don't need this, but if we decide // to move new value jump prior to RA, we would be needing this. MachineRegisterInfo &MRI = MF.getRegInfo(); - if (secondReg && !Register::isPhysicalRegister(cmpOp2)) { + if (!Register::isPhysicalRegister(cmpOp2)) { MachineInstr *def = MRI.getVRegDef(cmpOp2); if (def->getOpcode() == TargetOpcode::COPY) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 886034d9601ac..c718e5f2d9fbe 100644 --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -12,9 +12,6 @@ #include "HexagonInstrInfo.h" #include "HexagonSubtarget.h" #include "MCTargetDesc/HexagonBaseInfo.h" -#include "RDFGraph.h" -#include "RDFLiveness.h" -#include "RDFRegisters.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/StringRef.h" @@ -27,6 +24,9 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" +#include "llvm/CodeGen/RDFRegisters.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/InitializePasses.h" #include "llvm/MC/MCInstrDesc.h" @@ -561,6 +561,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); MIB.add(OldMI->getOperand(3)); OpStart = 4; + Changed = true; } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) { short NewOpCode = HII->changeAddrMode_io_abs(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -570,10 +571,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); MIB.add(OldMI->getOperand(2)); OpStart = 3; + Changed = true; } - Changed = true; - LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -582,12 +581,14 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 3; Changed = true; + } + if (Changed) { LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); - } - if (Changed) + for (unsigned i = OpStart; i < OpEnd; ++i) MIB.add(OldMI->getOperand(i)); + } return Changed; } diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index cf711058823cd..cc10627955fb0 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -362,6 +362,16 @@ def Rol: pf2<rotl>; // --(1) Immediate ------------------------------------------------------- // +def Imm64Lo: SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), + SDLoc(N), MVT::i32); +}]>; +def Imm64Hi: SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), + SDLoc(N), MVT::i32); +}]>; + + def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; @@ -389,7 +399,10 @@ def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; def: Pat<(i1 0), (PS_false)>; def: Pat<(i1 1), (PS_true)>; -def: Pat<(i64 imm:$v), (CONST64 imm:$v)>; +def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, + Requires<[UseSmallData,NotOptTinyCore]>; +def: Pat<(i64 imm:$v), + (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; def ftoi : SDNodeXForm<fpimm, [{ APInt I = N->getValueAPF().bitcastToAPInt(); @@ -923,6 +936,13 @@ let AddedComplexity = 100 in { defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; } +let AddedComplexity = 100, Predicates = [HasV67] in { + defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; + defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; + defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; + defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; +} + defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setgt, v8i1, V8I8>; defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setge, v8i1, V8I8>; defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setgt, v4i1, V4I16>; @@ -1075,7 +1095,7 @@ def Divu64_8: SDNodeXForm<imm, [{ // Special cases: let AddedComplexity = 100 in { def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), - (A2_combine_hl I32:$Rs, I32:$Rt)>; + (A2_combine_lh I32:$Rs, I32:$Rt)>; def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; } @@ -1109,7 +1129,7 @@ def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), // Special cases: let AddedComplexity = 100 in { def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), - (A2_combine_hl I32:$Rs, I32:$Rt)>; + (A2_combine_lh I32:$Rs, I32:$Rt)>; def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; } @@ -1231,7 +1251,7 @@ class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; -let AddedComplexity = 200 in { +let AddedComplexity = 200, Predicates = [UseCompound] in { def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; @@ -1408,6 +1428,26 @@ let Predicates = [HasV66] in { def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; } +def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), + (F2_dfmpyhh + (F2_dfmpylh + (F2_dfmpylh + (F2_dfmpyll $Rs, $Rt), + $Rs, $Rt), + $Rt, $Rs), + $Rs, $Rt)>; + +let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { + def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; +} +let Predicates = [HasV67] in { + def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; + def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; + + def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), + (F2_dfmpyfix $Rt, $Rs))>; +} + // In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, // over add-add with individual multiplies as inputs. let AddedComplexity = 10 in { @@ -1510,7 +1550,7 @@ let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. // S4_addaddi and S4_subaddi don't have tied operands, so give them // a bit of preference. -let AddedComplexity = 30 in { +let AddedComplexity = 30, Predicates = [UseCompound] in { def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), @@ -1523,8 +1563,10 @@ let AddedComplexity = 30 in { (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; } +let Predicates = [UseCompound] in def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; + def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), @@ -1625,7 +1667,7 @@ def : Pat <(mulhs I64:$Rss, I64:$Rtt), // will put the immediate addend into a register, while these instructions will // use it directly. Such a construct does not appear in the middle of a gep, // where M2_macsip would be preferable. -let AddedComplexity = 20 in { +let AddedComplexity = 20, Predicates = [UseCompound] in { def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), @@ -1633,13 +1675,14 @@ let AddedComplexity = 20 in { } // Keep these instructions less preferable to M2_macsip/M2_macsin. -def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), - (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; -def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), - (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; -def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), - (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; - +let Predicates = [UseCompound] in { + def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), + (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; + def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), + (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; + def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), + (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; +} def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; @@ -1648,7 +1691,6 @@ def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; - def: Pat<(mul V2I32:$Rs, V2I32:$Rt), (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index 0ccfe64ad1e55..d0b02f035d1ea 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -45,7 +45,7 @@ #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/IR/Constants.h" -#include "llvm/PassSupport.h" +#include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index d2b6d64e3c92d..20c939577586e 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -112,7 +112,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, opExtendable = 0, hasSideEffects = 0 in class LOOP_iBase<string mnemonic, InstHexagon rootInst> : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2), - #mnemonic#"($offset,#$src2)", + mnemonic#"($offset,#$src2)", [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon { bits<9> offset; bits<10> src2; @@ -132,7 +132,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, opExtendable = 0, hasSideEffects = 0 in class LOOP_rBase<string mnemonic, InstHexagon rootInst> : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2), - #mnemonic#"($offset,$src2)", + mnemonic#"($offset,$src2)", [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon { bits<9> offset; bits<5> src2; @@ -490,7 +490,7 @@ def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst), A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon; // Hexagon doesn't have a vector multiply with C semantics. -// Instead, generate a pseudo instruction that gets expaneded into two +// Instead, generate a pseudo instruction that gets expanded into two // scalar MPYI instructions. // This is expanded by ExpandPostRAPseudos. let isPseudo = 1 in @@ -527,13 +527,15 @@ multiclass NewCircularLoad<RegisterClass RC, MemAccessSize MS> { let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS], addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in { + // Use timing class of L2_loadrb_pci. def NAME#_pci : LDInst<(outs RC:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs), - ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e93a3d71>; + ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_5ceb2f9e>; + // Use timing class of L2_loadrb_pcr. def NAME#_pcr : LDInst<(outs RC:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs), - ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_44d3da28>; + ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_075c8dd8>; } } @@ -548,13 +550,15 @@ multiclass NewCircularStore<RegisterClass RC, MemAccessSize MS> { let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS], addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in { + // Use timing class of S2_storerb_pci. def NAME#_pci : STInst<(outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs), - ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e86aa961>; + ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_b4dc7630>; + // Use timing class of S2_storerb_pcr. def NAME#_pcr : STInst<(outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs), - ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_da97ee82>; + ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_a2b365d2>; } } diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index 517ad1c6ee7b4..f26e23befde21 100644 --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -11,9 +11,6 @@ #include "MCTargetDesc/HexagonBaseInfo.h" #include "RDFCopy.h" #include "RDFDeadCode.h" -#include "RDFGraph.h" -#include "RDFLiveness.h" -#include "RDFRegisters.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetVector.h" @@ -24,6 +21,9 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" +#include "llvm/CodeGen/RDFRegisters.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index d55aeaf10852d..52f247977094b 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -172,6 +172,13 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) Reserved.set(Hexagon::C8); Reserved.set(Hexagon::USR_OVF); + // Leveraging these registers will require more work to recognize + // the new semantics posed, Hi/LoVec patterns, etc. + // Note well: if enabled, they should be restricted to only + // where `HST.useHVXOps() && HST.hasV67Ops()` is true. + for (auto Reg : Hexagon_MC::GetVectRegRev()) + Reserved.set(Reg); + if (MF.getSubtarget<HexagonSubtarget>().hasReservedR19()) Reserved.set(Hexagon::R19); @@ -196,7 +203,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, auto &HII = *HST.getInstrInfo(); auto &HFI = *HST.getFrameLowering(); - unsigned BP = 0; + Register BP; int FI = MI.getOperand(FIOp).getIndex(); // Select the base pointer (BP) and calculate the actual offset from BP // to the beginning of the object at index FI. diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h index fc166b5a34109..52d15da3bcb53 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -56,10 +56,6 @@ public: /// Returns true if the frame pointer is valid. bool useFPForScavengingIndex(const MachineFunction &MF) const override; - bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { - return true; - } - bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index c23b837bb62fc..49428db223a1f 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -18,6 +18,12 @@ let Namespace = "Hexagon" in { let HWEncoding{4-0} = num; } + // These registers are used to preserve a distinction between + // vector register pairs of differing order. + class HexagonFakeReg<string n> : Register<n> { + let isArtificial = 1; + } + class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, list<string> alt = []> : RegisterWithSubRegs<n, subregs> { @@ -30,6 +36,13 @@ let Namespace = "Hexagon" in { class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt>; + // Rp - false/pseudo registers. These registers are used + // to provide a distinct set of aliases for both styles of vector + // register pairs without encountering subregister indexing constraints. + class R_fake<string n> : + HexagonFakeReg<n>; + + // Rf - 32-bit floating-point registers. class Rf<bits<5> num, string n> : HexagonReg<num, n>; @@ -81,6 +94,7 @@ let Namespace = "Hexagon" in { def isub_hi : SubRegIndex<32, 32>; def vsub_lo : SubRegIndex<512>; def vsub_hi : SubRegIndex<512, 512>; + def vsub_fake: SubRegIndex<512>; def wsub_lo : SubRegIndex<1024>; def wsub_hi : SubRegIndex<1024, 1024>; def subreg_overflow : SubRegIndex<1, 0>; @@ -183,27 +197,49 @@ let Namespace = "Hexagon" in { foreach i = 0-31 in { def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; + def VF#i : R_fake<"__"#!add(i,999999)>, DwarfRegNum<[!add(i, 999999)]>; + def VFR#i : R_fake<"__"#!add(i,9999999)>, DwarfRegNum<[!add(i, 9999999)]>; } def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; // Aliases of the V* registers used to hold double vec values. - let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in { - def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>; - def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>; - def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>; - def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>; - def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>; - def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>; - def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>; - def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>; - def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>; - def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>; - def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>; - def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>; - def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>; - def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>; - def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>; - def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>; + let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { + def W0 : Rd< 0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>; + def W1 : Rd< 2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>; + def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>; + def W3 : Rd< 6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>; + def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>; + def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>; + def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>; + def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>; + def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>; + def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>; + def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>; + def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>; + def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>; + def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>; + def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>; + def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>; + } + + // Reverse Aliases of the V* registers used to hold double vec values. + let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { + def WR0 : Rd< 1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>; + def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>; + def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>; + def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>; + def WR4 : Rd< 9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>; + def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>; + def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>; + def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>; + def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>; + def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>; + def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>; + def WR11: Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>; + def WR12: Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>; + def WR13: Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>; + def WR14: Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>; + def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>; } // Aliases of the V* registers used to hold quad vec values. @@ -283,7 +319,7 @@ let Namespace = "Hexagon" in { // HVX types def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v512i1, v1024i1, v512i1]>; + [v64i1, v128i1, v64i1]>; def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], [v64i8, v128i8, v64i8]>; def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], @@ -314,15 +350,15 @@ def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512, } def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024, - (add (sequence "W%u", 0, 15))> { + (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> { let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; } -def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 512, +def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 128, (add Q0, Q1, Q2, Q3)> { let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], - [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; + [RegInfo<64,512,512>, RegInfo<128,1024,1024>, RegInfo<64,512,512>]>; } def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048, @@ -365,6 +401,10 @@ def CtrRegs : RegisterClass<"Hexagon", [i32], 32, FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, M0, M1, USR)>; +let Size = 64 in +def VectRegRev : RegisterClass<"Hexagon", [i64], 64, + (add (sequence "WR%u", 0, 15))>; + let isAllocatable = 0 in def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; diff --git a/llvm/lib/Target/Hexagon/HexagonSchedule.td b/llvm/lib/Target/Hexagon/HexagonSchedule.td index 0834e90004606..5efd02ada54cf 100644 --- a/llvm/lib/Target/Hexagon/HexagonSchedule.td +++ b/llvm/lib/Target/Hexagon/HexagonSchedule.td @@ -56,37 +56,15 @@ def tc_ENDLOOP : InstrItinClass; include "HexagonDepIICScalar.td" include "HexagonDepIICHVX.td" -//===----------------------------------------------------------------------===// -// V5 Machine Info + -//===----------------------------------------------------------------------===// - include "HexagonScheduleV5.td" - -// V55 Machine Info + include "HexagonScheduleV55.td" -//===----------------------------------------------------------------------===// -// V60 Machine Info - -//===----------------------------------------------------------------------===// - include "HexagonIICScalar.td" include "HexagonIICHVX.td" include "HexagonScheduleV60.td" -//===----------------------------------------------------------------------===// -// V62 Machine Info + -//===----------------------------------------------------------------------===// - include "HexagonScheduleV62.td" - -//===----------------------------------------------------------------------===// -// V65 Machine Info + -//===----------------------------------------------------------------------===// - include "HexagonScheduleV65.td" - -//===----------------------------------------------------------------------===// -// V66 Machine Info + -//===----------------------------------------------------------------------===// - include "HexagonScheduleV66.td" +include "HexagonScheduleV67.td" +include "HexagonScheduleV67T.td" diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV67.td b/llvm/lib/Target/Hexagon/HexagonScheduleV67.td new file mode 100644 index 0000000000000..4f9d861a55048 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV67.td @@ -0,0 +1,39 @@ +//=-HexagonScheduleV67.td - HexagonV67 Scheduling Definitions *- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// +// ScalarItin and HVXItin contain some old itineraries +// still used by a handful of instructions. Hopefully, we will be able +// to get rid of them soon. + +def HexagonV67ItinList : DepScalarItinV66, ScalarItin, + DepHVXItinV66, HVXItin, PseudoItin { + list<InstrItinData> ItinList = + !listconcat(DepScalarItinV66_list, ScalarItin_list, + DepHVXItinV66_list, HVXItin_list, PseudoItin_list); +} + +def HexagonItinerariesV67 : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM, CVI_ZW], + [Hex_FWD, HVX_FWD], + HexagonV67ItinList.ItinList>; + +def HexagonModelV67 : SchedMachineModel { + // Max issue per cycle == bundle width. + let IssueWidth = 4; + let Itineraries = HexagonItinerariesV67; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V67 Resource Definitions - +//===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV67T.td b/llvm/lib/Target/Hexagon/HexagonScheduleV67T.td new file mode 100644 index 0000000000000..f2bcb1e7256c3 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV67T.td @@ -0,0 +1,61 @@ +//=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +class HexagonV67TPseudoItin { + list<InstrItinData> V67TPseudoItin_list = [ + InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], + [2, 1, 1]>, + InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> + ]; +} + +// V67TItin_list and HVXItin contain some old itineraries +// still used by a handful of instructions. Hopefully, we will be able to +// get rid of them soon. +def HexagonV67TItinList : DepScalarItinV67T, + DepHVXItinV67, HVXItin, HexagonV67TPseudoItin { + list<InstrItinData> V67TItin_list = [ + InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>], + [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>], + [1, 1, 3, 3], + [Hex_FWD, Hex_FWD]> + ]; + + list<InstrItinData> ItinList = + !listconcat(DepScalarItinV67T_list, + DepHVXItinV67_list, V67TItin_list, + HVXItin_list, V67TPseudoItin_list); +} + +def HexagonItinerariesV67T : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM, CVI_ZW], + [Hex_FWD, HVX_FWD], + HexagonV67TItinList.ItinList>; + + +def HexagonModelV67T : SchedMachineModel { + let IssueWidth = 3; + let Itineraries = HexagonItinerariesV67T; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V67 Tiny Core Resource Definitions - +//===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp index c5ba7ced4c308..1b724e8fcae91 100644 --- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp @@ -18,10 +18,10 @@ using namespace llvm; SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, + SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); - if (AlwaysInline || (Align & 0x3) != 0 || !ConstantSize) + if (AlwaysInline || Alignment < Align(4) || !ConstantSize) return SDValue(); uint64_t SizeVal = ConstantSize->getZExtValue(); diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h index af8b8318b059e..0d3b1725d1bc4 100644 --- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h @@ -23,8 +23,8 @@ public: SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVolatile, - bool AlwaysInline, + SDValue Size, Align Alignment, + bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override; }; diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index d80e0ed50c931..b45d871e04d6e 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -504,7 +504,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L, // Get the registers on which the loop controlling compare instruction // depends. - unsigned CmpR1 = 0, CmpR2 = 0; + Register CmpR1, CmpR2; const MachineInstr *CmpI = MRI->getVRegDef(PR); while (CmpI->getOpcode() == Hexagon::C2_not) CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); @@ -688,11 +688,12 @@ void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI, for (auto &MO : MI->memoperands()) { const MachinePointerInfo &Ptr = MO->getPointerInfo(); MachineMemOperand::Flags F = MO->getFlags(); - int A = MO->getAlignment(); + Align A = MO->getAlign(); - auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, A); + auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A); LowI->addMemOperand(MF, Tmp1); - auto *Tmp2 = MF.getMachineMemOperand(Ptr, F, 4/*size*/, std::min(A, 4)); + auto *Tmp2 = + MF.getMachineMemOperand(Ptr, F, 4 /*size*/, std::min(A, Align(4))); HighI->addMemOperand(MF, Tmp2); } } diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp index aab37393ed365..2c4007145bd0d 100644 --- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -314,7 +314,7 @@ bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin, MachineInstr *FirstMI = *Begin; assert(!FirstMI->memoperands_empty() && "Expecting some memory operands"); const MachineMemOperand &FirstMMO = getStoreTarget(FirstMI); - unsigned Alignment = FirstMMO.getAlignment(); + unsigned Alignment = FirstMMO.getAlign().value(); unsigned SizeAccum = FirstMMO.getSize(); unsigned FirstOffset = getStoreOffset(FirstMI); @@ -417,9 +417,8 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, DebugLoc DL = OG.back()->getDebugLoc(); const MachineMemOperand &OldM = getStoreTarget(FirstSt); MachineMemOperand *NewM = - MF->getMachineMemOperand(OldM.getPointerInfo(), OldM.getFlags(), - TotalSize, OldM.getAlignment(), - OldM.getAAInfo()); + MF->getMachineMemOperand(OldM.getPointerInfo(), OldM.getFlags(), + TotalSize, OldM.getAlign(), OldM.getAAInfo()); if (Acc < 0x10000) { // Create mem[hw] = #Acc diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 6c706fea096bf..2b7e1bcba9a31 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -75,14 +75,14 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts")); - HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()), - CPUString(Hexagon_MC::selectHexagonCPU(CPU)), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), + CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))), + TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), RegInfo(getHwMode()), TLInfo(TM, *this), InstrItins(getInstrItineraryForCPU(CPUString)) { + Hexagon_MC::addArchSubtarget(this, FS); // Beware of the default constructor of InstrItineraryData: it will // reset all members to 0. assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized"); @@ -90,24 +90,16 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { - static std::map<StringRef, Hexagon::ArchEnum> CpuTable{ - {"generic", Hexagon::ArchEnum::V60}, - {"hexagonv5", Hexagon::ArchEnum::V5}, - {"hexagonv55", Hexagon::ArchEnum::V55}, - {"hexagonv60", Hexagon::ArchEnum::V60}, - {"hexagonv62", Hexagon::ArchEnum::V62}, - {"hexagonv65", Hexagon::ArchEnum::V65}, - {"hexagonv66", Hexagon::ArchEnum::V66}, - }; - - auto FoundIt = CpuTable.find(CPUString); - if (FoundIt != CpuTable.end()) - HexagonArchVersion = FoundIt->second; + Optional<Hexagon::ArchEnum> ArchVer = + Hexagon::GetCpu(Hexagon::CpuTable, CPUString); + if (ArchVer) + HexagonArchVersion = *ArchVer; else llvm_unreachable("Unrecognized Hexagon processor version"); UseHVX128BOps = false; UseHVX64BOps = false; + UseAudioOps = false; UseLongCalls = false; UseBSBScheduling = hasV60Ops() && EnableBSBSched; @@ -117,6 +109,13 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { if (OverrideLongCalls.getPosition()) UseLongCalls = OverrideLongCalls; + if (isTinyCore()) { + // Tiny core has a single thread, so back-to-back scheduling is enabled by + // default. + if (!EnableBSBSched.getPosition()) + UseBSBScheduling = false; + } + FeatureBitset Features = getFeatureBits(); if (HexagonDisableDuplex) setFeatureBits(Features.reset(Hexagon::FeatureDuplex)); @@ -316,13 +315,14 @@ bool HexagonSubtarget::useAA() const { /// Perform target specific adjustments to the latency of a schedule /// dependency. -void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, +void HexagonSubtarget::adjustSchedDependency(SUnit *Src, int SrcOpIdx, + SUnit *Dst, int DstOpIdx, SDep &Dep) const { - MachineInstr *SrcInst = Src->getInstr(); - MachineInstr *DstInst = Dst->getInstr(); if (!Src->isInstr() || !Dst->isInstr()) return; + MachineInstr *SrcInst = Src->getInstr(); + MachineInstr *DstInst = Dst->getInstr(); const HexagonInstrInfo *QII = getInstrInfo(); // Instructions with .new operands have zero latency. @@ -424,8 +424,17 @@ void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const { int DefIdx = -1; for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) { const MachineOperand &MO = SrcI->getOperand(OpNum); - if (MO.isReg() && MO.isDef() && MO.getReg() == DepR) - DefIdx = OpNum; + bool IsSameOrSubReg = false; + if (MO.isReg()) { + unsigned MOReg = MO.getReg(); + if (Register::isVirtualRegister(DepR)) { + IsSameOrSubReg = (MOReg == DepR); + } else { + IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); + } + if (MO.isDef() && IsSameOrSubReg) + DefIdx = OpNum; + } } assert(DefIdx >= 0 && "Def Reg not found in Src MI"); MachineInstr *DstI = Dst->getInstr(); diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 31157a0065d9b..de4f245519e43 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -13,7 +13,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H -#include "HexagonDepArch.h" +#include "HexagonArch.h" #include "HexagonFrameLowering.h" #include "HexagonISelLowering.h" #include "HexagonInstrInfo.h" @@ -45,14 +45,18 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool UseHVX64BOps = false; bool UseHVX128BOps = false; + bool UseAudioOps = false; + bool UseCompound = false; bool UseLongCalls = false; bool UseMemops = false; bool UsePackets = false; bool UseNewValueJumps = false; bool UseNewValueStores = false; bool UseSmallData = false; + bool UseUnsafeMath = false; bool UseZRegOps = false; + bool HasPreV65 = false; bool HasMemNoShuf = false; bool EnableDuplex = false; bool ReservedR19 = false; @@ -83,7 +87,14 @@ public: }; private: + enum HexagonProcFamilyEnum { Others, TinyCore }; + std::string CPUString; + Triple TargetTriple; + + // The following objects can use the TargetTriple, so they must be + // declared after it. + HexagonProcFamilyEnum HexagonProcFamily = Others; HexagonInstrInfo InstrInfo; HexagonRegisterInfo RegInfo; HexagonTargetLowering TLInfo; @@ -95,6 +106,11 @@ public: HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM); + const Triple &getTargetTriple() const { return TargetTriple; } + bool isEnvironmentMusl() const { + return TargetTriple.getEnvironment() == Triple::Musl; + } + /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. const InstrItineraryData *getInstrItineraryData() const override { @@ -157,18 +173,45 @@ public: bool hasV66OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V66; } + bool hasV67Ops() const { + return getHexagonArchVersion() >= Hexagon::ArchEnum::V67; + } + bool hasV67OpsOnly() const { + return getHexagonArchVersion() == Hexagon::ArchEnum::V67; + } + bool useAudioOps() const { return UseAudioOps; } + bool useCompound() const { return UseCompound; } bool useLongCalls() const { return UseLongCalls; } bool useMemops() const { return UseMemops; } bool usePackets() const { return UsePackets; } bool useNewValueJumps() const { return UseNewValueJumps; } bool useNewValueStores() const { return UseNewValueStores; } bool useSmallData() const { return UseSmallData; } + bool useUnsafeMath() const { return UseUnsafeMath; } bool useZRegOps() const { return UseZRegOps; } + bool isTinyCore() const { return HexagonProcFamily == TinyCore; } + bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; } + bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::NoArch; } + bool useHVXV60Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V60; + } + bool useHVXV62Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V62; + } + bool useHVXV65Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V65; + } + bool useHVXV66Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V66; + } + bool useHVXV67Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V67; + } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } @@ -186,7 +229,11 @@ public: // compiler time and will be removed eventually anyway. bool enableMachineSchedDefaultSched() const override { return false; } + // For use with PostRAScheduling: get the anti-dependence breaking that should + // be performed before post-RA scheduling. AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; } + /// True if the subtarget should run a scheduler after register + /// allocation. bool enablePostRAScheduler() const override { return true; } bool enableSubRegLiveness() const override; @@ -211,7 +258,8 @@ public: /// Perform target specific adjustments to the latency of a schedule /// dependency. - void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override; + void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, + SDep &Dep) const override; unsigned getVectorLength() const { assert(useHVXOps()); @@ -239,9 +287,6 @@ public: ArrayRef<MVT> ElemTypes = getHVXElementTypes(); if (IncludeBool && ElemTy == MVT::i1) { - // Special case for the v512i1, etc. - if (8*HwLen == NumElems) - return true; // Boolean HVX vector types are formed from regular HVX vector types // by replacing the element type with i1. for (MVT T : ElemTypes) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 9e9ce209a825b..3fe42ea13f51b 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -237,6 +237,14 @@ HexagonTargetMachine::getSubtargetImpl(const Function &F) const { std::string FS = !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString().str() : TargetFS; + // Append the preexisting target features last, so that +mattr overrides + // the "unsafe-fp-math" function attribute. + // Creating a separate target feature is not strictly necessary, it only + // exists to make "unsafe-fp-math" force creating a new subtarget. + + if (FnAttrs.hasFnAttribute("unsafe-fp-math") && + F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true") + FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS; auto &I = SubtargetMap[CPU + FS]; if (!I) { diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index fdcc41a4ca41d..cfc8ed813c92a 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -22,6 +22,7 @@ #include "llvm/IR/GlobalObject.h" #include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/SectionKind.h" @@ -112,7 +113,6 @@ static const char *getSectionSuffixForSize(unsigned Size) { void HexagonTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { TargetLoweringObjectFileELF::Initialize(Ctx, TM); - InitializeELF(TM.Options.UseInitArray); SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, @@ -308,7 +308,8 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, const ArrayType *ATy = cast<const ArrayType>(Ty); return getSmallestAddressableSize(ATy->getElementType(), GV, TM); } - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { const VectorType *PTy = cast<const VectorType>(Ty); return getSmallestAddressableSize(PTy->getElementType(), GV, TM); } @@ -323,6 +324,7 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, } case Type::FunctionTyID: case Type::VoidTyID: + case Type::BFloatTyID: case Type::X86_FP80TyID: case Type::FP128TyID: case Type::PPC_FP128TyID: diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h index b362825789503..550aac72346f3 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h @@ -13,6 +13,7 @@ #include "llvm/MC/MCSectionELF.h" namespace llvm { + class Type; class HexagonTargetObjectFile : public TargetLoweringObjectFileELF { public: diff --git a/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h b/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h index c5200b76933e9..a5b14a7e0764d 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h @@ -15,13 +15,13 @@ namespace llvm { class HexagonTargetStreamer : public MCTargetStreamer { public: HexagonTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} - virtual void EmitCodeAlignment(unsigned ByteAlignment, + virtual void emitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit = 0){}; virtual void emitFAlign(unsigned Size, unsigned MaxBytesToEmit){}; - virtual void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + virtual void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessGranularity){}; - virtual void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + virtual void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlign, unsigned AccessGranularity){}; }; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 4d4627cd20718..80c8736cb74a0 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -45,7 +45,7 @@ bool HexagonTTIImpl::useHVX() const { bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const { assert(VecTy->isVectorTy()); - if (cast<VectorType>(VecTy)->isScalable()) + if (isa<ScalableVectorType>(VecTy)) return false; // Avoid types like <2 x i32*>. if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy()) @@ -60,8 +60,8 @@ bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const { } unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const { - if (Ty->isVectorTy()) - return Ty->getVectorNumElements(); + if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) + return VTy->getNumElements(); assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) && "Expecting scalar type"); return 1; @@ -78,12 +78,17 @@ HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const { void HexagonTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP) { UP.Runtime = UP.Partial = true; +} + +void HexagonTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, + TTI::PeelingPreferences &PP) { + BaseT::getPeelingPreferences(L, SE, PP); // Only try to peel innermost loops with small runtime trip counts. if (L && L->empty() && canPeel(L) && SE.getSmallConstantTripCount(L) == 0 && SE.getSmallConstantMaxTripCount(L) > 0 && SE.getSmallConstantMaxTripCount(L) <= 5) { - UP.PeelCount = 2; + PP.PeelCount = 2; } } @@ -115,9 +120,10 @@ unsigned HexagonTTIImpl::getMinimumVF(unsigned ElemWidth) const { return (8 * ST.getVectorLength()) / ElemWidth; } -unsigned HexagonTTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, - bool Extract) { - return BaseT::getScalarizationOverhead(Ty, Insert, Extract); +unsigned HexagonTTIImpl::getScalarizationOverhead(VectorType *Ty, + const APInt &DemandedElts, + bool Insert, bool Extract) { + return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); } unsigned HexagonTTIImpl::getOperandsScalarizationOverhead( @@ -126,24 +132,18 @@ unsigned HexagonTTIImpl::getOperandsScalarizationOverhead( } unsigned HexagonTTIImpl::getCallInstrCost(Function *F, Type *RetTy, - ArrayRef<Type*> Tys) { - return BaseT::getCallInstrCost(F, RetTy, Tys); -} - -unsigned HexagonTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, - ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF) { - return BaseT::getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF); + ArrayRef<Type*> Tys, TTI::TargetCostKind CostKind) { + return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind); } -unsigned HexagonTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, - ArrayRef<Type*> Tys, FastMathFlags FMF, - unsigned ScalarizationCostPassed) { - if (ID == Intrinsic::bswap) { - std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, RetTy); +unsigned +HexagonTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) { + if (ICA.getID() == Intrinsic::bswap) { + std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ICA.getReturnType()); return LT.first + 2; } - return BaseT::getIntrinsicInstrCost(ID, RetTy, Tys, FMF, - ScalarizationCostPassed); + return BaseT::getIntrinsicInstrCost(ICA, CostKind); } unsigned HexagonTTIImpl::getAddressComputationCost(Type *Tp, @@ -154,14 +154,20 @@ unsigned HexagonTTIImpl::getAddressComputationCost(Type *Tp, unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, + TTI::TargetCostKind CostKind, const Instruction *I) { assert(Opcode == Instruction::Load || Opcode == Instruction::Store); + // TODO: Handle other cost kinds. + if (CostKind != TTI::TCK_RecipThroughput) + return 1; + if (Opcode == Instruction::Store) - return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); + return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, + CostKind, I); if (Src->isVectorTy()) { VectorType *VecTy = cast<VectorType>(Src); - unsigned VecWidth = VecTy->getBitWidth(); + unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize(); if (useHVX() && isTypeForHVX(VecTy)) { unsigned RegWidth = getRegisterBitWidth(true); assert(RegWidth && "Non-zero vector register width expected"); @@ -183,7 +189,7 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Cost = VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1; - // At this point unspecified alignment is considered as Align::None(). + // At this point unspecified alignment is considered as Align(1). const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8)); unsigned AlignWidth = 8 * BoundAlignment.value(); unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth; @@ -195,12 +201,16 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, return (3 - LogA) * Cost * NumLoads; } - return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); + return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, + CostKind, I); } -unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, - Type *Src, unsigned Alignment, unsigned AddressSpace) { - return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace); +unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, + Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) { + return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, + CostKind); } unsigned HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, @@ -208,57 +218,70 @@ unsigned HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, return 1; } -unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy, - Value *Ptr, bool VariableMask, unsigned Alignment) { +unsigned HexagonTTIImpl::getGatherScatterOpCost( + unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, + Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) { return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, - Alignment); + Alignment, CostKind, I); } -unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, - Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, - unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, - bool UseMaskForGaps) { +unsigned HexagonTTIImpl::getInterleavedMemoryOpCost( + unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, + Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, + bool UseMaskForCond, bool UseMaskForGaps) { if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps) return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, + CostKind, UseMaskForCond, UseMaskForGaps); return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, - nullptr); + CostKind); } unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, - Type *CondTy, const Instruction *I) { - if (ValTy->isVectorTy()) { + Type *CondTy, TTI::TargetCostKind CostKind, const Instruction *I) { + if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) { std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy); if (Opcode == Instruction::FCmp) return LT.first + FloatFactor * getTypeNumElements(ValTy); } - return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); + return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); } unsigned HexagonTTIImpl::getArithmeticInstrCost( - unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, + unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, + TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) { + // TODO: Handle more cost kinds. + if (CostKind != TTI::TCK_RecipThroughput) + return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, + Opd2Info, Opd1PropInfo, + Opd2PropInfo, Args, CxtI); + if (Ty->isVectorTy()) { std::pair<int, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty); if (LT.second.isFloatingPoint()) return LT.first + FloatFactor * getTypeNumElements(Ty); } - return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, + return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo, Args, CxtI); } unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, - Type *SrcTy, const Instruction *I) { + Type *SrcTy, TTI::TargetCostKind CostKind, const Instruction *I) { if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) { unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0; unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0; std::pair<int, MVT> SrcLT = TLI.getTypeLegalizationCost(DL, SrcTy); std::pair<int, MVT> DstLT = TLI.getTypeLegalizationCost(DL, DstTy); - return std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN); + unsigned Cost = std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN); + // TODO: Allow non-throughput costs that aren't binary. + if (CostKind != TTI::TCK_RecipThroughput) + return Cost == 0 ? 0 : 1; + return Cost; } return 1; } @@ -292,8 +315,10 @@ unsigned HexagonTTIImpl::getCacheLineSize() const { return ST.getL1CacheLineSize(); } -int HexagonTTIImpl::getUserCost(const User *U, - ArrayRef<const Value *> Operands) { +int +HexagonTTIImpl::getUserCost(const User *U, + ArrayRef<const Value *> Operands, + TTI::TargetCostKind CostKind) { auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool { if (!CI->isIntegerCast()) return false; @@ -315,7 +340,7 @@ int HexagonTTIImpl::getUserCost(const User *U, if (const CastInst *CI = dyn_cast<const CastInst>(U)) if (isCastFoldedIntoLoad(CI)) return TargetTransformInfo::TCC_Free; - return BaseT::getUserCost(U, Operands); + return BaseT::getUserCost(U, Operands, CostKind); } bool HexagonTTIImpl::shouldBuildLookupTables() const { diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index ace0d797bbdbd..5fe397486402e 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -64,6 +64,9 @@ public: void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP); + void getPeelingPreferences(Loop *L, ScalarEvolution &SE, + TTI::PeelingPreferences &PP); + /// Bias LSR towards creating post-increment opportunities. bool shouldFavorPostInc() const; @@ -101,34 +104,41 @@ public: return true; } - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); - unsigned getOperandsScalarizationOverhead(ArrayRef<const Value*> Args, - unsigned VF); - unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type*> Tys); - unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, - ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF); - unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, - ArrayRef<Type*> Tys, FastMathFlags FMF, - unsigned ScalarizationCostPassed = UINT_MAX); + unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, + bool Insert, bool Extract); + unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args, + unsigned VF); + unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type*> Tys, + TTI::TargetCostKind CostKind); + unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind); unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S); unsigned getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, + TTI::TargetCostKind CostKind, const Instruction *I = nullptr); - unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); + unsigned + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency); unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp); - unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, - bool VariableMask, unsigned Alignment); - unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, - unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, - unsigned AddressSpace, bool UseMaskForCond = false, - bool UseMaskForGaps = false); + unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, + const Value *Ptr, bool VariableMask, + Align Alignment, TTI::TargetCostKind CostKind, + const Instruction *I); + unsigned getInterleavedMemoryOpCost( + unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, + Align Alignment, unsigned AddressSpace, + TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, + bool UseMaskForCond = false, bool UseMaskForGaps = false); unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, - const Instruction *I); + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr); unsigned getArithmeticInstrCost( unsigned Opcode, Type *Ty, + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, @@ -136,16 +146,18 @@ public: ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr); unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::TargetCostKind CostKind, const Instruction *I = nullptr); unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); - unsigned getCFInstrCost(unsigned Opcode) { + unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { return 1; } /// @} - int getUserCost(const User *U, ArrayRef<const Value *> Operands); + int getUserCost(const User *U, ArrayRef<const Value *> Operands, + TTI::TargetCostKind CostKind); // Hexagon specific decision to generate a lookup table. bool shouldBuildLookupTables() const; diff --git a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp index b7d6dbe21c743..b5f06ebd3189f 100644 --- a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp @@ -15,7 +15,7 @@ #include "HexagonRegisterInfo.h" #include "HexagonSubtarget.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/PassSupport.h" +#include "llvm/Pass.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -107,7 +107,7 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { Register AR = MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseVReg(); std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap; - unsigned MaxAlign = 0; + MaybeAlign MaxAlign; bool Changed = false; for (MachineBasicBlock &MBB : MF) { @@ -137,14 +137,14 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { continue; const auto &VecRC = *MRI.getRegClass(VecR); - unsigned Align = HRI.getSpillAlignment(VecRC); - MaxAlign = std::max(MaxAlign, Align); + Align Alignment = HRI.getSpillAlign(VecRC); + MaxAlign = max(MaxAlign, Alignment); // Make sure this is not a spill slot: spill slots cannot be aligned // if there are variable-sized objects on the stack. They must be // accessible via FP (which is not aligned), because SP is unknown, // and AP may not be available at the location of the load/store. - int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Align, - /*isSpillSlot*/false); + int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, + /*isSpillSlot*/ false); MachineInstr *DefI = MRI.getVRegDef(VecR); MachineBasicBlock::iterator At = std::next(DefI->getIterator()); @@ -178,13 +178,13 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { } } - if (AR) { + if (AR && MaxAlign) { // Update the required stack alignment. MachineInstr *AlignaI = MRI.getVRegDef(AR); assert(AlignaI->getOpcode() == Hexagon::PS_aligna); MachineOperand &Op = AlignaI->getOperand(1); - if (MaxAlign > Op.getImm()) - Op.setImm(MaxAlign); + if (*MaxAlign > Op.getImm()) + Op.setImm(MaxAlign->value()); } return Changed; diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 36d71c41da543..fa1ba4f2e469b 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -242,6 +242,10 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { } } + // TinyCore with Duplexes: Translate to big-instructions. + if (HST.isTinyCoreWithDuplex()) + HII->translateInstrsForDup(MF, true); + // Loop over all of the basic blocks. for (auto &MB : MF) { auto Begin = MB.begin(), End = MB.end(); @@ -267,6 +271,10 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { } } + // TinyCore with Duplexes: Translate to tiny-instructions. + if (HST.isTinyCoreWithDuplex()) + HII->translateInstrsForDup(MF, false); + Packetizer.unpacketizeSoloInstrs(MF); return true; } @@ -1052,12 +1060,11 @@ bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI, // we ignore the instruction. const MCInstrDesc& TID = MI.getDesc(); auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass()); - unsigned FuncUnits = IS->getUnits(); - return !FuncUnits; + return !IS->getUnits(); } bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) { - // Ensure any bundles created by gather packetize remain seperate. + // Ensure any bundles created by gather packetize remain separate. if (MI.isBundle()) return true; @@ -1802,6 +1809,8 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, setmemShufDisabled(false); } + PacketHasDuplex = false; + PacketHasSLOT0OnlyInsn = false; ResourceTracker->clearResources(); LLVM_DEBUG(dbgs() << "End packet\n"); } @@ -1809,7 +1818,64 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) { if (Minimal) return false; - return !producesStall(MI); + + // Constrainst for not packetizing this MI with existing instructions in a + // packet. + // MI is a store instruction. + // CurrentPacketMIs has a SLOT0 only instruction with constraint + // A_RESTRICT_NOSLOT1_STORE/isRestrictNoSlot1Store. + if (MI.mayStore() && isPureSlot0InsnWithNoSlot1Store(MI)) + return false; + + if (producesStall(MI)) + return false; + + // If TinyCore with Duplexes is enabled, check if this MI can form a Duplex + // with any other instruction in the existing packet. + auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>(); + // Constraint 1: Only one duplex allowed per packet. + // Constraint 2: Consider duplex checks only if there is atleast one + // instruction in a packet. + // Constraint 3: If one of the existing instructions in the packet has a + // SLOT0 only instruction that can not be duplexed, do not attempt to form + // duplexes. (TODO: This will invalidate the L4_return* instructions to form a + // duplex) + if (HST.isTinyCoreWithDuplex() && CurrentPacketMIs.size() > 0 && + !PacketHasDuplex) { + // Check for SLOT0 only non-duplexable instruction in packet. + for (auto &MJ : CurrentPacketMIs) + PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ); + // Get the Big Core Opcode (dup_*). + int Opcode = HII->getDuplexOpcode(MI, false); + if (Opcode >= 0) { + // We now have an instruction that can be duplexed. + for (auto &MJ : CurrentPacketMIs) { + if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) { + PacketHasDuplex = true; + return true; + } + } + // If it can not be duplexed, check if there is a valid transition in DFA + // with the original opcode. + MachineInstr &MIRef = const_cast<MachineInstr &>(MI); + MIRef.setDesc(HII->get(Opcode)); + return ResourceTracker->canReserveResources(MIRef); + } + } + + return true; +} + +bool HexagonPacketizerList::isPureSlot0InsnWithNoSlot1Store( + const MachineInstr &MI) { + bool noSlot1Store = false; + bool isSlot0Only = false; + for (auto J : CurrentPacketMIs) { + noSlot1Store |= HII->isRestrictNoSlot1Store(*J); + isSlot0Only |= HII->isPureSlot0(*J); + } + + return (noSlot1Store && isSlot0Only); } // V60 forward scheduling. diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h index 943b9ac7ecc49..27a47220570a1 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -57,6 +57,13 @@ class HexagonPacketizerList : public VLIWPacketizerList { // instruction from the previous packet. bool PacketStalls = false; + // Set to true if the packet has a duplex pair of sub-instructions. + bool PacketHasDuplex = false; + + // Set to true if the packet has a instruction that can only be executed + // in SLOT0. + bool PacketHasSLOT0OnlyInsn = false; + protected: /// A handle to the branch probability pass. const MachineBranchProbabilityInfo *MBPI; @@ -149,6 +156,7 @@ protected: bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J); bool producesStall(const MachineInstr &MI); + bool isPureSlot0InsnWithNoSlot1Store(const MachineInstr &MI); }; } // end namespace llvm diff --git a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp index 65a8dcd75bdca..fbc5e5c344eda 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -71,9 +71,10 @@ public: char HexagonVectorPrint::ID = 0; static bool isVecReg(unsigned Reg) { - return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) - || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) - || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); + return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || + (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || + (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || + (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); } static std::string getStringReg(unsigned R) { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 8f1e5c1c3a979..e7069819fa575 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/EndianStream.h" #include "llvm/Support/TargetRegistry.h" #include <sstream> @@ -43,6 +44,7 @@ class HexagonAsmBackend : public MCAsmBackend { std::unique_ptr <MCInstrInfo> MCII; std::unique_ptr <MCInst *> RelaxTarget; MCInst * Extender; + unsigned MaxPacketSize; void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF, MCInst &HMB) const { @@ -62,7 +64,8 @@ public: StringRef CPU) : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU), relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), - Extender(nullptr) {} + Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU)) + {} std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override { @@ -648,11 +651,12 @@ public: llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override { assert(HexagonMCInstrInfo::isBundle(Inst) && "Hexagon relaxInstruction only works on bundles"); + MCInst Res; Res.setOpcode(Hexagon::BUNDLE); Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm())); // Copy the results into the bundle. @@ -676,6 +680,8 @@ public: // now copy over the original instruction(the one we may have extended) Res.addOperand(MCOperand::createInst(I.getInst())); } + + Inst = std::move(Res); (void)Update; assert(Update && "Didn't find relaxation target"); } @@ -685,7 +691,7 @@ public: ParseIn = 0x00004000, // In packet parse-bits. ParseEnd = 0x0000c000; // End of packet parse-bits. - while(Count % HEXAGON_INSTR_SIZE) { + while (Count % HEXAGON_INSTR_SIZE) { LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); @@ -693,11 +699,11 @@ public: OS << '\0'; } - while(Count) { + while (Count) { Count -= HEXAGON_INSTR_SIZE; // Close the packet whenever a multiple of the maximum packet size remains - uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))? - ParseIn: ParseEnd; + uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ? + ParseIn : ParseEnd; support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian); } return true; @@ -728,7 +734,8 @@ public: MCContext &Context = Asm.getContext(); auto &RF = cast<MCRelaxableFragment>(*K); auto &Inst = const_cast<MCInst &>(RF.getInst()); - while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) { + while (Size > 0 && + HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) { MCInst *Nop = new (Context) MCInst; Nop->setOpcode(Hexagon::A2_nop); Inst.addOperand(MCOperand::createInst(Nop)); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 3c64893bae45e..4125566bc58a3 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -27,11 +27,6 @@ namespace HexagonII { unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY; unsigned const TypeCVI_LAST = TypeCVI_ZW; - enum SubTarget { - HasV55SubT = 0x3c, - HasV60SubT = 0x38, - }; - enum AddrMode { NoAddrMode = 0, // No addressing mode Absolute = 1, // Absolute addressing mode @@ -165,6 +160,9 @@ namespace HexagonII { CVINewPos = 62, CVINewMask = 0x1, + + isCVIPos = 63, + isCVIMask = 0x1, }; // *** The code above must match HexagonInstrFormat*.td *** // diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp index cdbeae38b3a11..3dba6b07c4603 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp @@ -64,7 +64,7 @@ unsigned HexagonELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_HEX_IE_GOT_32; case MCSymbolRefExpr::VariantKind::VK_Hexagon_LD_GOT: return ELF::R_HEX_LD_GOT_32; - case MCSymbolRefExpr::VariantKind::VK_Hexagon_PCREL: + case MCSymbolRefExpr::VariantKind::VK_PCREL: return ELF::R_HEX_32_PCREL; case MCSymbolRefExpr::VariantKind::VK_TPREL: return ELF::R_HEX_TPREL_32; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index f3da675623209..e5e5d08937ef2 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -34,4 +34,5 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { UsesELFSectionDirectiveForBSS = true; ExceptionsType = ExceptionHandling::DwarfCFI; UseLogicalShr = false; + UseIntegratedAssembler = false; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index 8b262bd0248e0..fee1acdbbe8ab 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -81,6 +81,9 @@ void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, if (!MCSubRegIterator(*SRI, &RI).isValid()) // Skip super-registers used indirectly. Uses.insert(*SRI); + + if (HexagonMCInstrInfo::IsReverseVecRegPair(R)) + ReversePairs.insert(R); } void HexagonMCChecker::init(MCInst const &MCI) { @@ -133,6 +136,9 @@ void HexagonMCChecker::init(MCInst const &MCI) { if (R == Hexagon::C8) R = Hexagon::USR; + if (HexagonMCInstrInfo::IsReverseVecRegPair(R)) + ReversePairs.insert(R); + // Note register definitions, direct ones as well as indirect side-effects. // Super-registers are not tracked directly, but their components. for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); @@ -192,7 +198,7 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCRegisterInfo const &ri, bool ReportErrors) : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI), - ReportErrors(ReportErrors) { + ReportErrors(ReportErrors), ReversePairs() { init(); } @@ -200,7 +206,10 @@ HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other, MCSubtargetInfo const &STI, bool CopyReportErrors) : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII), - STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {} + STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false), + ReversePairs() { + init(); +} bool HexagonMCChecker::check(bool FullCheck) { bool chkP = checkPredicates(); @@ -218,8 +227,9 @@ bool HexagonMCChecker::check(bool FullCheck) { bool chkAXOK = checkAXOK(); bool chkCofMax1 = checkCOFMax1(); bool chkHWLoop = checkHWLoop(); + bool chkLegalVecRegPair = checkLegalVecRegPair(); bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && - chkAXOK && chkCofMax1 && chkHWLoop; + chkAXOK && chkCofMax1 && chkHWLoop && chkLegalVecRegPair; return chk; } @@ -381,7 +391,7 @@ bool HexagonMCChecker::checkPredicates() { for (const auto &I : NewPreds) { unsigned P = I; - if (!Defs.count(P) || LatePreds.count(P)) { + if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { // Error out if the new predicate register is not defined, // or defined "late" // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }"). @@ -729,3 +739,16 @@ void HexagonMCChecker::reportWarning(Twine const &Msg) { if (ReportErrors) Context.reportWarning(MCB.getLoc(), Msg); } + +bool HexagonMCChecker::checkLegalVecRegPair() { + const bool IsPermitted = STI.getFeatureBits()[Hexagon::ArchV67]; + const bool HasReversePairs = ReversePairs.size() != 0; + + if (!IsPermitted && HasReversePairs) { + for (auto R : ReversePairs) + reportError("register pair `" + Twine(RI.getName(R)) + + "' is not permitted for this architecture"); + return false; + } + return true; +} diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h index bc55ade9ccd78..00afdb664ba51 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h @@ -72,6 +72,10 @@ class HexagonMCChecker { using ReadOnlyIterator = std::set<unsigned>::iterator; std::set<unsigned> ReadOnly; + // Contains the vector-pair-registers with the even number + // first ("v0:1", e.g.) used/def'd in this packet. + std::set<unsigned> ReversePairs; + void init(); void init(MCInst const &); void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue); @@ -94,6 +98,7 @@ class HexagonMCChecker { bool checkAXOK(); bool checkHWLoop(); bool checkCOFMax1(); + bool checkLegalVecRegPair(); static void compoundRegisterMap(unsigned &); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 95e23c99868a4..24169c83bdb93 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -147,7 +147,7 @@ static const std::map<unsigned, std::vector<unsigned>> ExtFixups = { _, _, _, _, _, _, _, _, _ }}, - { MCSymbolRefExpr::VK_Hexagon_PCREL, + { MCSymbolRefExpr::VK_PCREL, { _, _, _, _, _, _, P(_6_PCREL_X), _, _, P(_9_X), _, _, @@ -311,7 +311,7 @@ static const std::map<unsigned, std::vector<unsigned>> StdFixups = { _, _, _, _, _, _, _, _, _ }}, - { MCSymbolRefExpr::VK_Hexagon_PCREL, + { MCSymbolRefExpr::VK_PCREL, { _, _, _, _, _, _, _, _, _, _, _, _, @@ -391,15 +391,9 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2) { - if (Consumer == Producer) - return true; - if (Consumer == Producer2) - return true; - // Calculate if we're a single vector consumer referencing a double producer - if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) - if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) - return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0); - return false; + return (Consumer == Producer) || (Consumer == Producer2) || + HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(Producer, + Consumer); } /// EncodeSingleInstruction - Emit a single @@ -497,7 +491,7 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_32_6_X }, { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_32_6_X }, { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_32_6_X }, - { MCSymbolRefExpr::VK_Hexagon_PCREL, fixup_Hexagon_B32_PCREL_X }, + { MCSymbolRefExpr::VK_PCREL, fixup_Hexagon_B32_PCREL_X }, { MCSymbolRefExpr::VK_Hexagon_GD_PLT, fixup_Hexagon_GD_PLT_B32_PCREL_X }, { MCSymbolRefExpr::VK_Hexagon_LD_PLT, fixup_Hexagon_LD_PLT_B32_PCREL_X }, }; @@ -735,7 +729,8 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, unsigned SOffset = 0; unsigned VOffset = 0; unsigned UseReg = MO.getReg(); - unsigned DefReg1, DefReg2; + unsigned DefReg1 = Hexagon::NoRegister; + unsigned DefReg2 = Hexagon::NoRegister; auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle); const MCOperand *I = Instrs.begin() + State.Index - 1; @@ -746,7 +741,8 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, if (HexagonMCInstrInfo::isImmext(Inst)) continue; - DefReg1 = DefReg2 = 0; + DefReg1 = Hexagon::NoRegister; + DefReg2 = Hexagon::NoRegister; ++SOffset; if (HexagonMCInstrInfo::isVector(MCII, Inst)) { // Vector instructions don't count scalars. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index 3cbb8600ce7aa..5154a0a1e46c1 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -10,12 +10,11 @@ // //===----------------------------------------------------------------------===// +#include "HexagonMCExpr.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -296,8 +295,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { DstReg = MCI.getOperand(1).getReg(); SrcReg = MCI.getOperand(0).getReg(); // [if ([!]p0[.new])] jumpr r31 - if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) && - (Hexagon::R31 == DstReg)) { + if ((Hexagon::P0 == SrcReg) && (Hexagon::R31 == DstReg)) { return HexagonII::HSIG_L2; } break; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp index a799f7f7c0b97..53e76a8b9ed77 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -58,7 +58,7 @@ HexagonMCELFStreamer::HexagonMCELFStreamer( : MCELFStreamer(Context, std::move(TAB), std::move(OW), std::move(Emitter)), MCII(createHexagonMCInstrInfo()) {} -void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, +void HexagonMCELFStreamer::emitInstruction(const MCInst &MCB, const MCSubtargetInfo &STI) { assert(MCB.getOpcode() == Hexagon::BUNDLE); assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE); @@ -71,7 +71,7 @@ void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, EmitSymbol(*MCI); } - MCObjectStreamer::EmitInstruction(MCB, STI); + MCObjectStreamer::emitInstruction(MCB, STI); } void HexagonMCELFStreamer::EmitSymbol(const MCInst &Inst) { @@ -110,9 +110,9 @@ void HexagonMCELFStreamer::HexagonMCEmitCommonSymbol(MCSymbol *Symbol, SwitchSection(&Section); if (ELFSymbol->isUndefined()) { - EmitValueToAlignment(ByteAlignment, 0, 1, 0); - EmitLabel(Symbol); - EmitZeros(Size); + emitValueToAlignment(ByteAlignment, 0, 1, 0); + emitLabel(Symbol); + emitZeros(Size); } // Update the maximum alignment of the section if necessary. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h index 6248bd25d433b..edf4ce29f908c 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h @@ -30,7 +30,7 @@ public: std::unique_ptr<MCCodeEmitter> Emitter, MCAssembler *Assembler); - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; void EmitSymbol(const MCInst &Inst); void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h index 59b1326adf0cc..e88f46a04dae4 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h @@ -12,7 +12,6 @@ #include "llvm/MC/MCExpr.h" namespace llvm { -class MCInst; class HexagonMCExpr : public MCTargetExpr { public: static HexagonMCExpr *create(MCExpr const *Expr, MCContext &Ctx); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 0750bfe74f760..f9f342a07f6dd 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -17,6 +17,7 @@ #include "MCTargetDesc/HexagonMCShuffler.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -119,10 +120,10 @@ size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) { return (1); } -bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, - MCSubtargetInfo const &STI, - MCContext &Context, MCInst &MCB, - HexagonMCChecker *Check) { +namespace { +bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, + MCContext &Context, MCInst &MCB, + HexagonMCChecker *Check) { // Check the bundle for errors. bool CheckOk = Check ? Check->check(false) : true; if (!CheckOk) @@ -132,9 +133,9 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, if (!HexagonDisableCompound) HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB); HexagonMCShuffle(Context, false, MCII, STI, MCB); + // Examine the packet and convert pairs of instructions to duplex // instructions when possible. - MCInst InstBundlePreDuplex = MCInst(MCB); if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) { SmallVector<DuplexCandidate, 8> possibleDuplexes; possibleDuplexes = @@ -146,8 +147,11 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, HexagonMCInstrInfo::padEndloop(MCB, Context); // If compounding and duplexing didn't reduce the size below // 4 or less we have a packet that is too big. - if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) + if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) { + if (Check) + Check->reportError("invalid instruction packet: out of slots"); return false; + } // Check the bundle for errors. CheckOk = Check ? Check->check(true) : true; if (!CheckOk) @@ -155,6 +159,27 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, HexagonMCShuffle(Context, true, MCII, STI, MCB); return true; } +} // namespace + +bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + MCContext &Context, MCInst &MCB, + HexagonMCChecker *Check, + bool AttemptCompatibility) { + auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI); + if (!AttemptCompatibility || ArchSTI == nullptr) + return canonicalizePacketImpl(MCII, STI, Context, MCB, Check); + + const MCRegisterInfo *RI = Context.getRegisterInfo(); + HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false); + HexagonMCChecker *BaseCheck = (Check == nullptr) ? &DefaultCheck : Check; + HexagonMCChecker PerfCheck(*BaseCheck, STI, false); + if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck)) + return true; + + HexagonMCChecker ArchCheck(*BaseCheck, *ArchSTI, true); + return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck); +} MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, @@ -394,6 +419,26 @@ unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII, return ((F >> HexagonII::TypePos) & HexagonII::TypeMask); } +/// Return the resources used by this instruction +unsigned HexagonMCInstrInfo::getCVIResources(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + MCInst const &MCI) { + + const InstrItinerary *II = STI.getSchedModel().InstrItineraries; + int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); + int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage; + + // HVX resources used are currenty located at the second to last stage. + // This could also be done with a linear search of the stages looking for: + // CVI_ALL, CVI_MPY01, CVI_XLSHF, CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE, + // CVI_ZW + unsigned Stage = II[SchedClass].LastStage - 1; + + if (Size < 2) + return 0; + return ((Stage + HexagonStages)->getUnits()); +} + /// Return the slots this instruction can execute out of unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, @@ -473,7 +518,7 @@ bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII, MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) { assert(isBundle(MCB)); - assert(Index < HEXAGON_PACKET_SIZE); + assert(Index < HEXAGON_PRESHUFFLE_PACKET_SIZE); return *MCB.getOperand(bundleInstructionsOffset + Index).getInst(); } @@ -613,6 +658,12 @@ bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII, return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask); } +bool HexagonMCInstrInfo::isNewValueStore(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask; +} + /// Return whether the operand is extendable. bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short O) { @@ -625,6 +676,45 @@ bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) { return (Flags & outerLoopMask) != 0; } +bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { + return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || + (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); +} + +bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { + return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); +} + +bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { + return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); +} + +std::pair<unsigned, unsigned> +HexagonMCInstrInfo::GetVecRegPairIndices(unsigned VecRegPair) { + assert(IsVecRegPair(VecRegPair) && + "VecRegPair must be a vector register pair"); + + const bool IsRev = IsReverseVecRegPair(VecRegPair); + const unsigned PairIndex = + 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0); + + return IsRev ? std::make_pair(PairIndex, PairIndex + 1) + : std::make_pair(PairIndex + 1, PairIndex); +} + +bool HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(unsigned Producer, + unsigned Consumer) { + if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) { + const unsigned ProdPairIndex = IsReverseVecRegPair(Producer) + ? Producer - Hexagon::WR0 + : Producer - Hexagon::W0; + const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1; + + return ConsumerSingleIndex == ProdPairIndex; + } + return false; +} + bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -655,8 +745,17 @@ bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII, !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask)); } -bool HexagonMCInstrInfo::isPredReg(unsigned Reg) { - return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0); +bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, unsigned Reg) { + auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID); + return PredRegClass.contains(Reg); +} + +bool HexagonMCInstrInfo::isPredRegister(MCInstrInfo const &MCII, + MCInst const &Inst, unsigned I) { + MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); + + return Inst.getOperand(I).isReg() && + Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID; } /// Return whether the insn can be packaged only with A and X-type insns. @@ -753,10 +852,8 @@ bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) { } bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) { - if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) && - (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST)) - return true; - return false; + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return (F >> HexagonII::isCVIPos) & HexagonII::isCVIMask; } int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) { @@ -802,6 +899,18 @@ bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) { return HExpr->s27_2_reloc(); } +unsigned HexagonMCInstrInfo::packetSizeSlots(MCSubtargetInfo const &STI) { + const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore]; + + return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE; +} + +unsigned HexagonMCInstrInfo::packetSize(StringRef CPU) { + return llvm::StringSwitch<unsigned>(CPU) + .Case("hexagonv67t", 3) + .Default(4); +} + void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) { MCInst Nop; Nop.setOpcode(Hexagon::A2_nop); @@ -836,6 +945,33 @@ bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) { return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask; } +bool HexagonMCInstrInfo::requiresSlot(MCSubtargetInfo const &STI, + MCInst const &MCI) { + const unsigned OpCode = MCI.getOpcode(); + const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore]; + const bool NoSlotReqd = Hexagon::A4_ext == OpCode || + (IsTiny && Hexagon::A2_nop == OpCode) || + (IsTiny && Hexagon::J4_hintjumpr == OpCode); + + return !NoSlotReqd; +} + +unsigned HexagonMCInstrInfo::slotsConsumed(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + MCInst const &MCI) { + unsigned slotsUsed = 0; + for (auto HMI : bundleInstructions(MCI)) { + MCInst const &MCI = *HMI.getInst(); + if (!requiresSlot(STI, MCI)) + continue; + if (isDuplex(MCII, MCI)) + slotsUsed += 2; + else + ++slotsUsed; + } + return slotsUsed; +} + void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate) { assert(Candidate.packetIndexI < MCB.size()); @@ -874,9 +1010,8 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer, unsigned Producer2) { // If we're a single vector consumer of a double producer, set subreg bit // based on if we're accessing the lower or upper register component - if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) - if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) - return (Consumer - Hexagon::V0) & 0x1; + if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) + return (Consumer - Hexagon::V0) & 0x1; if (Producer2 != Hexagon::NoRegister) return Consumer == Producer; return 0; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index 829f872c453e4..7b3c079880f8d 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -28,6 +28,7 @@ class MCContext; class MCExpr; class MCInstrDesc; class MCInstrInfo; +class MCRegisterInfo; class MCSubtargetInfo; class DuplexCandidate { @@ -91,7 +92,8 @@ size_t bundleSize(MCInst const &MCI); // Put the packet in to canonical form, compound, duplex, pad, and shuffle bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, - HexagonMCChecker *Checker); + HexagonMCChecker *Checker, + bool AttemptCompatibility = false); // Create a duplex instruction given the two subinsts MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, @@ -165,6 +167,11 @@ MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII, // Return the Hexagon ISA class for the insn. unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI); +/// Return the resources used by this instruction +unsigned getCVIResources(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + MCInst const &MCI); + /// Return the slots used by the insn. unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI); @@ -252,6 +259,8 @@ bool isMemReorderDisabled(MCInst const &MCI); // Return whether the insn is a new-value consumer. bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); +/// Return true if the operand is a new-value store insn. +bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI); bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short); // Can these two instructions be duplexed @@ -270,8 +279,11 @@ bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI); // Return whether the predicate sense is true bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI); -// Is this a predicate register -bool isPredReg(unsigned Reg); +// Return true if this is a scalar predicate register. +bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg); + +// Returns true if the Ith operand is a predicate register. +bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I); // Return whether the insn is a prefix. bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI); @@ -290,6 +302,21 @@ bool isVector(MCInstrInfo const &MCII, MCInst const &MCI); bool mustExtend(MCExpr const &Expr); bool mustNotExtend(MCExpr const &Expr); +// Returns true if this instruction requires a slot to execute. +bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI); + +unsigned packetSize(StringRef CPU); + +// Returns the maximum number of slots available in the given +// subtarget's packets. +unsigned packetSizeSlots(MCSubtargetInfo const &STI); + +// Returns the number of slots consumed by this packet, considering duplexed +// and compound instructions. +unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, + MCInst const &MCI); + + // Pad the bundle with nops to satisfy endloop requirements void padEndloop(MCInst &MCI, MCContext &Context); class PredicateInfo { @@ -324,6 +351,16 @@ bool subInstWouldBeExtended(MCInst const &potentialDuplex); unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2); +bool IsVecRegSingle(unsigned VecReg); +bool IsVecRegPair(unsigned VecReg); +bool IsReverseVecRegPair(unsigned VecReg); +bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer); + +/// Returns an ordered pair of the constituent register ordinals for +/// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1") +/// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }. +std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair); + // Attempt to find and replace compound pairs void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index f8dc0547baad9..7514d0e677449 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -10,13 +10,13 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/HexagonMCTargetDesc.h" -#include "HexagonDepArch.h" +#include "HexagonArch.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonMCELFStreamer.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" #include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" @@ -37,8 +37,10 @@ #include "llvm/Support/raw_ostream.h" #include <cassert> #include <cstdint> +#include <mutex> #include <new> #include <string> +#include <unordered_map> using namespace llvm; @@ -72,6 +74,10 @@ cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"), cl::init(false)); cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"), cl::init(false)); +cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"), + cl::init(false)); +cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"), + cl::init(false)); cl::opt<Hexagon::ArchEnum> EnableHVX("mhvx", @@ -81,6 +87,7 @@ cl::opt<Hexagon::ArchEnum> clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), + clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), // Sentinel for no value specified. clEnumValN(Hexagon::ArchEnum::Generic, "", "")), // Sentinel for flag not present. @@ -107,14 +114,22 @@ static StringRef HexagonGetArchVariant() { return "hexagonv65"; if (MV66) return "hexagonv66"; + if (MV67) + return "hexagonv67"; + if (MV67T) + return "hexagonv67t"; return ""; } StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { StringRef ArchV = HexagonGetArchVariant(); if (!ArchV.empty() && !CPU.empty()) { - if (ArchV != CPU) - report_fatal_error("conflicting architectures specified."); + // Tiny cores have a "t" suffix that is discarded when creating a secondary + // non-tiny subtarget. See: addArchSubtarget + std::pair<StringRef,StringRef> ArchP = ArchV.split('t'); + std::pair<StringRef,StringRef> CPUP = CPU.split('t'); + if (!ArchP.first.equals(CPUP.first)) + report_fatal_error("conflicting architectures specified."); return CPU; } if (ArchV.empty()) { @@ -127,6 +142,56 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; } +unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) { + enum { + CVI_NONE = 0, + CVI_XLANE = 1 << 0, + CVI_SHIFT = 1 << 1, + CVI_MPY0 = 1 << 2, + CVI_MPY1 = 1 << 3, + CVI_ZW = 1 << 4 + }; + + if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL || + ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM) + return (*Lanes = 4, CVI_XLANE); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 && + ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF) + return (*Lanes = 2, CVI_XLANE | CVI_MPY0); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01) + return (*Lanes = 2, CVI_MPY0); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF) + return (*Lanes = 2, CVI_XLANE); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE && + ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY1) + return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE && + ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT) + return (*Lanes = 1, CVI_XLANE | CVI_SHIFT); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY1) + return (*Lanes = 1, CVI_MPY0 | CVI_MPY1); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW) + return (*Lanes = 1, CVI_ZW); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE) + return (*Lanes = 1, CVI_XLANE); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT) + return (*Lanes = 1, CVI_SHIFT); + + return (*Lanes = 0, CVI_NONE); +} + + +namespace llvm { +namespace HexagonFUnits { +bool isSlot0Only(unsigned units) { + return HexagonItinerariesV62FU::SLOT0 == units; +} +} // namespace HexagonFUnits +} // namespace llvm + namespace { class HexagonTargetAsmStreamer : public HexagonTargetStreamer { @@ -186,7 +251,7 @@ public: } - void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize) override { HexagonMCELFStreamer &HexagonELFStreamer = @@ -195,7 +260,7 @@ public: AccessSize); } - void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize) override { HexagonMCELFStreamer &HexagonELFStreamer = @@ -225,9 +290,8 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, - MRI.getDwarfRegNum(Hexagon::R30, true), 0); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( + nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0); MAI->addInitialFrameState(Inst); return MAI; @@ -296,40 +360,51 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { case Hexagon::ArchEnum::V66: Result.push_back("+hvxv66"); break; + case Hexagon::ArchEnum::V67: + Result.push_back("+hvxv67"); + break; case Hexagon::ArchEnum::Generic:{ Result.push_back(StringSwitch<StringRef>(CPU) .Case("hexagonv60", "+hvxv60") .Case("hexagonv62", "+hvxv62") .Case("hexagonv65", "+hvxv65") - .Case("hexagonv66", "+hvxv66")); + .Case("hexagonv66", "+hvxv66") + .Case("hexagonv67", "+hvxv67") + .Case("hexagonv67t", "+hvxv67")); break; } case Hexagon::ArchEnum::NoArch: - // Sentinal if -mhvx isn't specified + // Sentinel if -mhvx isn't specified break; } return join(Result.begin(), Result.end(), ","); } } -static bool isCPUValid(std::string CPU) -{ - std::vector<std::string> table { - "generic", "hexagonv5", "hexagonv55", "hexagonv60", - "hexagonv62", "hexagonv65", "hexagonv66", - }; - - return std::find(table.begin(), table.end(), CPU) != table.end(); +static bool isCPUValid(const std::string &CPU) { + return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend(); } namespace { std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU, StringRef FS) { std::pair<std::string, std::string> Result; - Result.first = Hexagon_MC::selectHexagonCPU(CPU); + Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU)); Result.second = selectHexagonFS(Result.first, FS); return Result; } +std::mutex ArchSubtargetMutex; +std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>> + ArchSubtarget; +} // namespace + +MCSubtargetInfo const * +Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) { + std::lock_guard<std::mutex> Lock(ArchSubtargetMutex); + auto Existing = ArchSubtarget.find(std::string(STI->getCPU())); + if (Existing == ArchSubtarget.end()) + return nullptr; + return Existing->second.get(); } FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { @@ -338,7 +413,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // turns on hvxvNN, corresponding to the existing ArchVNN. FeatureBitset FB = S; unsigned CpuArch = ArchV5; - for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) { + for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, + ArchV5}) { if (!FB.test(F)) continue; CpuArch = F; @@ -353,7 +429,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { } bool HasHvxVer = false; for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, - ExtensionHVXV66}) { + ExtensionHVXV66, ExtensionHVXV67}) { if (!FB.test(F)) continue; HasHvxVer = true; @@ -366,6 +442,9 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // HasHvxVer is false, and UseHvx is true. switch (CpuArch) { + case ArchV67: + FB.set(ExtensionHVXV67); + LLVM_FALLTHROUGH; case ArchV66: FB.set(ExtensionHVXV66); LLVM_FALLTHROUGH; @@ -389,22 +468,52 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPUName = Features.first; StringRef ArchFS = Features.second; + MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); + if (X != nullptr && (CPUName == "hexagonv67t")) + addArchSubtarget(X, ArchFS); + + if (CPU.equals("help")) + exit(0); + if (!isCPUValid(CPUName.str())) { errs() << "error: invalid CPU \"" << CPUName.str().c_str() << "\" specified\n"; return nullptr; } - MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); if (HexagonDisableDuplex) { llvm::FeatureBitset Features = X->getFeatureBits(); X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex)); } X->setFeatureBits(completeHVXFeatures(X->getFeatureBits())); + + // The Z-buffer instructions are grandfathered in for current + // architectures but omitted for new ones. Future instruction + // sets may introduce new/conflicting z-buffer instructions. + const bool ZRegOnDefault = + (CPUName == "hexagonv67") || (CPUName == "hexagonv66"); + if (ZRegOnDefault) { + llvm::FeatureBitset Features = X->getFeatureBits(); + X->setFeatureBits(Features.set(Hexagon::ExtensionZReg)); + } + return X; } +void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI, + StringRef FS) { + assert(STI != nullptr); + if (STI->getCPU().contains("t")) { + auto ArchSTI = createHexagonMCSubtargetInfo( + STI->getTargetTriple(), + STI->getCPU().substr(0, STI->getCPU().size() - 1), FS); + std::lock_guard<std::mutex> Lock(ArchSubtargetMutex); + ArchSubtarget[std::string(STI->getCPU())] = + std::unique_ptr<MCSubtargetInfo const>(ArchSTI); + } +} + unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { static std::map<StringRef,unsigned> ElfFlags = { {"hexagonv5", ELF::EF_HEXAGON_MACH_V5}, @@ -413,6 +522,8 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { {"hexagonv62", ELF::EF_HEXAGON_MACH_V62}, {"hexagonv65", ELF::EF_HEXAGON_MACH_V65}, {"hexagonv66", ELF::EF_HEXAGON_MACH_V66}, + {"hexagonv67", ELF::EF_HEXAGON_MACH_V67}, + {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T}, }; auto F = ElfFlags.find(STI.getCPU()); @@ -420,6 +531,10 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { return F->second; } +llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() { + return makeArrayRef(VectRegRev); +} + namespace { class HexagonMCInstrAnalysis : public MCInstrAnalysis { public: @@ -437,6 +552,10 @@ public: bool evaluateBranch(MCInst const &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override { + if (!(isCall(Inst) || isUnconditionalBranch(Inst) || + isConditionalBranch(Inst))) + return false; + //assert(!HexagonMCInstrInfo::isBundle(Inst)); if(!HexagonMCInstrInfo::isExtendable(*Info, Inst)) return false; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 7b42460a2a1ce..5bf7c9a1a908d 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include <cstdint> #include <string> @@ -46,7 +47,6 @@ namespace llvm { -struct InstrItinerary; struct InstrStage; class FeatureBitset; class MCAsmBackend; @@ -60,8 +60,6 @@ class MCTargetOptions; class Target; class Triple; class StringRef; -class raw_ostream; -class raw_pwrite_stream; extern cl::opt<bool> HexagonDisableCompound; extern cl::opt<bool> HexagonDisableDuplex; @@ -78,7 +76,12 @@ namespace Hexagon_MC { /// etc. do not need to go through TargetRegistry. MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS); + MCSubtargetInfo const *getArchSubtarget(MCSubtargetInfo const *STI); + void addArchSubtarget(MCSubtargetInfo const *STI, + StringRef FS); unsigned GetELFFlags(const MCSubtargetInfo &STI); + + llvm::ArrayRef<MCPhysReg> GetVectRegRev(); } MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, @@ -94,6 +97,7 @@ std::unique_ptr<MCObjectTargetWriter> createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU); unsigned HexagonGetLastSlot(); +unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes); } // End llvm namespace diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 18c7790a17cc1..2788b86181e27 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -105,62 +105,30 @@ unsigned HexagonResource::setWeight(unsigned s) { return Weight; } -void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { - (*TUL)[HexagonII::TypeCVI_VA] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); - (*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VX_LATE] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2); - (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); - (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); - (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); - (*TUL)[HexagonII::TypeCVI_VS_VX] = UnitsAndLanes(CVI_XLANE | CVI_SHIFT, 1); - (*TUL)[HexagonII::TypeCVI_VINLANESAT] = - (CPU == "hexagonv60") - ? UnitsAndLanes(CVI_SHIFT, 1) - : UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VM_LD] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0); - (*TUL)[HexagonII::TypeCVI_VM_VP_LDU] = UnitsAndLanes(CVI_XLANE, 1); - (*TUL)[HexagonII::TypeCVI_VM_ST] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0); - (*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1); - (*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4); - (*TUL)[HexagonII::TypeCVI_GATHER] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_SCATTER] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_SCATTER_DV] = - UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); - (*TUL)[HexagonII::TypeCVI_SCATTER_NEW_ST] = - UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); - (*TUL)[HexagonII::TypeCVI_4SLOT_MPY] = UnitsAndLanes(CVI_XLANE, 4); - (*TUL)[HexagonII::TypeCVI_ZW] = UnitsAndLanes(CVI_ZW, 1); -} - -HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL, - MCInstrInfo const &MCII, unsigned s, +HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + unsigned s, MCInst const *id) : HexagonResource(s) { - unsigned T = HexagonMCInstrInfo::getType(MCII, *id); - if (TUL->count(T)) { - // For an HVX insn. - Valid = true; - setUnits((*TUL)[T].first); - setLanes((*TUL)[T].second); - setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); - setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); - } else { + const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id); + unsigned Lanes; + const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes); + + if (Units == 0 && Lanes == 0) { // For core insns. Valid = false; setUnits(0); setLanes(0); setLoad(false); setStore(false); + } else { + // For an HVX insn. + Valid = true; + setUnits(Units); + setLanes(Lanes); + setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); + setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); } } @@ -201,124 +169,293 @@ HexagonShuffler::HexagonShuffler(MCContext &Context, bool ReportErrors, MCSubtargetInfo const &STI) : Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) { reset(); - HexagonCVIResource::SetupTUL(&TUL, STI.getCPU()); } void HexagonShuffler::reset() { Packet.clear(); BundleFlags = 0; + CheckFailure = false; } void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender, unsigned S) { - HexagonInstr PI(&TUL, MCII, &ID, Extender, S); + HexagonInstr PI(MCII, STI, &ID, Extender, S); Packet.push_back(PI); } -static struct { - unsigned first; - unsigned second; -} jumpSlots[] = {{8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}}; -#define MAX_JUMP_SLOTS (sizeof(jumpSlots) / sizeof(jumpSlots[0])) -void HexagonShuffler::restrictSlot1AOK() { - bool HasRestrictSlot1AOK = false; - SMLoc RestrictLoc; - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &Inst = ISJ->getDesc(); - if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, Inst)) { - HasRestrictSlot1AOK = true; - RestrictLoc = Inst.getLoc(); - } - } - if (HasRestrictSlot1AOK) - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &Inst = ISJ->getDesc(); - unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); +static const unsigned Slot0Mask = 1 << 0; +static const unsigned Slot1Mask = 1 << 1; +static const unsigned Slot3Mask = 1 << 3; +static const unsigned slotSingleLoad = Slot0Mask; +static const unsigned slotSingleStore = Slot0Mask; + +void HexagonShuffler::restrictSlot1AOK(HexagonPacketSummary const &Summary) { + if (Summary.Slot1AOKLoc) + for (HexagonInstr &ISJ : insts()) { + MCInst const &Inst = ISJ.getDesc(); + const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); if (Type != HexagonII::TypeALU32_2op && Type != HexagonII::TypeALU32_3op && Type != HexagonII::TypeALU32_ADDI) { - unsigned Units = ISJ->Core.getUnits(); - if (Units & 2U) { + const unsigned Units = ISJ.Core.getUnits(); + + if (Units & Slot1Mask) { AppliedRestrictions.push_back(std::make_pair( Inst.getLoc(), "Instruction was restricted from being in slot 1")); - AppliedRestrictions.push_back( - std::make_pair(RestrictLoc, "Instruction can only be combine " - "with an ALU instruction in slot 1")); - ISJ->Core.setUnits(Units & ~2U); + AppliedRestrictions.push_back(std::make_pair( + *Summary.Slot1AOKLoc, "Instruction can only be combined " + "with an ALU instruction in slot 1")); + ISJ.Core.setUnits(Units & ~Slot1Mask); } } } } -void HexagonShuffler::restrictNoSlot1Store() { - bool HasRestrictNoSlot1Store = false; - SMLoc RestrictLoc; - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &Inst = ISJ->getDesc(); - if (HexagonMCInstrInfo::isRestrictNoSlot1Store(MCII, Inst)) { - HasRestrictNoSlot1Store = true; - RestrictLoc = Inst.getLoc(); +void HexagonShuffler::restrictNoSlot1Store( + HexagonPacketSummary const &Summary) { + // If this packet contains an instruction that bars slot-1 stores, + // we should mask off slot 1 from all of the store instructions in + // this packet. + + if (!Summary.NoSlot1StoreLoc) + return; + + bool AppliedRestriction = false; + + for (HexagonInstr &ISJ : insts()) { + MCInst const &Inst = ISJ.getDesc(); + if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { + unsigned Units = ISJ.Core.getUnits(); + if (Units & Slot1Mask) { + AppliedRestriction = true; + AppliedRestrictions.push_back(std::make_pair( + Inst.getLoc(), "Instruction was restricted from being in slot 1")); + ISJ.Core.setUnits(Units & ~Slot1Mask); + } } } - if (HasRestrictNoSlot1Store) { - bool AppliedRestriction = false; - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &Inst = ISJ->getDesc(); - if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { - unsigned Units = ISJ->Core.getUnits(); - if (Units & 2U) { - AppliedRestriction = true; - AppliedRestrictions.push_back(std::make_pair( - Inst.getLoc(), - "Instruction was restricted from being in slot 1")); - ISJ->Core.setUnits(Units & ~2U); + + if (AppliedRestriction) + AppliedRestrictions.push_back( + std::make_pair(*Summary.NoSlot1StoreLoc, + "Instruction does not allow a store in slot 1")); +} + +bool HexagonShuffler::applySlotRestrictions( + HexagonPacketSummary const &Summary) { + // These restrictions can modify the slot masks in the instructions + // in the Packet member. They should run unconditionally and their + // order does not matter. + restrictSlot1AOK(Summary); + restrictNoSlot1Store(Summary); + + permitNonSlot(); + + // These restrictions can modify the slot masks in the instructions + // in the Packet member, but they can also detect constraint failures + // which are fatal. + if (!CheckFailure) + restrictStoreLoadOrder(Summary); + if (!CheckFailure) + restrictBranchOrder(Summary); + if (!CheckFailure) + restrictPreferSlot3(Summary); + return !CheckFailure; +} + +void HexagonShuffler::restrictBranchOrder(HexagonPacketSummary const &Summary) { + // preserve branch order + const bool HasMultipleBranches = Summary.branchInsts.size() > 1; + if (!HasMultipleBranches) + return; + + if (Summary.branchInsts.size() > 2) { + reportError(Twine("too many branches in packet")); + return; + } + + const static std::pair<unsigned, unsigned> jumpSlots[] = { + {8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}}; + // try all possible choices + for (std::pair<unsigned, unsigned> jumpSlot : jumpSlots) { + // validate first jump with this slot rule + if (!(jumpSlot.first & Summary.branchInsts[0]->Core.getUnits())) + continue; + + // validate second jump with this slot rule + if (!(jumpSlot.second & Summary.branchInsts[1]->Core.getUnits())) + continue; + + // both valid for this configuration, set new slot rules + const HexagonPacket PacketSave = Packet; + Summary.branchInsts[0]->Core.setUnits(jumpSlot.first); + Summary.branchInsts[1]->Core.setUnits(jumpSlot.second); + + const bool HasShuffledPacket = tryAuction(Summary).hasValue(); + if (HasShuffledPacket) + return; + + // if yes, great, if not then restore original slot mask + // restore original values + Packet = PacketSave; + } + + reportError("invalid instruction packet: out of slots"); +} + + +void HexagonShuffler::permitNonSlot() { + for (HexagonInstr &ISJ : insts()) { + const bool RequiresSlot = HexagonMCInstrInfo::requiresSlot(STI, *ISJ.ID); + if (!RequiresSlot) + ISJ.Core.setAllUnits(); + } +} + +bool HexagonShuffler::ValidResourceUsage(HexagonPacketSummary const &Summary) { + Optional<HexagonPacket> ShuffledPacket = tryAuction(Summary); + + if (!ShuffledPacket) { + reportError("invalid instruction packet: slot error"); + return false; + } else { + Packet = *ShuffledPacket; + } + + // Verify the CVI slot subscriptions. + std::stable_sort(begin(), end(), HexagonInstr::lessCVI); + // create vector of hvx instructions to check + HVXInstsT hvxInsts; + hvxInsts.clear(); + for (const_iterator I = cbegin(); I != cend(); ++I) { + struct CVIUnits inst; + inst.Units = I->CVI.getUnits(); + inst.Lanes = I->CVI.getLanes(); + if (inst.Units == 0) + continue; // not an hvx inst or an hvx inst that doesn't uses any pipes + hvxInsts.push_back(inst); + } + + // if there are any hvx instructions in this packet, check pipe usage + if (hvxInsts.size() > 0) { + unsigned startIdx, usedUnits; + startIdx = usedUnits = 0x0; + if (!checkHVXPipes(hvxInsts, startIdx, usedUnits)) { + // too many pipes used to be valid + reportError(Twine("invalid instruction packet: slot error")); + return false; + } + } + return true; +} + +bool HexagonShuffler::restrictStoreLoadOrder( + HexagonPacketSummary const &Summary) { + // Modify packet accordingly. + // TODO: need to reserve slots #0 and #1 for duplex insns. + static const unsigned slotFirstLoadStore = Slot1Mask; + static const unsigned slotLastLoadStore = Slot0Mask; + unsigned slotLoadStore = slotFirstLoadStore; + + for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { + MCInst const &ID = ISJ->getDesc(); + + if (!ISJ->Core.getUnits()) + // Error if insn may not be executed in any slot. + return false; + + // A single load must use slot #0. + if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { + if (Summary.loads == 1 && Summary.loads == Summary.memory && + Summary.memops == 0) + // Pin the load to slot #0. + switch (ID.getOpcode()) { + case Hexagon::V6_vgathermw: + case Hexagon::V6_vgathermh: + case Hexagon::V6_vgathermhw: + case Hexagon::V6_vgathermwq: + case Hexagon::V6_vgathermhq: + case Hexagon::V6_vgathermhwq: + // Slot1 only loads + break; + default: + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); + break; + } + else if (Summary.loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf + // Loads must keep the original order ONLY if + // isMemReorderDisabled() == true + if (slotLoadStore < slotLastLoadStore) { + // Error if no more slots available for loads. + reportError("invalid instruction packet: too many loads"); + return false; + } + // Pin the load to the highest slot available to it. + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); + // Update the next highest slot available to loads. + slotLoadStore >>= 1; + } + } + + // A single store must use slot #0. + if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { + if (!Summary.store0) { + const bool PacketHasNoOnlySlot0 = + llvm::none_of(insts(), [&](HexagonInstr const &I) { + return I.Core.getUnits() == Slot0Mask && + I.ID->getOpcode() != ID.getOpcode(); + }); + const bool SafeToMoveToSlot0 = + (Summary.loads == 0) || + (!isMemReorderDisabled() && PacketHasNoOnlySlot0); + + if (Summary.stores == 1 && SafeToMoveToSlot0) + // Pin the store to slot #0 only if isMemReorderDisabled() == false + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); + else if (Summary.stores >= 1) { + if (slotLoadStore < slotLastLoadStore) { + // Error if no more slots available for stores. + reportError("invalid instruction packet: too many stores"); + return false; + } + // Pin the store to the highest slot available to it. + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); + // Update the next highest slot available to stores. + slotLoadStore >>= 1; } } + if (Summary.store1 && Summary.stores > 1) { + // Error if a single store with another store. + reportError("invalid instruction packet: too many stores"); + return false; + } } - if (AppliedRestriction) - AppliedRestrictions.push_back(std::make_pair( - RestrictLoc, "Instruction does not allow a store in slot 1")); } -} -void HexagonShuffler::applySlotRestrictions() { - restrictSlot1AOK(); - restrictNoSlot1Store(); + return true; } -/// Check that the packet is legal and enforce relative insn order. -bool HexagonShuffler::check() { - // Descriptive slot masks. - const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, - slotThree = 0x8, // slotFirstJump = 0x8, - slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1; - // Highest slots for branches and stores used to keep their original order. - // unsigned slotJump = slotFirstJump; - unsigned slotLoadStore = slotFirstLoadStore; - // Number of memory operations, loads, solo loads, stores, solo stores, single - // stores. - unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0; - unsigned NonZCVIloads = 0, AllCVIloads = 0, CVIstores = 0; - // Number of duplex insns - unsigned duplex = 0; - unsigned pSlot3Cnt = 0; - unsigned memops = 0; - iterator slot3ISJ = end(); - std::vector<iterator> foundBranches; - unsigned reservedSlots = 0; +HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() { + HexagonPacketSummary Summary = HexagonPacketSummary(); // Collect information from the insns in the packet. for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { MCInst const &ID = ISJ->getDesc(); + if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, ID)) + Summary.Slot1AOKLoc = ID.getLoc(); + if (HexagonMCInstrInfo::isRestrictNoSlot1Store(MCII, ID)) + Summary.NoSlot1StoreLoc = ID.getLoc(); + if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { - ++pSlot3Cnt; - slot3ISJ = ISJ; + ++Summary.pSlot3Cnt; + Summary.PrefSlot3Inst = ISJ; } - reservedSlots |= HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID); + Summary.ReservedSlotMask |= + HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID); switch (HexagonMCInstrInfo::getType(MCII, ID)) { case HexagonII::TypeS_2op: @@ -326,26 +463,27 @@ bool HexagonShuffler::check() { case HexagonII::TypeALU64: break; case HexagonII::TypeJ: - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); break; case HexagonII::TypeCVI_VM_VP_LDU: case HexagonII::TypeCVI_VM_LD: case HexagonII::TypeCVI_VM_TMP_LD: case HexagonII::TypeCVI_GATHER: + case HexagonII::TypeCVI_GATHER_DV: case HexagonII::TypeCVI_GATHER_RST: - ++NonZCVIloads; + ++Summary.NonZCVIloads; LLVM_FALLTHROUGH; case HexagonII::TypeCVI_ZW: - ++AllCVIloads; + ++Summary.AllCVIloads; LLVM_FALLTHROUGH; case HexagonII::TypeLD: - ++loads; - ++memory; + ++Summary.loads; + ++Summary.memory; if (ISJ->Core.getUnits() == slotSingleLoad || HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU) - ++load0; + ++Summary.load0; if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); break; case HexagonII::TypeCVI_VM_STU: case HexagonII::TypeCVI_VM_ST: @@ -355,266 +493,143 @@ bool HexagonShuffler::check() { case HexagonII::TypeCVI_SCATTER_RST: case HexagonII::TypeCVI_SCATTER_NEW_RST: case HexagonII::TypeCVI_SCATTER_NEW_ST: - ++CVIstores; + ++Summary.CVIstores; LLVM_FALLTHROUGH; case HexagonII::TypeST: - ++stores; - ++memory; + ++Summary.stores; + ++Summary.memory; if (ISJ->Core.getUnits() == slotSingleStore || HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_STU) - ++store0; + ++Summary.store0; break; case HexagonII::TypeV4LDST: - ++loads; - ++stores; - ++store1; - ++memops; - ++memory; + ++Summary.loads; + ++Summary.stores; + ++Summary.store1; + ++Summary.memops; + ++Summary.memory; break; case HexagonII::TypeNCJ: - ++memory; // NV insns are memory-like. - foundBranches.push_back(ISJ); + ++Summary.memory; // NV insns are memory-like. + Summary.branchInsts.push_back(ISJ); break; case HexagonII::TypeV2LDST: if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { - ++loads; - ++memory; + ++Summary.loads; + ++Summary.memory; if (ISJ->Core.getUnits() == slotSingleLoad || HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU) - ++load0; + ++Summary.load0; } else { assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()); - ++memory; - ++stores; + ++Summary.memory; + ++Summary.stores; } break; case HexagonII::TypeCR: // Legacy conditional branch predicated on a register. case HexagonII::TypeCJ: if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); break; case HexagonII::TypeDUPLEX: { - ++duplex; + ++Summary.duplex; MCInst const &Inst0 = *ID.getOperand(0).getInst(); MCInst const &Inst1 = *ID.getOperand(1).getInst(); if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) - foundBranches.push_back(ISJ); + Summary.branchInsts.push_back(ISJ); break; } } } - applySlotRestrictions(); + return Summary; +} +bool HexagonShuffler::ValidPacketMemoryOps( + HexagonPacketSummary const &Summary) const { // Check if the packet is legal. - const unsigned ZCVIloads = AllCVIloads - NonZCVIloads; + const unsigned ZCVIloads = Summary.AllCVIloads - Summary.NonZCVIloads; const bool ValidHVXMem = - NonZCVIloads <= 1 && ZCVIloads <= 1 && CVIstores <= 1; - if ((load0 > 1 || store0 > 1 || !ValidHVXMem) || - (duplex > 1 || (duplex && memory))) { - reportError(llvm::Twine("invalid instruction packet")); - return false; - } - - // Modify packet accordingly. - // TODO: need to reserve slots #0 and #1 for duplex insns. - bool bOnlySlot3 = false; - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &ID = ISJ->getDesc(); - - if (!ISJ->Core.getUnits()) { - // Error if insn may not be executed in any slot. - return false; - } - - // A single load must use slot #0. - if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { - if (loads == 1 && loads == memory && memops == 0) - // Pin the load to slot #0. - switch (ID.getOpcode()) { - case Hexagon::V6_vgathermw: - case Hexagon::V6_vgathermh: - case Hexagon::V6_vgathermhw: - case Hexagon::V6_vgathermwq: - case Hexagon::V6_vgathermhq: - case Hexagon::V6_vgathermhwq: - // Slot1 only loads - break; - default: - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); - break; - } - else if (loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf - // Loads must keep the original order ONLY if - // isMemReorderDisabled() == true - if (slotLoadStore < slotLastLoadStore) { - // Error if no more slots available for loads. - reportError( - llvm::Twine("invalid instruction packet: too many loads")); - return false; - } - // Pin the load to the highest slot available to it. - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); - // Update the next highest slot available to loads. - slotLoadStore >>= 1; - } - } + Summary.NonZCVIloads <= 1 && ZCVIloads <= 1 && Summary.CVIstores <= 1; + const bool InvalidPacket = + ((Summary.load0 > 1 || Summary.store0 > 1 || !ValidHVXMem) || + (Summary.duplex > 1 || (Summary.duplex && Summary.memory))); - // A single store must use slot #0. - if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { - if (!store0) { - if (stores == 1 && (loads == 0 || !isMemReorderDisabled())) - // Pin the store to slot #0 only if isMemReorderDisabled() == false - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); - else if (stores >= 1) { - if (slotLoadStore < slotLastLoadStore) { - // Error if no more slots available for stores. - reportError(Twine("invalid instruction packet: too many stores")); - return false; - } - // Pin the store to the highest slot available to it. - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); - // Update the next highest slot available to stores. - slotLoadStore >>= 1; - } - } - if (store1 && stores > 1) { - // Error if a single store with another store. - reportError(Twine("invalid instruction packet: too many stores")); - return false; - } - } - - // flag if an instruction requires to be in slot 3 - if (ISJ->Core.getUnits() == slotThree) - bOnlySlot3 = true; - - if (!ISJ->Core.getUnits()) { - // Error if insn may not be executed in any slot. - reportError(Twine("invalid instruction packet: out of slots")); - return false; - } - } - - // preserve branch order - bool validateSlots = true; - if (foundBranches.size() > 1) { - if (foundBranches.size() > 2) { - reportError(Twine("too many branches in packet")); - return false; - } - - // try all possible choices - for (unsigned int i = 0; i < MAX_JUMP_SLOTS; ++i) { - // validate first jump with this slot rule - if (!(jumpSlots[i].first & foundBranches[0]->Core.getUnits())) - continue; - - // validate second jump with this slot rule - if (!(jumpSlots[i].second & foundBranches[1]->Core.getUnits())) - continue; - - // both valid for this configuration, set new slot rules - PacketSave = Packet; - foundBranches[0]->Core.setUnits(jumpSlots[i].first); - foundBranches[1]->Core.setUnits(jumpSlots[i].second); - - HexagonUnitAuction AuctionCore(reservedSlots); - std::stable_sort(begin(), end(), HexagonInstr::lessCore); - - // see if things ok with that instruction being pinned to slot "slotJump" - bool bFail = false; - for (iterator I = begin(); I != end() && !bFail; ++I) - if (!AuctionCore.bid(I->Core.getUnits())) - bFail = true; - - // if yes, great, if not then restore original slot mask - if (!bFail) { - validateSlots = false; // all good, no need to re-do auction - break; - } else - // restore original values - Packet = PacketSave; - } - if (validateSlots) { - reportError(Twine("invalid instruction packet: out of slots")); - return false; - } - } - - if (foundBranches.size() <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 && - slot3ISJ != end()) { - validateSlots = true; - // save off slot mask of instruction marked with A_PREFER_SLOT3 - // and then pin it to slot #3 - unsigned saveUnits = slot3ISJ->Core.getUnits(); - slot3ISJ->Core.setUnits(saveUnits & slotThree); + return !InvalidPacket; +} - HexagonUnitAuction AuctionCore(reservedSlots); - std::stable_sort(begin(), end(), HexagonInstr::lessCore); +void HexagonShuffler::restrictPreferSlot3(HexagonPacketSummary const &Summary) { + // flag if an instruction requires to be in slot 3 + const bool HasOnlySlot3 = llvm::any_of(insts(), [&](HexagonInstr const &I) { + return (I.Core.getUnits() == Slot3Mask); + }); + const bool NeedsPrefSlot3Shuffle = + (Summary.branchInsts.size() <= 1 && !HasOnlySlot3 && + Summary.pSlot3Cnt == 1 && Summary.PrefSlot3Inst); + + if (!NeedsPrefSlot3Shuffle) + return; + + HexagonInstr *PrefSlot3Inst = *Summary.PrefSlot3Inst; + // save off slot mask of instruction marked with A_PREFER_SLOT3 + // and then pin it to slot #3 + const unsigned saveUnits = PrefSlot3Inst->Core.getUnits(); + PrefSlot3Inst->Core.setUnits(saveUnits & Slot3Mask); + const bool HasShuffledPacket = tryAuction(Summary).hasValue(); + if (HasShuffledPacket) + return; + + PrefSlot3Inst->Core.setUnits(saveUnits); +} - // see if things ok with that instruction being pinned to slot #3 - bool bFail = false; - for (iterator I = begin(); I != end() && !bFail; ++I) - if (!AuctionCore.bid(I->Core.getUnits())) - bFail = true; +/// Check that the packet is legal and enforce relative insn order. +bool HexagonShuffler::check() { + const HexagonPacketSummary Summary = GetPacketSummary(); + if (!applySlotRestrictions(Summary)) + return false; - // if yes, great, if not then restore original slot mask - if (!bFail) - validateSlots = false; // all good, no need to re-do auction - else - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const &ID = ISJ->getDesc(); - if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) - ISJ->Core.setUnits(saveUnits); - } + if (!ValidPacketMemoryOps(Summary)) { + reportError("invalid instruction packet"); + return false; } - // Check if any slot, core or CVI, is over-subscribed. - // Verify the core slot subscriptions. - if (validateSlots) { - HexagonUnitAuction AuctionCore(reservedSlots); + ValidResourceUsage(Summary); - std::stable_sort(begin(), end(), HexagonInstr::lessCore); - - for (iterator I = begin(); I != end(); ++I) - if (!AuctionCore.bid(I->Core.getUnits())) { - reportError(Twine("invalid instruction packet: slot error")); - return false; - } - } - // Verify the CVI slot subscriptions. - std::stable_sort(begin(), end(), HexagonInstr::lessCVI); - // create vector of hvx instructions to check - HVXInstsT hvxInsts; - hvxInsts.clear(); - for (iterator I = begin(); I != end(); ++I) { - struct CVIUnits inst; - inst.Units = I->CVI.getUnits(); - inst.Lanes = I->CVI.getLanes(); - if (inst.Units == 0) - continue; // not an hvx inst or an hvx inst that doesn't uses any pipes - hvxInsts.push_back(inst); - } - // if there are any hvx instructions in this packet, check pipe usage - if (hvxInsts.size() > 0) { - unsigned startIdx, usedUnits; - startIdx = usedUnits = 0x0; - if (!checkHVXPipes(hvxInsts, startIdx, usedUnits)) { - // too many pipes used to be valid - reportError(Twine("invalid instruction packet: slot error")); - return false; - } - } + return !CheckFailure; +} - return true; +llvm::Optional<HexagonShuffler::HexagonPacket> +HexagonShuffler::tryAuction(HexagonPacketSummary const &Summary) const { + HexagonPacket PacketResult = Packet; + HexagonUnitAuction AuctionCore(Summary.ReservedSlotMask); + std::stable_sort(PacketResult.begin(), PacketResult.end(), + HexagonInstr::lessCore); + + const bool ValidSlots = + llvm::all_of(insts(PacketResult), [&AuctionCore](HexagonInstr const &I) { + return AuctionCore.bid(I.Core.getUnits()); + }); + + LLVM_DEBUG( + dbgs() << "Shuffle attempt: " << (ValidSlots ? "passed" : "failed") + << "\n"; + for (HexagonInstr const &ISJ : insts(PacketResult)) + dbgs() << "\t" << HexagonMCInstrInfo::getName(MCII, *ISJ.ID) << ": " + << llvm::format_hex(ISJ.Core.getUnits(), 4, true) << "\n"; + ); + + Optional<HexagonPacket> Res; + if (ValidSlots) + Res = PacketResult; + + return Res; } bool HexagonShuffler::shuffle() { @@ -653,20 +668,25 @@ bool HexagonShuffler::shuffle() { ++emptySlots; } - for (iterator ISJ = begin(); ISJ != end(); ++ISJ) - LLVM_DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { - dbgs() << '/'; - dbgs().write_hex(ISJ->CVI.getUnits()) << '|'; - dbgs() << ISJ->CVI.getLanes(); - } dbgs() << ':' - << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode(); - dbgs() << '\n'); - LLVM_DEBUG(dbgs() << '\n'); + LLVM_DEBUG( + for (HexagonInstr const &ISJ : insts()) { + dbgs().write_hex(ISJ.Core.getUnits()); + if (ISJ.CVI.isValid()) { + dbgs() << '/'; + dbgs().write_hex(ISJ.CVI.getUnits()) << '|'; + dbgs() << ISJ.CVI.getLanes(); + } + dbgs() << ':' + << HexagonMCInstrInfo::getDesc(MCII, ISJ.getDesc()).getOpcode() + << '\n'; + } dbgs() << '\n'; + ); return Ok; } void HexagonShuffler::reportError(Twine const &Msg) { + CheckFailure = true; if (ReportErrors) { for (auto const &I : AppliedRestrictions) { auto SM = Context.getSourceManager(); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h index bf3bad36dfe55..1b4ebc5111dba 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -17,11 +17,13 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" #include <cstdint> +#include <functional> #include <utility> namespace llvm { @@ -45,6 +47,9 @@ public: setWeight(s); } + void setAllUnits() { + setUnits(((1u << HEXAGON_PACKET_SIZE) - 1)); + } unsigned setWeight(unsigned s); unsigned getUnits() const { return (Slots); } @@ -65,7 +70,6 @@ public: class HexagonCVIResource : public HexagonResource { public: using UnitsAndLanes = std::pair<unsigned, unsigned>; - using TypeUnitsAndLanes = DenseMap<unsigned, UnitsAndLanes>; private: // Available HVX slots. @@ -90,11 +94,10 @@ private: void setStore(bool f = true) { Store = f; } public: - HexagonCVIResource(TypeUnitsAndLanes *TUL, MCInstrInfo const &MCII, + HexagonCVIResource(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, unsigned s, MCInst const *id); - static void SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU); - bool isValid() const { return Valid; } unsigned getLanes() const { return Lanes; } bool mayLoad() const { return Load; } @@ -111,10 +114,10 @@ class HexagonInstr { HexagonCVIResource CVI; public: - HexagonInstr(HexagonCVIResource::TypeUnitsAndLanes *T, - MCInstrInfo const &MCII, MCInst const *id, + HexagonInstr(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst const *id, MCInst const *Extender, unsigned s) - : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {} + : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; MCInst const &getDesc() const { return *ID; } MCInst const *getExtender() const { return Extender; } @@ -140,11 +143,30 @@ class HexagonShuffler { using HexagonPacket = SmallVector<HexagonInstr, HEXAGON_PRESHUFFLE_PACKET_SIZE>; + struct HexagonPacketSummary { + // Number of memory operations, loads, solo loads, stores, solo stores, + // single stores. + unsigned memory; + unsigned loads; + unsigned load0; + unsigned stores; + unsigned store0; + unsigned store1; + unsigned NonZCVIloads; + unsigned AllCVIloads; + unsigned CVIstores; + // Number of duplex insns + unsigned duplex; + unsigned pSlot3Cnt; + Optional<HexagonInstr *> PrefSlot3Inst; + unsigned memops; + unsigned ReservedSlotMask; + SmallVector<HexagonInstr *, HEXAGON_PRESHUFFLE_PACKET_SIZE> branchInsts; + Optional<SMLoc> Slot1AOKLoc; + Optional<SMLoc> NoSlot1StoreLoc; + }; // Insn handles in a bundle. HexagonPacket Packet; - HexagonPacket PacketSave; - - HexagonCVIResource::TypeUnitsAndLanes TUL; protected: MCContext &Context; @@ -153,13 +175,29 @@ protected: MCSubtargetInfo const &STI; SMLoc Loc; bool ReportErrors; + bool CheckFailure; std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions; - void applySlotRestrictions(); - void restrictSlot1AOK(); - void restrictNoSlot1Store(); + bool applySlotRestrictions(HexagonPacketSummary const &Summary); + void restrictSlot1AOK(HexagonPacketSummary const &Summary); + void restrictNoSlot1Store(HexagonPacketSummary const &Summary); + void restrictNoSlot1(); + bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary); + void restrictBranchOrder(HexagonPacketSummary const &Summary); + void restrictPreferSlot3(HexagonPacketSummary const &Summary); + void permitNonSlot(); + + Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary) const; + + HexagonPacketSummary GetPacketSummary(); + bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const; + bool ValidResourceUsage(HexagonPacketSummary const &Summary); + bool validPacketInsts() const; public: using iterator = HexagonPacket::iterator; + using const_iterator = HexagonPacket::const_iterator; + using packet_range = iterator_range<HexagonPacket::iterator>; + using const_packet_range = iterator_range<HexagonPacket::const_iterator>; HexagonShuffler(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI); @@ -179,6 +217,25 @@ public: iterator begin() { return (Packet.begin()); } iterator end() { return (Packet.end()); } + const_iterator cbegin() const { return (Packet.begin()); } + const_iterator cend() const { return (Packet.end()); } + packet_range insts(HexagonPacket &P) { + return make_range(P.begin(), P.end()); + } + const_packet_range insts(HexagonPacket const &P) const { + return make_range(P.begin(), P.end()); + } + packet_range insts() { return make_range(begin(), end()); } + const_packet_range insts() const { return make_range(cbegin(), cend()); } + + using InstPredicate = bool (*)(MCInstrInfo const &, MCInst const &); + + bool HasInstWith(InstPredicate Pred) const { + return llvm::any_of(insts(), [&](HexagonInstr const &I) { + MCInst const &Inst = I.getDesc(); + return (*Pred)(MCII, Inst); + }); + } // Add insn handle to the bundle . void append(MCInst const &ID, MCInst const *Extender, unsigned S); diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp index a9d39fd4b2dcb..34d58f0a7a230 100644 --- a/llvm/lib/Target/Hexagon/RDFCopy.cpp +++ b/llvm/lib/Target/Hexagon/RDFCopy.cpp @@ -11,13 +11,13 @@ //===----------------------------------------------------------------------===// #include "RDFCopy.h" -#include "RDFGraph.h" -#include "RDFLiveness.h" -#include "RDFRegisters.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" +#include "llvm/CodeGen/RDFRegisters.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/MC/MCRegisterInfo.h" diff --git a/llvm/lib/Target/Hexagon/RDFCopy.h b/llvm/lib/Target/Hexagon/RDFCopy.h index 1450ab8848492..99b18a75d8c2b 100644 --- a/llvm/lib/Target/Hexagon/RDFCopy.h +++ b/llvm/lib/Target/Hexagon/RDFCopy.h @@ -9,9 +9,9 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H #define LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H -#include "RDFGraph.h" -#include "RDFLiveness.h" -#include "RDFRegisters.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" +#include "llvm/CodeGen/RDFRegisters.h" #include "llvm/CodeGen/MachineFunction.h" #include <map> #include <vector> diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp index af86c7b1956bc..5a98debd3c000 100644 --- a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp +++ b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp @@ -9,13 +9,13 @@ // RDF-based generic dead code elimination. #include "RDFDeadCode.h" -#include "RDFGraph.h" -#include "RDFLiveness.h" #include "llvm/ADT/SetVector.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" #include "llvm/Support/Debug.h" #include <queue> diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.h b/llvm/lib/Target/Hexagon/RDFDeadCode.h index 7f91977e1d6cd..859c8161d355c 100644 --- a/llvm/lib/Target/Hexagon/RDFDeadCode.h +++ b/llvm/lib/Target/Hexagon/RDFDeadCode.h @@ -23,8 +23,8 @@ #ifndef RDF_DEADCODE_H #define RDF_DEADCODE_H -#include "RDFGraph.h" -#include "RDFLiveness.h" +#include "llvm/CodeGen/RDFGraph.h" +#include "llvm/CodeGen/RDFLiveness.h" #include "llvm/ADT/SetVector.h" namespace llvm { diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp deleted file mode 100644 index 0cb35dc988196..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFGraph.cpp +++ /dev/null @@ -1,1835 +0,0 @@ -//===- RDFGraph.cpp -------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Target-independent, SSA-based data flow graph for register data flow (RDF). -// -#include "RDFGraph.h" -#include "RDFRegisters.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SetVector.h" -#include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/MachineDominanceFrontier.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineOperand.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/TargetInstrInfo.h" -#include "llvm/CodeGen/TargetLowering.h" -#include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/CodeGen/TargetSubtargetInfo.h" -#include "llvm/IR/Function.h" -#include "llvm/MC/LaneBitmask.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include <algorithm> -#include <cassert> -#include <cstdint> -#include <cstring> -#include <iterator> -#include <set> -#include <utility> -#include <vector> - -using namespace llvm; -using namespace rdf; - -// Printing functions. Have them here first, so that the rest of the code -// can use them. -namespace llvm { -namespace rdf { - -raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P) { - if (!P.Mask.all()) - OS << ':' << PrintLaneMask(P.Mask); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) { - auto &TRI = P.G.getTRI(); - if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs()) - OS << TRI.getName(P.Obj.Reg); - else - OS << '#' << P.Obj.Reg; - OS << PrintLaneMaskOpt(P.Obj.Mask); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeId> &P) { - auto NA = P.G.addr<NodeBase*>(P.Obj); - uint16_t Attrs = NA.Addr->getAttrs(); - uint16_t Kind = NodeAttrs::kind(Attrs); - uint16_t Flags = NodeAttrs::flags(Attrs); - switch (NodeAttrs::type(Attrs)) { - case NodeAttrs::Code: - switch (Kind) { - case NodeAttrs::Func: OS << 'f'; break; - case NodeAttrs::Block: OS << 'b'; break; - case NodeAttrs::Stmt: OS << 's'; break; - case NodeAttrs::Phi: OS << 'p'; break; - default: OS << "c?"; break; - } - break; - case NodeAttrs::Ref: - if (Flags & NodeAttrs::Undef) - OS << '/'; - if (Flags & NodeAttrs::Dead) - OS << '\\'; - if (Flags & NodeAttrs::Preserving) - OS << '+'; - if (Flags & NodeAttrs::Clobbering) - OS << '~'; - switch (Kind) { - case NodeAttrs::Use: OS << 'u'; break; - case NodeAttrs::Def: OS << 'd'; break; - case NodeAttrs::Block: OS << 'b'; break; - default: OS << "r?"; break; - } - break; - default: - OS << '?'; - break; - } - OS << P.Obj; - if (Flags & NodeAttrs::Shadow) - OS << '"'; - return OS; -} - -static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, - const DataFlowGraph &G) { - OS << Print<NodeId>(RA.Id, G) << '<' - << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>'; - if (RA.Addr->getFlags() & NodeAttrs::Fixed) - OS << '!'; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<DefNode*>> &P) { - printRefHeader(OS, P.Obj, P.G); - OS << '('; - if (NodeId N = P.Obj.Addr->getReachingDef()) - OS << Print<NodeId>(N, P.G); - OS << ','; - if (NodeId N = P.Obj.Addr->getReachedDef()) - OS << Print<NodeId>(N, P.G); - OS << ','; - if (NodeId N = P.Obj.Addr->getReachedUse()) - OS << Print<NodeId>(N, P.G); - OS << "):"; - if (NodeId N = P.Obj.Addr->getSibling()) - OS << Print<NodeId>(N, P.G); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<UseNode*>> &P) { - printRefHeader(OS, P.Obj, P.G); - OS << '('; - if (NodeId N = P.Obj.Addr->getReachingDef()) - OS << Print<NodeId>(N, P.G); - OS << "):"; - if (NodeId N = P.Obj.Addr->getSibling()) - OS << Print<NodeId>(N, P.G); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, - const Print<NodeAddr<PhiUseNode*>> &P) { - printRefHeader(OS, P.Obj, P.G); - OS << '('; - if (NodeId N = P.Obj.Addr->getReachingDef()) - OS << Print<NodeId>(N, P.G); - OS << ','; - if (NodeId N = P.Obj.Addr->getPredecessor()) - OS << Print<NodeId>(N, P.G); - OS << "):"; - if (NodeId N = P.Obj.Addr->getSibling()) - OS << Print<NodeId>(N, P.G); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<RefNode*>> &P) { - switch (P.Obj.Addr->getKind()) { - case NodeAttrs::Def: - OS << PrintNode<DefNode*>(P.Obj, P.G); - break; - case NodeAttrs::Use: - if (P.Obj.Addr->getFlags() & NodeAttrs::PhiRef) - OS << PrintNode<PhiUseNode*>(P.Obj, P.G); - else - OS << PrintNode<UseNode*>(P.Obj, P.G); - break; - } - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeList> &P) { - unsigned N = P.Obj.size(); - for (auto I : P.Obj) { - OS << Print<NodeId>(I.Id, P.G); - if (--N) - OS << ' '; - } - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeSet> &P) { - unsigned N = P.Obj.size(); - for (auto I : P.Obj) { - OS << Print<NodeId>(I, P.G); - if (--N) - OS << ' '; - } - return OS; -} - -namespace { - - template <typename T> - struct PrintListV { - PrintListV(const NodeList &L, const DataFlowGraph &G) : List(L), G(G) {} - - using Type = T; - const NodeList &List; - const DataFlowGraph &G; - }; - - template <typename T> - raw_ostream &operator<< (raw_ostream &OS, const PrintListV<T> &P) { - unsigned N = P.List.size(); - for (NodeAddr<T> A : P.List) { - OS << PrintNode<T>(A, P.G); - if (--N) - OS << ", "; - } - return OS; - } - -} // end anonymous namespace - -raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<PhiNode*>> &P) { - OS << Print<NodeId>(P.Obj.Id, P.G) << ": phi [" - << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']'; - return OS; -} - -raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<StmtNode *>> &P) { - const MachineInstr &MI = *P.Obj.Addr->getCode(); - unsigned Opc = MI.getOpcode(); - OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); - // Print the target for calls and branches (for readability). - if (MI.isCall() || MI.isBranch()) { - MachineInstr::const_mop_iterator T = - llvm::find_if(MI.operands(), - [] (const MachineOperand &Op) -> bool { - return Op.isMBB() || Op.isGlobal() || Op.isSymbol(); - }); - if (T != MI.operands_end()) { - OS << ' '; - if (T->isMBB()) - OS << printMBBReference(*T->getMBB()); - else if (T->isGlobal()) - OS << T->getGlobal()->getName(); - else if (T->isSymbol()) - OS << T->getSymbolName(); - } - } - OS << " [" << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']'; - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, - const Print<NodeAddr<InstrNode*>> &P) { - switch (P.Obj.Addr->getKind()) { - case NodeAttrs::Phi: - OS << PrintNode<PhiNode*>(P.Obj, P.G); - break; - case NodeAttrs::Stmt: - OS << PrintNode<StmtNode*>(P.Obj, P.G); - break; - default: - OS << "instr? " << Print<NodeId>(P.Obj.Id, P.G); - break; - } - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, - const Print<NodeAddr<BlockNode*>> &P) { - MachineBasicBlock *BB = P.Obj.Addr->getCode(); - unsigned NP = BB->pred_size(); - std::vector<int> Ns; - auto PrintBBs = [&OS] (std::vector<int> Ns) -> void { - unsigned N = Ns.size(); - for (int I : Ns) { - OS << "%bb." << I; - if (--N) - OS << ", "; - } - }; - - OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB) - << " --- preds(" << NP << "): "; - for (MachineBasicBlock *B : BB->predecessors()) - Ns.push_back(B->getNumber()); - PrintBBs(Ns); - - unsigned NS = BB->succ_size(); - OS << " succs(" << NS << "): "; - Ns.clear(); - for (MachineBasicBlock *B : BB->successors()) - Ns.push_back(B->getNumber()); - PrintBBs(Ns); - OS << '\n'; - - for (auto I : P.Obj.Addr->members(P.G)) - OS << PrintNode<InstrNode*>(I, P.G) << '\n'; - return OS; -} - -raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<FuncNode *>> &P) { - OS << "DFG dump:[\n" << Print<NodeId>(P.Obj.Id, P.G) << ": Function: " - << P.Obj.Addr->getCode()->getName() << '\n'; - for (auto I : P.Obj.Addr->members(P.G)) - OS << PrintNode<BlockNode*>(I, P.G) << '\n'; - OS << "]\n"; - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &P) { - OS << '{'; - for (auto I : P.Obj) - OS << ' ' << Print<RegisterRef>(I, P.G); - OS << " }"; - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterAggr> &P) { - P.Obj.print(OS); - return OS; -} - -raw_ostream &operator<< (raw_ostream &OS, - const Print<DataFlowGraph::DefStack> &P) { - for (auto I = P.Obj.top(), E = P.Obj.bottom(); I != E; ) { - OS << Print<NodeId>(I->Id, P.G) - << '<' << Print<RegisterRef>(I->Addr->getRegRef(P.G), P.G) << '>'; - I.down(); - if (I != E) - OS << ' '; - } - return OS; -} - -} // end namespace rdf -} // end namespace llvm - -// Node allocation functions. -// -// Node allocator is like a slab memory allocator: it allocates blocks of -// memory in sizes that are multiples of the size of a node. Each block has -// the same size. Nodes are allocated from the currently active block, and -// when it becomes full, a new one is created. -// There is a mapping scheme between node id and its location in a block, -// and within that block is described in the header file. -// -void NodeAllocator::startNewBlock() { - void *T = MemPool.Allocate(NodesPerBlock*NodeMemSize, NodeMemSize); - char *P = static_cast<char*>(T); - Blocks.push_back(P); - // Check if the block index is still within the allowed range, i.e. less - // than 2^N, where N is the number of bits in NodeId for the block index. - // BitsPerIndex is the number of bits per node index. - assert((Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex))) && - "Out of bits for block index"); - ActiveEnd = P; -} - -bool NodeAllocator::needNewBlock() { - if (Blocks.empty()) - return true; - - char *ActiveBegin = Blocks.back(); - uint32_t Index = (ActiveEnd-ActiveBegin)/NodeMemSize; - return Index >= NodesPerBlock; -} - -NodeAddr<NodeBase*> NodeAllocator::New() { - if (needNewBlock()) - startNewBlock(); - - uint32_t ActiveB = Blocks.size()-1; - uint32_t Index = (ActiveEnd - Blocks[ActiveB])/NodeMemSize; - NodeAddr<NodeBase*> NA = { reinterpret_cast<NodeBase*>(ActiveEnd), - makeId(ActiveB, Index) }; - ActiveEnd += NodeMemSize; - return NA; -} - -NodeId NodeAllocator::id(const NodeBase *P) const { - uintptr_t A = reinterpret_cast<uintptr_t>(P); - for (unsigned i = 0, n = Blocks.size(); i != n; ++i) { - uintptr_t B = reinterpret_cast<uintptr_t>(Blocks[i]); - if (A < B || A >= B + NodesPerBlock*NodeMemSize) - continue; - uint32_t Idx = (A-B)/NodeMemSize; - return makeId(i, Idx); - } - llvm_unreachable("Invalid node address"); -} - -void NodeAllocator::clear() { - MemPool.Reset(); - Blocks.clear(); - ActiveEnd = nullptr; -} - -// Insert node NA after "this" in the circular chain. -void NodeBase::append(NodeAddr<NodeBase*> NA) { - NodeId Nx = Next; - // If NA is already "next", do nothing. - if (Next != NA.Id) { - Next = NA.Id; - NA.Addr->Next = Nx; - } -} - -// Fundamental node manipulator functions. - -// Obtain the register reference from a reference node. -RegisterRef RefNode::getRegRef(const DataFlowGraph &G) const { - assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref); - if (NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef) - return G.unpack(Ref.PR); - assert(Ref.Op != nullptr); - return G.makeRegRef(*Ref.Op); -} - -// Set the register reference in the reference node directly (for references -// in phi nodes). -void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { - assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref); - assert(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef); - Ref.PR = G.pack(RR); -} - -// Set the register reference in the reference node based on a machine -// operand (for references in statement nodes). -void RefNode::setRegRef(MachineOperand *Op, DataFlowGraph &G) { - assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref); - assert(!(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef)); - (void)G; - Ref.Op = Op; -} - -// Get the owner of a given reference node. -NodeAddr<NodeBase*> RefNode::getOwner(const DataFlowGraph &G) { - NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext()); - - while (NA.Addr != this) { - if (NA.Addr->getType() == NodeAttrs::Code) - return NA; - NA = G.addr<NodeBase*>(NA.Addr->getNext()); - } - llvm_unreachable("No owner in circular list"); -} - -// Connect the def node to the reaching def node. -void DefNode::linkToDef(NodeId Self, NodeAddr<DefNode*> DA) { - Ref.RD = DA.Id; - Ref.Sib = DA.Addr->getReachedDef(); - DA.Addr->setReachedDef(Self); -} - -// Connect the use node to the reaching def node. -void UseNode::linkToDef(NodeId Self, NodeAddr<DefNode*> DA) { - Ref.RD = DA.Id; - Ref.Sib = DA.Addr->getReachedUse(); - DA.Addr->setReachedUse(Self); -} - -// Get the first member of the code node. -NodeAddr<NodeBase*> CodeNode::getFirstMember(const DataFlowGraph &G) const { - if (Code.FirstM == 0) - return NodeAddr<NodeBase*>(); - return G.addr<NodeBase*>(Code.FirstM); -} - -// Get the last member of the code node. -NodeAddr<NodeBase*> CodeNode::getLastMember(const DataFlowGraph &G) const { - if (Code.LastM == 0) - return NodeAddr<NodeBase*>(); - return G.addr<NodeBase*>(Code.LastM); -} - -// Add node NA at the end of the member list of the given code node. -void CodeNode::addMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G) { - NodeAddr<NodeBase*> ML = getLastMember(G); - if (ML.Id != 0) { - ML.Addr->append(NA); - } else { - Code.FirstM = NA.Id; - NodeId Self = G.id(this); - NA.Addr->setNext(Self); - } - Code.LastM = NA.Id; -} - -// Add node NA after member node MA in the given code node. -void CodeNode::addMemberAfter(NodeAddr<NodeBase*> MA, NodeAddr<NodeBase*> NA, - const DataFlowGraph &G) { - MA.Addr->append(NA); - if (Code.LastM == MA.Id) - Code.LastM = NA.Id; -} - -// Remove member node NA from the given code node. -void CodeNode::removeMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G) { - NodeAddr<NodeBase*> MA = getFirstMember(G); - assert(MA.Id != 0); - - // Special handling if the member to remove is the first member. - if (MA.Id == NA.Id) { - if (Code.LastM == MA.Id) { - // If it is the only member, set both first and last to 0. - Code.FirstM = Code.LastM = 0; - } else { - // Otherwise, advance the first member. - Code.FirstM = MA.Addr->getNext(); - } - return; - } - - while (MA.Addr != this) { - NodeId MX = MA.Addr->getNext(); - if (MX == NA.Id) { - MA.Addr->setNext(NA.Addr->getNext()); - // If the member to remove happens to be the last one, update the - // LastM indicator. - if (Code.LastM == NA.Id) - Code.LastM = MA.Id; - return; - } - MA = G.addr<NodeBase*>(MX); - } - llvm_unreachable("No such member"); -} - -// Return the list of all members of the code node. -NodeList CodeNode::members(const DataFlowGraph &G) const { - static auto True = [] (NodeAddr<NodeBase*>) -> bool { return true; }; - return members_if(True, G); -} - -// Return the owner of the given instr node. -NodeAddr<NodeBase*> InstrNode::getOwner(const DataFlowGraph &G) { - NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext()); - - while (NA.Addr != this) { - assert(NA.Addr->getType() == NodeAttrs::Code); - if (NA.Addr->getKind() == NodeAttrs::Block) - return NA; - NA = G.addr<NodeBase*>(NA.Addr->getNext()); - } - llvm_unreachable("No owner in circular list"); -} - -// Add the phi node PA to the given block node. -void BlockNode::addPhi(NodeAddr<PhiNode*> PA, const DataFlowGraph &G) { - NodeAddr<NodeBase*> M = getFirstMember(G); - if (M.Id == 0) { - addMember(PA, G); - return; - } - - assert(M.Addr->getType() == NodeAttrs::Code); - if (M.Addr->getKind() == NodeAttrs::Stmt) { - // If the first member of the block is a statement, insert the phi as - // the first member. - Code.FirstM = PA.Id; - PA.Addr->setNext(M.Id); - } else { - // If the first member is a phi, find the last phi, and append PA to it. - assert(M.Addr->getKind() == NodeAttrs::Phi); - NodeAddr<NodeBase*> MN = M; - do { - M = MN; - MN = G.addr<NodeBase*>(M.Addr->getNext()); - assert(MN.Addr->getType() == NodeAttrs::Code); - } while (MN.Addr->getKind() == NodeAttrs::Phi); - - // M is the last phi. - addMemberAfter(M, PA, G); - } -} - -// Find the block node corresponding to the machine basic block BB in the -// given func node. -NodeAddr<BlockNode*> FuncNode::findBlock(const MachineBasicBlock *BB, - const DataFlowGraph &G) const { - auto EqBB = [BB] (NodeAddr<NodeBase*> NA) -> bool { - return NodeAddr<BlockNode*>(NA).Addr->getCode() == BB; - }; - NodeList Ms = members_if(EqBB, G); - if (!Ms.empty()) - return Ms[0]; - return NodeAddr<BlockNode*>(); -} - -// Get the block node for the entry block in the given function. -NodeAddr<BlockNode*> FuncNode::getEntryBlock(const DataFlowGraph &G) { - MachineBasicBlock *EntryB = &getCode()->front(); - return findBlock(EntryB, G); -} - -// Target operand information. -// - -// For a given instruction, check if there are any bits of RR that can remain -// unchanged across this def. -bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum) - const { - return TII.isPredicated(In); -} - -// Check if the definition of RR produces an unspecified value. -bool TargetOperandInfo::isClobbering(const MachineInstr &In, unsigned OpNum) - const { - const MachineOperand &Op = In.getOperand(OpNum); - if (Op.isRegMask()) - return true; - assert(Op.isReg()); - if (In.isCall()) - if (Op.isDef() && Op.isDead()) - return true; - return false; -} - -// Check if the given instruction specifically requires -bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum) - const { - if (In.isCall() || In.isReturn() || In.isInlineAsm()) - return true; - // Check for a tail call. - if (In.isBranch()) - for (const MachineOperand &O : In.operands()) - if (O.isGlobal() || O.isSymbol()) - return true; - - const MCInstrDesc &D = In.getDesc(); - if (!D.getImplicitDefs() && !D.getImplicitUses()) - return false; - const MachineOperand &Op = In.getOperand(OpNum); - // If there is a sub-register, treat the operand as non-fixed. Currently, - // fixed registers are those that are listed in the descriptor as implicit - // uses or defs, and those lists do not allow sub-registers. - if (Op.getSubReg() != 0) - return false; - Register Reg = Op.getReg(); - const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() - : D.getImplicitUses(); - if (!ImpR) - return false; - while (*ImpR) - if (*ImpR++ == Reg) - return true; - return false; -} - -// -// The data flow graph construction. -// - -DataFlowGraph::DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, - const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, - const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi) - : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi), - LiveIns(PRI) { -} - -// The implementation of the definition stack. -// Each register reference has its own definition stack. In particular, -// for a register references "Reg" and "Reg:subreg" will each have their -// own definition stacks. - -// Construct a stack iterator. -DataFlowGraph::DefStack::Iterator::Iterator(const DataFlowGraph::DefStack &S, - bool Top) : DS(S) { - if (!Top) { - // Initialize to bottom. - Pos = 0; - return; - } - // Initialize to the top, i.e. top-most non-delimiter (or 0, if empty). - Pos = DS.Stack.size(); - while (Pos > 0 && DS.isDelimiter(DS.Stack[Pos-1])) - Pos--; -} - -// Return the size of the stack, including block delimiters. -unsigned DataFlowGraph::DefStack::size() const { - unsigned S = 0; - for (auto I = top(), E = bottom(); I != E; I.down()) - S++; - return S; -} - -// Remove the top entry from the stack. Remove all intervening delimiters -// so that after this, the stack is either empty, or the top of the stack -// is a non-delimiter. -void DataFlowGraph::DefStack::pop() { - assert(!empty()); - unsigned P = nextDown(Stack.size()); - Stack.resize(P); -} - -// Push a delimiter for block node N on the stack. -void DataFlowGraph::DefStack::start_block(NodeId N) { - assert(N != 0); - Stack.push_back(NodeAddr<DefNode*>(nullptr, N)); -} - -// Remove all nodes from the top of the stack, until the delimited for -// block node N is encountered. Remove the delimiter as well. In effect, -// this will remove from the stack all definitions from block N. -void DataFlowGraph::DefStack::clear_block(NodeId N) { - assert(N != 0); - unsigned P = Stack.size(); - while (P > 0) { - bool Found = isDelimiter(Stack[P-1], N); - P--; - if (Found) - break; - } - // This will also remove the delimiter, if found. - Stack.resize(P); -} - -// Move the stack iterator up by one. -unsigned DataFlowGraph::DefStack::nextUp(unsigned P) const { - // Get the next valid position after P (skipping all delimiters). - // The input position P does not have to point to a non-delimiter. - unsigned SS = Stack.size(); - bool IsDelim; - assert(P < SS); - do { - P++; - IsDelim = isDelimiter(Stack[P-1]); - } while (P < SS && IsDelim); - assert(!IsDelim); - return P; -} - -// Move the stack iterator down by one. -unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const { - // Get the preceding valid position before P (skipping all delimiters). - // The input position P does not have to point to a non-delimiter. - assert(P > 0 && P <= Stack.size()); - bool IsDelim = isDelimiter(Stack[P-1]); - do { - if (--P == 0) - break; - IsDelim = isDelimiter(Stack[P-1]); - } while (P > 0 && IsDelim); - assert(!IsDelim); - return P; -} - -// Register information. - -RegisterSet DataFlowGraph::getLandingPadLiveIns() const { - RegisterSet LR; - const Function &F = MF.getFunction(); - const Constant *PF = F.hasPersonalityFn() ? F.getPersonalityFn() - : nullptr; - const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering(); - if (RegisterId R = TLI.getExceptionPointerRegister(PF)) - LR.insert(RegisterRef(R)); - if (RegisterId R = TLI.getExceptionSelectorRegister(PF)) - LR.insert(RegisterRef(R)); - return LR; -} - -// Node management functions. - -// Get the pointer to the node with the id N. -NodeBase *DataFlowGraph::ptr(NodeId N) const { - if (N == 0) - return nullptr; - return Memory.ptr(N); -} - -// Get the id of the node at the address P. -NodeId DataFlowGraph::id(const NodeBase *P) const { - if (P == nullptr) - return 0; - return Memory.id(P); -} - -// Allocate a new node and set the attributes to Attrs. -NodeAddr<NodeBase*> DataFlowGraph::newNode(uint16_t Attrs) { - NodeAddr<NodeBase*> P = Memory.New(); - P.Addr->init(); - P.Addr->setAttrs(Attrs); - return P; -} - -// Make a copy of the given node B, except for the data-flow links, which -// are set to 0. -NodeAddr<NodeBase*> DataFlowGraph::cloneNode(const NodeAddr<NodeBase*> B) { - NodeAddr<NodeBase*> NA = newNode(0); - memcpy(NA.Addr, B.Addr, sizeof(NodeBase)); - // Ref nodes need to have the data-flow links reset. - if (NA.Addr->getType() == NodeAttrs::Ref) { - NodeAddr<RefNode*> RA = NA; - RA.Addr->setReachingDef(0); - RA.Addr->setSibling(0); - if (NA.Addr->getKind() == NodeAttrs::Def) { - NodeAddr<DefNode*> DA = NA; - DA.Addr->setReachedDef(0); - DA.Addr->setReachedUse(0); - } - } - return NA; -} - -// Allocation routines for specific node types/kinds. - -NodeAddr<UseNode*> DataFlowGraph::newUse(NodeAddr<InstrNode*> Owner, - MachineOperand &Op, uint16_t Flags) { - NodeAddr<UseNode*> UA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags); - UA.Addr->setRegRef(&Op, *this); - return UA; -} - -NodeAddr<PhiUseNode*> DataFlowGraph::newPhiUse(NodeAddr<PhiNode*> Owner, - RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { - NodeAddr<PhiUseNode*> PUA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags); - assert(Flags & NodeAttrs::PhiRef); - PUA.Addr->setRegRef(RR, *this); - PUA.Addr->setPredecessor(PredB.Id); - return PUA; -} - -NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner, - MachineOperand &Op, uint16_t Flags) { - NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags); - DA.Addr->setRegRef(&Op, *this); - return DA; -} - -NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner, - RegisterRef RR, uint16_t Flags) { - NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags); - assert(Flags & NodeAttrs::PhiRef); - DA.Addr->setRegRef(RR, *this); - return DA; -} - -NodeAddr<PhiNode*> DataFlowGraph::newPhi(NodeAddr<BlockNode*> Owner) { - NodeAddr<PhiNode*> PA = newNode(NodeAttrs::Code | NodeAttrs::Phi); - Owner.Addr->addPhi(PA, *this); - return PA; -} - -NodeAddr<StmtNode*> DataFlowGraph::newStmt(NodeAddr<BlockNode*> Owner, - MachineInstr *MI) { - NodeAddr<StmtNode*> SA = newNode(NodeAttrs::Code | NodeAttrs::Stmt); - SA.Addr->setCode(MI); - Owner.Addr->addMember(SA, *this); - return SA; -} - -NodeAddr<BlockNode*> DataFlowGraph::newBlock(NodeAddr<FuncNode*> Owner, - MachineBasicBlock *BB) { - NodeAddr<BlockNode*> BA = newNode(NodeAttrs::Code | NodeAttrs::Block); - BA.Addr->setCode(BB); - Owner.Addr->addMember(BA, *this); - return BA; -} - -NodeAddr<FuncNode*> DataFlowGraph::newFunc(MachineFunction *MF) { - NodeAddr<FuncNode*> FA = newNode(NodeAttrs::Code | NodeAttrs::Func); - FA.Addr->setCode(MF); - return FA; -} - -// Build the data flow graph. -void DataFlowGraph::build(unsigned Options) { - reset(); - Func = newFunc(&MF); - - if (MF.empty()) - return; - - for (MachineBasicBlock &B : MF) { - NodeAddr<BlockNode*> BA = newBlock(Func, &B); - BlockNodes.insert(std::make_pair(&B, BA)); - for (MachineInstr &I : B) { - if (I.isDebugInstr()) - continue; - buildStmt(BA, I); - } - } - - NodeAddr<BlockNode*> EA = Func.Addr->getEntryBlock(*this); - NodeList Blocks = Func.Addr->members(*this); - - // Collect information about block references. - RegisterSet AllRefs; - for (NodeAddr<BlockNode*> BA : Blocks) - for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) - for (NodeAddr<RefNode*> RA : IA.Addr->members(*this)) - AllRefs.insert(RA.Addr->getRegRef(*this)); - - // Collect function live-ins and entry block live-ins. - MachineRegisterInfo &MRI = MF.getRegInfo(); - MachineBasicBlock &EntryB = *EA.Addr->getCode(); - assert(EntryB.pred_empty() && "Function entry block has predecessors"); - for (std::pair<unsigned,unsigned> P : MRI.liveins()) - LiveIns.insert(RegisterRef(P.first)); - if (MRI.tracksLiveness()) { - for (auto I : EntryB.liveins()) - LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask)); - } - - // Add function-entry phi nodes for the live-in registers. - //for (std::pair<RegisterId,LaneBitmask> P : LiveIns) { - for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) { - RegisterRef RR = *I; - NodeAddr<PhiNode*> PA = newPhi(EA); - uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving; - NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); - PA.Addr->addMember(DA, *this); - } - - // Add phis for landing pads. - // Landing pads, unlike usual backs blocks, are not entered through - // branches in the program, or fall-throughs from other blocks. They - // are entered from the exception handling runtime and target's ABI - // may define certain registers as defined on entry to such a block. - RegisterSet EHRegs = getLandingPadLiveIns(); - if (!EHRegs.empty()) { - for (NodeAddr<BlockNode*> BA : Blocks) { - const MachineBasicBlock &B = *BA.Addr->getCode(); - if (!B.isEHPad()) - continue; - - // Prepare a list of NodeIds of the block's predecessors. - NodeList Preds; - for (MachineBasicBlock *PB : B.predecessors()) - Preds.push_back(findBlock(PB)); - - // Build phi nodes for each live-in. - for (RegisterRef RR : EHRegs) { - NodeAddr<PhiNode*> PA = newPhi(BA); - uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving; - // Add def: - NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); - PA.Addr->addMember(DA, *this); - // Add uses (no reaching defs for phi uses): - for (NodeAddr<BlockNode*> PBA : Preds) { - NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA); - PA.Addr->addMember(PUA, *this); - } - } - } - } - - // Build a map "PhiM" which will contain, for each block, the set - // of references that will require phi definitions in that block. - BlockRefsMap PhiM; - for (NodeAddr<BlockNode*> BA : Blocks) - recordDefsForDF(PhiM, BA); - for (NodeAddr<BlockNode*> BA : Blocks) - buildPhis(PhiM, AllRefs, BA); - - // Link all the refs. This will recursively traverse the dominator tree. - DefStackMap DM; - linkBlockRefs(DM, EA); - - // Finally, remove all unused phi nodes. - if (!(Options & BuildOptions::KeepDeadPhis)) - removeUnusedPhis(); -} - -RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const { - assert(PhysicalRegisterInfo::isRegMaskId(Reg) || - Register::isPhysicalRegister(Reg)); - assert(Reg != 0); - if (Sub != 0) - Reg = TRI.getSubReg(Reg, Sub); - return RegisterRef(Reg); -} - -RegisterRef DataFlowGraph::makeRegRef(const MachineOperand &Op) const { - assert(Op.isReg() || Op.isRegMask()); - if (Op.isReg()) - return makeRegRef(Op.getReg(), Op.getSubReg()); - return RegisterRef(PRI.getRegMaskId(Op.getRegMask()), LaneBitmask::getAll()); -} - -RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const { - if (AR.Reg == BR.Reg) { - LaneBitmask M = AR.Mask & BR.Mask; - return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef(); - } -#ifndef NDEBUG -// RegisterRef NAR = PRI.normalize(AR); -// RegisterRef NBR = PRI.normalize(BR); -// assert(NAR.Reg != NBR.Reg); -#endif - // This isn't strictly correct, because the overlap may happen in the - // part masked out. - if (PRI.alias(AR, BR)) - return AR; - return RegisterRef(); -} - -// For each stack in the map DefM, push the delimiter for block B on it. -void DataFlowGraph::markBlock(NodeId B, DefStackMap &DefM) { - // Push block delimiters. - for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I) - I->second.start_block(B); -} - -// Remove all definitions coming from block B from each stack in DefM. -void DataFlowGraph::releaseBlock(NodeId B, DefStackMap &DefM) { - // Pop all defs from this block from the definition stack. Defs that were - // added to the map during the traversal of instructions will not have a - // delimiter, but for those, the whole stack will be emptied. - for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I) - I->second.clear_block(B); - - // Finally, remove empty stacks from the map. - for (auto I = DefM.begin(), E = DefM.end(), NextI = I; I != E; I = NextI) { - NextI = std::next(I); - // This preserves the validity of iterators other than I. - if (I->second.empty()) - DefM.erase(I); - } -} - -// Push all definitions from the instruction node IA to an appropriate -// stack in DefM. -void DataFlowGraph::pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { - pushClobbers(IA, DefM); - pushDefs(IA, DefM); -} - -// Push all definitions from the instruction node IA to an appropriate -// stack in DefM. -void DataFlowGraph::pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { - NodeSet Visited; - std::set<RegisterId> Defined; - - // The important objectives of this function are: - // - to be able to handle instructions both while the graph is being - // constructed, and after the graph has been constructed, and - // - maintain proper ordering of definitions on the stack for each - // register reference: - // - if there are two or more related defs in IA (i.e. coming from - // the same machine operand), then only push one def on the stack, - // - if there are multiple unrelated defs of non-overlapping - // subregisters of S, then the stack for S will have both (in an - // unspecified order), but the order does not matter from the data- - // -flow perspective. - - for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { - if (Visited.count(DA.Id)) - continue; - if (!(DA.Addr->getFlags() & NodeAttrs::Clobbering)) - continue; - - NodeList Rel = getRelatedRefs(IA, DA); - NodeAddr<DefNode*> PDA = Rel.front(); - RegisterRef RR = PDA.Addr->getRegRef(*this); - - // Push the definition on the stack for the register and all aliases. - // The def stack traversal in linkNodeUp will check the exact aliasing. - DefM[RR.Reg].push(DA); - Defined.insert(RR.Reg); - for (RegisterId A : PRI.getAliasSet(RR.Reg)) { - // Check that we don't push the same def twice. - assert(A != RR.Reg); - if (!Defined.count(A)) - DefM[A].push(DA); - } - // Mark all the related defs as visited. - for (NodeAddr<NodeBase*> T : Rel) - Visited.insert(T.Id); - } -} - -// Push all definitions from the instruction node IA to an appropriate -// stack in DefM. -void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { - NodeSet Visited; -#ifndef NDEBUG - std::set<RegisterId> Defined; -#endif - - // The important objectives of this function are: - // - to be able to handle instructions both while the graph is being - // constructed, and after the graph has been constructed, and - // - maintain proper ordering of definitions on the stack for each - // register reference: - // - if there are two or more related defs in IA (i.e. coming from - // the same machine operand), then only push one def on the stack, - // - if there are multiple unrelated defs of non-overlapping - // subregisters of S, then the stack for S will have both (in an - // unspecified order), but the order does not matter from the data- - // -flow perspective. - - for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { - if (Visited.count(DA.Id)) - continue; - if (DA.Addr->getFlags() & NodeAttrs::Clobbering) - continue; - - NodeList Rel = getRelatedRefs(IA, DA); - NodeAddr<DefNode*> PDA = Rel.front(); - RegisterRef RR = PDA.Addr->getRegRef(*this); -#ifndef NDEBUG - // Assert if the register is defined in two or more unrelated defs. - // This could happen if there are two or more def operands defining it. - if (!Defined.insert(RR.Reg).second) { - MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode(); - dbgs() << "Multiple definitions of register: " - << Print<RegisterRef>(RR, *this) << " in\n " << *MI << "in " - << printMBBReference(*MI->getParent()) << '\n'; - llvm_unreachable(nullptr); - } -#endif - // Push the definition on the stack for the register and all aliases. - // The def stack traversal in linkNodeUp will check the exact aliasing. - DefM[RR.Reg].push(DA); - for (RegisterId A : PRI.getAliasSet(RR.Reg)) { - // Check that we don't push the same def twice. - assert(A != RR.Reg); - DefM[A].push(DA); - } - // Mark all the related defs as visited. - for (NodeAddr<NodeBase*> T : Rel) - Visited.insert(T.Id); - } -} - -// Return the list of all reference nodes related to RA, including RA itself. -// See "getNextRelated" for the meaning of a "related reference". -NodeList DataFlowGraph::getRelatedRefs(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const { - assert(IA.Id != 0 && RA.Id != 0); - - NodeList Refs; - NodeId Start = RA.Id; - do { - Refs.push_back(RA); - RA = getNextRelated(IA, RA); - } while (RA.Id != 0 && RA.Id != Start); - return Refs; -} - -// Clear all information in the graph. -void DataFlowGraph::reset() { - Memory.clear(); - BlockNodes.clear(); - Func = NodeAddr<FuncNode*>(); -} - -// Return the next reference node in the instruction node IA that is related -// to RA. Conceptually, two reference nodes are related if they refer to the -// same instance of a register access, but differ in flags or other minor -// characteristics. Specific examples of related nodes are shadow reference -// nodes. -// Return the equivalent of nullptr if there are no more related references. -NodeAddr<RefNode*> DataFlowGraph::getNextRelated(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const { - assert(IA.Id != 0 && RA.Id != 0); - - auto Related = [this,RA](NodeAddr<RefNode*> TA) -> bool { - if (TA.Addr->getKind() != RA.Addr->getKind()) - return false; - if (TA.Addr->getRegRef(*this) != RA.Addr->getRegRef(*this)) - return false; - return true; - }; - auto RelatedStmt = [&Related,RA](NodeAddr<RefNode*> TA) -> bool { - return Related(TA) && - &RA.Addr->getOp() == &TA.Addr->getOp(); - }; - auto RelatedPhi = [&Related,RA](NodeAddr<RefNode*> TA) -> bool { - if (!Related(TA)) - return false; - if (TA.Addr->getKind() != NodeAttrs::Use) - return true; - // For phi uses, compare predecessor blocks. - const NodeAddr<const PhiUseNode*> TUA = TA; - const NodeAddr<const PhiUseNode*> RUA = RA; - return TUA.Addr->getPredecessor() == RUA.Addr->getPredecessor(); - }; - - RegisterRef RR = RA.Addr->getRegRef(*this); - if (IA.Addr->getKind() == NodeAttrs::Stmt) - return RA.Addr->getNextRef(RR, RelatedStmt, true, *this); - return RA.Addr->getNextRef(RR, RelatedPhi, true, *this); -} - -// Find the next node related to RA in IA that satisfies condition P. -// If such a node was found, return a pair where the second element is the -// located node. If such a node does not exist, return a pair where the -// first element is the element after which such a node should be inserted, -// and the second element is a null-address. -template <typename Predicate> -std::pair<NodeAddr<RefNode*>,NodeAddr<RefNode*>> -DataFlowGraph::locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA, - Predicate P) const { - assert(IA.Id != 0 && RA.Id != 0); - - NodeAddr<RefNode*> NA; - NodeId Start = RA.Id; - while (true) { - NA = getNextRelated(IA, RA); - if (NA.Id == 0 || NA.Id == Start) - break; - if (P(NA)) - break; - RA = NA; - } - - if (NA.Id != 0 && NA.Id != Start) - return std::make_pair(RA, NA); - return std::make_pair(RA, NodeAddr<RefNode*>()); -} - -// Get the next shadow node in IA corresponding to RA, and optionally create -// such a node if it does not exist. -NodeAddr<RefNode*> DataFlowGraph::getNextShadow(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA, bool Create) { - assert(IA.Id != 0 && RA.Id != 0); - - uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow; - auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool { - return TA.Addr->getFlags() == Flags; - }; - auto Loc = locateNextRef(IA, RA, IsShadow); - if (Loc.second.Id != 0 || !Create) - return Loc.second; - - // Create a copy of RA and mark is as shadow. - NodeAddr<RefNode*> NA = cloneNode(RA); - NA.Addr->setFlags(Flags | NodeAttrs::Shadow); - IA.Addr->addMemberAfter(Loc.first, NA, *this); - return NA; -} - -// Get the next shadow node in IA corresponding to RA. Return null-address -// if such a node does not exist. -NodeAddr<RefNode*> DataFlowGraph::getNextShadow(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const { - assert(IA.Id != 0 && RA.Id != 0); - uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow; - auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool { - return TA.Addr->getFlags() == Flags; - }; - return locateNextRef(IA, RA, IsShadow).second; -} - -// Create a new statement node in the block node BA that corresponds to -// the machine instruction MI. -void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) { - NodeAddr<StmtNode*> SA = newStmt(BA, &In); - - auto isCall = [] (const MachineInstr &In) -> bool { - if (In.isCall()) - return true; - // Is tail call? - if (In.isBranch()) { - for (const MachineOperand &Op : In.operands()) - if (Op.isGlobal() || Op.isSymbol()) - return true; - // Assume indirect branches are calls. This is for the purpose of - // keeping implicit operands, and so it won't hurt on intra-function - // indirect branches. - if (In.isIndirectBranch()) - return true; - } - return false; - }; - - auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool { - // This instruction defines DR. Check if there is a use operand that - // would make DR live on entry to the instruction. - for (const MachineOperand &Op : In.operands()) { - if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef()) - continue; - RegisterRef UR = makeRegRef(Op); - if (PRI.alias(DR, UR)) - return false; - } - return true; - }; - - bool IsCall = isCall(In); - unsigned NumOps = In.getNumOperands(); - - // Avoid duplicate implicit defs. This will not detect cases of implicit - // defs that define registers that overlap, but it is not clear how to - // interpret that in the absence of explicit defs. Overlapping explicit - // defs are likely illegal already. - BitVector DoneDefs(TRI.getNumRegs()); - // Process explicit defs first. - for (unsigned OpN = 0; OpN < NumOps; ++OpN) { - MachineOperand &Op = In.getOperand(OpN); - if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) - continue; - Register R = Op.getReg(); - if (!R || !Register::isPhysicalRegister(R)) - continue; - uint16_t Flags = NodeAttrs::None; - if (TOI.isPreserving(In, OpN)) { - Flags |= NodeAttrs::Preserving; - // If the def is preserving, check if it is also undefined. - if (isDefUndef(In, makeRegRef(Op))) - Flags |= NodeAttrs::Undef; - } - if (TOI.isClobbering(In, OpN)) - Flags |= NodeAttrs::Clobbering; - if (TOI.isFixedReg(In, OpN)) - Flags |= NodeAttrs::Fixed; - if (IsCall && Op.isDead()) - Flags |= NodeAttrs::Dead; - NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); - SA.Addr->addMember(DA, *this); - assert(!DoneDefs.test(R)); - DoneDefs.set(R); - } - - // Process reg-masks (as clobbers). - BitVector DoneClobbers(TRI.getNumRegs()); - for (unsigned OpN = 0; OpN < NumOps; ++OpN) { - MachineOperand &Op = In.getOperand(OpN); - if (!Op.isRegMask()) - continue; - uint16_t Flags = NodeAttrs::Clobbering | NodeAttrs::Fixed | - NodeAttrs::Dead; - NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); - SA.Addr->addMember(DA, *this); - // Record all clobbered registers in DoneDefs. - const uint32_t *RM = Op.getRegMask(); - for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) - if (!(RM[i/32] & (1u << (i%32)))) - DoneClobbers.set(i); - } - - // Process implicit defs, skipping those that have already been added - // as explicit. - for (unsigned OpN = 0; OpN < NumOps; ++OpN) { - MachineOperand &Op = In.getOperand(OpN); - if (!Op.isReg() || !Op.isDef() || !Op.isImplicit()) - continue; - Register R = Op.getReg(); - if (!R || !Register::isPhysicalRegister(R) || DoneDefs.test(R)) - continue; - RegisterRef RR = makeRegRef(Op); - uint16_t Flags = NodeAttrs::None; - if (TOI.isPreserving(In, OpN)) { - Flags |= NodeAttrs::Preserving; - // If the def is preserving, check if it is also undefined. - if (isDefUndef(In, RR)) - Flags |= NodeAttrs::Undef; - } - if (TOI.isClobbering(In, OpN)) - Flags |= NodeAttrs::Clobbering; - if (TOI.isFixedReg(In, OpN)) - Flags |= NodeAttrs::Fixed; - if (IsCall && Op.isDead()) { - if (DoneClobbers.test(R)) - continue; - Flags |= NodeAttrs::Dead; - } - NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); - SA.Addr->addMember(DA, *this); - DoneDefs.set(R); - } - - for (unsigned OpN = 0; OpN < NumOps; ++OpN) { - MachineOperand &Op = In.getOperand(OpN); - if (!Op.isReg() || !Op.isUse()) - continue; - Register R = Op.getReg(); - if (!R || !Register::isPhysicalRegister(R)) - continue; - uint16_t Flags = NodeAttrs::None; - if (Op.isUndef()) - Flags |= NodeAttrs::Undef; - if (TOI.isFixedReg(In, OpN)) - Flags |= NodeAttrs::Fixed; - NodeAddr<UseNode*> UA = newUse(SA, Op, Flags); - SA.Addr->addMember(UA, *this); - } -} - -// Scan all defs in the block node BA and record in PhiM the locations of -// phi nodes corresponding to these defs. -void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM, - NodeAddr<BlockNode*> BA) { - // Check all defs from block BA and record them in each block in BA's - // iterated dominance frontier. This information will later be used to - // create phi nodes. - MachineBasicBlock *BB = BA.Addr->getCode(); - assert(BB); - auto DFLoc = MDF.find(BB); - if (DFLoc == MDF.end() || DFLoc->second.empty()) - return; - - // Traverse all instructions in the block and collect the set of all - // defined references. For each reference there will be a phi created - // in the block's iterated dominance frontier. - // This is done to make sure that each defined reference gets only one - // phi node, even if it is defined multiple times. - RegisterSet Defs; - for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) - for (NodeAddr<RefNode*> RA : IA.Addr->members_if(IsDef, *this)) - Defs.insert(RA.Addr->getRegRef(*this)); - - // Calculate the iterated dominance frontier of BB. - const MachineDominanceFrontier::DomSetType &DF = DFLoc->second; - SetVector<MachineBasicBlock*> IDF(DF.begin(), DF.end()); - for (unsigned i = 0; i < IDF.size(); ++i) { - auto F = MDF.find(IDF[i]); - if (F != MDF.end()) - IDF.insert(F->second.begin(), F->second.end()); - } - - // Finally, add the set of defs to each block in the iterated dominance - // frontier. - for (auto DB : IDF) { - NodeAddr<BlockNode*> DBA = findBlock(DB); - PhiM[DBA.Id].insert(Defs.begin(), Defs.end()); - } -} - -// Given the locations of phi nodes in the map PhiM, create the phi nodes -// that are located in the block node BA. -void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs, - NodeAddr<BlockNode*> BA) { - // Check if this blocks has any DF defs, i.e. if there are any defs - // that this block is in the iterated dominance frontier of. - auto HasDF = PhiM.find(BA.Id); - if (HasDF == PhiM.end() || HasDF->second.empty()) - return; - - // First, remove all R in Refs in such that there exists T in Refs - // such that T covers R. In other words, only leave those refs that - // are not covered by another ref (i.e. maximal with respect to covering). - - auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { - for (RegisterRef I : RRs) - if (I != RR && RegisterAggr::isCoverOf(I, RR, PRI)) - RR = I; - return RR; - }; - - RegisterSet MaxDF; - for (RegisterRef I : HasDF->second) - MaxDF.insert(MaxCoverIn(I, HasDF->second)); - - std::vector<RegisterRef> MaxRefs; - for (RegisterRef I : MaxDF) - MaxRefs.push_back(MaxCoverIn(I, AllRefs)); - - // Now, for each R in MaxRefs, get the alias closure of R. If the closure - // only has R in it, create a phi a def for R. Otherwise, create a phi, - // and add a def for each S in the closure. - - // Sort the refs so that the phis will be created in a deterministic order. - llvm::sort(MaxRefs); - // Remove duplicates. - auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end()); - MaxRefs.erase(NewEnd, MaxRefs.end()); - - auto Aliased = [this,&MaxRefs](RegisterRef RR, - std::vector<unsigned> &Closure) -> bool { - for (unsigned I : Closure) - if (PRI.alias(RR, MaxRefs[I])) - return true; - return false; - }; - - // Prepare a list of NodeIds of the block's predecessors. - NodeList Preds; - const MachineBasicBlock *MBB = BA.Addr->getCode(); - for (MachineBasicBlock *PB : MBB->predecessors()) - Preds.push_back(findBlock(PB)); - - while (!MaxRefs.empty()) { - // Put the first element in the closure, and then add all subsequent - // elements from MaxRefs to it, if they alias at least one element - // already in the closure. - // ClosureIdx: vector of indices in MaxRefs of members of the closure. - std::vector<unsigned> ClosureIdx = { 0 }; - for (unsigned i = 1; i != MaxRefs.size(); ++i) - if (Aliased(MaxRefs[i], ClosureIdx)) - ClosureIdx.push_back(i); - - // Build a phi for the closure. - unsigned CS = ClosureIdx.size(); - NodeAddr<PhiNode*> PA = newPhi(BA); - - // Add defs. - for (unsigned X = 0; X != CS; ++X) { - RegisterRef RR = MaxRefs[ClosureIdx[X]]; - uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving; - NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); - PA.Addr->addMember(DA, *this); - } - // Add phi uses. - for (NodeAddr<BlockNode*> PBA : Preds) { - for (unsigned X = 0; X != CS; ++X) { - RegisterRef RR = MaxRefs[ClosureIdx[X]]; - NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA); - PA.Addr->addMember(PUA, *this); - } - } - - // Erase from MaxRefs all elements in the closure. - auto Begin = MaxRefs.begin(); - for (unsigned i = ClosureIdx.size(); i != 0; --i) - MaxRefs.erase(Begin + ClosureIdx[i-1]); - } -} - -// Remove any unneeded phi nodes that were created during the build process. -void DataFlowGraph::removeUnusedPhis() { - // This will remove unused phis, i.e. phis where each def does not reach - // any uses or other defs. This will not detect or remove circular phi - // chains that are otherwise dead. Unused/dead phis are created during - // the build process and this function is intended to remove these cases - // that are easily determinable to be unnecessary. - - SetVector<NodeId> PhiQ; - for (NodeAddr<BlockNode*> BA : Func.Addr->members(*this)) { - for (auto P : BA.Addr->members_if(IsPhi, *this)) - PhiQ.insert(P.Id); - } - - static auto HasUsedDef = [](NodeList &Ms) -> bool { - for (NodeAddr<NodeBase*> M : Ms) { - if (M.Addr->getKind() != NodeAttrs::Def) - continue; - NodeAddr<DefNode*> DA = M; - if (DA.Addr->getReachedDef() != 0 || DA.Addr->getReachedUse() != 0) - return true; - } - return false; - }; - - // Any phi, if it is removed, may affect other phis (make them dead). - // For each removed phi, collect the potentially affected phis and add - // them back to the queue. - while (!PhiQ.empty()) { - auto PA = addr<PhiNode*>(PhiQ[0]); - PhiQ.remove(PA.Id); - NodeList Refs = PA.Addr->members(*this); - if (HasUsedDef(Refs)) - continue; - for (NodeAddr<RefNode*> RA : Refs) { - if (NodeId RD = RA.Addr->getReachingDef()) { - auto RDA = addr<DefNode*>(RD); - NodeAddr<InstrNode*> OA = RDA.Addr->getOwner(*this); - if (IsPhi(OA)) - PhiQ.insert(OA.Id); - } - if (RA.Addr->isDef()) - unlinkDef(RA, true); - else - unlinkUse(RA, true); - } - NodeAddr<BlockNode*> BA = PA.Addr->getOwner(*this); - BA.Addr->removeMember(PA, *this); - } -} - -// For a given reference node TA in an instruction node IA, connect the -// reaching def of TA to the appropriate def node. Create any shadow nodes -// as appropriate. -template <typename T> -void DataFlowGraph::linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA, - DefStack &DS) { - if (DS.empty()) - return; - RegisterRef RR = TA.Addr->getRegRef(*this); - NodeAddr<T> TAP; - - // References from the def stack that have been examined so far. - RegisterAggr Defs(PRI); - - for (auto I = DS.top(), E = DS.bottom(); I != E; I.down()) { - RegisterRef QR = I->Addr->getRegRef(*this); - - // Skip all defs that are aliased to any of the defs that we have already - // seen. If this completes a cover of RR, stop the stack traversal. - bool Alias = Defs.hasAliasOf(QR); - bool Cover = Defs.insert(QR).hasCoverOf(RR); - if (Alias) { - if (Cover) - break; - continue; - } - - // The reaching def. - NodeAddr<DefNode*> RDA = *I; - - // Pick the reached node. - if (TAP.Id == 0) { - TAP = TA; - } else { - // Mark the existing ref as "shadow" and create a new shadow. - TAP.Addr->setFlags(TAP.Addr->getFlags() | NodeAttrs::Shadow); - TAP = getNextShadow(IA, TAP, true); - } - - // Create the link. - TAP.Addr->linkToDef(TAP.Id, RDA); - - if (Cover) - break; - } -} - -// Create data-flow links for all reference nodes in the statement node SA. -template <typename Predicate> -void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA, - Predicate P) { -#ifndef NDEBUG - RegisterSet Defs; -#endif - - // Link all nodes (upwards in the data-flow) with their reaching defs. - for (NodeAddr<RefNode*> RA : SA.Addr->members_if(P, *this)) { - uint16_t Kind = RA.Addr->getKind(); - assert(Kind == NodeAttrs::Def || Kind == NodeAttrs::Use); - RegisterRef RR = RA.Addr->getRegRef(*this); -#ifndef NDEBUG - // Do not expect multiple defs of the same reference. - assert(Kind != NodeAttrs::Def || !Defs.count(RR)); - Defs.insert(RR); -#endif - - auto F = DefM.find(RR.Reg); - if (F == DefM.end()) - continue; - DefStack &DS = F->second; - if (Kind == NodeAttrs::Use) - linkRefUp<UseNode*>(SA, RA, DS); - else if (Kind == NodeAttrs::Def) - linkRefUp<DefNode*>(SA, RA, DS); - else - llvm_unreachable("Unexpected node in instruction"); - } -} - -// Create data-flow links for all instructions in the block node BA. This -// will include updating any phi nodes in BA. -void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA) { - // Push block delimiters. - markBlock(BA.Id, DefM); - - auto IsClobber = [] (NodeAddr<RefNode*> RA) -> bool { - return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering); - }; - auto IsNoClobber = [] (NodeAddr<RefNode*> RA) -> bool { - return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering); - }; - - assert(BA.Addr && "block node address is needed to create a data-flow link"); - // For each non-phi instruction in the block, link all the defs and uses - // to their reaching defs. For any member of the block (including phis), - // push the defs on the corresponding stacks. - for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) { - // Ignore phi nodes here. They will be linked part by part from the - // predecessors. - if (IA.Addr->getKind() == NodeAttrs::Stmt) { - linkStmtRefs(DefM, IA, IsUse); - linkStmtRefs(DefM, IA, IsClobber); - } - - // Push the definitions on the stack. - pushClobbers(IA, DefM); - - if (IA.Addr->getKind() == NodeAttrs::Stmt) - linkStmtRefs(DefM, IA, IsNoClobber); - - pushDefs(IA, DefM); - } - - // Recursively process all children in the dominator tree. - MachineDomTreeNode *N = MDT.getNode(BA.Addr->getCode()); - for (auto I : *N) { - MachineBasicBlock *SB = I->getBlock(); - NodeAddr<BlockNode*> SBA = findBlock(SB); - linkBlockRefs(DefM, SBA); - } - - // Link the phi uses from the successor blocks. - auto IsUseForBA = [BA](NodeAddr<NodeBase*> NA) -> bool { - if (NA.Addr->getKind() != NodeAttrs::Use) - return false; - assert(NA.Addr->getFlags() & NodeAttrs::PhiRef); - NodeAddr<PhiUseNode*> PUA = NA; - return PUA.Addr->getPredecessor() == BA.Id; - }; - - RegisterSet EHLiveIns = getLandingPadLiveIns(); - MachineBasicBlock *MBB = BA.Addr->getCode(); - - for (MachineBasicBlock *SB : MBB->successors()) { - bool IsEHPad = SB->isEHPad(); - NodeAddr<BlockNode*> SBA = findBlock(SB); - for (NodeAddr<InstrNode*> IA : SBA.Addr->members_if(IsPhi, *this)) { - // Do not link phi uses for landing pad live-ins. - if (IsEHPad) { - // Find what register this phi is for. - NodeAddr<RefNode*> RA = IA.Addr->getFirstMember(*this); - assert(RA.Id != 0); - if (EHLiveIns.count(RA.Addr->getRegRef(*this))) - continue; - } - // Go over each phi use associated with MBB, and link it. - for (auto U : IA.Addr->members_if(IsUseForBA, *this)) { - NodeAddr<PhiUseNode*> PUA = U; - RegisterRef RR = PUA.Addr->getRegRef(*this); - linkRefUp<UseNode*>(IA, PUA, DefM[RR.Reg]); - } - } - } - - // Pop all defs from this block from the definition stacks. - releaseBlock(BA.Id, DefM); -} - -// Remove the use node UA from any data-flow and structural links. -void DataFlowGraph::unlinkUseDF(NodeAddr<UseNode*> UA) { - NodeId RD = UA.Addr->getReachingDef(); - NodeId Sib = UA.Addr->getSibling(); - - if (RD == 0) { - assert(Sib == 0); - return; - } - - auto RDA = addr<DefNode*>(RD); - auto TA = addr<UseNode*>(RDA.Addr->getReachedUse()); - if (TA.Id == UA.Id) { - RDA.Addr->setReachedUse(Sib); - return; - } - - while (TA.Id != 0) { - NodeId S = TA.Addr->getSibling(); - if (S == UA.Id) { - TA.Addr->setSibling(UA.Addr->getSibling()); - return; - } - TA = addr<UseNode*>(S); - } -} - -// Remove the def node DA from any data-flow and structural links. -void DataFlowGraph::unlinkDefDF(NodeAddr<DefNode*> DA) { - // - // RD - // | reached - // | def - // : - // . - // +----+ - // ... -- | DA | -- ... -- 0 : sibling chain of DA - // +----+ - // | | reached - // | : def - // | . - // | ... : Siblings (defs) - // | - // : reached - // . use - // ... : sibling chain of reached uses - - NodeId RD = DA.Addr->getReachingDef(); - - // Visit all siblings of the reached def and reset their reaching defs. - // Also, defs reached by DA are now "promoted" to being reached by RD, - // so all of them will need to be spliced into the sibling chain where - // DA belongs. - auto getAllNodes = [this] (NodeId N) -> NodeList { - NodeList Res; - while (N) { - auto RA = addr<RefNode*>(N); - // Keep the nodes in the exact sibling order. - Res.push_back(RA); - N = RA.Addr->getSibling(); - } - return Res; - }; - NodeList ReachedDefs = getAllNodes(DA.Addr->getReachedDef()); - NodeList ReachedUses = getAllNodes(DA.Addr->getReachedUse()); - - if (RD == 0) { - for (NodeAddr<RefNode*> I : ReachedDefs) - I.Addr->setSibling(0); - for (NodeAddr<RefNode*> I : ReachedUses) - I.Addr->setSibling(0); - } - for (NodeAddr<DefNode*> I : ReachedDefs) - I.Addr->setReachingDef(RD); - for (NodeAddr<UseNode*> I : ReachedUses) - I.Addr->setReachingDef(RD); - - NodeId Sib = DA.Addr->getSibling(); - if (RD == 0) { - assert(Sib == 0); - return; - } - - // Update the reaching def node and remove DA from the sibling list. - auto RDA = addr<DefNode*>(RD); - auto TA = addr<DefNode*>(RDA.Addr->getReachedDef()); - if (TA.Id == DA.Id) { - // If DA is the first reached def, just update the RD's reached def - // to the DA's sibling. - RDA.Addr->setReachedDef(Sib); - } else { - // Otherwise, traverse the sibling list of the reached defs and remove - // DA from it. - while (TA.Id != 0) { - NodeId S = TA.Addr->getSibling(); - if (S == DA.Id) { - TA.Addr->setSibling(Sib); - break; - } - TA = addr<DefNode*>(S); - } - } - - // Splice the DA's reached defs into the RDA's reached def chain. - if (!ReachedDefs.empty()) { - auto Last = NodeAddr<DefNode*>(ReachedDefs.back()); - Last.Addr->setSibling(RDA.Addr->getReachedDef()); - RDA.Addr->setReachedDef(ReachedDefs.front().Id); - } - // Splice the DA's reached uses into the RDA's reached use chain. - if (!ReachedUses.empty()) { - auto Last = NodeAddr<UseNode*>(ReachedUses.back()); - Last.Addr->setSibling(RDA.Addr->getReachedUse()); - RDA.Addr->setReachedUse(ReachedUses.front().Id); - } -} diff --git a/llvm/lib/Target/Hexagon/RDFGraph.h b/llvm/lib/Target/Hexagon/RDFGraph.h deleted file mode 100644 index 585f43e116f96..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFGraph.h +++ /dev/null @@ -1,968 +0,0 @@ -//===- RDFGraph.h -----------------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Target-independent, SSA-based data flow graph for register data flow (RDF) -// for a non-SSA program representation (e.g. post-RA machine code). -// -// -// *** Introduction -// -// The RDF graph is a collection of nodes, each of which denotes some element -// of the program. There are two main types of such elements: code and refe- -// rences. Conceptually, "code" is something that represents the structure -// of the program, e.g. basic block or a statement, while "reference" is an -// instance of accessing a register, e.g. a definition or a use. Nodes are -// connected with each other based on the structure of the program (such as -// blocks, instructions, etc.), and based on the data flow (e.g. reaching -// definitions, reached uses, etc.). The single-reaching-definition principle -// of SSA is generally observed, although, due to the non-SSA representation -// of the program, there are some differences between the graph and a "pure" -// SSA representation. -// -// -// *** Implementation remarks -// -// Since the graph can contain a large number of nodes, memory consumption -// was one of the major design considerations. As a result, there is a single -// base class NodeBase which defines all members used by all possible derived -// classes. The members are arranged in a union, and a derived class cannot -// add any data members of its own. Each derived class only defines the -// functional interface, i.e. member functions. NodeBase must be a POD, -// which implies that all of its members must also be PODs. -// Since nodes need to be connected with other nodes, pointers have been -// replaced with 32-bit identifiers: each node has an id of type NodeId. -// There are mapping functions in the graph that translate between actual -// memory addresses and the corresponding identifiers. -// A node id of 0 is equivalent to nullptr. -// -// -// *** Structure of the graph -// -// A code node is always a collection of other nodes. For example, a code -// node corresponding to a basic block will contain code nodes corresponding -// to instructions. In turn, a code node corresponding to an instruction will -// contain a list of reference nodes that correspond to the definitions and -// uses of registers in that instruction. The members are arranged into a -// circular list, which is yet another consequence of the effort to save -// memory: for each member node it should be possible to obtain its owner, -// and it should be possible to access all other members. There are other -// ways to accomplish that, but the circular list seemed the most natural. -// -// +- CodeNode -+ -// | | <---------------------------------------------------+ -// +-+--------+-+ | -// |FirstM |LastM | -// | +-------------------------------------+ | -// | | | -// V V | -// +----------+ Next +----------+ Next Next +----------+ Next | -// | |----->| |-----> ... ----->| |----->-+ -// +- Member -+ +- Member -+ +- Member -+ -// -// The order of members is such that related reference nodes (see below) -// should be contiguous on the member list. -// -// A reference node is a node that encapsulates an access to a register, -// in other words, data flowing into or out of a register. There are two -// major kinds of reference nodes: defs and uses. A def node will contain -// the id of the first reached use, and the id of the first reached def. -// Each def and use will contain the id of the reaching def, and also the -// id of the next reached def (for def nodes) or use (for use nodes). -// The "next node sharing the same reaching def" is denoted as "sibling". -// In summary: -// - Def node contains: reaching def, sibling, first reached def, and first -// reached use. -// - Use node contains: reaching def and sibling. -// -// +-- DefNode --+ -// | R2 = ... | <---+--------------------+ -// ++---------+--+ | | -// |Reached |Reached | | -// |Def |Use | | -// | | |Reaching |Reaching -// | V |Def |Def -// | +-- UseNode --+ Sib +-- UseNode --+ Sib Sib -// | | ... = R2 |----->| ... = R2 |----> ... ----> 0 -// | +-------------+ +-------------+ -// V -// +-- DefNode --+ Sib -// | R2 = ... |----> ... -// ++---------+--+ -// | | -// | | -// ... ... -// -// To get a full picture, the circular lists connecting blocks within a -// function, instructions within a block, etc. should be superimposed with -// the def-def, def-use links shown above. -// To illustrate this, consider a small example in a pseudo-assembly: -// foo: -// add r2, r0, r1 ; r2 = r0+r1 -// addi r0, r2, 1 ; r0 = r2+1 -// ret r0 ; return value in r0 -// -// The graph (in a format used by the debugging functions) would look like: -// -// DFG dump:[ -// f1: Function foo -// b2: === %bb.0 === preds(0), succs(0): -// p3: phi [d4<r0>(,d12,u9):] -// p5: phi [d6<r1>(,,u10):] -// s7: add [d8<r2>(,,u13):, u9<r0>(d4):, u10<r1>(d6):] -// s11: addi [d12<r0>(d4,,u15):, u13<r2>(d8):] -// s14: ret [u15<r0>(d12):] -// ] -// -// The f1, b2, p3, etc. are node ids. The letter is prepended to indicate the -// kind of the node (i.e. f - function, b - basic block, p - phi, s - state- -// ment, d - def, u - use). -// The format of a def node is: -// dN<R>(rd,d,u):sib, -// where -// N - numeric node id, -// R - register being defined -// rd - reaching def, -// d - reached def, -// u - reached use, -// sib - sibling. -// The format of a use node is: -// uN<R>[!](rd):sib, -// where -// N - numeric node id, -// R - register being used, -// rd - reaching def, -// sib - sibling. -// Possible annotations (usually preceding the node id): -// + - preserving def, -// ~ - clobbering def, -// " - shadow ref (follows the node id), -// ! - fixed register (appears after register name). -// -// The circular lists are not explicit in the dump. -// -// -// *** Node attributes -// -// NodeBase has a member "Attrs", which is the primary way of determining -// the node's characteristics. The fields in this member decide whether -// the node is a code node or a reference node (i.e. node's "type"), then -// within each type, the "kind" determines what specifically this node -// represents. The remaining bits, "flags", contain additional information -// that is even more detailed than the "kind". -// CodeNode's kinds are: -// - Phi: Phi node, members are reference nodes. -// - Stmt: Statement, members are reference nodes. -// - Block: Basic block, members are instruction nodes (i.e. Phi or Stmt). -// - Func: The whole function. The members are basic block nodes. -// RefNode's kinds are: -// - Use. -// - Def. -// -// Meaning of flags: -// - Preserving: applies only to defs. A preserving def is one that can -// preserve some of the original bits among those that are included in -// the register associated with that def. For example, if R0 is a 32-bit -// register, but a def can only change the lower 16 bits, then it will -// be marked as preserving. -// - Shadow: a reference that has duplicates holding additional reaching -// defs (see more below). -// - Clobbering: applied only to defs, indicates that the value generated -// by this def is unspecified. A typical example would be volatile registers -// after function calls. -// - Fixed: the register in this def/use cannot be replaced with any other -// register. A typical case would be a parameter register to a call, or -// the register with the return value from a function. -// - Undef: the register in this reference the register is assumed to have -// no pre-existing value, even if it appears to be reached by some def. -// This is typically used to prevent keeping registers artificially live -// in cases when they are defined via predicated instructions. For example: -// r0 = add-if-true cond, r10, r11 (1) -// r0 = add-if-false cond, r12, r13, implicit r0 (2) -// ... = r0 (3) -// Before (1), r0 is not intended to be live, and the use of r0 in (3) is -// not meant to be reached by any def preceding (1). However, since the -// defs in (1) and (2) are both preserving, these properties alone would -// imply that the use in (3) may indeed be reached by some prior def. -// Adding Undef flag to the def in (1) prevents that. The Undef flag -// may be applied to both defs and uses. -// - Dead: applies only to defs. The value coming out of a "dead" def is -// assumed to be unused, even if the def appears to be reaching other defs -// or uses. The motivation for this flag comes from dead defs on function -// calls: there is no way to determine if such a def is dead without -// analyzing the target's ABI. Hence the graph should contain this info, -// as it is unavailable otherwise. On the other hand, a def without any -// uses on a typical instruction is not the intended target for this flag. -// -// *** Shadow references -// -// It may happen that a super-register can have two (or more) non-overlapping -// sub-registers. When both of these sub-registers are defined and followed -// by a use of the super-register, the use of the super-register will not -// have a unique reaching def: both defs of the sub-registers need to be -// accounted for. In such cases, a duplicate use of the super-register is -// added and it points to the extra reaching def. Both uses are marked with -// a flag "shadow". Example: -// Assume t0 is a super-register of r0 and r1, r0 and r1 do not overlap: -// set r0, 1 ; r0 = 1 -// set r1, 1 ; r1 = 1 -// addi t1, t0, 1 ; t1 = t0+1 -// -// The DFG: -// s1: set [d2<r0>(,,u9):] -// s3: set [d4<r1>(,,u10):] -// s5: addi [d6<t1>(,,):, u7"<t0>(d2):, u8"<t0>(d4):] -// -// The statement s5 has two use nodes for t0: u7" and u9". The quotation -// mark " indicates that the node is a shadow. -// - -#ifndef LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H -#define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H - -#include "RDFRegisters.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/MC/LaneBitmask.h" -#include "llvm/Support/Allocator.h" -#include "llvm/Support/MathExtras.h" -#include <cassert> -#include <cstdint> -#include <cstring> -#include <map> -#include <set> -#include <unordered_map> -#include <utility> -#include <vector> - -// RDF uses uint32_t to refer to registers. This is to ensure that the type -// size remains specific. In other places, registers are often stored using -// unsigned. -static_assert(sizeof(uint32_t) == sizeof(unsigned), "Those should be equal"); - -namespace llvm { - -class MachineBasicBlock; -class MachineDominanceFrontier; -class MachineDominatorTree; -class MachineFunction; -class MachineInstr; -class MachineOperand; -class raw_ostream; -class TargetInstrInfo; -class TargetRegisterInfo; - -namespace rdf { - - using NodeId = uint32_t; - - struct DataFlowGraph; - - struct NodeAttrs { - enum : uint16_t { - None = 0x0000, // Nothing - - // Types: 2 bits - TypeMask = 0x0003, - Code = 0x0001, // 01, Container - Ref = 0x0002, // 10, Reference - - // Kind: 3 bits - KindMask = 0x0007 << 2, - Def = 0x0001 << 2, // 001 - Use = 0x0002 << 2, // 010 - Phi = 0x0003 << 2, // 011 - Stmt = 0x0004 << 2, // 100 - Block = 0x0005 << 2, // 101 - Func = 0x0006 << 2, // 110 - - // Flags: 7 bits for now - FlagMask = 0x007F << 5, - Shadow = 0x0001 << 5, // 0000001, Has extra reaching defs. - Clobbering = 0x0002 << 5, // 0000010, Produces unspecified values. - PhiRef = 0x0004 << 5, // 0000100, Member of PhiNode. - Preserving = 0x0008 << 5, // 0001000, Def can keep original bits. - Fixed = 0x0010 << 5, // 0010000, Fixed register. - Undef = 0x0020 << 5, // 0100000, Has no pre-existing value. - Dead = 0x0040 << 5, // 1000000, Does not define a value. - }; - - static uint16_t type(uint16_t T) { return T & TypeMask; } - static uint16_t kind(uint16_t T) { return T & KindMask; } - static uint16_t flags(uint16_t T) { return T & FlagMask; } - - static uint16_t set_type(uint16_t A, uint16_t T) { - return (A & ~TypeMask) | T; - } - - static uint16_t set_kind(uint16_t A, uint16_t K) { - return (A & ~KindMask) | K; - } - - static uint16_t set_flags(uint16_t A, uint16_t F) { - return (A & ~FlagMask) | F; - } - - // Test if A contains B. - static bool contains(uint16_t A, uint16_t B) { - if (type(A) != Code) - return false; - uint16_t KB = kind(B); - switch (kind(A)) { - case Func: - return KB == Block; - case Block: - return KB == Phi || KB == Stmt; - case Phi: - case Stmt: - return type(B) == Ref; - } - return false; - } - }; - - struct BuildOptions { - enum : unsigned { - None = 0x00, - KeepDeadPhis = 0x01, // Do not remove dead phis during build. - }; - }; - - template <typename T> struct NodeAddr { - NodeAddr() = default; - NodeAddr(T A, NodeId I) : Addr(A), Id(I) {} - - // Type cast (casting constructor). The reason for having this class - // instead of std::pair. - template <typename S> NodeAddr(const NodeAddr<S> &NA) - : Addr(static_cast<T>(NA.Addr)), Id(NA.Id) {} - - bool operator== (const NodeAddr<T> &NA) const { - assert((Addr == NA.Addr) == (Id == NA.Id)); - return Addr == NA.Addr; - } - bool operator!= (const NodeAddr<T> &NA) const { - return !operator==(NA); - } - - T Addr = nullptr; - NodeId Id = 0; - }; - - struct NodeBase; - - // Fast memory allocation and translation between node id and node address. - // This is really the same idea as the one underlying the "bump pointer - // allocator", the difference being in the translation. A node id is - // composed of two components: the index of the block in which it was - // allocated, and the index within the block. With the default settings, - // where the number of nodes per block is 4096, the node id (minus 1) is: - // - // bit position: 11 0 - // +----------------------------+--------------+ - // | Index of the block |Index in block| - // +----------------------------+--------------+ - // - // The actual node id is the above plus 1, to avoid creating a node id of 0. - // - // This method significantly improved the build time, compared to using maps - // (std::unordered_map or DenseMap) to translate between pointers and ids. - struct NodeAllocator { - // Amount of storage for a single node. - enum { NodeMemSize = 32 }; - - NodeAllocator(uint32_t NPB = 4096) - : NodesPerBlock(NPB), BitsPerIndex(Log2_32(NPB)), - IndexMask((1 << BitsPerIndex)-1) { - assert(isPowerOf2_32(NPB)); - } - - NodeBase *ptr(NodeId N) const { - uint32_t N1 = N-1; - uint32_t BlockN = N1 >> BitsPerIndex; - uint32_t Offset = (N1 & IndexMask) * NodeMemSize; - return reinterpret_cast<NodeBase*>(Blocks[BlockN]+Offset); - } - - NodeId id(const NodeBase *P) const; - NodeAddr<NodeBase*> New(); - void clear(); - - private: - void startNewBlock(); - bool needNewBlock(); - - uint32_t makeId(uint32_t Block, uint32_t Index) const { - // Add 1 to the id, to avoid the id of 0, which is treated as "null". - return ((Block << BitsPerIndex) | Index) + 1; - } - - const uint32_t NodesPerBlock; - const uint32_t BitsPerIndex; - const uint32_t IndexMask; - char *ActiveEnd = nullptr; - std::vector<char*> Blocks; - using AllocatorTy = BumpPtrAllocatorImpl<MallocAllocator, 65536>; - AllocatorTy MemPool; - }; - - using RegisterSet = std::set<RegisterRef>; - - struct TargetOperandInfo { - TargetOperandInfo(const TargetInstrInfo &tii) : TII(tii) {} - virtual ~TargetOperandInfo() = default; - - virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const; - virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const; - virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const; - - const TargetInstrInfo &TII; - }; - - // Packed register reference. Only used for storage. - struct PackedRegisterRef { - RegisterId Reg; - uint32_t MaskId; - }; - - struct LaneMaskIndex : private IndexedSet<LaneBitmask> { - LaneMaskIndex() = default; - - LaneBitmask getLaneMaskForIndex(uint32_t K) const { - return K == 0 ? LaneBitmask::getAll() : get(K); - } - - uint32_t getIndexForLaneMask(LaneBitmask LM) { - assert(LM.any()); - return LM.all() ? 0 : insert(LM); - } - - uint32_t getIndexForLaneMask(LaneBitmask LM) const { - assert(LM.any()); - return LM.all() ? 0 : find(LM); - } - }; - - struct NodeBase { - public: - // Make sure this is a POD. - NodeBase() = default; - - uint16_t getType() const { return NodeAttrs::type(Attrs); } - uint16_t getKind() const { return NodeAttrs::kind(Attrs); } - uint16_t getFlags() const { return NodeAttrs::flags(Attrs); } - NodeId getNext() const { return Next; } - - uint16_t getAttrs() const { return Attrs; } - void setAttrs(uint16_t A) { Attrs = A; } - void setFlags(uint16_t F) { setAttrs(NodeAttrs::set_flags(getAttrs(), F)); } - - // Insert node NA after "this" in the circular chain. - void append(NodeAddr<NodeBase*> NA); - - // Initialize all members to 0. - void init() { memset(this, 0, sizeof *this); } - - void setNext(NodeId N) { Next = N; } - - protected: - uint16_t Attrs; - uint16_t Reserved; - NodeId Next; // Id of the next node in the circular chain. - // Definitions of nested types. Using anonymous nested structs would make - // this class definition clearer, but unnamed structs are not a part of - // the standard. - struct Def_struct { - NodeId DD, DU; // Ids of the first reached def and use. - }; - struct PhiU_struct { - NodeId PredB; // Id of the predecessor block for a phi use. - }; - struct Code_struct { - void *CP; // Pointer to the actual code. - NodeId FirstM, LastM; // Id of the first member and last. - }; - struct Ref_struct { - NodeId RD, Sib; // Ids of the reaching def and the sibling. - union { - Def_struct Def; - PhiU_struct PhiU; - }; - union { - MachineOperand *Op; // Non-phi refs point to a machine operand. - PackedRegisterRef PR; // Phi refs store register info directly. - }; - }; - - // The actual payload. - union { - Ref_struct Ref; - Code_struct Code; - }; - }; - // The allocator allocates chunks of 32 bytes for each node. The fact that - // each node takes 32 bytes in memory is used for fast translation between - // the node id and the node address. - static_assert(sizeof(NodeBase) <= NodeAllocator::NodeMemSize, - "NodeBase must be at most NodeAllocator::NodeMemSize bytes"); - - using NodeList = SmallVector<NodeAddr<NodeBase *>, 4>; - using NodeSet = std::set<NodeId>; - - struct RefNode : public NodeBase { - RefNode() = default; - - RegisterRef getRegRef(const DataFlowGraph &G) const; - - MachineOperand &getOp() { - assert(!(getFlags() & NodeAttrs::PhiRef)); - return *Ref.Op; - } - - void setRegRef(RegisterRef RR, DataFlowGraph &G); - void setRegRef(MachineOperand *Op, DataFlowGraph &G); - - NodeId getReachingDef() const { - return Ref.RD; - } - void setReachingDef(NodeId RD) { - Ref.RD = RD; - } - - NodeId getSibling() const { - return Ref.Sib; - } - void setSibling(NodeId Sib) { - Ref.Sib = Sib; - } - - bool isUse() const { - assert(getType() == NodeAttrs::Ref); - return getKind() == NodeAttrs::Use; - } - - bool isDef() const { - assert(getType() == NodeAttrs::Ref); - return getKind() == NodeAttrs::Def; - } - - template <typename Predicate> - NodeAddr<RefNode*> getNextRef(RegisterRef RR, Predicate P, bool NextOnly, - const DataFlowGraph &G); - NodeAddr<NodeBase*> getOwner(const DataFlowGraph &G); - }; - - struct DefNode : public RefNode { - NodeId getReachedDef() const { - return Ref.Def.DD; - } - void setReachedDef(NodeId D) { - Ref.Def.DD = D; - } - NodeId getReachedUse() const { - return Ref.Def.DU; - } - void setReachedUse(NodeId U) { - Ref.Def.DU = U; - } - - void linkToDef(NodeId Self, NodeAddr<DefNode*> DA); - }; - - struct UseNode : public RefNode { - void linkToDef(NodeId Self, NodeAddr<DefNode*> DA); - }; - - struct PhiUseNode : public UseNode { - NodeId getPredecessor() const { - assert(getFlags() & NodeAttrs::PhiRef); - return Ref.PhiU.PredB; - } - void setPredecessor(NodeId B) { - assert(getFlags() & NodeAttrs::PhiRef); - Ref.PhiU.PredB = B; - } - }; - - struct CodeNode : public NodeBase { - template <typename T> T getCode() const { - return static_cast<T>(Code.CP); - } - void setCode(void *C) { - Code.CP = C; - } - - NodeAddr<NodeBase*> getFirstMember(const DataFlowGraph &G) const; - NodeAddr<NodeBase*> getLastMember(const DataFlowGraph &G) const; - void addMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G); - void addMemberAfter(NodeAddr<NodeBase*> MA, NodeAddr<NodeBase*> NA, - const DataFlowGraph &G); - void removeMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G); - - NodeList members(const DataFlowGraph &G) const; - template <typename Predicate> - NodeList members_if(Predicate P, const DataFlowGraph &G) const; - }; - - struct InstrNode : public CodeNode { - NodeAddr<NodeBase*> getOwner(const DataFlowGraph &G); - }; - - struct PhiNode : public InstrNode { - MachineInstr *getCode() const { - return nullptr; - } - }; - - struct StmtNode : public InstrNode { - MachineInstr *getCode() const { - return CodeNode::getCode<MachineInstr*>(); - } - }; - - struct BlockNode : public CodeNode { - MachineBasicBlock *getCode() const { - return CodeNode::getCode<MachineBasicBlock*>(); - } - - void addPhi(NodeAddr<PhiNode*> PA, const DataFlowGraph &G); - }; - - struct FuncNode : public CodeNode { - MachineFunction *getCode() const { - return CodeNode::getCode<MachineFunction*>(); - } - - NodeAddr<BlockNode*> findBlock(const MachineBasicBlock *BB, - const DataFlowGraph &G) const; - NodeAddr<BlockNode*> getEntryBlock(const DataFlowGraph &G); - }; - - struct DataFlowGraph { - DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, - const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, - const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi); - - NodeBase *ptr(NodeId N) const; - template <typename T> T ptr(NodeId N) const { - return static_cast<T>(ptr(N)); - } - - NodeId id(const NodeBase *P) const; - - template <typename T> NodeAddr<T> addr(NodeId N) const { - return { ptr<T>(N), N }; - } - - NodeAddr<FuncNode*> getFunc() const { return Func; } - MachineFunction &getMF() const { return MF; } - const TargetInstrInfo &getTII() const { return TII; } - const TargetRegisterInfo &getTRI() const { return TRI; } - const PhysicalRegisterInfo &getPRI() const { return PRI; } - const MachineDominatorTree &getDT() const { return MDT; } - const MachineDominanceFrontier &getDF() const { return MDF; } - const RegisterAggr &getLiveIns() const { return LiveIns; } - - struct DefStack { - DefStack() = default; - - bool empty() const { return Stack.empty() || top() == bottom(); } - - private: - using value_type = NodeAddr<DefNode *>; - struct Iterator { - using value_type = DefStack::value_type; - - Iterator &up() { Pos = DS.nextUp(Pos); return *this; } - Iterator &down() { Pos = DS.nextDown(Pos); return *this; } - - value_type operator*() const { - assert(Pos >= 1); - return DS.Stack[Pos-1]; - } - const value_type *operator->() const { - assert(Pos >= 1); - return &DS.Stack[Pos-1]; - } - bool operator==(const Iterator &It) const { return Pos == It.Pos; } - bool operator!=(const Iterator &It) const { return Pos != It.Pos; } - - private: - friend struct DefStack; - - Iterator(const DefStack &S, bool Top); - - // Pos-1 is the index in the StorageType object that corresponds to - // the top of the DefStack. - const DefStack &DS; - unsigned Pos; - }; - - public: - using iterator = Iterator; - - iterator top() const { return Iterator(*this, true); } - iterator bottom() const { return Iterator(*this, false); } - unsigned size() const; - - void push(NodeAddr<DefNode*> DA) { Stack.push_back(DA); } - void pop(); - void start_block(NodeId N); - void clear_block(NodeId N); - - private: - friend struct Iterator; - - using StorageType = std::vector<value_type>; - - bool isDelimiter(const StorageType::value_type &P, NodeId N = 0) const { - return (P.Addr == nullptr) && (N == 0 || P.Id == N); - } - - unsigned nextUp(unsigned P) const; - unsigned nextDown(unsigned P) const; - - StorageType Stack; - }; - - // Make this std::unordered_map for speed of accessing elements. - // Map: Register (physical or virtual) -> DefStack - using DefStackMap = std::unordered_map<RegisterId, DefStack>; - - void build(unsigned Options = BuildOptions::None); - void pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM); - void markBlock(NodeId B, DefStackMap &DefM); - void releaseBlock(NodeId B, DefStackMap &DefM); - - PackedRegisterRef pack(RegisterRef RR) { - return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; - } - PackedRegisterRef pack(RegisterRef RR) const { - return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; - } - RegisterRef unpack(PackedRegisterRef PR) const { - return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); - } - - RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const; - RegisterRef makeRegRef(const MachineOperand &Op) const; - RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const; - - NodeAddr<RefNode*> getNextRelated(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const; - NodeAddr<RefNode*> getNextImp(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA, bool Create); - NodeAddr<RefNode*> getNextImp(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const; - NodeAddr<RefNode*> getNextShadow(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA, bool Create); - NodeAddr<RefNode*> getNextShadow(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const; - - NodeList getRelatedRefs(NodeAddr<InstrNode*> IA, - NodeAddr<RefNode*> RA) const; - - NodeAddr<BlockNode*> findBlock(MachineBasicBlock *BB) const { - return BlockNodes.at(BB); - } - - void unlinkUse(NodeAddr<UseNode*> UA, bool RemoveFromOwner) { - unlinkUseDF(UA); - if (RemoveFromOwner) - removeFromOwner(UA); - } - - void unlinkDef(NodeAddr<DefNode*> DA, bool RemoveFromOwner) { - unlinkDefDF(DA); - if (RemoveFromOwner) - removeFromOwner(DA); - } - - // Some useful filters. - template <uint16_t Kind> - static bool IsRef(const NodeAddr<NodeBase*> BA) { - return BA.Addr->getType() == NodeAttrs::Ref && - BA.Addr->getKind() == Kind; - } - - template <uint16_t Kind> - static bool IsCode(const NodeAddr<NodeBase*> BA) { - return BA.Addr->getType() == NodeAttrs::Code && - BA.Addr->getKind() == Kind; - } - - static bool IsDef(const NodeAddr<NodeBase*> BA) { - return BA.Addr->getType() == NodeAttrs::Ref && - BA.Addr->getKind() == NodeAttrs::Def; - } - - static bool IsUse(const NodeAddr<NodeBase*> BA) { - return BA.Addr->getType() == NodeAttrs::Ref && - BA.Addr->getKind() == NodeAttrs::Use; - } - - static bool IsPhi(const NodeAddr<NodeBase*> BA) { - return BA.Addr->getType() == NodeAttrs::Code && - BA.Addr->getKind() == NodeAttrs::Phi; - } - - static bool IsPreservingDef(const NodeAddr<DefNode*> DA) { - uint16_t Flags = DA.Addr->getFlags(); - return (Flags & NodeAttrs::Preserving) && !(Flags & NodeAttrs::Undef); - } - - private: - void reset(); - - RegisterSet getLandingPadLiveIns() const; - - NodeAddr<NodeBase*> newNode(uint16_t Attrs); - NodeAddr<NodeBase*> cloneNode(const NodeAddr<NodeBase*> B); - NodeAddr<UseNode*> newUse(NodeAddr<InstrNode*> Owner, - MachineOperand &Op, uint16_t Flags = NodeAttrs::None); - NodeAddr<PhiUseNode*> newPhiUse(NodeAddr<PhiNode*> Owner, - RegisterRef RR, NodeAddr<BlockNode*> PredB, - uint16_t Flags = NodeAttrs::PhiRef); - NodeAddr<DefNode*> newDef(NodeAddr<InstrNode*> Owner, - MachineOperand &Op, uint16_t Flags = NodeAttrs::None); - NodeAddr<DefNode*> newDef(NodeAddr<InstrNode*> Owner, - RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef); - NodeAddr<PhiNode*> newPhi(NodeAddr<BlockNode*> Owner); - NodeAddr<StmtNode*> newStmt(NodeAddr<BlockNode*> Owner, - MachineInstr *MI); - NodeAddr<BlockNode*> newBlock(NodeAddr<FuncNode*> Owner, - MachineBasicBlock *BB); - NodeAddr<FuncNode*> newFunc(MachineFunction *MF); - - template <typename Predicate> - std::pair<NodeAddr<RefNode*>,NodeAddr<RefNode*>> - locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA, - Predicate P) const; - - using BlockRefsMap = std::map<NodeId, RegisterSet>; - - void buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In); - void recordDefsForDF(BlockRefsMap &PhiM, NodeAddr<BlockNode*> BA); - void buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs, - NodeAddr<BlockNode*> BA); - void removeUnusedPhis(); - - void pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DM); - void pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM); - template <typename T> void linkRefUp(NodeAddr<InstrNode*> IA, - NodeAddr<T> TA, DefStack &DS); - template <typename Predicate> void linkStmtRefs(DefStackMap &DefM, - NodeAddr<StmtNode*> SA, Predicate P); - void linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA); - - void unlinkUseDF(NodeAddr<UseNode*> UA); - void unlinkDefDF(NodeAddr<DefNode*> DA); - - void removeFromOwner(NodeAddr<RefNode*> RA) { - NodeAddr<InstrNode*> IA = RA.Addr->getOwner(*this); - IA.Addr->removeMember(RA, *this); - } - - MachineFunction &MF; - const TargetInstrInfo &TII; - const TargetRegisterInfo &TRI; - const PhysicalRegisterInfo PRI; - const MachineDominatorTree &MDT; - const MachineDominanceFrontier &MDF; - const TargetOperandInfo &TOI; - - RegisterAggr LiveIns; - NodeAddr<FuncNode*> Func; - NodeAllocator Memory; - // Local map: MachineBasicBlock -> NodeAddr<BlockNode*> - std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes; - // Lane mask map. - LaneMaskIndex LMI; - }; // struct DataFlowGraph - - template <typename Predicate> - NodeAddr<RefNode*> RefNode::getNextRef(RegisterRef RR, Predicate P, - bool NextOnly, const DataFlowGraph &G) { - // Get the "Next" reference in the circular list that references RR and - // satisfies predicate "Pred". - auto NA = G.addr<NodeBase*>(getNext()); - - while (NA.Addr != this) { - if (NA.Addr->getType() == NodeAttrs::Ref) { - NodeAddr<RefNode*> RA = NA; - if (RA.Addr->getRegRef(G) == RR && P(NA)) - return NA; - if (NextOnly) - break; - NA = G.addr<NodeBase*>(NA.Addr->getNext()); - } else { - // We've hit the beginning of the chain. - assert(NA.Addr->getType() == NodeAttrs::Code); - NodeAddr<CodeNode*> CA = NA; - NA = CA.Addr->getFirstMember(G); - } - } - // Return the equivalent of "nullptr" if such a node was not found. - return NodeAddr<RefNode*>(); - } - - template <typename Predicate> - NodeList CodeNode::members_if(Predicate P, const DataFlowGraph &G) const { - NodeList MM; - auto M = getFirstMember(G); - if (M.Id == 0) - return MM; - - while (M.Addr != this) { - if (P(M)) - MM.push_back(M); - M = G.addr<NodeBase*>(M.Addr->getNext()); - } - return MM; - } - - template <typename T> - struct Print { - Print(const T &x, const DataFlowGraph &g) : Obj(x), G(g) {} - - const T &Obj; - const DataFlowGraph &G; - }; - - template <typename T> - struct PrintNode : Print<NodeAddr<T>> { - PrintNode(const NodeAddr<T> &x, const DataFlowGraph &g) - : Print<NodeAddr<T>>(x, g) {} - }; - - raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterRef> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeId> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<DefNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<UseNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<NodeAddr<PhiUseNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<RefNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeList> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeSet> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<PhiNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<NodeAddr<StmtNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<NodeAddr<InstrNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<NodeAddr<BlockNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<NodeAddr<FuncNode *>> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterSet> &P); - raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterAggr> &P); - raw_ostream &operator<<(raw_ostream &OS, - const Print<DataFlowGraph::DefStack> &P); - -} // end namespace rdf - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp deleted file mode 100644 index e2c007c9d01af..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp +++ /dev/null @@ -1,1118 +0,0 @@ -//===- RDFLiveness.cpp ----------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Computation of the liveness information from the data-flow graph. -// -// The main functionality of this code is to compute block live-in -// information. With the live-in information in place, the placement -// of kill flags can also be recalculated. -// -// The block live-in calculation is based on the ideas from the following -// publication: -// -// Dibyendu Das, Ramakrishna Upadrasta, Benoit Dupont de Dinechin. -// "Efficient Liveness Computation Using Merge Sets and DJ-Graphs." -// ACM Transactions on Architecture and Code Optimization, Association for -// Computing Machinery, 2012, ACM TACO Special Issue on "High-Performance -// and Embedded Architectures and Compilers", 8 (4), -// <10.1145/2086696.2086706>. <hal-00647369> -// -#include "RDFLiveness.h" -#include "RDFGraph.h" -#include "RDFRegisters.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SetVector.h" -#include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/MachineDominanceFrontier.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/MC/LaneBitmask.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include <algorithm> -#include <cassert> -#include <cstdint> -#include <iterator> -#include <map> -#include <utility> -#include <vector> - -using namespace llvm; -using namespace rdf; - -static cl::opt<unsigned> MaxRecNest("rdf-liveness-max-rec", cl::init(25), - cl::Hidden, cl::desc("Maximum recursion level")); - -namespace llvm { -namespace rdf { - - raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) { - OS << '{'; - for (auto &I : P.Obj) { - OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{'; - for (auto J = I.second.begin(), E = I.second.end(); J != E; ) { - OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second); - if (++J != E) - OS << ','; - } - OS << '}'; - } - OS << " }"; - return OS; - } - -} // end namespace rdf -} // end namespace llvm - -// The order in the returned sequence is the order of reaching defs in the -// upward traversal: the first def is the closest to the given reference RefA, -// the next one is further up, and so on. -// The list ends at a reaching phi def, or when the reference from RefA is -// covered by the defs in the list (see FullChain). -// This function provides two modes of operation: -// (1) Returning the sequence of reaching defs for a particular reference -// node. This sequence will terminate at the first phi node [1]. -// (2) Returning a partial sequence of reaching defs, where the final goal -// is to traverse past phi nodes to the actual defs arising from the code -// itself. -// In mode (2), the register reference for which the search was started -// may be different from the reference node RefA, for which this call was -// made, hence the argument RefRR, which holds the original register. -// Also, some definitions may have already been encountered in a previous -// call that will influence register covering. The register references -// already defined are passed in through DefRRs. -// In mode (1), the "continuation" considerations do not apply, and the -// RefRR is the same as the register in RefA, and the set DefRRs is empty. -// -// [1] It is possible for multiple phi nodes to be included in the returned -// sequence: -// SubA = phi ... -// SubB = phi ... -// ... = SuperAB(rdef:SubA), SuperAB"(rdef:SubB) -// However, these phi nodes are independent from one another in terms of -// the data-flow. - -NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, - NodeAddr<RefNode*> RefA, bool TopShadows, bool FullChain, - const RegisterAggr &DefRRs) { - NodeList RDefs; // Return value. - SetVector<NodeId> DefQ; - SetVector<NodeId> Owners; - - // Dead defs will be treated as if they were live, since they are actually - // on the data-flow path. They cannot be ignored because even though they - // do not generate meaningful values, they still modify registers. - - // If the reference is undefined, there is nothing to do. - if (RefA.Addr->getFlags() & NodeAttrs::Undef) - return RDefs; - - // The initial queue should not have reaching defs for shadows. The - // whole point of a shadow is that it will have a reaching def that - // is not aliased to the reaching defs of the related shadows. - NodeId Start = RefA.Id; - auto SNA = DFG.addr<RefNode*>(Start); - if (NodeId RD = SNA.Addr->getReachingDef()) - DefQ.insert(RD); - if (TopShadows) { - for (auto S : DFG.getRelatedRefs(RefA.Addr->getOwner(DFG), RefA)) - if (NodeId RD = NodeAddr<RefNode*>(S).Addr->getReachingDef()) - DefQ.insert(RD); - } - - // Collect all the reaching defs, going up until a phi node is encountered, - // or there are no more reaching defs. From this set, the actual set of - // reaching defs will be selected. - // The traversal upwards must go on until a covering def is encountered. - // It is possible that a collection of non-covering (individually) defs - // will be sufficient, but keep going until a covering one is found. - for (unsigned i = 0; i < DefQ.size(); ++i) { - auto TA = DFG.addr<DefNode*>(DefQ[i]); - if (TA.Addr->getFlags() & NodeAttrs::PhiRef) - continue; - // Stop at the covering/overwriting def of the initial register reference. - RegisterRef RR = TA.Addr->getRegRef(DFG); - if (!DFG.IsPreservingDef(TA)) - if (RegisterAggr::isCoverOf(RR, RefRR, PRI)) - continue; - // Get the next level of reaching defs. This will include multiple - // reaching defs for shadows. - for (auto S : DFG.getRelatedRefs(TA.Addr->getOwner(DFG), TA)) - if (NodeId RD = NodeAddr<RefNode*>(S).Addr->getReachingDef()) - DefQ.insert(RD); - } - - // Remove all non-phi defs that are not aliased to RefRR, and collect - // the owners of the remaining defs. - SetVector<NodeId> Defs; - for (NodeId N : DefQ) { - auto TA = DFG.addr<DefNode*>(N); - bool IsPhi = TA.Addr->getFlags() & NodeAttrs::PhiRef; - if (!IsPhi && !PRI.alias(RefRR, TA.Addr->getRegRef(DFG))) - continue; - Defs.insert(TA.Id); - Owners.insert(TA.Addr->getOwner(DFG).Id); - } - - // Return the MachineBasicBlock containing a given instruction. - auto Block = [this] (NodeAddr<InstrNode*> IA) -> MachineBasicBlock* { - if (IA.Addr->getKind() == NodeAttrs::Stmt) - return NodeAddr<StmtNode*>(IA).Addr->getCode()->getParent(); - assert(IA.Addr->getKind() == NodeAttrs::Phi); - NodeAddr<PhiNode*> PA = IA; - NodeAddr<BlockNode*> BA = PA.Addr->getOwner(DFG); - return BA.Addr->getCode(); - }; - // Less(A,B) iff instruction A is further down in the dominator tree than B. - auto Less = [&Block,this] (NodeId A, NodeId B) -> bool { - if (A == B) - return false; - auto OA = DFG.addr<InstrNode*>(A), OB = DFG.addr<InstrNode*>(B); - MachineBasicBlock *BA = Block(OA), *BB = Block(OB); - if (BA != BB) - return MDT.dominates(BB, BA); - // They are in the same block. - bool StmtA = OA.Addr->getKind() == NodeAttrs::Stmt; - bool StmtB = OB.Addr->getKind() == NodeAttrs::Stmt; - if (StmtA) { - if (!StmtB) // OB is a phi and phis dominate statements. - return true; - MachineInstr *CA = NodeAddr<StmtNode*>(OA).Addr->getCode(); - MachineInstr *CB = NodeAddr<StmtNode*>(OB).Addr->getCode(); - // The order must be linear, so tie-break such equalities. - if (CA == CB) - return A < B; - return MDT.dominates(CB, CA); - } else { - // OA is a phi. - if (StmtB) - return false; - // Both are phis. There is no ordering between phis (in terms of - // the data-flow), so tie-break this via node id comparison. - return A < B; - } - }; - - std::vector<NodeId> Tmp(Owners.begin(), Owners.end()); - llvm::sort(Tmp, Less); - - // The vector is a list of instructions, so that defs coming from - // the same instruction don't need to be artificially ordered. - // Then, when computing the initial segment, and iterating over an - // instruction, pick the defs that contribute to the covering (i.e. is - // not covered by previously added defs). Check the defs individually, - // i.e. first check each def if is covered or not (without adding them - // to the tracking set), and then add all the selected ones. - - // The reason for this is this example: - // *d1<A>, *d2<B>, ... Assume A and B are aliased (can happen in phi nodes). - // *d3<C> If A \incl BuC, and B \incl AuC, then *d2 would be - // covered if we added A first, and A would be covered - // if we added B first. - - RegisterAggr RRs(DefRRs); - - auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool { - return TA.Addr->getKind() == NodeAttrs::Def && - Defs.count(TA.Id); - }; - for (NodeId T : Tmp) { - if (!FullChain && RRs.hasCoverOf(RefRR)) - break; - auto TA = DFG.addr<InstrNode*>(T); - bool IsPhi = DFG.IsCode<NodeAttrs::Phi>(TA); - NodeList Ds; - for (NodeAddr<DefNode*> DA : TA.Addr->members_if(DefInSet, DFG)) { - RegisterRef QR = DA.Addr->getRegRef(DFG); - // Add phi defs even if they are covered by subsequent defs. This is - // for cases where the reached use is not covered by any of the defs - // encountered so far: the phi def is needed to expose the liveness - // of that use to the entry of the block. - // Example: - // phi d1<R3>(,d2,), ... Phi def d1 is covered by d2. - // d2<R3>(d1,,u3), ... - // ..., u3<D1>(d2) This use needs to be live on entry. - if (FullChain || IsPhi || !RRs.hasCoverOf(QR)) - Ds.push_back(DA); - } - RDefs.insert(RDefs.end(), Ds.begin(), Ds.end()); - for (NodeAddr<DefNode*> DA : Ds) { - // When collecting a full chain of definitions, do not consider phi - // defs to actually define a register. - uint16_t Flags = DA.Addr->getFlags(); - if (!FullChain || !(Flags & NodeAttrs::PhiRef)) - if (!(Flags & NodeAttrs::Preserving)) // Don't care about Undef here. - RRs.insert(DA.Addr->getRegRef(DFG)); - } - } - - auto DeadP = [](const NodeAddr<DefNode*> DA) -> bool { - return DA.Addr->getFlags() & NodeAttrs::Dead; - }; - RDefs.resize(std::distance(RDefs.begin(), llvm::remove_if(RDefs, DeadP))); - - return RDefs; -} - -std::pair<NodeSet,bool> -Liveness::getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, - NodeSet &Visited, const NodeSet &Defs) { - return getAllReachingDefsRecImpl(RefRR, RefA, Visited, Defs, 0, MaxRecNest); -} - -std::pair<NodeSet,bool> -Liveness::getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode*> RefA, - NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) { - if (Nest > MaxNest) - return { NodeSet(), false }; - // Collect all defined registers. Do not consider phis to be defining - // anything, only collect "real" definitions. - RegisterAggr DefRRs(PRI); - for (NodeId D : Defs) { - const auto DA = DFG.addr<const DefNode*>(D); - if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef)) - DefRRs.insert(DA.Addr->getRegRef(DFG)); - } - - NodeList RDs = getAllReachingDefs(RefRR, RefA, false, true, DefRRs); - if (RDs.empty()) - return { Defs, true }; - - // Make a copy of the preexisting definitions and add the newly found ones. - NodeSet TmpDefs = Defs; - for (NodeAddr<NodeBase*> R : RDs) - TmpDefs.insert(R.Id); - - NodeSet Result = Defs; - - for (NodeAddr<DefNode*> DA : RDs) { - Result.insert(DA.Id); - if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef)) - continue; - NodeAddr<PhiNode*> PA = DA.Addr->getOwner(DFG); - if (Visited.count(PA.Id)) - continue; - Visited.insert(PA.Id); - // Go over all phi uses and get the reaching defs for each use. - for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) { - const auto &T = getAllReachingDefsRecImpl(RefRR, U, Visited, TmpDefs, - Nest+1, MaxNest); - if (!T.second) - return { T.first, false }; - Result.insert(T.first.begin(), T.first.end()); - } - } - - return { Result, true }; -} - -/// Find the nearest ref node aliased to RefRR, going upwards in the data -/// flow, starting from the instruction immediately preceding Inst. -NodeAddr<RefNode*> Liveness::getNearestAliasedRef(RegisterRef RefRR, - NodeAddr<InstrNode*> IA) { - NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG); - NodeList Ins = BA.Addr->members(DFG); - NodeId FindId = IA.Id; - auto E = Ins.rend(); - auto B = std::find_if(Ins.rbegin(), E, - [FindId] (const NodeAddr<InstrNode*> T) { - return T.Id == FindId; - }); - // Do not scan IA (which is what B would point to). - if (B != E) - ++B; - - do { - // Process the range of instructions from B to E. - for (NodeAddr<InstrNode*> I : make_range(B, E)) { - NodeList Refs = I.Addr->members(DFG); - NodeAddr<RefNode*> Clob, Use; - // Scan all the refs in I aliased to RefRR, and return the one that - // is the closest to the output of I, i.e. def > clobber > use. - for (NodeAddr<RefNode*> R : Refs) { - if (!PRI.alias(R.Addr->getRegRef(DFG), RefRR)) - continue; - if (DFG.IsDef(R)) { - // If it's a non-clobbering def, just return it. - if (!(R.Addr->getFlags() & NodeAttrs::Clobbering)) - return R; - Clob = R; - } else { - Use = R; - } - } - if (Clob.Id != 0) - return Clob; - if (Use.Id != 0) - return Use; - } - - // Go up to the immediate dominator, if any. - MachineBasicBlock *BB = BA.Addr->getCode(); - BA = NodeAddr<BlockNode*>(); - if (MachineDomTreeNode *N = MDT.getNode(BB)) { - if ((N = N->getIDom())) - BA = DFG.findBlock(N->getBlock()); - } - if (!BA.Id) - break; - - Ins = BA.Addr->members(DFG); - B = Ins.rbegin(); - E = Ins.rend(); - } while (true); - - return NodeAddr<RefNode*>(); -} - -NodeSet Liveness::getAllReachedUses(RegisterRef RefRR, - NodeAddr<DefNode*> DefA, const RegisterAggr &DefRRs) { - NodeSet Uses; - - // If the original register is already covered by all the intervening - // defs, no more uses can be reached. - if (DefRRs.hasCoverOf(RefRR)) - return Uses; - - // Add all directly reached uses. - // If the def is dead, it does not provide a value for any use. - bool IsDead = DefA.Addr->getFlags() & NodeAttrs::Dead; - NodeId U = !IsDead ? DefA.Addr->getReachedUse() : 0; - while (U != 0) { - auto UA = DFG.addr<UseNode*>(U); - if (!(UA.Addr->getFlags() & NodeAttrs::Undef)) { - RegisterRef UR = UA.Addr->getRegRef(DFG); - if (PRI.alias(RefRR, UR) && !DefRRs.hasCoverOf(UR)) - Uses.insert(U); - } - U = UA.Addr->getSibling(); - } - - // Traverse all reached defs. This time dead defs cannot be ignored. - for (NodeId D = DefA.Addr->getReachedDef(), NextD; D != 0; D = NextD) { - auto DA = DFG.addr<DefNode*>(D); - NextD = DA.Addr->getSibling(); - RegisterRef DR = DA.Addr->getRegRef(DFG); - // If this def is already covered, it cannot reach anything new. - // Similarly, skip it if it is not aliased to the interesting register. - if (DefRRs.hasCoverOf(DR) || !PRI.alias(RefRR, DR)) - continue; - NodeSet T; - if (DFG.IsPreservingDef(DA)) { - // If it is a preserving def, do not update the set of intervening defs. - T = getAllReachedUses(RefRR, DA, DefRRs); - } else { - RegisterAggr NewDefRRs = DefRRs; - NewDefRRs.insert(DR); - T = getAllReachedUses(RefRR, DA, NewDefRRs); - } - Uses.insert(T.begin(), T.end()); - } - return Uses; -} - -void Liveness::computePhiInfo() { - RealUseMap.clear(); - - NodeList Phis; - NodeAddr<FuncNode*> FA = DFG.getFunc(); - NodeList Blocks = FA.Addr->members(DFG); - for (NodeAddr<BlockNode*> BA : Blocks) { - auto Ps = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG); - Phis.insert(Phis.end(), Ps.begin(), Ps.end()); - } - - // phi use -> (map: reaching phi -> set of registers defined in between) - std::map<NodeId,std::map<NodeId,RegisterAggr>> PhiUp; - std::vector<NodeId> PhiUQ; // Work list of phis for upward propagation. - std::map<NodeId,RegisterAggr> PhiDRs; // Phi -> registers defined by it. - - // Go over all phis. - for (NodeAddr<PhiNode*> PhiA : Phis) { - // Go over all defs and collect the reached uses that are non-phi uses - // (i.e. the "real uses"). - RefMap &RealUses = RealUseMap[PhiA.Id]; - NodeList PhiRefs = PhiA.Addr->members(DFG); - - // Have a work queue of defs whose reached uses need to be found. - // For each def, add to the queue all reached (non-phi) defs. - SetVector<NodeId> DefQ; - NodeSet PhiDefs; - RegisterAggr DRs(PRI); - for (NodeAddr<RefNode*> R : PhiRefs) { - if (!DFG.IsRef<NodeAttrs::Def>(R)) - continue; - DRs.insert(R.Addr->getRegRef(DFG)); - DefQ.insert(R.Id); - PhiDefs.insert(R.Id); - } - PhiDRs.insert(std::make_pair(PhiA.Id, DRs)); - - // Collect the super-set of all possible reached uses. This set will - // contain all uses reached from this phi, either directly from the - // phi defs, or (recursively) via non-phi defs reached by the phi defs. - // This set of uses will later be trimmed to only contain these uses that - // are actually reached by the phi defs. - for (unsigned i = 0; i < DefQ.size(); ++i) { - NodeAddr<DefNode*> DA = DFG.addr<DefNode*>(DefQ[i]); - // Visit all reached uses. Phi defs should not really have the "dead" - // flag set, but check it anyway for consistency. - bool IsDead = DA.Addr->getFlags() & NodeAttrs::Dead; - NodeId UN = !IsDead ? DA.Addr->getReachedUse() : 0; - while (UN != 0) { - NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN); - uint16_t F = A.Addr->getFlags(); - if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) { - RegisterRef R = PRI.normalize(A.Addr->getRegRef(DFG)); - RealUses[R.Reg].insert({A.Id,R.Mask}); - } - UN = A.Addr->getSibling(); - } - // Visit all reached defs, and add them to the queue. These defs may - // override some of the uses collected here, but that will be handled - // later. - NodeId DN = DA.Addr->getReachedDef(); - while (DN != 0) { - NodeAddr<DefNode*> A = DFG.addr<DefNode*>(DN); - for (auto T : DFG.getRelatedRefs(A.Addr->getOwner(DFG), A)) { - uint16_t Flags = NodeAddr<DefNode*>(T).Addr->getFlags(); - // Must traverse the reached-def chain. Consider: - // def(D0) -> def(R0) -> def(R0) -> use(D0) - // The reachable use of D0 passes through a def of R0. - if (!(Flags & NodeAttrs::PhiRef)) - DefQ.insert(T.Id); - } - DN = A.Addr->getSibling(); - } - } - // Filter out these uses that appear to be reachable, but really - // are not. For example: - // - // R1:0 = d1 - // = R1:0 u2 Reached by d1. - // R0 = d3 - // = R1:0 u4 Still reached by d1: indirectly through - // the def d3. - // R1 = d5 - // = R1:0 u6 Not reached by d1 (covered collectively - // by d3 and d5), but following reached - // defs and uses from d1 will lead here. - for (auto UI = RealUses.begin(), UE = RealUses.end(); UI != UE; ) { - // For each reached register UI->first, there is a set UI->second, of - // uses of it. For each such use, check if it is reached by this phi, - // i.e. check if the set of its reaching uses intersects the set of - // this phi's defs. - NodeRefSet Uses = UI->second; - UI->second.clear(); - for (std::pair<NodeId,LaneBitmask> I : Uses) { - auto UA = DFG.addr<UseNode*>(I.first); - // Undef flag is checked above. - assert((UA.Addr->getFlags() & NodeAttrs::Undef) == 0); - RegisterRef R(UI->first, I.second); - // Calculate the exposed part of the reached use. - RegisterAggr Covered(PRI); - for (NodeAddr<DefNode*> DA : getAllReachingDefs(R, UA)) { - if (PhiDefs.count(DA.Id)) - break; - Covered.insert(DA.Addr->getRegRef(DFG)); - } - if (RegisterRef RC = Covered.clearIn(R)) { - // We are updating the map for register UI->first, so we need - // to map RC to be expressed in terms of that register. - RegisterRef S = PRI.mapTo(RC, UI->first); - UI->second.insert({I.first, S.Mask}); - } - } - UI = UI->second.empty() ? RealUses.erase(UI) : std::next(UI); - } - - // If this phi reaches some "real" uses, add it to the queue for upward - // propagation. - if (!RealUses.empty()) - PhiUQ.push_back(PhiA.Id); - - // Go over all phi uses and check if the reaching def is another phi. - // Collect the phis that are among the reaching defs of these uses. - // While traversing the list of reaching defs for each phi use, accumulate - // the set of registers defined between this phi (PhiA) and the owner phi - // of the reaching def. - NodeSet SeenUses; - - for (auto I : PhiRefs) { - if (!DFG.IsRef<NodeAttrs::Use>(I) || SeenUses.count(I.Id)) - continue; - NodeAddr<PhiUseNode*> PUA = I; - if (PUA.Addr->getReachingDef() == 0) - continue; - - RegisterRef UR = PUA.Addr->getRegRef(DFG); - NodeList Ds = getAllReachingDefs(UR, PUA, true, false, NoRegs); - RegisterAggr DefRRs(PRI); - - for (NodeAddr<DefNode*> D : Ds) { - if (D.Addr->getFlags() & NodeAttrs::PhiRef) { - NodeId RP = D.Addr->getOwner(DFG).Id; - std::map<NodeId,RegisterAggr> &M = PhiUp[PUA.Id]; - auto F = M.find(RP); - if (F == M.end()) - M.insert(std::make_pair(RP, DefRRs)); - else - F->second.insert(DefRRs); - } - DefRRs.insert(D.Addr->getRegRef(DFG)); - } - - for (NodeAddr<PhiUseNode*> T : DFG.getRelatedRefs(PhiA, PUA)) - SeenUses.insert(T.Id); - } - } - - if (Trace) { - dbgs() << "Phi-up-to-phi map with intervening defs:\n"; - for (auto I : PhiUp) { - dbgs() << "phi " << Print<NodeId>(I.first, DFG) << " -> {"; - for (auto R : I.second) - dbgs() << ' ' << Print<NodeId>(R.first, DFG) - << Print<RegisterAggr>(R.second, DFG); - dbgs() << " }\n"; - } - } - - // Propagate the reached registers up in the phi chain. - // - // The following type of situation needs careful handling: - // - // phi d1<R1:0> (1) - // | - // ... d2<R1> - // | - // phi u3<R1:0> (2) - // | - // ... u4<R1> - // - // The phi node (2) defines a register pair R1:0, and reaches a "real" - // use u4 of just R1. The same phi node is also known to reach (upwards) - // the phi node (1). However, the use u4 is not reached by phi (1), - // because of the intervening definition d2 of R1. The data flow between - // phis (1) and (2) is restricted to R1:0 minus R1, i.e. R0. - // - // When propagating uses up the phi chains, get the all reaching defs - // for a given phi use, and traverse the list until the propagated ref - // is covered, or until reaching the final phi. Only assume that the - // reference reaches the phi in the latter case. - - for (unsigned i = 0; i < PhiUQ.size(); ++i) { - auto PA = DFG.addr<PhiNode*>(PhiUQ[i]); - NodeList PUs = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG); - RefMap &RUM = RealUseMap[PA.Id]; - - for (NodeAddr<UseNode*> UA : PUs) { - std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id]; - RegisterRef UR = PRI.normalize(UA.Addr->getRegRef(DFG)); - for (const std::pair<const NodeId, RegisterAggr> &P : PUM) { - bool Changed = false; - const RegisterAggr &MidDefs = P.second; - - // Collect the set PropUp of uses that are reached by the current - // phi PA, and are not covered by any intervening def between the - // currently visited use UA and the upward phi P. - - if (MidDefs.hasCoverOf(UR)) - continue; - - // General algorithm: - // for each (R,U) : U is use node of R, U is reached by PA - // if MidDefs does not cover (R,U) - // then add (R-MidDefs,U) to RealUseMap[P] - // - for (const std::pair<const RegisterId, NodeRefSet> &T : RUM) { - RegisterRef R(T.first); - // The current phi (PA) could be a phi for a regmask. It could - // reach a whole variety of uses that are not related to the - // specific upward phi (P.first). - const RegisterAggr &DRs = PhiDRs.at(P.first); - if (!DRs.hasAliasOf(R)) - continue; - R = PRI.mapTo(DRs.intersectWith(R), T.first); - for (std::pair<NodeId,LaneBitmask> V : T.second) { - LaneBitmask M = R.Mask & V.second; - if (M.none()) - continue; - if (RegisterRef SS = MidDefs.clearIn(RegisterRef(R.Reg, M))) { - NodeRefSet &RS = RealUseMap[P.first][SS.Reg]; - Changed |= RS.insert({V.first,SS.Mask}).second; - } - } - } - - if (Changed) - PhiUQ.push_back(P.first); - } - } - } - - if (Trace) { - dbgs() << "Real use map:\n"; - for (auto I : RealUseMap) { - dbgs() << "phi " << Print<NodeId>(I.first, DFG); - NodeAddr<PhiNode*> PA = DFG.addr<PhiNode*>(I.first); - NodeList Ds = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Def>, DFG); - if (!Ds.empty()) { - RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG); - dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>'; - } else { - dbgs() << "<noreg>"; - } - dbgs() << " -> " << Print<RefMap>(I.second, DFG) << '\n'; - } - } -} - -void Liveness::computeLiveIns() { - // Populate the node-to-block map. This speeds up the calculations - // significantly. - NBMap.clear(); - for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) { - MachineBasicBlock *BB = BA.Addr->getCode(); - for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) { - for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) - NBMap.insert(std::make_pair(RA.Id, BB)); - NBMap.insert(std::make_pair(IA.Id, BB)); - } - } - - MachineFunction &MF = DFG.getMF(); - - // Compute IDF first, then the inverse. - decltype(IIDF) IDF; - for (MachineBasicBlock &B : MF) { - auto F1 = MDF.find(&B); - if (F1 == MDF.end()) - continue; - SetVector<MachineBasicBlock*> IDFB(F1->second.begin(), F1->second.end()); - for (unsigned i = 0; i < IDFB.size(); ++i) { - auto F2 = MDF.find(IDFB[i]); - if (F2 != MDF.end()) - IDFB.insert(F2->second.begin(), F2->second.end()); - } - // Add B to the IDF(B). This will put B in the IIDF(B). - IDFB.insert(&B); - IDF[&B].insert(IDFB.begin(), IDFB.end()); - } - - for (auto I : IDF) - for (auto S : I.second) - IIDF[S].insert(I.first); - - computePhiInfo(); - - NodeAddr<FuncNode*> FA = DFG.getFunc(); - NodeList Blocks = FA.Addr->members(DFG); - - // Build the phi live-on-entry map. - for (NodeAddr<BlockNode*> BA : Blocks) { - MachineBasicBlock *MB = BA.Addr->getCode(); - RefMap &LON = PhiLON[MB]; - for (auto P : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG)) - for (const RefMap::value_type &S : RealUseMap[P.Id]) - LON[S.first].insert(S.second.begin(), S.second.end()); - } - - if (Trace) { - dbgs() << "Phi live-on-entry map:\n"; - for (auto &I : PhiLON) - dbgs() << "block #" << I.first->getNumber() << " -> " - << Print<RefMap>(I.second, DFG) << '\n'; - } - - // Build the phi live-on-exit map. Each phi node has some set of reached - // "real" uses. Propagate this set backwards into the block predecessors - // through the reaching defs of the corresponding phi uses. - for (NodeAddr<BlockNode*> BA : Blocks) { - NodeList Phis = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG); - for (NodeAddr<PhiNode*> PA : Phis) { - RefMap &RUs = RealUseMap[PA.Id]; - if (RUs.empty()) - continue; - - NodeSet SeenUses; - for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) { - if (!SeenUses.insert(U.Id).second) - continue; - NodeAddr<PhiUseNode*> PUA = U; - if (PUA.Addr->getReachingDef() == 0) - continue; - - // Each phi has some set (possibly empty) of reached "real" uses, - // that is, uses that are part of the compiled program. Such a use - // may be located in some farther block, but following a chain of - // reaching defs will eventually lead to this phi. - // Any chain of reaching defs may fork at a phi node, but there - // will be a path upwards that will lead to this phi. Now, this - // chain will need to fork at this phi, since some of the reached - // uses may have definitions joining in from multiple predecessors. - // For each reached "real" use, identify the set of reaching defs - // coming from each predecessor P, and add them to PhiLOX[P]. - // - auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor()); - RefMap &LOX = PhiLOX[PrA.Addr->getCode()]; - - for (const std::pair<const RegisterId, NodeRefSet> &RS : RUs) { - // We need to visit each individual use. - for (std::pair<NodeId,LaneBitmask> P : RS.second) { - // Create a register ref corresponding to the use, and find - // all reaching defs starting from the phi use, and treating - // all related shadows as a single use cluster. - RegisterRef S(RS.first, P.second); - NodeList Ds = getAllReachingDefs(S, PUA, true, false, NoRegs); - for (NodeAddr<DefNode*> D : Ds) { - // Calculate the mask corresponding to the visited def. - RegisterAggr TA(PRI); - TA.insert(D.Addr->getRegRef(DFG)).intersect(S); - LaneBitmask TM = TA.makeRegRef().Mask; - LOX[S.Reg].insert({D.Id, TM}); - } - } - } - - for (NodeAddr<PhiUseNode*> T : DFG.getRelatedRefs(PA, PUA)) - SeenUses.insert(T.Id); - } // for U : phi uses - } // for P : Phis - } // for B : Blocks - - if (Trace) { - dbgs() << "Phi live-on-exit map:\n"; - for (auto &I : PhiLOX) - dbgs() << "block #" << I.first->getNumber() << " -> " - << Print<RefMap>(I.second, DFG) << '\n'; - } - - RefMap LiveIn; - traverse(&MF.front(), LiveIn); - - // Add function live-ins to the live-in set of the function entry block. - LiveMap[&MF.front()].insert(DFG.getLiveIns()); - - if (Trace) { - // Dump the liveness map - for (MachineBasicBlock &B : MF) { - std::vector<RegisterRef> LV; - for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I) - LV.push_back(RegisterRef(I->PhysReg, I->LaneMask)); - llvm::sort(LV); - dbgs() << printMBBReference(B) << "\t rec = {"; - for (auto I : LV) - dbgs() << ' ' << Print<RegisterRef>(I, DFG); - dbgs() << " }\n"; - //dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n'; - - LV.clear(); - const RegisterAggr &LG = LiveMap[&B]; - for (auto I = LG.rr_begin(), E = LG.rr_end(); I != E; ++I) - LV.push_back(*I); - llvm::sort(LV); - dbgs() << "\tcomp = {"; - for (auto I : LV) - dbgs() << ' ' << Print<RegisterRef>(I, DFG); - dbgs() << " }\n"; - - } - } -} - -void Liveness::resetLiveIns() { - for (auto &B : DFG.getMF()) { - // Remove all live-ins. - std::vector<unsigned> T; - for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I) - T.push_back(I->PhysReg); - for (auto I : T) - B.removeLiveIn(I); - // Add the newly computed live-ins. - const RegisterAggr &LiveIns = LiveMap[&B]; - for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) { - RegisterRef R = *I; - B.addLiveIn({MCPhysReg(R.Reg), R.Mask}); - } - } -} - -void Liveness::resetKills() { - for (auto &B : DFG.getMF()) - resetKills(&B); -} - -void Liveness::resetKills(MachineBasicBlock *B) { - auto CopyLiveIns = [this] (MachineBasicBlock *B, BitVector &LV) -> void { - for (auto I : B->liveins()) { - MCSubRegIndexIterator S(I.PhysReg, &TRI); - if (!S.isValid()) { - LV.set(I.PhysReg); - continue; - } - do { - LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex()); - if ((M & I.LaneMask).any()) - LV.set(S.getSubReg()); - ++S; - } while (S.isValid()); - } - }; - - BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs()); - CopyLiveIns(B, LiveIn); - for (auto SI : B->successors()) - CopyLiveIns(SI, Live); - - for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) { - MachineInstr *MI = &*I; - if (MI->isDebugInstr()) - continue; - - MI->clearKillInfo(); - for (auto &Op : MI->operands()) { - // An implicit def of a super-register may not necessarily start a - // live range of it, since an implicit use could be used to keep parts - // of it live. Instead of analyzing the implicit operands, ignore - // implicit defs. - if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) - continue; - Register R = Op.getReg(); - if (!Register::isPhysicalRegister(R)) - continue; - for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR) - Live.reset(*SR); - } - for (auto &Op : MI->operands()) { - if (!Op.isReg() || !Op.isUse() || Op.isUndef()) - continue; - Register R = Op.getReg(); - if (!Register::isPhysicalRegister(R)) - continue; - bool IsLive = false; - for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) { - if (!Live[*AR]) - continue; - IsLive = true; - break; - } - if (!IsLive) - Op.setIsKill(true); - for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR) - Live.set(*SR); - } - } -} - -// Helper function to obtain the basic block containing the reaching def -// of the given use. -MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const { - auto F = NBMap.find(RN); - if (F != NBMap.end()) - return F->second; - llvm_unreachable("Node id not in map"); -} - -void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { - // The LiveIn map, for each (physical) register, contains the set of live - // reaching defs of that register that are live on entry to the associated - // block. - - // The summary of the traversal algorithm: - // - // R is live-in in B, if there exists a U(R), such that rdef(R) dom B - // and (U \in IDF(B) or B dom U). - // - // for (C : children) { - // LU = {} - // traverse(C, LU) - // LiveUses += LU - // } - // - // LiveUses -= Defs(B); - // LiveUses += UpwardExposedUses(B); - // for (C : IIDF[B]) - // for (U : LiveUses) - // if (Rdef(U) dom C) - // C.addLiveIn(U) - // - - // Go up the dominator tree (depth-first). - MachineDomTreeNode *N = MDT.getNode(B); - for (auto I : *N) { - RefMap L; - MachineBasicBlock *SB = I->getBlock(); - traverse(SB, L); - - for (auto S : L) - LiveIn[S.first].insert(S.second.begin(), S.second.end()); - } - - if (Trace) { - dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__ - << " after recursion into: {"; - for (auto I : *N) - dbgs() << ' ' << I->getBlock()->getNumber(); - dbgs() << " }\n"; - dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n'; - dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n'; - } - - // Add reaching defs of phi uses that are live on exit from this block. - RefMap &PUs = PhiLOX[B]; - for (auto &S : PUs) - LiveIn[S.first].insert(S.second.begin(), S.second.end()); - - if (Trace) { - dbgs() << "after LOX\n"; - dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n'; - dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n'; - } - - // The LiveIn map at this point has all defs that are live-on-exit from B, - // as if they were live-on-entry to B. First, we need to filter out all - // defs that are present in this block. Then we will add reaching defs of - // all upward-exposed uses. - - // To filter out the defs, first make a copy of LiveIn, and then re-populate - // LiveIn with the defs that should remain. - RefMap LiveInCopy = LiveIn; - LiveIn.clear(); - - for (const std::pair<const RegisterId, NodeRefSet> &LE : LiveInCopy) { - RegisterRef LRef(LE.first); - NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled. - const NodeRefSet &OldDefs = LE.second; - for (NodeRef OR : OldDefs) { - // R is a def node that was live-on-exit - auto DA = DFG.addr<DefNode*>(OR.first); - NodeAddr<InstrNode*> IA = DA.Addr->getOwner(DFG); - NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG); - if (B != BA.Addr->getCode()) { - // Defs from a different block need to be preserved. Defs from this - // block will need to be processed further, except for phi defs, the - // liveness of which is handled through the PhiLON/PhiLOX maps. - NewDefs.insert(OR); - continue; - } - - // Defs from this block need to stop the liveness from being - // propagated upwards. This only applies to non-preserving defs, - // and to the parts of the register actually covered by those defs. - // (Note that phi defs should always be preserving.) - RegisterAggr RRs(PRI); - LRef.Mask = OR.second; - - if (!DFG.IsPreservingDef(DA)) { - assert(!(IA.Addr->getFlags() & NodeAttrs::Phi)); - // DA is a non-phi def that is live-on-exit from this block, and - // that is also located in this block. LRef is a register ref - // whose use this def reaches. If DA covers LRef, then no part - // of LRef is exposed upwards.A - if (RRs.insert(DA.Addr->getRegRef(DFG)).hasCoverOf(LRef)) - continue; - } - - // DA itself was not sufficient to cover LRef. In general, it is - // the last in a chain of aliased defs before the exit from this block. - // There could be other defs in this block that are a part of that - // chain. Check that now: accumulate the registers from these defs, - // and if they all together cover LRef, it is not live-on-entry. - for (NodeAddr<DefNode*> TA : getAllReachingDefs(DA)) { - // DefNode -> InstrNode -> BlockNode. - NodeAddr<InstrNode*> ITA = TA.Addr->getOwner(DFG); - NodeAddr<BlockNode*> BTA = ITA.Addr->getOwner(DFG); - // Reaching defs are ordered in the upward direction. - if (BTA.Addr->getCode() != B) { - // We have reached past the beginning of B, and the accumulated - // registers are not covering LRef. The first def from the - // upward chain will be live. - // Subtract all accumulated defs (RRs) from LRef. - RegisterRef T = RRs.clearIn(LRef); - assert(T); - NewDefs.insert({TA.Id,T.Mask}); - break; - } - - // TA is in B. Only add this def to the accumulated cover if it is - // not preserving. - if (!(TA.Addr->getFlags() & NodeAttrs::Preserving)) - RRs.insert(TA.Addr->getRegRef(DFG)); - // If this is enough to cover LRef, then stop. - if (RRs.hasCoverOf(LRef)) - break; - } - } - } - - emptify(LiveIn); - - if (Trace) { - dbgs() << "after defs in block\n"; - dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n'; - dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n'; - } - - // Scan the block for upward-exposed uses and add them to the tracking set. - for (auto I : DFG.getFunc().Addr->findBlock(B, DFG).Addr->members(DFG)) { - NodeAddr<InstrNode*> IA = I; - if (IA.Addr->getKind() != NodeAttrs::Stmt) - continue; - for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) { - if (UA.Addr->getFlags() & NodeAttrs::Undef) - continue; - RegisterRef RR = PRI.normalize(UA.Addr->getRegRef(DFG)); - for (NodeAddr<DefNode*> D : getAllReachingDefs(UA)) - if (getBlockWithRef(D.Id) != B) - LiveIn[RR.Reg].insert({D.Id,RR.Mask}); - } - } - - if (Trace) { - dbgs() << "after uses in block\n"; - dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n'; - dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n'; - } - - // Phi uses should not be propagated up the dominator tree, since they - // are not dominated by their corresponding reaching defs. - RegisterAggr &Local = LiveMap[B]; - RefMap &LON = PhiLON[B]; - for (auto &R : LON) { - LaneBitmask M; - for (auto P : R.second) - M |= P.second; - Local.insert(RegisterRef(R.first,M)); - } - - if (Trace) { - dbgs() << "after phi uses in block\n"; - dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n'; - dbgs() << " Local: " << Print<RegisterAggr>(Local, DFG) << '\n'; - } - - for (auto C : IIDF[B]) { - RegisterAggr &LiveC = LiveMap[C]; - for (const std::pair<const RegisterId, NodeRefSet> &S : LiveIn) - for (auto R : S.second) - if (MDT.properlyDominates(getBlockWithRef(R.first), C)) - LiveC.insert(RegisterRef(S.first, R.second)); - } -} - -void Liveness::emptify(RefMap &M) { - for (auto I = M.begin(), E = M.end(); I != E; ) - I = I->second.empty() ? M.erase(I) : std::next(I); -} diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.h b/llvm/lib/Target/Hexagon/RDFLiveness.h deleted file mode 100644 index ea48902717266..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFLiveness.h +++ /dev/null @@ -1,151 +0,0 @@ -//===- RDFLiveness.h --------------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Recalculate the liveness information given a data flow graph. -// This includes block live-ins and kill flags. - -#ifndef LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H -#define LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H - -#include "RDFGraph.h" -#include "RDFRegisters.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/MC/LaneBitmask.h" -#include <map> -#include <set> -#include <utility> - -namespace llvm { - -class MachineBasicBlock; -class MachineDominanceFrontier; -class MachineDominatorTree; -class MachineRegisterInfo; -class TargetRegisterInfo; - -namespace rdf { - - struct Liveness { - public: - // This is really a std::map, except that it provides a non-trivial - // default constructor to the element accessed via []. - struct LiveMapType { - LiveMapType(const PhysicalRegisterInfo &pri) : Empty(pri) {} - - RegisterAggr &operator[] (MachineBasicBlock *B) { - return Map.emplace(B, Empty).first->second; - } - - private: - RegisterAggr Empty; - std::map<MachineBasicBlock*,RegisterAggr> Map; - }; - - using NodeRef = std::pair<NodeId, LaneBitmask>; - using NodeRefSet = std::set<NodeRef>; - // RegisterId in RefMap must be normalized. - using RefMap = std::map<RegisterId, NodeRefSet>; - - Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g) - : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()), - MDF(g.getDF()), LiveMap(g.getPRI()), Empty(), NoRegs(g.getPRI()) {} - - NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA, - bool TopShadows, bool FullChain, const RegisterAggr &DefRRs); - - NodeList getAllReachingDefs(NodeAddr<RefNode*> RefA) { - return getAllReachingDefs(RefA.Addr->getRegRef(DFG), RefA, false, - false, NoRegs); - } - - NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA) { - return getAllReachingDefs(RefRR, RefA, false, false, NoRegs); - } - - NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA, - const RegisterAggr &DefRRs); - - NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA) { - return getAllReachedUses(RefRR, DefA, NoRegs); - } - - std::pair<NodeSet,bool> getAllReachingDefsRec(RegisterRef RefRR, - NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs); - - NodeAddr<RefNode*> getNearestAliasedRef(RegisterRef RefRR, - NodeAddr<InstrNode*> IA); - - LiveMapType &getLiveMap() { return LiveMap; } - const LiveMapType &getLiveMap() const { return LiveMap; } - - const RefMap &getRealUses(NodeId P) const { - auto F = RealUseMap.find(P); - return F == RealUseMap.end() ? Empty : F->second; - } - - void computePhiInfo(); - void computeLiveIns(); - void resetLiveIns(); - void resetKills(); - void resetKills(MachineBasicBlock *B); - - void trace(bool T) { Trace = T; } - - private: - const DataFlowGraph &DFG; - const TargetRegisterInfo &TRI; - const PhysicalRegisterInfo &PRI; - const MachineDominatorTree &MDT; - const MachineDominanceFrontier &MDF; - LiveMapType LiveMap; - const RefMap Empty; - const RegisterAggr NoRegs; - bool Trace = false; - - // Cache of mapping from node ids (for RefNodes) to the containing - // basic blocks. Not computing it each time for each node reduces - // the liveness calculation time by a large fraction. - using NodeBlockMap = DenseMap<NodeId, MachineBasicBlock *>; - NodeBlockMap NBMap; - - // Phi information: - // - // RealUseMap - // map: NodeId -> (map: RegisterId -> NodeRefSet) - // phi id -> (map: register -> set of reached non-phi uses) - std::map<NodeId, RefMap> RealUseMap; - - // Inverse iterated dominance frontier. - std::map<MachineBasicBlock*,std::set<MachineBasicBlock*>> IIDF; - - // Live on entry. - std::map<MachineBasicBlock*,RefMap> PhiLON; - - // Phi uses are considered to be located at the end of the block that - // they are associated with. The reaching def of a phi use dominates the - // block that the use corresponds to, but not the block that contains - // the phi itself. To include these uses in the liveness propagation (up - // the dominator tree), create a map: block -> set of uses live on exit. - std::map<MachineBasicBlock*,RefMap> PhiLOX; - - MachineBasicBlock *getBlockWithRef(NodeId RN) const; - void traverse(MachineBasicBlock *B, RefMap &LiveIn); - void emptify(RefMap &M); - - std::pair<NodeSet,bool> getAllReachingDefsRecImpl(RegisterRef RefRR, - NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs, - unsigned Nest, unsigned MaxNest); - }; - - raw_ostream &operator<<(raw_ostream &OS, const Print<Liveness::RefMap> &P); - -} // end namespace rdf - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/Target/Hexagon/RDFRegisters.cpp deleted file mode 100644 index b5675784e34b8..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp +++ /dev/null @@ -1,380 +0,0 @@ -//===- RDFRegisters.cpp ---------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "RDFRegisters.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineOperand.h" -#include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/MC/LaneBitmask.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include <cassert> -#include <cstdint> -#include <set> -#include <utility> - -using namespace llvm; -using namespace rdf; - -PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri, - const MachineFunction &mf) - : TRI(tri) { - RegInfos.resize(TRI.getNumRegs()); - - BitVector BadRC(TRI.getNumRegs()); - for (const TargetRegisterClass *RC : TRI.regclasses()) { - for (MCPhysReg R : *RC) { - RegInfo &RI = RegInfos[R]; - if (RI.RegClass != nullptr && !BadRC[R]) { - if (RC->LaneMask != RI.RegClass->LaneMask) { - BadRC.set(R); - RI.RegClass = nullptr; - } - } else - RI.RegClass = RC; - } - } - - UnitInfos.resize(TRI.getNumRegUnits()); - - for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) { - if (UnitInfos[U].Reg != 0) - continue; - MCRegUnitRootIterator R(U, &TRI); - assert(R.isValid()); - RegisterId F = *R; - ++R; - if (R.isValid()) { - UnitInfos[U].Mask = LaneBitmask::getAll(); - UnitInfos[U].Reg = F; - } else { - for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) { - std::pair<uint32_t,LaneBitmask> P = *I; - UnitInfo &UI = UnitInfos[P.first]; - UI.Reg = F; - if (P.second.any()) { - UI.Mask = P.second; - } else { - if (const TargetRegisterClass *RC = RegInfos[F].RegClass) - UI.Mask = RC->LaneMask; - else - UI.Mask = LaneBitmask::getAll(); - } - } - } - } - - for (const uint32_t *RM : TRI.getRegMasks()) - RegMasks.insert(RM); - for (const MachineBasicBlock &B : mf) - for (const MachineInstr &In : B) - for (const MachineOperand &Op : In.operands()) - if (Op.isRegMask()) - RegMasks.insert(Op.getRegMask()); - - MaskInfos.resize(RegMasks.size()+1); - for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) { - BitVector PU(TRI.getNumRegUnits()); - const uint32_t *MB = RegMasks.get(M); - for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) { - if (!(MB[i/32] & (1u << (i%32)))) - continue; - for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U) - PU.set(*U); - } - MaskInfos[M].Units = PU.flip(); - } -} - -RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { - return RR; -} - -std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const { - // Do not include RR in the alias set. - std::set<RegisterId> AS; - assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); - if (isRegMaskId(Reg)) { - // XXX SLOW - const uint32_t *MB = getRegMaskBits(Reg); - for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) { - if (MB[i/32] & (1u << (i%32))) - continue; - AS.insert(i); - } - for (const uint32_t *RM : RegMasks) { - RegisterId MI = getRegMaskId(RM); - if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) - AS.insert(MI); - } - return AS; - } - - for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI) - AS.insert(*AI); - for (const uint32_t *RM : RegMasks) { - RegisterId MI = getRegMaskId(RM); - if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) - AS.insert(MI); - } - return AS; -} - -bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { - assert(Register::isPhysicalRegister(RA.Reg)); - assert(Register::isPhysicalRegister(RB.Reg)); - - MCRegUnitMaskIterator UMA(RA.Reg, &TRI); - MCRegUnitMaskIterator UMB(RB.Reg, &TRI); - // Reg units are returned in the numerical order. - while (UMA.isValid() && UMB.isValid()) { - // Skip units that are masked off in RA. - std::pair<RegisterId,LaneBitmask> PA = *UMA; - if (PA.second.any() && (PA.second & RA.Mask).none()) { - ++UMA; - continue; - } - // Skip units that are masked off in RB. - std::pair<RegisterId,LaneBitmask> PB = *UMB; - if (PB.second.any() && (PB.second & RB.Mask).none()) { - ++UMB; - continue; - } - - if (PA.first == PB.first) - return true; - if (PA.first < PB.first) - ++UMA; - else if (PB.first < PA.first) - ++UMB; - } - return false; -} - -bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { - assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); - const uint32_t *MB = getRegMaskBits(RM.Reg); - bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); - // If the lane mask information is "full", e.g. when the given lane mask - // is a superset of the lane mask from the register class, check the regmask - // bit directly. - if (RR.Mask == LaneBitmask::getAll()) - return !Preserved; - const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; - if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask) - return !Preserved; - - // Otherwise, check all subregisters whose lane mask overlaps the given - // mask. For each such register, if it is preserved by the regmask, then - // clear the corresponding bits in the given mask. If at the end, all - // bits have been cleared, the register does not alias the regmask (i.e. - // is it preserved by it). - LaneBitmask M = RR.Mask; - for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) { - LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); - if ((SM & RR.Mask).none()) - continue; - unsigned SR = SI.getSubReg(); - if (!(MB[SR/32] & (1u << (SR%32)))) - continue; - // The subregister SR is preserved. - M &= ~SM; - if (M.none()) - return false; - } - - return true; -} - -bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const { - assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); - unsigned NumRegs = TRI.getNumRegs(); - const uint32_t *BM = getRegMaskBits(RM.Reg); - const uint32_t *BN = getRegMaskBits(RN.Reg); - - for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) { - // Intersect the negations of both words. Disregard reg=0, - // i.e. 0th bit in the 0th word. - uint32_t C = ~BM[w] & ~BN[w]; - if (w == 0) - C &= ~1; - if (C) - return true; - } - - // Check the remaining registers in the last word. - unsigned TailRegs = NumRegs % 32; - if (TailRegs == 0) - return false; - unsigned TW = NumRegs / 32; - uint32_t TailMask = (1u << TailRegs) - 1; - if (~BM[TW] & ~BN[TW] & TailMask) - return true; - - return false; -} - -RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const { - if (RR.Reg == R) - return RR; - if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg)) - return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask)); - if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) { - const RegInfo &RI = RegInfos[R]; - LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask - : LaneBitmask::getAll(); - LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask); - return RegisterRef(R, M & RCM); - } - llvm_unreachable("Invalid arguments: unrelated registers?"); -} - -bool RegisterAggr::hasAliasOf(RegisterRef RR) const { - if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) - return Units.anyCommon(PRI.getMaskUnits(RR.Reg)); - - for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { - std::pair<uint32_t,LaneBitmask> P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) - if (Units.test(P.first)) - return true; - } - return false; -} - -bool RegisterAggr::hasCoverOf(RegisterRef RR) const { - if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { - BitVector T(PRI.getMaskUnits(RR.Reg)); - return T.reset(Units).none(); - } - - for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { - std::pair<uint32_t,LaneBitmask> P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) - if (!Units.test(P.first)) - return false; - } - return true; -} - -RegisterAggr &RegisterAggr::insert(RegisterRef RR) { - if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { - Units |= PRI.getMaskUnits(RR.Reg); - return *this; - } - - for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { - std::pair<uint32_t,LaneBitmask> P = *U; - if (P.second.none() || (P.second & RR.Mask).any()) - Units.set(P.first); - } - return *this; -} - -RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) { - Units |= RG.Units; - return *this; -} - -RegisterAggr &RegisterAggr::intersect(RegisterRef RR) { - return intersect(RegisterAggr(PRI).insert(RR)); -} - -RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) { - Units &= RG.Units; - return *this; -} - -RegisterAggr &RegisterAggr::clear(RegisterRef RR) { - return clear(RegisterAggr(PRI).insert(RR)); -} - -RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) { - Units.reset(RG.Units); - return *this; -} - -RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const { - RegisterAggr T(PRI); - T.insert(RR).intersect(*this); - if (T.empty()) - return RegisterRef(); - RegisterRef NR = T.makeRegRef(); - assert(NR); - return NR; -} - -RegisterRef RegisterAggr::clearIn(RegisterRef RR) const { - return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef(); -} - -RegisterRef RegisterAggr::makeRegRef() const { - int U = Units.find_first(); - if (U < 0) - return RegisterRef(); - - auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { - for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R) - for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S) - Regs.set(*S); - }; - - // Find the set of all registers that are aliased to all the units - // in this aggregate. - - // Get all the registers aliased to the first unit in the bit vector. - BitVector Regs(PRI.getTRI().getNumRegs()); - AliasedRegs(U, Regs); - U = Units.find_next(U); - - // For each other unit, intersect it with the set of all registers - // aliased that unit. - while (U >= 0) { - BitVector AR(PRI.getTRI().getNumRegs()); - AliasedRegs(U, AR); - Regs &= AR; - U = Units.find_next(U); - } - - // If there is at least one register remaining, pick the first one, - // and consolidate the masks of all of its units contained in this - // aggregate. - - int F = Regs.find_first(); - if (F <= 0) - return RegisterRef(); - - LaneBitmask M; - for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) { - std::pair<uint32_t,LaneBitmask> P = *I; - if (Units.test(P.first)) - M |= P.second.none() ? LaneBitmask::getAll() : P.second; - } - return RegisterRef(F, M); -} - -void RegisterAggr::print(raw_ostream &OS) const { - OS << '{'; - for (int U = Units.find_first(); U >= 0; U = Units.find_next(U)) - OS << ' ' << printRegUnit(U, &PRI.getTRI()); - OS << " }"; -} - -RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG, - bool End) - : Owner(&RG) { - for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) { - RegisterRef R = RG.PRI.getRefForUnit(U); - Masks[R.Reg] |= R.Mask; - } - Pos = End ? Masks.end() : Masks.begin(); - Index = End ? Masks.size() : 0; -} diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.h b/llvm/lib/Target/Hexagon/RDFRegisters.h deleted file mode 100644 index 4afaf80e46595..0000000000000 --- a/llvm/lib/Target/Hexagon/RDFRegisters.h +++ /dev/null @@ -1,240 +0,0 @@ -//===- RDFRegisters.h -------------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H -#define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H - -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/MC/LaneBitmask.h" -#include <cassert> -#include <cstdint> -#include <map> -#include <set> -#include <vector> - -namespace llvm { - -class MachineFunction; -class raw_ostream; - -namespace rdf { - - using RegisterId = uint32_t; - - // Template class for a map translating uint32_t into arbitrary types. - // The map will act like an indexed set: upon insertion of a new object, - // it will automatically assign a new index to it. Index of 0 is treated - // as invalid and is never allocated. - template <typename T, unsigned N = 32> - struct IndexedSet { - IndexedSet() { Map.reserve(N); } - - T get(uint32_t Idx) const { - // Index Idx corresponds to Map[Idx-1]. - assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); - return Map[Idx-1]; - } - - uint32_t insert(T Val) { - // Linear search. - auto F = llvm::find(Map, Val); - if (F != Map.end()) - return F - Map.begin() + 1; - Map.push_back(Val); - return Map.size(); // Return actual_index + 1. - } - - uint32_t find(T Val) const { - auto F = llvm::find(Map, Val); - assert(F != Map.end()); - return F - Map.begin() + 1; - } - - uint32_t size() const { return Map.size(); } - - using const_iterator = typename std::vector<T>::const_iterator; - - const_iterator begin() const { return Map.begin(); } - const_iterator end() const { return Map.end(); } - - private: - std::vector<T> Map; - }; - - struct RegisterRef { - RegisterId Reg = 0; - LaneBitmask Mask = LaneBitmask::getNone(); - - RegisterRef() = default; - explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) - : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} - - operator bool() const { - return Reg != 0 && Mask.any(); - } - - bool operator== (const RegisterRef &RR) const { - return Reg == RR.Reg && Mask == RR.Mask; - } - - bool operator!= (const RegisterRef &RR) const { - return !operator==(RR); - } - - bool operator< (const RegisterRef &RR) const { - return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); - } - }; - - - struct PhysicalRegisterInfo { - PhysicalRegisterInfo(const TargetRegisterInfo &tri, - const MachineFunction &mf); - - static bool isRegMaskId(RegisterId R) { - return Register::isStackSlot(R); - } - - RegisterId getRegMaskId(const uint32_t *RM) const { - return Register::index2StackSlot(RegMasks.find(RM)); - } - - const uint32_t *getRegMaskBits(RegisterId R) const { - return RegMasks.get(Register::stackSlot2Index(R)); - } - - RegisterRef normalize(RegisterRef RR) const; - - bool alias(RegisterRef RA, RegisterRef RB) const { - if (!isRegMaskId(RA.Reg)) - return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); - return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); - } - - std::set<RegisterId> getAliasSet(RegisterId Reg) const; - - RegisterRef getRefForUnit(uint32_t U) const { - return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); - } - - const BitVector &getMaskUnits(RegisterId MaskId) const { - return MaskInfos[Register::stackSlot2Index(MaskId)].Units; - } - - RegisterRef mapTo(RegisterRef RR, unsigned R) const; - const TargetRegisterInfo &getTRI() const { return TRI; } - - private: - struct RegInfo { - const TargetRegisterClass *RegClass = nullptr; - }; - struct UnitInfo { - RegisterId Reg = 0; - LaneBitmask Mask; - }; - struct MaskInfo { - BitVector Units; - }; - - const TargetRegisterInfo &TRI; - IndexedSet<const uint32_t*> RegMasks; - std::vector<RegInfo> RegInfos; - std::vector<UnitInfo> UnitInfos; - std::vector<MaskInfo> MaskInfos; - - bool aliasRR(RegisterRef RA, RegisterRef RB) const; - bool aliasRM(RegisterRef RR, RegisterRef RM) const; - bool aliasMM(RegisterRef RM, RegisterRef RN) const; - }; - - struct RegisterAggr { - RegisterAggr(const PhysicalRegisterInfo &pri) - : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} - RegisterAggr(const RegisterAggr &RG) = default; - - bool empty() const { return Units.none(); } - bool hasAliasOf(RegisterRef RR) const; - bool hasCoverOf(RegisterRef RR) const; - - static bool isCoverOf(RegisterRef RA, RegisterRef RB, - const PhysicalRegisterInfo &PRI) { - return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); - } - - RegisterAggr &insert(RegisterRef RR); - RegisterAggr &insert(const RegisterAggr &RG); - RegisterAggr &intersect(RegisterRef RR); - RegisterAggr &intersect(const RegisterAggr &RG); - RegisterAggr &clear(RegisterRef RR); - RegisterAggr &clear(const RegisterAggr &RG); - - RegisterRef intersectWith(RegisterRef RR) const; - RegisterRef clearIn(RegisterRef RR) const; - RegisterRef makeRegRef() const; - - void print(raw_ostream &OS) const; - - struct rr_iterator { - using MapType = std::map<RegisterId, LaneBitmask>; - - private: - MapType Masks; - MapType::iterator Pos; - unsigned Index; - const RegisterAggr *Owner; - - public: - rr_iterator(const RegisterAggr &RG, bool End); - - RegisterRef operator*() const { - return RegisterRef(Pos->first, Pos->second); - } - - rr_iterator &operator++() { - ++Pos; - ++Index; - return *this; - } - - bool operator==(const rr_iterator &I) const { - assert(Owner == I.Owner); - (void)Owner; - return Index == I.Index; - } - - bool operator!=(const rr_iterator &I) const { - return !(*this == I); - } - }; - - rr_iterator rr_begin() const { - return rr_iterator(*this, false); - } - rr_iterator rr_end() const { - return rr_iterator(*this, true); - } - - private: - BitVector Units; - const PhysicalRegisterInfo &PRI; - }; - - // Optionally print the lane mask, if it is not ~0. - struct PrintLaneMaskOpt { - PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {} - LaneBitmask Mask; - }; - raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P); - -} // end namespace rdf - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H |